add comments about DRAM sync clock being identical to main clock

diff --git a/src/crg.py b/src/crg.py
index 3cf483f5893bebfe7723da13c3b0553753b8b7a7..6fb8dd1f00df252455c1d1bd7d143168dc9c86a5 100644 (file)
--- a/src/crg.py
+++ b/src/crg.py
@@ -236,6 +236,8 @@ class ECPIX5CRG(Elaboratable):
             i_CLKI=ClockSignal("sync2x"),
             i_RST=0,
             o_CDIVX=ClockSignal("sync"))
+
+        # temporarily set dram sync clock exactly equal to main sync
         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
 
         return m