whoops, a Simulation bug, dcache bus ack Signal needed to be

copied into a separate combinatorial Signal

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index abef5d6d3fdc34270deaec349a4e3f90c4123c78..1a34aa2c96979a44330c23a30a86e0a48a19f58e 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1529,8 +1529,10 @@ class DCache(Elaboratable):
                     sync += r1.wb.adr[:LINE_OFF_BITS-ROW_OFF_BITS].eq(row+1)
 
                 # Incoming acks processing
-                sync += r1.forward_valid1.eq(bus.ack)
-                with m.If(bus.ack):
+                bus_ack = Signal()
+                comb += bus_ack.eq(bus.ack) # o dear - Simulation bug....
+                sync += r1.forward_valid1.eq(bus_ack)
+                with m.If(bus_ack):
                     srow = Signal(ROW_LINE_BITS)
                     comb += srow.eq(r1.store_row)
                     sync += r1.rows_valid[srow].eq(1)