set only the SO bit as sticky, not the OV flags as sticky

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 9e3df2e0cdd52763fa6b913d7dd7c1010281f315..f6380c5fd7d5cd9955a8dcd7c196396357201bfc 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -22,19 +22,13 @@ class ALUOutputStage(CommonOutputStage):
         op = self.i.ctx.op
         xer_so_i, xer_ov_i = self.i.xer_so.data, self.i.xer_ov.data
 
-        # create overflow
-        ov = Signal(2, reset_less=True) # OV, OV32
-
         # XXX see https://bugs.libre-soc.org/show_bug.cgi?id=319#c5
-        comb += ov[0].eq(xer_so_i | xer_ov_i[0]) # OV
-        comb += ov[1].eq(xer_so_i | xer_ov_i[1]) # OV32 XXX!
-
-        comb += self.so.eq(ov[0]) # SO
+        comb += self.so.eq(xer_so_i[0] | xer_ov_i[0]) # SO
 
         # copy overflow and sticky-overflow
         comb += self.o.xer_so.data.eq(self.so)
         comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok)
-        comb += self.o.xer_ov.data.eq(ov)
+        comb += self.o.xer_ov.data.eq(xer_ov_i)
         comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set
 
         return m