investigating div fsm and simulator bug

diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 700a620643f6732f6ff0a3e6a0f0b345cc091f96..f98f6162ec625ba2defbf3ed95c520c18c5292ea 100644 (file)
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -254,7 +254,9 @@ class SelectableInt:
         return SelectableInt(~self.value, self.bits)
 
     def __neg__(self):
-        return SelectableInt(~self.value + 1, self.bits)
+        res = SelectableInt((~self.value) + 1, self.bits)
+        print ("neg", hex(self.value), hex(res.value))
+        return res
 
     def __lshift__(self, b):
         b = check_extsign(self, b)

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 9a978b4531bc9b751e280d990ed3765abcef0a09..c4280fee54e915462b23dc838a614c645435916a 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -226,7 +226,7 @@ class AllFunctionUnits(Elaboratable):
 
     """
 
-    def __init__(self, pspec, pilist=None, div_fsm=False):
+    def __init__(self, pspec, pilist=None, div_fsm=True):
         addrwid = pspec.addr_wid
         units = pspec.units
         if not isinstance(units, dict):

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index ee8e5b95ecdff6de3f71e5094f93226b6042a87f..4c8ee38765961fdf0eebb8959e9ac0f4fdf96ae4 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
 
 class DivTestCases(TestAccumulatorBase):
     def case_divw_regression(self):
-        # simulator is wrong, FSM and power-instruction-analyzer are both correct
+        # simulator is wrong, FSM and power-instruction-analyzer both correct
         lst = [f"divw 0, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[2] = 0x2