"""
from math import log
-from nmigen import Signal, Cat, Const, Mux, Module, Array
+from nmigen import Signal, Cat, Const, Mux, Module, Array, Elaboratable
from nmigen.cli import verilog, rtlil
from nmigen.lib.coding import PriorityEncoder
from nmigen.hdl.rec import Record, Layout
from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
-class MultiInControlBase:
+class MultiInControlBase(Elaboratable):
""" Common functions for Pipeline API
"""
def __init__(self, in_multi=None, p_len=1):
"""
return eq(self.p[idx].i_data, i)
+ def elaborate(self, platform):
+ m = Module()
+ for i, p in enumerate(self.p):
+ setattr(m.submodules, "p%d" % i, p)
+ m.submodules.n = self.n
+ return m
+
def __iter__(self):
for p in self.p:
yield from p
return list(self)
-class MultiOutControlBase:
+class MultiOutControlBase(Elaboratable):
""" Common functions for Pipeline API
"""
def __init__(self, n_len=1, in_multi=None):
return self.n[idx]._connect_out(nxt.n)
return self.n[idx]._connect_out(nxt.n[nxt_idx])
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.p = self.p
+ for i, n in enumerate(self.n):
+ setattr(m.submodules, "n%d" % i, n)
+ return m
+
def set_input(self, i):
""" helper function to set the input data
"""
self.n[i].o_data = stage.ospec() # output type
def elaborate(self, platform):
- m = Module()
+ m = MultiOutControlBase.elaborate(self, platform)
if hasattr(self.n_mux, "elaborate"): # TODO: identify submodule?
m.submodules += self.n_mux
self.n.o_data = stage.ospec()
def elaborate(self, platform):
- m = Module()
+ m = MultiInControlBase.elaborate(self, platform)
m.submodules += self.p_mux
-class InputPriorityArbiter:
+class InputPriorityArbiter(Elaboratable):
""" arbitration module for Input-Mux pipe, baed on PriorityEncoder
"""
def __init__(self, pipe, num_rows):
from random import randint
from math import log
-from nmigen import Module, Signal, Cat, Value
+from nmigen import Module, Signal, Cat, Value, Elaboratable
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
-class TestInOutPipe:
+class TestInOutPipe(Elaboratable):
def __init__(self, num_rows=4):
self.num_rows = num_rows
self.inpipe = TestPriorityMuxPipe(num_rows) # fan-in (combinatorial)