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diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py
index 11ff8d8e6602481083ccdb61832d3232f3670c02..2c7121152deb263ec87828803ebe5dbc876713f5 100644 (file)
--- a/src/soc/fu/spr/formal/proof_main_stage.py
+++ b/src/soc/fu/spr/formal/proof_main_stage.py
@@ -23,7 +23,7 @@ from soc.decoder.power_enums import MicrOp, SPR, XER_bits
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-
+# use POWER numbering. sigh.
 def xer_bit(name):
     return 63-XER_bits[name]