enable rvfi, fix imports

diff --git a/src/soc/minerva/core.py b/src/soc/minerva/core.py
index c73d5fd08c4de4beea9bebd8953fbe1fde77b4b9..51e94e6dc1a74e8b1601b3fa91b46903b249e17b 100644 (file)
--- a/src/soc/minerva/core.py
+++ b/src/soc/minerva/core.py
@@ -14,7 +14,7 @@ from soc.minerva.units.decoder import InstructionDecoder
 from soc.minerva.units.divider import Divider, DummyDivider
 from soc.minerva.units.exception import ExceptionUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit, PCSelector
-from soc.minerva.units.rvficon import RVFIController
+from soc.minerva.units.rvficon import RVFIController, rvfi_layout
 from soc.minerva.units.loadstore import (BareLoadStoreUnit, CachedLoadStoreUnit,
                                          DataSelector)
 from soc.minerva.units.logic import LogicUnit

diff --git a/src/soc/minerva/units/rvficon.py b/src/soc/minerva/units/rvficon.py
index 266fd12ac51136b86e273d6c4f019cc595e3f456..a167f496658ebfc3908ce9d9c09745d6db1f0a54 100644 (file)
--- a/src/soc/minerva/units/rvficon.py
+++ b/src/soc/minerva/units/rvficon.py
@@ -1,7 +1,7 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import Elaboratable, Module, Signal, Record
+from nmigen import Elaboratable, Module, Signal, Record, Const
 from nmigen.hdl.rec import DIR_FANOUT
 
 from ..wishbone import wishbone_layout