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diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index eb7c80a65f5d1ea9d6d1580b0bb699c315b2cfa9..d72a054fb9026937830cabf35e3fae4c16217d38 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -63,6 +63,7 @@ from collections import namedtuple
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
 
+
 Subdecoder = namedtuple("Subdecoder", ["pattern", "opcodes", "opint",
                                        "bitsel", "suffix", "subdecoders"])
 
@@ -177,6 +178,7 @@ class PowerDecoder(Elaboratable):
         comb = m.d.comb
 
         # note: default opcode is "illegal" as this is a combinatorial block
+        # this only works because OP_ILLEGAL=0 and the default (unset) is 0
 
         # go through the list of CSV decoders first
         for d in self.dec:

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index be41b5ccf1d73d7057834f7b09c6835320662161..e123a8be22bb81758445675725b7935e89d1b519 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -79,10 +79,10 @@ class Form(Enum):
     Z23 = 28
 
 
-
+# Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique
 class InternalOp(Enum):
-    OP_ILLEGAL = 0
+    OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
     OP_NOP = 1
     OP_ADD = 2
     OP_ADDPCIS = 3
@@ -214,6 +214,9 @@ class CryIn(Enum):
     ONE = 1
     CA = 2
 
+
+# SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971
+
 @unique
 class SPR(Enum):
     XER    = 1