when doing LD-immediate only acknowledge register 1 rd-req

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index a2dcaa127cc52e759d8f3a4deccc3e2134957b5b..a15a88fd072926b400384e77cfe851a3d4dc074d 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -571,7 +571,10 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.rd.go.eq(0b11)
+    if imm_ok:
+        yield dut.rd.go.eq(0b01)
+    else:
+        yield dut.rd.go.eq(0b11)
     yield from wait_for(dut.rd.rel)
     yield dut.rd.go.eq(0)