check msr in trap test, fix OP_RFID

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 009797dc7e05ab050dec3533ac5eb86881a4233d..0b8dd58f63453feb417a9ba378005f90ff550db2 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -349,6 +349,13 @@ class ALUHelpers:
             print(f"expected {expected:x}, actual: {alu_out:x}")
             dut.assertEqual(expected, alu_out, msg)
 
+    def check_msr(dut, res, sim_o, msg):
+        if 'msr' in res:
+            expected = sim_o['msr']
+            alu_out = res['msr']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
     def check_nia(dut, res, sim_o, msg):
         if 'nia' in res:
             expected = sim_o['nia']

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 6a12eb2fbd92d2033345cde09448aff1f87e0a9a..ee09d9ec070f53169f9874988365b62a961ec2d2 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -194,6 +194,17 @@ class TrapMainStage(PipeModBase):
                 # MSR was in srr1
                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
                 msr_check_pr(m, msr_o.data)
+
+                # hypervisor stuff
+                comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV])
+                comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) |
+                                             (~msr_i[MSR.HV] & srr1_i[MSR.HV]))
+                # don't understand but it's in the spec
+                with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) |
+                          (srr1_i[63-31:63-29] != Const(0b000, 3))):
+                    comb += msr_o.data[63-31:63-29].eq(srr1_i[63-31:63-29])
+                with m.Else():
+                    comb += msr_o.data[63-31:63-29].eq(msr_i[63-31:63-29])
                 comb += msr_o.ok.eq(1)
 
             # OP_SC

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 251ce50edfed72e416a8ac8347228f99fbb0240a..6fbf960b109ab91cbb147b2b289a29f7949df583 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -229,6 +229,7 @@ class TestRunner(FHDLTestCase):
         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
         ALUHelpers.check_fast_spr2(self, res, sim_o, code)
         ALUHelpers.check_nia(self, res, sim_o, code)
+        ALUHelpers.check_msr(self, res, sim_o, code)
 
 
 if __name__ == "__main__":