split out CacheTag Record to separate structure

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 971976bd79a41325424f30487b8f4fd41696b820..9f6ba0d4edf9fb67cd0f19e48946487e095b395b 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -164,16 +164,23 @@ print ("    TAG_WIDTH", TAG_WIDTH)
 print ("     NUM_WAYS", NUM_WAYS)
 print ("    NUM_LINES", NUM_LINES)
 
-def CacheTagArray():
+
+def CacheTag(name=None):
     tag_layout = [('valid', NUM_WAYS),
                   ('tag', TAG_RAM_WIDTH),
                  ]
-    return Array(Record(tag_layout, name="tag%d" % x) for x in range(NUM_LINES))
+    return Record(tag_layout, name=name)
+
+
+def CacheTagArray():
+    return Array(CacheTag(name="tag%d" % x) for x in range(NUM_LINES))
+
 
 def RowPerLineValidArray():
     return Array(Signal(name="rows_valid%d" % x) \
                         for x in range(ROW_PER_LINE))
 
+
 # L1 TLB
 TLB_SET_BITS     = log2_int(TLB_SET_SIZE)
 TLB_WAY_BITS     = log2_int(TLB_NUM_WAYS)