add pseudo-op conversion

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 4c2554b7545a6951af18e32835378d804a63b4fd..b44d059f064258c9d4aa557a5ea839acc1cfd208 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -58,6 +58,12 @@ class GeneralTestCases(FHDLTestCase):
         32b4:   00 00 00 60     nop
         32b8:   fc ff 00 42     bdnz    32b4 <cdelay+0x10>
         32bc:   20 00 80 4e     blr
+
+        notes on converting pseudo-assembler to actual:
+
+        * bdnz target (equivalent to: bc 16,0,target)
+        * Clear left immediate clrldi ra,rs,n (n < 64) rldicl ra,rs,0,n
+        * CTR mtctr Rx mtspr 9,Rx
         """
         pass