adjust litex bios cmp test

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 6f537e32a8238f0c73b9027e1eb5fca8116cf8c5..b6cb3097cf297cd996a075be555f1009778e281b 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -52,11 +52,11 @@ class GeneralTestCases(FHDLTestCase):
     def test_0_litex_bios_cmp(self):
         """litex bios cmp test
         """
-        lst = [ "addi     26, 0, 43690",
-                "ori      26, 26, 43690",
+        lst = [ "addis    26, 0, 21845",
+                "ori      26, 26, 21845",
+                "addi     5, 26, 0",
+                "rldicr  5,5,32,31",
                 "addi     5, 26, 0",
-                #"rldicr  5,5,32,31",
-                #"addi     5, 26, 0",
                 "cmp     0, 0, 5, 26",
                 "bc      12, 2, 28",
                 "addis   6, 0, 1",