imports: get div and mul working

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8e928bb7b27e1cd19443693f8a64ee3813f8f6de..a65700eb0da0388b647a69a1d401af9c729d7436 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,8 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState, FPGetOp
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpcommon.getop import FPGetOp
 
 
 class FPMUL(FPBase):

diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index e074c5c66364462b058db06f91d0554c6f2d613c..abbcf95ff793aa9dd5ee4406c5defd6d4877c4ed 100644 (file)
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -5,8 +5,8 @@
 from nmigen import Module, Signal, Const, Cat
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState, FPGetOp
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpcommon.getop import FPGetOp
 
 class Div:
     def __init__(self, width):