output to issuer_simulator.vcd

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 0bf9246ad3c38a0ad78281915673110fbab3b1d0..74ad054346b6b0e83107420bae5a637359f54418 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -114,7 +114,7 @@ class TestRunner(FHDLTestCase):
                     yield from check_sim_memory(self, l0, sim, code)
 
         sim.add_sync_process(process)
-        with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
+        with sim.write_vcd("issuer_simulator.vcd",
                             traces=[]):
             sim.run()