add the div pipe kind plus prog.assembly to the assert debug output

diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py
index a506c0a8ecd1071213539319552aef41507105c3..6ce4c7a9189bb86893045a47e1f11eee5eec77d4 100644 (file)
--- a/src/soc/fu/div/test/runner.py
+++ b/src/soc/fu/div/test/runner.py
@@ -188,8 +188,10 @@ class DivRunner(unittest.TestCase):
                         # TODO: raise bugreport with whitequark
                         # requesting a public API to access this "officially"
                         # XXX print("time:", sim._state.timeline.now)
+                        msg = "%s: %s" % (self.div_pipe_kind.name, core)
+                        msg += " %s" % (repr(prog.assembly))
                         yield from self.check_alu_outputs(alu, pdecode2,
-                                                          isa_sim, code)
+                                                          isa_sim, msg)
 
         sim.add_sync_process(process)
         with sim.write_vcd(f"div_simulator_{self.div_pipe_kind.name}.vcd"):