rename long parameter name to shorter n_stages

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 547af3ceed09834d5665964a6ee1e17897066faf..9fd5eb856cb0b4e85a4800c321623ce956028fe8 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -44,7 +44,7 @@ class DivPipeCoreConfig:
             + f"{self.fract_width}, {self.log2_radix})"
 
     @property
-    def num_calculate_stages(self):
+    def n_stages(self):
         """ Get the number of ``DivPipeCoreCalculateStage`` needed. """
         return (self.bit_width + self.log2_radix - 1) // self.log2_radix
 
@@ -265,7 +265,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
     def __init__(self, core_config, stage_index):
         """ Create a ``DivPipeCoreSetupStage`` instance. """
         self.core_config = core_config
-        assert stage_index in range(core_config.num_calculate_stages)
+        assert stage_index in range(core_config.n_stages)
         self.stage_index = stage_index
         self.i = self.ispec()
         self.o = self.ospec()

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 88b61326820c7e812013ee11ae1d40284cff74a6..fc42829ba24a3cbe51b0ce4b5e3a3a3a2fd03356 100755 (executable)
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -180,11 +180,11 @@ class DivPipeCoreTestPipeline(Elaboratable):
         self.setup_stage = DivPipeCoreSetupStage(core_config)
         self.calculate_stages = [
             DivPipeCoreCalculateStage(core_config, stage_index)
-            for stage_index in range(core_config.num_calculate_stages)]
+            for stage_index in range(core_config.n_stages)]
         self.final_stage = DivPipeCoreFinalStage(core_config)
         self.interstage_signals = [
             DivPipeCoreInterstageData(core_config, reset_less=True)
-            for i in range(core_config.num_calculate_stages + 1)]
+            for i in range(core_config.n_stages + 1)]
         self.i = DivPipeCoreInputData(core_config, reset_less=True)
         self.o = DivPipeCoreOutputData(core_config, reset_less=True)
         self.sync = sync
@@ -245,7 +245,7 @@ class TestDivPipeCore(unittest.TestCase):
                 # sync with generator
                 if sync:
                     yield
-                    for _ in range(core_config.num_calculate_stages):
+                    for _ in range(core_config.n_stages):
                         yield
                     yield