experiment adding 3x extra SRAMs back in but still @ 32-bit WB

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index 27e6a4462ccdb036d1ec9cbd6832f62029b8ad14..3d746a300e2548b6fd4c039f2bd8d3f6418037f0 100644 (file)
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -220710,2412 +220710,2514 @@ module \logical_pipe2
   connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
   connect \output_muxid \muxid
 end
-attribute \src "ls180.v:4.1-10555.10"
+attribute \src "ls180.v:4.1-10732.10"
 attribute \cells_not_processed 1
 module \ls180
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691
-  attribute \src "ls180.v:10043.1-10053.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692
-  attribute \src "ls180.v:10063.1-10067.4"
-  wire width 3 $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695
-  attribute \src "ls180.v:10063.1-10067.4"
-  wire width 25 $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696
-  attribute \src "ls180.v:10063.1-10067.4"
-  wire width 25 $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697
-  attribute \src "ls180.v:10077.1-10081.4"
-  wire width 3 $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702
-  attribute \src "ls180.v:10077.1-10081.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703
-  attribute \src "ls180.v:10077.1-10081.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704
-  attribute \src "ls180.v:10091.1-10095.4"
-  wire width 3 $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709
-  attribute \src "ls180.v:10091.1-10095.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710
-  attribute \src "ls180.v:10091.1-10095.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711
-  attribute \src "ls180.v:10105.1-10109.4"
-  wire width 3 $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716
-  attribute \src "ls180.v:10105.1-10109.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717
-  attribute \src "ls180.v:10105.1-10109.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718
-  attribute \src "ls180.v:10120.1-10124.4"
-  wire width 4 $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723
-  attribute \src "ls180.v:10120.1-10124.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724
-  attribute \src "ls180.v:10120.1-10124.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725
-  attribute \src "ls180.v:10137.1-10141.4"
-  wire width 4 $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730
-  attribute \src "ls180.v:10137.1-10141.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731
-  attribute \src "ls180.v:10137.1-10141.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 5 $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739
-  attribute \src "ls180.v:10167.1-10171.4"
-  wire width 5 $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744
-  attribute \src "ls180.v:10167.1-10171.4"
-  wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745
-  attribute \src "ls180.v:10167.1-10171.4"
-  wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769
+  attribute \src "ls180.v:10160.1-10170.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 7 $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 7 $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 7 $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 7 $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 7 $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 7 $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 7 $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 7 $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 7 $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 7 $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 7 $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 7 $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812
+  attribute \src "ls180.v:10240.1-10244.4"
+  wire width 3 $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815
+  attribute \src "ls180.v:10240.1-10244.4"
+  wire width 25 $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816
+  attribute \src "ls180.v:10240.1-10244.4"
+  wire width 25 $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817
+  attribute \src "ls180.v:10254.1-10258.4"
+  wire width 3 $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822
+  attribute \src "ls180.v:10254.1-10258.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823
+  attribute \src "ls180.v:10254.1-10258.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824
+  attribute \src "ls180.v:10268.1-10272.4"
+  wire width 3 $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829
+  attribute \src "ls180.v:10268.1-10272.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830
+  attribute \src "ls180.v:10268.1-10272.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831
+  attribute \src "ls180.v:10282.1-10286.4"
+  wire width 3 $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836
+  attribute \src "ls180.v:10282.1-10286.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837
+  attribute \src "ls180.v:10282.1-10286.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838
+  attribute \src "ls180.v:10297.1-10301.4"
+  wire width 4 $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843
+  attribute \src "ls180.v:10297.1-10301.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844
+  attribute \src "ls180.v:10297.1-10301.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845
+  attribute \src "ls180.v:10314.1-10318.4"
+  wire width 4 $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850
+  attribute \src "ls180.v:10314.1-10318.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851
+  attribute \src "ls180.v:10314.1-10318.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852
+  attribute \src "ls180.v:10330.1-10334.4"
+  wire width 5 $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857
+  attribute \src "ls180.v:10330.1-10334.4"
+  wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858
+  attribute \src "ls180.v:10330.1-10334.4"
+  wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859
+  attribute \src "ls180.v:10344.1-10348.4"
+  wire width 5 $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864
+  attribute \src "ls180.v:10344.1-10348.4"
+  wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865
+  attribute \src "ls180.v:10344.1-10348.4"
+  wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866
+  attribute \src "ls180.v:3297.1-3390.4"
   wire width 3 $0\builder_bankmachine0_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_bankmachine0_state[2:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire width 3 $0\builder_bankmachine1_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_bankmachine1_state[2:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire width 3 $0\builder_bankmachine2_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_bankmachine2_state[2:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire width 3 $0\builder_bankmachine3_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_bankmachine3_state[2:0]
-  attribute \src "ls180.v:6516.1-6532.4"
+  attribute \src "ls180.v:6618.1-6634.4"
   wire $0\builder_comb_rhs_array_muxed0[0:0]
-  attribute \src "ls180.v:6737.1-6753.4"
+  attribute \src "ls180.v:6839.1-6855.4"
   wire $0\builder_comb_rhs_array_muxed10[0:0]
-  attribute \src "ls180.v:6754.1-6770.4"
+  attribute \src "ls180.v:6856.1-6872.4"
   wire $0\builder_comb_rhs_array_muxed11[0:0]
-  attribute \src "ls180.v:6822.1-6829.4"
+  attribute \src "ls180.v:6924.1-6931.4"
   wire width 22 $0\builder_comb_rhs_array_muxed12[21:0]
-  attribute \src "ls180.v:6830.1-6837.4"
+  attribute \src "ls180.v:6932.1-6939.4"
   wire $0\builder_comb_rhs_array_muxed13[0:0]
-  attribute \src "ls180.v:6838.1-6845.4"
+  attribute \src "ls180.v:6940.1-6947.4"
   wire $0\builder_comb_rhs_array_muxed14[0:0]
-  attribute \src "ls180.v:6846.1-6853.4"
+  attribute \src "ls180.v:6948.1-6955.4"
   wire width 22 $0\builder_comb_rhs_array_muxed15[21:0]
-  attribute \src "ls180.v:6854.1-6861.4"
+  attribute \src "ls180.v:6956.1-6963.4"
   wire $0\builder_comb_rhs_array_muxed16[0:0]
-  attribute \src "ls180.v:6862.1-6869.4"
+  attribute \src "ls180.v:6964.1-6971.4"
   wire $0\builder_comb_rhs_array_muxed17[0:0]
-  attribute \src "ls180.v:6870.1-6877.4"
+  attribute \src "ls180.v:6972.1-6979.4"
   wire width 22 $0\builder_comb_rhs_array_muxed18[21:0]
-  attribute \src "ls180.v:6878.1-6885.4"
+  attribute \src "ls180.v:6980.1-6987.4"
   wire $0\builder_comb_rhs_array_muxed19[0:0]
-  attribute \src "ls180.v:6533.1-6549.4"
+  attribute \src "ls180.v:6635.1-6651.4"
   wire width 13 $0\builder_comb_rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:6886.1-6893.4"
+  attribute \src "ls180.v:6988.1-6995.4"
   wire $0\builder_comb_rhs_array_muxed20[0:0]
-  attribute \src "ls180.v:6894.1-6901.4"
+  attribute \src "ls180.v:6996.1-7003.4"
   wire width 22 $0\builder_comb_rhs_array_muxed21[21:0]
-  attribute \src "ls180.v:6902.1-6909.4"
+  attribute \src "ls180.v:7004.1-7011.4"
   wire $0\builder_comb_rhs_array_muxed22[0:0]
-  attribute \src "ls180.v:6910.1-6917.4"
+  attribute \src "ls180.v:7012.1-7019.4"
   wire $0\builder_comb_rhs_array_muxed23[0:0]
-  attribute \src "ls180.v:6918.1-6937.4"
+  attribute \src "ls180.v:7020.1-7039.4"
   wire width 32 $0\builder_comb_rhs_array_muxed24[31:0]
-  attribute \src "ls180.v:6938.1-6957.4"
+  attribute \src "ls180.v:7040.1-7059.4"
   wire width 32 $0\builder_comb_rhs_array_muxed25[31:0]
-  attribute \src "ls180.v:6958.1-6977.4"
+  attribute \src "ls180.v:7060.1-7079.4"
   wire width 4 $0\builder_comb_rhs_array_muxed26[3:0]
-  attribute \src "ls180.v:6978.1-6997.4"
+  attribute \src "ls180.v:7080.1-7099.4"
   wire $0\builder_comb_rhs_array_muxed27[0:0]
-  attribute \src "ls180.v:6998.1-7017.4"
+  attribute \src "ls180.v:7100.1-7119.4"
   wire $0\builder_comb_rhs_array_muxed28[0:0]
-  attribute \src "ls180.v:7018.1-7037.4"
+  attribute \src "ls180.v:7120.1-7139.4"
   wire $0\builder_comb_rhs_array_muxed29[0:0]
-  attribute \src "ls180.v:6550.1-6566.4"
+  attribute \src "ls180.v:6652.1-6668.4"
   wire width 2 $0\builder_comb_rhs_array_muxed2[1:0]
-  attribute \src "ls180.v:7038.1-7057.4"
+  attribute \src "ls180.v:7140.1-7159.4"
   wire width 3 $0\builder_comb_rhs_array_muxed30[2:0]
-  attribute \src "ls180.v:7058.1-7077.4"
+  attribute \src "ls180.v:7160.1-7179.4"
   wire width 2 $0\builder_comb_rhs_array_muxed31[1:0]
-  attribute \src "ls180.v:6567.1-6583.4"
+  attribute \src "ls180.v:6669.1-6685.4"
   wire $0\builder_comb_rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:6584.1-6600.4"
+  attribute \src "ls180.v:6686.1-6702.4"
   wire $0\builder_comb_rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:6601.1-6617.4"
+  attribute \src "ls180.v:6703.1-6719.4"
   wire $0\builder_comb_rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:6669.1-6685.4"
+  attribute \src "ls180.v:6771.1-6787.4"
   wire $0\builder_comb_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:6686.1-6702.4"
+  attribute \src "ls180.v:6788.1-6804.4"
   wire width 13 $0\builder_comb_rhs_array_muxed7[12:0]
-  attribute \src "ls180.v:6703.1-6719.4"
+  attribute \src "ls180.v:6805.1-6821.4"
   wire width 2 $0\builder_comb_rhs_array_muxed8[1:0]
-  attribute \src "ls180.v:6720.1-6736.4"
+  attribute \src "ls180.v:6822.1-6838.4"
   wire $0\builder_comb_rhs_array_muxed9[0:0]
-  attribute \src "ls180.v:6618.1-6634.4"
+  attribute \src "ls180.v:6720.1-6736.4"
   wire $0\builder_comb_t_array_muxed0[0:0]
-  attribute \src "ls180.v:6635.1-6651.4"
+  attribute \src "ls180.v:6737.1-6753.4"
   wire $0\builder_comb_t_array_muxed1[0:0]
-  attribute \src "ls180.v:6652.1-6668.4"
+  attribute \src "ls180.v:6754.1-6770.4"
   wire $0\builder_comb_t_array_muxed2[0:0]
-  attribute \src "ls180.v:6771.1-6787.4"
+  attribute \src "ls180.v:6873.1-6889.4"
   wire $0\builder_comb_t_array_muxed3[0:0]
-  attribute \src "ls180.v:6788.1-6804.4"
+  attribute \src "ls180.v:6890.1-6906.4"
   wire $0\builder_comb_t_array_muxed4[0:0]
-  attribute \src "ls180.v:6805.1-6821.4"
+  attribute \src "ls180.v:6907.1-6923.4"
   wire $0\builder_comb_t_array_muxed5[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\builder_converter0_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_converter0_state[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\builder_converter1_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_converter1_state[0:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\builder_converter2_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_converter2_state[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\builder_converter_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_converter_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 20 $0\builder_count[19:0]
-  attribute \src "ls180.v:5756.1-5767.4"
+  attribute \src "ls180.v:5858.1-5869.4"
   wire $0\builder_error[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_grant[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 14 $0\builder_libresocsim_adr[13:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire width 14 $0\builder_libresocsim_adr_next_value1[13:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire $0\builder_libresocsim_adr_next_value_ce1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\builder_libresocsim_dat_w[7:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_libresocsim_we[0:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire $0\builder_libresocsim_we_next_value2[0:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire $0\builder_libresocsim_we_next_value_ce2[0:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire $0\builder_libresocsim_wishbone_ack[0:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0]
-  attribute \src "ls180.v:1877.5-1877.44"
+  attribute \src "ls180.v:1922.5-1922.44"
   wire $0\builder_libresocsim_wishbone_err[0:0]
-  attribute \src "ls180.v:1766.5-1766.27"
+  attribute \src "ls180.v:1811.5-1811.27"
   wire $0\builder_locked0[0:0]
-  attribute \src "ls180.v:1767.5-1767.27"
+  attribute \src "ls180.v:1812.5-1812.27"
   wire $0\builder_locked1[0:0]
-  attribute \src "ls180.v:1768.5-1768.27"
+  attribute \src "ls180.v:1813.5-1813.27"
   wire $0\builder_locked2[0:0]
-  attribute \src "ls180.v:1769.5-1769.27"
+  attribute \src "ls180.v:1814.5-1814.27"
   wire $0\builder_locked3[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire width 3 $0\builder_multiplexer_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_multiplexer_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl0_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl0_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl10_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl10_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl11_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl11_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl12_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl12_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl13_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl13_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl14_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl14_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl15_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl15_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl16_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl16_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl1_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl1_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl2_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl2_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl3_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl3_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl4_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl4_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl5_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl5_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl6_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl6_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl7_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl7_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl8_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl8_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl9_regs0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_multiregimpl9_regs1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_new_master_rdata_valid0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_new_master_rdata_valid1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_new_master_rdata_valid2[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_new_master_rdata_valid3[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_new_master_wdata_ready[0:0]
-  attribute \src "ls180.v:5645.1-5681.4"
+  attribute \src "ls180.v:5720.1-5756.4"
   wire width 2 $0\builder_next_state[1:0]
-  attribute \src "ls180.v:3128.1-3158.4"
+  attribute \src "ls180.v:3203.1-3233.4"
   wire width 2 $0\builder_refresher_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_refresher_state[1:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire width 2 $0\builder_sdblock2memdma_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_sdblock2memdma_state[1:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_sdcore_crcupstreaminserter_state[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 3 $0\builder_sdcore_fsm_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_sdcore_fsm_state[2:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\builder_sdmem2blockdma_fsm_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_sdmem2blockdma_fsm_state[0:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire width 3 $0\builder_sdphy_fsm_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_sdphy_fsm_state[2:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\builder_sdphy_sdphycrcr_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_sdphy_sdphycrcr_state[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\builder_sdphy_sdphydatar_state[2:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\builder_sdphy_sdphyinit_next_state[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\builder_sdphy_sdphyinit_state[0:0]
-  attribute \src "ls180.v:5756.1-5767.4"
+  attribute \src "ls180.v:5858.1-5869.4"
   wire $0\builder_shared_ack[0:0]
-  attribute \src "ls180.v:5756.1-5767.4"
+  attribute \src "ls180.v:5858.1-5869.4"
   wire width 32 $0\builder_shared_dat_r[31:0]
-  attribute \src "ls180.v:5706.1-5713.4"
-  wire width 5 $0\builder_slave_sel[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
-  wire width 5 $0\builder_slave_sel_r[4:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:5781.1-5791.4"
+  wire width 8 $0\builder_slave_sel[7:0]
+  attribute \src "ls180.v:7529.1-10156.4"
+  wire width 8 $0\builder_slave_sel_r[7:0]
+  attribute \src "ls180.v:4304.1-4352.4"
   wire width 2 $0\builder_spimaster0_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_spimaster0_state[1:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire width 2 $0\builder_spimaster1_next_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_spimaster1_state[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\builder_state[1:0]
-  attribute \src "ls180.v:7197.1-7225.4"
+  attribute \src "ls180.v:7299.1-7327.4"
   wire $0\builder_sync_f_array_muxed0[0:0]
-  attribute \src "ls180.v:7226.1-7254.4"
+  attribute \src "ls180.v:7328.1-7356.4"
   wire $0\builder_sync_f_array_muxed1[0:0]
-  attribute \src "ls180.v:7078.1-7094.4"
+  attribute \src "ls180.v:7180.1-7196.4"
   wire width 2 $0\builder_sync_rhs_array_muxed0[1:0]
-  attribute \src "ls180.v:7095.1-7111.4"
+  attribute \src "ls180.v:7197.1-7213.4"
   wire width 13 $0\builder_sync_rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:7112.1-7128.4"
+  attribute \src "ls180.v:7214.1-7230.4"
   wire $0\builder_sync_rhs_array_muxed2[0:0]
-  attribute \src "ls180.v:7129.1-7145.4"
+  attribute \src "ls180.v:7231.1-7247.4"
   wire $0\builder_sync_rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:7146.1-7162.4"
+  attribute \src "ls180.v:7248.1-7264.4"
   wire $0\builder_sync_rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:7163.1-7179.4"
+  attribute \src "ls180.v:7265.1-7281.4"
   wire $0\builder_sync_rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:7180.1-7196.4"
+  attribute \src "ls180.v:7282.1-7298.4"
   wire $0\builder_sync_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_cmd_consumed[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_converter_counter[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_converter_counter_converter_next_value[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_converter_counter_converter_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_converter_dat_r[31:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_converter_skip[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 16 $0\main_dfi_p0_rddata[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_dfi_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 24 $0\main_dummy[23:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_gpio_oe_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_gpio_oe_storage[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_gpio_out_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_gpio_out_storage[15:0]
-  attribute \src "ls180.v:7312.1-7330.4"
+  attribute \src "ls180.v:7414.1-7432.4"
   wire width 16 $0\main_gpio_status[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_i2c_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_i2c_storage[2:0]
-  attribute \src "ls180.v:7351.1-7353.4"
+  attribute \src "ls180.v:7453.1-7455.4"
   wire $0\main_int_rst[0:0]
-  attribute \src "ls180.v:1554.11-1554.41"
+  attribute \src "ls180.v:1599.11-1599.41"
   wire width 2 $0\main_interface0_bus_bte[1:0]
-  attribute \src "ls180.v:1553.11-1553.41"
+  attribute \src "ls180.v:1598.11-1598.41"
   wire width 3 $0\main_interface0_bus_cti[2:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:7529.1-10156.4"
+  wire $0\main_interface0_ram_bus_ack[0:0]
+  attribute \src "ls180.v:255.5-255.39"
+  wire $0\main_interface0_ram_bus_err[0:0]
+  attribute \src "ls180.v:5589.1-5626.4"
   wire width 32 $0\main_interface1_bus_adr[31:0]
-  attribute \src "ls180.v:1645.11-1645.41"
+  attribute \src "ls180.v:1690.11-1690.41"
   wire width 2 $0\main_interface1_bus_bte[1:0]
-  attribute \src "ls180.v:1644.11-1644.41"
+  attribute \src "ls180.v:1689.11-1689.41"
   wire width 3 $0\main_interface1_bus_cti[2:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_interface1_bus_cyc[0:0]
-  attribute \src "ls180.v:1637.12-1637.45"
+  attribute \src "ls180.v:1682.12-1682.45"
   wire width 32 $0\main_interface1_bus_dat_w[31:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire width 4 $0\main_interface1_bus_sel[3:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_interface1_bus_stb[0:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_interface1_bus_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
+  wire $0\main_interface1_ram_bus_ack[0:0]
+  attribute \src "ls180.v:270.5-270.39"
+  wire $0\main_interface1_ram_bus_err[0:0]
+  attribute \src "ls180.v:7529.1-10156.4"
+  wire $0\main_interface2_ram_bus_ack[0:0]
+  attribute \src "ls180.v:285.5-285.39"
+  wire $0\main_interface2_ram_bus_err[0:0]
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_bus_errors[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_converter0_counter[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 64 $0\main_libresocsim_converter0_dat_r[63:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_converter0_skip[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_converter1_counter[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 64 $0\main_libresocsim_converter1_dat_r[63:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_converter1_skip[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_converter2_counter[0:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 64 $0\main_libresocsim_converter2_dat_r[63:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_converter2_skip[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_en_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_en_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_eventmanager_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_eventmanager_storage[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0]
   attribute \src "ls180.v:167.11-167.69"
   wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0]
   attribute \src "ls180.v:166.11-166.69"
   wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0]
-  attribute \src "ls180.v:2774.1-2784.4"
+  attribute \src "ls180.v:2819.1-2829.4"
   wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_interface0_converted_interface_stb[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_interface0_converted_interface_we[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0]
   attribute \src "ls180.v:182.11-182.69"
   wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0]
   attribute \src "ls180.v:181.11-181.69"
   wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0]
-  attribute \src "ls180.v:2834.1-2844.4"
+  attribute \src "ls180.v:2879.1-2889.4"
   wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_interface1_converted_interface_stb[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_interface1_converted_interface_we[0:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0]
   attribute \src "ls180.v:197.11-197.69"
   wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0]
   attribute \src "ls180.v:196.11-196.69"
   wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0]
-  attribute \src "ls180.v:2894.1-2904.4"
+  attribute \src "ls180.v:2939.1-2949.4"
   wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
-  attribute \src "ls180.v:2846.1-2892.4"
+  attribute \src "ls180.v:2891.1-2937.4"
   wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
   attribute \src "ls180.v:74.5-74.46"
   wire $0\main_libresocsim_libresoc_dbus_err[0:0]
-  attribute \src "ls180.v:2786.1-2832.4"
+  attribute \src "ls180.v:2831.1-2877.4"
   wire $0\main_libresocsim_libresoc_ibus_ack[0:0]
   attribute \src "ls180.v:83.5-83.46"
   wire $0\main_libresocsim_libresoc_ibus_err[0:0]
-  attribute \src "ls180.v:2767.1-2772.4"
+  attribute \src "ls180.v:2812.1-2817.4"
   wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0]
-  attribute \src "ls180.v:2906.1-2952.4"
+  attribute \src "ls180.v:2951.1-2997.4"
   wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
   attribute \src "ls180.v:114.5-114.49"
   wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_load_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_load_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_ram_bus_ack[0:0]
   attribute \src "ls180.v:213.5-213.40"
   wire $0\main_libresocsim_ram_bus_err[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_reload_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_reload_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_reset_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_reset_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_scratch_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_scratch_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_update_value_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_update_value_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_value[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_libresocsim_value_status[31:0]
-  attribute \src "ls180.v:2955.1-2961.4"
+  attribute \src "ls180.v:3000.1-3006.4"
   wire width 4 $0\main_libresocsim_we[3:0]
-  attribute \src "ls180.v:2967.1-2972.4"
+  attribute \src "ls180.v:3012.1-3017.4"
   wire $0\main_libresocsim_zero_clear[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_zero_old_trigger[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_libresocsim_zero_pending[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire width 30 $0\main_litedram_wb_adr[29:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_litedram_wb_cyc[0:0]
-  attribute \src "ls180.v:4027.1-4037.4"
+  attribute \src "ls180.v:4102.1-4112.4"
   wire width 16 $0\main_litedram_wb_dat_w[15:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire width 2 $0\main_litedram_wb_sel[1:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_litedram_wb_stb[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_litedram_wb_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm0_counter[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm0_enable_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm0_enable_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm0_period_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm0_period_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm0_width_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm0_width_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm1_counter[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm1_enable_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm1_enable_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm1_period_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm1_period_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_pwm1_width_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_pwm1_width_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_rddata_en[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdblock2mem_converter_demux[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_converter_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_converter_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_converter_strobe_all[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_sdblock2mem_fifo_consume[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 6 $0\main_sdblock2mem_fifo_level[5:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_sdblock2mem_fifo_produce[4:0]
-  attribute \src "ls180.v:1578.5-1578.41"
+  attribute \src "ls180.v:1623.5-1623.41"
   wire $0\main_sdblock2mem_fifo_replace[0:0]
-  attribute \src "ls180.v:5422.1-5429.4"
+  attribute \src "ls180.v:5497.1-5504.4"
   wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire $0\main_sdblock2mem_sink_sink_valid1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
-  attribute \src "ls180.v:5455.1-5494.4"
+  attribute \src "ls180.v:5530.1-5569.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_block_count_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdcore_block_count_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_block_length_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 10 $0\main_sdcore_block_length_storage[9:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_cmd_argument_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdcore_cmd_argument_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_cmd_command_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdcore_cmd_command_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdcore_cmd_count[2:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_cmd_done[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_cmd_error[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 128 $0\main_sdcore_cmd_response_status[127:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
-  attribute \src "ls180.v:1387.5-1387.34"
+  attribute \src "ls180.v:1432.5-1432.34"
   wire $0\main_sdcore_cmd_send_w[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_cmd_timeout[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0]
-  attribute \src "ls180.v:5110.1-5117.4"
+  attribute \src "ls180.v:5185.1-5192.4"
   wire $0\main_sdcore_crc16_checker_crc0_clr[0:0]
-  attribute \src "ls180.v:5166.1-5173.4"
+  attribute \src "ls180.v:5241.1-5248.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
-  attribute \src "ls180.v:5120.1-5127.4"
+  attribute \src "ls180.v:5195.1-5202.4"
   wire $0\main_sdcore_crc16_checker_crc1_clr[0:0]
-  attribute \src "ls180.v:5176.1-5183.4"
+  attribute \src "ls180.v:5251.1-5258.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
-  attribute \src "ls180.v:5130.1-5137.4"
+  attribute \src "ls180.v:5205.1-5212.4"
   wire $0\main_sdcore_crc16_checker_crc2_clr[0:0]
-  attribute \src "ls180.v:5186.1-5193.4"
+  attribute \src "ls180.v:5261.1-5268.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
-  attribute \src "ls180.v:5140.1-5147.4"
+  attribute \src "ls180.v:5215.1-5222.4"
   wire $0\main_sdcore_crc16_checker_crc3_clr[0:0]
-  attribute \src "ls180.v:5196.1-5203.4"
+  attribute \src "ls180.v:5271.1-5278.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_crc16_checker_sink_first[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_crc16_checker_sink_last[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0]
-  attribute \src "ls180.v:5155.1-5162.4"
+  attribute \src "ls180.v:5230.1-5237.4"
   wire $0\main_sdcore_crc16_checker_sink_ready[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_crc16_checker_sink_valid[0:0]
-  attribute \src "ls180.v:1493.5-1493.50"
+  attribute \src "ls180.v:1538.5-1538.50"
   wire $0\main_sdcore_crc16_checker_source_first[0:0]
-  attribute \src "ls180.v:5149.1-5154.4"
+  attribute \src "ls180.v:5224.1-5229.4"
   wire $0\main_sdcore_crc16_checker_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdcore_crc16_checker_val[7:0]
-  attribute \src "ls180.v:5102.1-5107.4"
+  attribute \src "ls180.v:5177.1-5182.4"
   wire $0\main_sdcore_crc16_checker_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
-  attribute \src "ls180.v:4984.1-4991.4"
+  attribute \src "ls180.v:5059.1-5066.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
-  attribute \src "ls180.v:4994.1-5001.4"
+  attribute \src "ls180.v:5069.1-5076.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
-  attribute \src "ls180.v:5004.1-5011.4"
+  attribute \src "ls180.v:5079.1-5086.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
-  attribute \src "ls180.v:5014.1-5021.4"
+  attribute \src "ls180.v:5089.1-5096.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_sink_ready[0:0]
-  attribute \src "ls180.v:1450.5-1450.51"
+  attribute \src "ls180.v:1495.5-1495.51"
   wire $0\main_sdcore_crc16_inserter_source_first[0:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_source_last[0:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_crc16_inserter_source_ready[0:0]
-  attribute \src "ls180.v:5022.1-5101.4"
+  attribute \src "ls180.v:5097.1-5176.4"
   wire $0\main_sdcore_crc16_inserter_source_valid[0:0]
-  attribute \src "ls180.v:4962.1-4969.4"
+  attribute \src "ls180.v:5037.1-5044.4"
   wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdcore_data_count[31:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_data_done[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_data_error[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdcore_data_timeout[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdmem2block_converter_mux[1:0]
-  attribute \src "ls180.v:5600.1-5616.4"
+  attribute \src "ls180.v:5675.1-5691.4"
   wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_base_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 64 $0\main_sdmem2block_dma_base_storage[63:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdmem2block_dma_data[31:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire $0\main_sdmem2block_dma_done_status[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_enable_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_enable_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_length_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdmem2block_dma_length_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_loop_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdmem2block_dma_loop_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdmem2block_dma_offset[31:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire $0\main_sdmem2block_dma_sink_last[0:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_sdmem2block_dma_sink_ready[0:0]
-  attribute \src "ls180.v:5552.1-5588.4"
+  attribute \src "ls180.v:5627.1-5663.4"
   wire $0\main_sdmem2block_dma_sink_valid[0:0]
-  attribute \src "ls180.v:1658.5-1658.45"
+  attribute \src "ls180.v:1703.5-1703.45"
   wire $0\main_sdmem2block_dma_source_first[0:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_sdmem2block_dma_source_last[0:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0]
-  attribute \src "ls180.v:5514.1-5551.4"
+  attribute \src "ls180.v:5589.1-5626.4"
   wire $0\main_sdmem2block_dma_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_sdmem2block_fifo_consume[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 6 $0\main_sdmem2block_fifo_level[5:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_sdmem2block_fifo_produce[4:0]
-  attribute \src "ls180.v:1714.5-1714.41"
+  attribute \src "ls180.v:1759.5-1759.41"
   wire $0\main_sdmem2block_fifo_replace[0:0]
-  attribute \src "ls180.v:5630.1-5637.4"
+  attribute \src "ls180.v:5705.1-5712.4"
   wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_clocker_clk0[0:0]
-  attribute \src "ls180.v:4368.1-4396.4"
+  attribute \src "ls180.v:4443.1-4471.4"
   wire $0\main_sdphy_clocker_clk1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_clocker_clk_d[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 9 $0\main_sdphy_clocker_clks[8:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_clocker_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 9 $0\main_sdphy_clocker_storage[8:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
-  attribute \src "ls180.v:1179.5-1179.53"
+  attribute \src "ls180.v:1224.5-1224.53"
   wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
-  attribute \src "ls180.v:1180.5-1180.52"
+  attribute \src "ls180.v:1225.5-1225.52"
   wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1160.5-1160.46"
+  attribute \src "ls180.v:1205.5-1205.46"
   wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_reset[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_cmdr_cmdr_run[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_cmdr_count[7:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
-  attribute \src "ls180.v:1133.5-1133.49"
+  attribute \src "ls180.v:1178.5-1178.49"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
-  attribute \src "ls180.v:1134.5-1134.48"
+  attribute \src "ls180.v:1179.5-1179.48"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
-  attribute \src "ls180.v:1135.5-1135.55"
+  attribute \src "ls180.v:1180.5-1180.55"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
-  attribute \src "ls180.v:1137.5-1137.57"
+  attribute \src "ls180.v:1182.5-1182.57"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1138.5-1138.58"
+  attribute \src "ls180.v:1183.5-1183.58"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1140.11-1140.64"
+  attribute \src "ls180.v:1185.11-1185.64"
   wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
-  attribute \src "ls180.v:1141.5-1141.59"
+  attribute \src "ls180.v:1186.5-1186.59"
   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1146.11-1146.57"
+  attribute \src "ls180.v:1191.11-1191.57"
   wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:1147.5-1147.52"
+  attribute \src "ls180.v:1192.5-1192.52"
   wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_cmdr_sink_last[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_sink_ready[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_cmdr_sink_valid[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_source_last[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_cmdr_source_ready[0:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdphy_cmdr_timeout[31:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
-  attribute \src "ls180.v:4542.1-4635.4"
+  attribute \src "ls180.v:4617.1-4710.4"
   wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_cmdw_count[7:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_done[0:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1123.11-1123.57"
+  attribute \src "ls180.v:1168.11-1168.57"
   wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:1124.5-1124.52"
+  attribute \src "ls180.v:1169.5-1169.52"
   wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_cmdw_sink_last[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0]
-  attribute \src "ls180.v:4432.1-4508.4"
+  attribute \src "ls180.v:4507.1-4583.4"
   wire $0\main_sdphy_cmdw_sink_ready[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_cmdw_sink_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 10 $0\main_sdphy_datar_count[9:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_buf_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_buf_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_buf_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_converter_demux[0:0]
-  attribute \src "ls180.v:1335.5-1335.55"
+  attribute \src "ls180.v:1380.5-1380.55"
   wire $0\main_sdphy_datar_datar_converter_sink_first[0:0]
-  attribute \src "ls180.v:1336.5-1336.54"
+  attribute \src "ls180.v:1381.5-1381.54"
   wire $0\main_sdphy_datar_datar_converter_sink_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_converter_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_converter_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1316.5-1316.48"
+  attribute \src "ls180.v:1361.5-1361.48"
   wire $0\main_sdphy_datar_datar_pads_in_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_reset[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_datar_datar_run[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_datar_source_source_ready0[0:0]
-  attribute \src "ls180.v:1287.5-1287.50"
+  attribute \src "ls180.v:1332.5-1332.50"
   wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
-  attribute \src "ls180.v:1288.5-1288.49"
+  attribute \src "ls180.v:1333.5-1333.49"
   wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
-  attribute \src "ls180.v:1289.5-1289.56"
+  attribute \src "ls180.v:1334.5-1334.56"
   wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
-  attribute \src "ls180.v:1291.5-1291.58"
+  attribute \src "ls180.v:1336.5-1336.58"
   wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1292.5-1292.59"
+  attribute \src "ls180.v:1337.5-1337.59"
   wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1294.11-1294.65"
+  attribute \src "ls180.v:1339.11-1339.65"
   wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
-  attribute \src "ls180.v:1295.5-1295.60"
+  attribute \src "ls180.v:1340.5-1340.60"
   wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1298.5-1298.51"
+  attribute \src "ls180.v:1343.5-1343.51"
   wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1299.5-1299.52"
+  attribute \src "ls180.v:1344.5-1344.52"
   wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1300.11-1300.58"
+  attribute \src "ls180.v:1345.11-1345.58"
   wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:1301.5-1301.53"
+  attribute \src "ls180.v:1346.5-1346.53"
   wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_datar_sink_last[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_sink_ready[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_datar_sink_valid[0:0]
-  attribute \src "ls180.v:1308.5-1308.41"
+  attribute \src "ls180.v:1353.5-1353.41"
   wire $0\main_sdphy_datar_source_first[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_source_last[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire width 8 $0\main_sdphy_datar_source_payload_data[7:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire width 3 $0\main_sdphy_datar_source_payload_status[2:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_datar_source_ready[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_source_valid[0:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_stop[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_sdphy_datar_timeout[31:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
-  attribute \src "ls180.v:4803.1-4904.4"
+  attribute \src "ls180.v:4878.1-4979.4"
   wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_dataw_count[7:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0]
-  attribute \src "ls180.v:1257.5-1257.54"
+  attribute \src "ls180.v:1302.5-1302.54"
   wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
-  attribute \src "ls180.v:1258.5-1258.53"
+  attribute \src "ls180.v:1303.5-1303.53"
   wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1238.5-1238.47"
+  attribute \src "ls180.v:1283.5-1283.47"
   wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_reset[0:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdphy_dataw_crcr_run[0:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\main_sdphy_dataw_error[0:0]
-  attribute \src "ls180.v:1225.5-1225.50"
+  attribute \src "ls180.v:1270.5-1270.50"
   wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
-  attribute \src "ls180.v:1226.5-1226.49"
+  attribute \src "ls180.v:1271.5-1271.49"
   wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
-  attribute \src "ls180.v:1227.5-1227.56"
+  attribute \src "ls180.v:1272.5-1272.56"
   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
-  attribute \src "ls180.v:1228.5-1228.58"
+  attribute \src "ls180.v:1273.5-1273.58"
   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
-  attribute \src "ls180.v:1229.5-1229.58"
+  attribute \src "ls180.v:1274.5-1274.58"
   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1230.5-1230.59"
+  attribute \src "ls180.v:1275.5-1275.59"
   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1231.11-1231.65"
+  attribute \src "ls180.v:1276.11-1276.65"
   wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
-  attribute \src "ls180.v:1232.11-1232.65"
+  attribute \src "ls180.v:1277.11-1277.65"
   wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
-  attribute \src "ls180.v:1233.5-1233.60"
+  attribute \src "ls180.v:1278.5-1278.60"
   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
-  attribute \src "ls180.v:1223.5-1223.50"
+  attribute \src "ls180.v:1268.5-1268.50"
   wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1212.5-1212.51"
+  attribute \src "ls180.v:1257.5-1257.51"
   wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1213.5-1213.52"
+  attribute \src "ls180.v:1258.5-1258.52"
   wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_dataw_sink_first[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_dataw_sink_last[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_sink_ready[0:0]
-  attribute \src "ls180.v:5204.1-5394.4"
+  attribute \src "ls180.v:5279.1-5469.4"
   wire $0\main_sdphy_dataw_sink_valid[0:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_start[0:0]
-  attribute \src "ls180.v:4697.1-4769.4"
+  attribute \src "ls180.v:4772.1-4844.4"
   wire $0\main_sdphy_dataw_stop[0:0]
-  attribute \src "ls180.v:4669.1-4696.4"
+  attribute \src "ls180.v:4744.1-4771.4"
   wire $0\main_sdphy_dataw_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_sdphy_init_count[7:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
-  attribute \src "ls180.v:1105.5-1105.40"
+  attribute \src "ls180.v:1150.5-1150.40"
   wire $0\main_sdphy_init_initialize_w[0:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\main_sdphy_init_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:4398.1-4431.4"
+  attribute \src "ls180.v:4473.1-4506.4"
   wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\main_sdphy_sdpads_cmd_i[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 4 $0\main_sdphy_sdpads_data_i[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_address_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_address_storage[12:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_baddress_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdram_baddress_storage[1:0]
-  attribute \src "ls180.v:3184.1-3191.4"
+  attribute \src "ls180.v:3259.1-3266.4"
   wire $0\main_sdram_bankmachine0_auto_precharge[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:445.5-445.64"
+  attribute \src "ls180.v:490.5-490.64"
   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:428.5-428.67"
+  attribute \src "ls180.v:473.5-473.67"
   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:429.5-429.66"
+  attribute \src "ls180.v:474.5-474.66"
   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:3206.1-3213.4"
+  attribute \src "ls180.v:3281.1-3288.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:3173.1-3180.4"
+  attribute \src "ls180.v:3248.1-3255.4"
   wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3871.1-3879.4"
+  attribute \src "ls180.v:3946.1-3954.4"
   wire $0\main_sdram_bankmachine0_cmd_ready[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_cmd_valid[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_refresh_gnt[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_bankmachine0_row[12:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_row_close[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:3222.1-3315.4"
+  attribute \src "ls180.v:3297.1-3390.4"
   wire $0\main_sdram_bankmachine0_row_open[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_row_opened[0:0]
-  attribute \src "ls180.v:487.32-487.76"
+  attribute \src "ls180.v:532.32-532.76"
   wire $0\main_sdram_bankmachine0_trascon_ready[0:0]
-  attribute \src "ls180.v:485.32-485.75"
+  attribute \src "ls180.v:530.32-530.75"
   wire $0\main_sdram_bankmachine0_trccon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
-  attribute \src "ls180.v:3341.1-3348.4"
+  attribute \src "ls180.v:3416.1-3423.4"
   wire $0\main_sdram_bankmachine1_auto_precharge[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:527.5-527.64"
+  attribute \src "ls180.v:572.5-572.64"
   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:510.5-510.67"
+  attribute \src "ls180.v:555.5-555.67"
   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:511.5-511.66"
+  attribute \src "ls180.v:556.5-556.66"
   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:3363.1-3370.4"
+  attribute \src "ls180.v:3438.1-3445.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:3330.1-3337.4"
+  attribute \src "ls180.v:3405.1-3412.4"
   wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3880.1-3888.4"
+  attribute \src "ls180.v:3955.1-3963.4"
   wire $0\main_sdram_bankmachine1_cmd_ready[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_cmd_valid[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_refresh_gnt[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_bankmachine1_row[12:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_row_close[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:3379.1-3472.4"
+  attribute \src "ls180.v:3454.1-3547.4"
   wire $0\main_sdram_bankmachine1_row_open[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_row_opened[0:0]
-  attribute \src "ls180.v:569.32-569.76"
+  attribute \src "ls180.v:614.32-614.76"
   wire $0\main_sdram_bankmachine1_trascon_ready[0:0]
-  attribute \src "ls180.v:567.32-567.75"
+  attribute \src "ls180.v:612.32-612.75"
   wire $0\main_sdram_bankmachine1_trccon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
-  attribute \src "ls180.v:3498.1-3505.4"
+  attribute \src "ls180.v:3573.1-3580.4"
   wire $0\main_sdram_bankmachine2_auto_precharge[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:609.5-609.64"
+  attribute \src "ls180.v:654.5-654.64"
   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:592.5-592.67"
+  attribute \src "ls180.v:637.5-637.67"
   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:593.5-593.66"
+  attribute \src "ls180.v:638.5-638.66"
   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:3520.1-3527.4"
+  attribute \src "ls180.v:3595.1-3602.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:3487.1-3494.4"
+  attribute \src "ls180.v:3562.1-3569.4"
   wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3889.1-3897.4"
+  attribute \src "ls180.v:3964.1-3972.4"
   wire $0\main_sdram_bankmachine2_cmd_ready[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_cmd_valid[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_refresh_gnt[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_bankmachine2_row[12:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_row_close[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:3536.1-3629.4"
+  attribute \src "ls180.v:3611.1-3704.4"
   wire $0\main_sdram_bankmachine2_row_open[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_row_opened[0:0]
-  attribute \src "ls180.v:651.32-651.76"
+  attribute \src "ls180.v:696.32-696.76"
   wire $0\main_sdram_bankmachine2_trascon_ready[0:0]
-  attribute \src "ls180.v:649.32-649.75"
+  attribute \src "ls180.v:694.32-694.75"
   wire $0\main_sdram_bankmachine2_trccon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
-  attribute \src "ls180.v:3655.1-3662.4"
+  attribute \src "ls180.v:3730.1-3737.4"
   wire $0\main_sdram_bankmachine3_auto_precharge[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:691.5-691.64"
+  attribute \src "ls180.v:736.5-736.64"
   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:674.5-674.67"
+  attribute \src "ls180.v:719.5-719.67"
   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:675.5-675.66"
+  attribute \src "ls180.v:720.5-720.66"
   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:3677.1-3684.4"
+  attribute \src "ls180.v:3752.1-3759.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:3644.1-3651.4"
+  attribute \src "ls180.v:3719.1-3726.4"
   wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3898.1-3906.4"
+  attribute \src "ls180.v:3973.1-3981.4"
   wire $0\main_sdram_bankmachine3_cmd_ready[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_cmd_valid[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_refresh_gnt[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_bankmachine3_row[12:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_row_close[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:3693.1-3786.4"
+  attribute \src "ls180.v:3768.1-3861.4"
   wire $0\main_sdram_bankmachine3_row_open[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_row_opened[0:0]
-  attribute \src "ls180.v:733.32-733.76"
+  attribute \src "ls180.v:778.32-778.76"
   wire $0\main_sdram_bankmachine3_trascon_ready[0:0]
-  attribute \src "ls180.v:731.32-731.75"
+  attribute \src "ls180.v:776.32-776.75"
   wire $0\main_sdram_bankmachine3_trccon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
-  attribute \src "ls180.v:3820.1-3825.4"
+  attribute \src "ls180.v:3895.1-3900.4"
   wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3826.1-3831.4"
+  attribute \src "ls180.v:3901.1-3906.4"
   wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3832.1-3837.4"
+  attribute \src "ls180.v:3907.1-3912.4"
   wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
-  attribute \src "ls180.v:741.5-741.43"
+  attribute \src "ls180.v:786.5-786.43"
   wire $0\main_sdram_choose_cmd_cmd_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdram_choose_cmd_grant[1:0]
-  attribute \src "ls180.v:3806.1-3812.4"
+  attribute \src "ls180.v:3881.1-3887.4"
   wire width 4 $0\main_sdram_choose_cmd_valids[3:0]
-  attribute \src "ls180.v:739.5-739.48"
+  attribute \src "ls180.v:784.5-784.48"
   wire $0\main_sdram_choose_cmd_want_activates[0:0]
-  attribute \src "ls180.v:738.5-738.43"
+  attribute \src "ls180.v:783.5-783.43"
   wire $0\main_sdram_choose_cmd_want_cmds[0:0]
-  attribute \src "ls180.v:736.5-736.44"
+  attribute \src "ls180.v:781.5-781.44"
   wire $0\main_sdram_choose_cmd_want_reads[0:0]
-  attribute \src "ls180.v:737.5-737.45"
+  attribute \src "ls180.v:782.5-782.45"
   wire $0\main_sdram_choose_cmd_want_writes[0:0]
-  attribute \src "ls180.v:3853.1-3858.4"
+  attribute \src "ls180.v:3928.1-3933.4"
   wire $0\main_sdram_choose_req_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:3859.1-3864.4"
+  attribute \src "ls180.v:3934.1-3939.4"
   wire $0\main_sdram_choose_req_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:3865.1-3870.4"
+  attribute \src "ls180.v:3940.1-3945.4"
   wire $0\main_sdram_choose_req_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_choose_req_cmd_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdram_choose_req_grant[1:0]
-  attribute \src "ls180.v:3839.1-3845.4"
+  attribute \src "ls180.v:3914.1-3920.4"
   wire width 4 $0\main_sdram_choose_req_valids[3:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_choose_req_want_activates[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_choose_req_want_reads[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_choose_req_want_writes[0:0]
-  attribute \src "ls180.v:3128.1-3158.4"
+  attribute \src "ls180.v:3203.1-3233.4"
   wire $0\main_sdram_cmd_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_cmd_payload_a[12:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdram_cmd_payload_ba[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:389.5-389.42"
+  attribute \src "ls180.v:434.5-434.42"
   wire $0\main_sdram_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:390.5-390.43"
+  attribute \src "ls180.v:435.5-435.43"
   wire $0\main_sdram_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_cmd_payload_we[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_cmd_ready[0:0]
-  attribute \src "ls180.v:3128.1-3158.4"
+  attribute \src "ls180.v:3203.1-3233.4"
   wire $0\main_sdram_cmd_valid[0:0]
-  attribute \src "ls180.v:325.5-325.38"
+  attribute \src "ls180.v:370.5-370.38"
   wire $0\main_sdram_command_issue_w[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_command_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 6 $0\main_sdram_command_storage[5:0]
-  attribute \src "ls180.v:374.5-374.35"
+  attribute \src "ls180.v:419.5-419.35"
   wire $0\main_sdram_dfi_p0_act_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 13 $0\main_sdram_dfi_p0_address[12:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_sdram_dfi_p0_bank[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_cas_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_cs_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_ras_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_rddata_en[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_we_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_dfi_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_en0[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire $0\main_sdram_en1[0:0]
-  attribute \src "ls180.v:4007.1-4020.4"
+  attribute \src "ls180.v:4082.1-4095.4"
   wire width 16 $0\main_sdram_interface_wdata[15:0]
-  attribute \src "ls180.v:4007.1-4020.4"
+  attribute \src "ls180.v:4082.1-4095.4"
   wire width 2 $0\main_sdram_interface_wdata_we[1:0]
-  attribute \src "ls180.v:275.5-275.36"
+  attribute \src "ls180.v:320.5-320.36"
   wire $0\main_sdram_inti_p0_act_n[0:0]
-  attribute \src "ls180.v:3069.1-3085.4"
+  attribute \src "ls180.v:3144.1-3160.4"
   wire $0\main_sdram_inti_p0_cas_n[0:0]
-  attribute \src "ls180.v:3069.1-3085.4"
+  attribute \src "ls180.v:3144.1-3160.4"
   wire $0\main_sdram_inti_p0_cs_n[0:0]
-  attribute \src "ls180.v:3069.1-3085.4"
+  attribute \src "ls180.v:3144.1-3160.4"
   wire $0\main_sdram_inti_p0_ras_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 16 $0\main_sdram_inti_p0_rddata[15:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_inti_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:3069.1-3085.4"
+  attribute \src "ls180.v:3144.1-3160.4"
   wire $0\main_sdram_inti_p0_we_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_act_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 13 $0\main_sdram_master_p0_address[12:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 2 $0\main_sdram_master_p0_bank[1:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_cas_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_cke[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_cs_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_odt[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_ras_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_rddata_en[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_reset_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_we_n[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 16 $0\main_sdram_master_p0_wrdata[15:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_master_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0]
-  attribute \src "ls180.v:772.12-772.36"
+  attribute \src "ls180.v:817.12-817.36"
   wire width 13 $0\main_sdram_nop_a[12:0]
-  attribute \src "ls180.v:773.11-773.35"
+  attribute \src "ls180.v:818.11-818.35"
   wire width 2 $0\main_sdram_nop_ba[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_postponer_count[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_postponer_req_o[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_sequencer_count[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_sequencer_counter[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_sequencer_done1[0:0]
-  attribute \src "ls180.v:3128.1-3158.4"
+  attribute \src "ls180.v:3203.1-3233.4"
   wire $0\main_sdram_sequencer_start0[0:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire width 16 $0\main_sdram_slave_p0_rddata[15:0]
-  attribute \src "ls180.v:3011.1-3065.4"
+  attribute \src "ls180.v:3086.1-3140.4"
   wire $0\main_sdram_slave_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdram_status[15:0]
-  attribute \src "ls180.v:775.5-775.31"
+  attribute \src "ls180.v:820.5-820.31"
   wire $0\main_sdram_steerer0[0:0]
-  attribute \src "ls180.v:776.5-776.31"
+  attribute \src "ls180.v:821.5-821.31"
   wire $0\main_sdram_steerer1[0:0]
-  attribute \src "ls180.v:3911.1-3983.4"
+  attribute \src "ls180.v:3986.1-4058.4"
   wire width 2 $0\main_sdram_steerer_sel[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_storage[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_tccdcon_count[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_tccdcon_ready[0:0]
-  attribute \src "ls180.v:780.32-780.63"
+  attribute \src "ls180.v:825.32-825.63"
   wire $0\main_sdram_tfawcon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_sdram_time0[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_sdram_time1[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 10 $0\main_sdram_timer_count1[9:0]
-  attribute \src "ls180.v:778.32-778.63"
+  attribute \src "ls180.v:823.32-823.63"
   wire $0\main_sdram_trrdcon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_sdram_twtrcon_count[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_twtrcon_ready[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_sdram_wrdata_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_sdram_wrdata_storage[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_spimaster11_storage[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster12_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spimaster16_storage[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster17_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster1_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_spimaster1_storage[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster21_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster22_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster23_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spimaster24_re[0:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster25_clk_enable[0:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster26_cs_enable[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_spimaster27_count[2:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster28_mosi_latch[0:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster29_miso_latch[0:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster2_done[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_spimaster30_clk_divider[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spimaster33_mosi_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_spimaster34_mosi_sel[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spimaster35_miso_data[7:0]
-  attribute \src "ls180.v:4229.1-4277.4"
+  attribute \src "ls180.v:4304.1-4352.4"
   wire $0\main_spimaster3_irq[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spimaster5_miso[7:0]
-  attribute \src "ls180.v:996.12-996.47"
+  attribute \src "ls180.v:1041.12-1041.47"
   wire width 16 $0\main_spimaster8_clk_divider[15:0]
-  attribute \src "ls180.v:6281.1-6286.4"
+  attribute \src "ls180.v:6383.1-6388.4"
   wire $0\main_spimaster9_start[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_spisdcard_clk_divider1[15:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_clk_enable[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_control_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 16 $0\main_spisdcard_control_storage[15:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_spisdcard_count[2:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_cs_enable[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_cs_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_cs_storage[0:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_done0[0:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_irq[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_loopback_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_loopback_storage[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spisdcard_miso[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spisdcard_miso_data[7:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_miso_latch[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spisdcard_mosi_data[7:0]
-  attribute \src "ls180.v:4288.1-4336.4"
+  attribute \src "ls180.v:4363.1-4411.4"
   wire $0\main_spisdcard_mosi_latch[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_spisdcard_mosi_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 3 $0\main_spisdcard_mosi_sel[2:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_spisdcard_mosi_storage[7:0]
-  attribute \src "ls180.v:6327.1-6332.4"
+  attribute \src "ls180.v:6429.1-6434.4"
   wire $0\main_spisdcard_start1[0:0]
-  attribute \src "ls180.v:4147.1-4151.4"
+  attribute \src "ls180.v:3021.1-3027.4"
+  wire width 4 $0\main_sram0_we[3:0]
+  attribute \src "ls180.v:3031.1-3037.4"
+  wire width 4 $0\main_sram1_we[3:0]
+  attribute \src "ls180.v:3041.1-3047.4"
+  wire width 4 $0\main_sram2_we[3:0]
+  attribute \src "ls180.v:4222.1-4226.4"
   wire width 2 $0\main_uart_eventmanager_pending_w[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_eventmanager_re[0:0]
-  attribute \src "ls180.v:4136.1-4140.4"
+  attribute \src "ls180.v:4211.1-4215.4"
   wire width 2 $0\main_uart_eventmanager_status_w[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\main_uart_eventmanager_storage[1:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_re[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_phy_rx_bitcount[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_rx_busy[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_rx_r[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_uart_phy_rx_reg[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_sink_ready[0:0]
-  attribute \src "ls180.v:851.5-851.38"
+  attribute \src "ls180.v:896.5-896.38"
   wire $0\main_uart_phy_source_first[0:0]
-  attribute \src "ls180.v:852.5-852.37"
+  attribute \src "ls180.v:897.5-897.37"
   wire $0\main_uart_phy_source_last[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_uart_phy_source_payload_data[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_source_valid[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 32 $0\main_uart_phy_storage[31:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_phy_tx_bitcount[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_tx_busy[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 8 $0\main_uart_phy_tx_reg[7:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_uart_clk_rxen[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_phy_uart_clk_txen[0:0]
-  attribute \src "ls180.v:978.5-978.27"
+  attribute \src "ls180.v:1023.5-1023.27"
   wire $0\main_uart_reset[0:0]
-  attribute \src "ls180.v:4141.1-4146.4"
+  attribute \src "ls180.v:4216.1-4221.4"
   wire $0\main_uart_rx_clear[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_rx_fifo_consume[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_uart_rx_fifo_level0[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_rx_fifo_produce[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_rx_fifo_readable[0:0]
-  attribute \src "ls180.v:960.5-960.37"
+  attribute \src "ls180.v:1005.5-1005.37"
   wire $0\main_uart_rx_fifo_replace[0:0]
-  attribute \src "ls180.v:4199.1-4206.4"
+  attribute \src "ls180.v:4274.1-4281.4"
   wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_rx_old_trigger[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_rx_pending[0:0]
-  attribute \src "ls180.v:4130.1-4135.4"
+  attribute \src "ls180.v:4205.1-4210.4"
   wire $0\main_uart_tx_clear[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_tx_fifo_consume[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 5 $0\main_uart_tx_fifo_level0[4:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 4 $0\main_uart_tx_fifo_produce[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_tx_fifo_readable[0:0]
-  attribute \src "ls180.v:923.5-923.37"
+  attribute \src "ls180.v:968.5-968.37"
   wire $0\main_uart_tx_fifo_replace[0:0]
-  attribute \src "ls180.v:906.5-906.40"
+  attribute \src "ls180.v:951.5-951.40"
   wire $0\main_uart_tx_fifo_sink_first[0:0]
-  attribute \src "ls180.v:907.5-907.39"
+  attribute \src "ls180.v:952.5-952.39"
   wire $0\main_uart_tx_fifo_sink_last[0:0]
-  attribute \src "ls180.v:4169.1-4176.4"
+  attribute \src "ls180.v:4244.1-4251.4"
   wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_tx_old_trigger[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_uart_tx_pending[0:0]
-  attribute \src "ls180.v:4039.1-4085.4"
+  attribute \src "ls180.v:4114.1-4160.4"
   wire $0\main_wb_sdram_ack[0:0]
-  attribute \src "ls180.v:819.5-819.29"
+  attribute \src "ls180.v:864.5-864.29"
   wire $0\main_wb_sdram_err[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\main_wdata_consumed[0:0]
-  attribute \src "ls180.v:10043.1-10053.4"
+  attribute \src "ls180.v:10160.1-10170.4"
   wire width 7 $0\memadr[6:0]
-  attribute \src "ls180.v:10063.1-10067.4"
+  attribute \src "ls180.v:10180.1-10190.4"
+  wire width 7 $0\memadr_1[6:0]
+  attribute \src "ls180.v:10200.1-10210.4"
+  wire width 7 $0\memadr_2[6:0]
+  attribute \src "ls180.v:10220.1-10230.4"
+  wire width 7 $0\memadr_3[6:0]
+  attribute \src "ls180.v:10240.1-10244.4"
   wire width 25 $0\memdat[24:0]
-  attribute \src "ls180.v:10077.1-10081.4"
+  attribute \src "ls180.v:10254.1-10258.4"
   wire width 25 $0\memdat_1[24:0]
-  attribute \src "ls180.v:10091.1-10095.4"
+  attribute \src "ls180.v:10268.1-10272.4"
   wire width 25 $0\memdat_2[24:0]
-  attribute \src "ls180.v:10105.1-10109.4"
+  attribute \src "ls180.v:10282.1-10286.4"
   wire width 25 $0\memdat_3[24:0]
-  attribute \src "ls180.v:10120.1-10124.4"
+  attribute \src "ls180.v:10297.1-10301.4"
   wire width 10 $0\memdat_4[9:0]
-  attribute \src "ls180.v:10126.1-10129.4"
+  attribute \src "ls180.v:10303.1-10306.4"
   wire width 10 $0\memdat_5[9:0]
-  attribute \src "ls180.v:10137.1-10141.4"
+  attribute \src "ls180.v:10314.1-10318.4"
   wire width 10 $0\memdat_6[9:0]
-  attribute \src "ls180.v:10143.1-10146.4"
+  attribute \src "ls180.v:10320.1-10323.4"
   wire width 10 $0\memdat_7[9:0]
-  attribute \src "ls180.v:10153.1-10157.4"
+  attribute \src "ls180.v:10330.1-10334.4"
   wire width 10 $0\memdat_8[9:0]
-  attribute \src "ls180.v:10167.1-10171.4"
+  attribute \src "ls180.v:10344.1-10348.4"
   wire width 10 $0\memdat_9[9:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire width 2 $0\pwm[1:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdcard_clk[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdcard_cmd_o[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdcard_cmd_oe[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 4 $0\sdcard_data_o[3:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdcard_data_oe[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 13 $0\sdram_a[12:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 2 $0\sdram_ba[1:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_cas_n[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_cke[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_clock[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_cs_n[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 2 $0\sdram_dm[1:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire width 16 $0\sdram_dq_o[15:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_dq_oe[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_ras_n[0:0]
-  attribute \src "ls180.v:7355.1-7425.4"
+  attribute \src "ls180.v:7457.1-7527.4"
   wire $0\sdram_we_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spimaster_clk[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spimaster_cs_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spimaster_mosi[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spisdcard_clk[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spisdcard_cs_n[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\spisdcard_mosi[0:0]
-  attribute \src "ls180.v:7427.1-10039.4"
+  attribute \src "ls180.v:7529.1-10156.4"
   wire $0\uart_tx[0:0]
-  attribute \src "ls180.v:1745.11-1745.49"
+  attribute \src "ls180.v:1790.11-1790.49"
   wire width 3 $1\builder_bankmachine0_next_state[2:0]
-  attribute \src "ls180.v:1744.11-1744.44"
+  attribute \src "ls180.v:1789.11-1789.44"
   wire width 3 $1\builder_bankmachine0_state[2:0]
-  attribute \src "ls180.v:1747.11-1747.49"
+  attribute \src "ls180.v:1792.11-1792.49"
   wire width 3 $1\builder_bankmachine1_next_state[2:0]
-  attribute \src "ls180.v:1746.11-1746.44"
+  attribute \src "ls180.v:1791.11-1791.44"
   wire width 3 $1\builder_bankmachine1_state[2:0]
-  attribute \src "ls180.v:1749.11-1749.49"
+  attribute \src "ls180.v:1794.11-1794.49"
   wire width 3 $1\builder_bankmachine2_next_state[2:0]
-  attribute \src "ls180.v:1748.11-1748.44"
+  attribute \src "ls180.v:1793.11-1793.44"
   wire width 3 $1\builder_bankmachine2_state[2:0]
-  attribute \src "ls180.v:1751.11-1751.49"
+  attribute \src "ls180.v:1796.11-1796.49"
   wire width 3 $1\builder_bankmachine3_next_state[2:0]
-  attribute \src "ls180.v:1750.11-1750.44"
+  attribute \src "ls180.v:1795.11-1795.44"
   wire width 3 $1\builder_bankmachine3_state[2:0]
-  attribute \src "ls180.v:2596.5-2596.41"
+  attribute \src "ls180.v:2641.5-2641.41"
   wire $1\builder_comb_rhs_array_muxed0[0:0]
-  attribute \src "ls180.v:2609.5-2609.42"
+  attribute \src "ls180.v:2654.5-2654.42"
   wire $1\builder_comb_rhs_array_muxed10[0:0]
-  attribute \src "ls180.v:2610.5-2610.42"
+  attribute \src "ls180.v:2655.5-2655.42"
   wire $1\builder_comb_rhs_array_muxed11[0:0]
-  attribute \src "ls180.v:2614.12-2614.50"
+  attribute \src "ls180.v:2659.12-2659.50"
   wire width 22 $1\builder_comb_rhs_array_muxed12[21:0]
-  attribute \src "ls180.v:2615.5-2615.42"
+  attribute \src "ls180.v:2660.5-2660.42"
   wire $1\builder_comb_rhs_array_muxed13[0:0]
-  attribute \src "ls180.v:2616.5-2616.42"
+  attribute \src "ls180.v:2661.5-2661.42"
   wire $1\builder_comb_rhs_array_muxed14[0:0]
-  attribute \src "ls180.v:2617.12-2617.50"
+  attribute \src "ls180.v:2662.12-2662.50"
   wire width 22 $1\builder_comb_rhs_array_muxed15[21:0]
-  attribute \src "ls180.v:2618.5-2618.42"
+  attribute \src "ls180.v:2663.5-2663.42"
   wire $1\builder_comb_rhs_array_muxed16[0:0]
-  attribute \src "ls180.v:2619.5-2619.42"
+  attribute \src "ls180.v:2664.5-2664.42"
   wire $1\builder_comb_rhs_array_muxed17[0:0]
-  attribute \src "ls180.v:2620.12-2620.50"
+  attribute \src "ls180.v:2665.12-2665.50"
   wire width 22 $1\builder_comb_rhs_array_muxed18[21:0]
-  attribute \src "ls180.v:2621.5-2621.42"
+  attribute \src "ls180.v:2666.5-2666.42"
   wire $1\builder_comb_rhs_array_muxed19[0:0]
-  attribute \src "ls180.v:2597.12-2597.49"
+  attribute \src "ls180.v:2642.12-2642.49"
   wire width 13 $1\builder_comb_rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:2622.5-2622.42"
+  attribute \src "ls180.v:2667.5-2667.42"
   wire $1\builder_comb_rhs_array_muxed20[0:0]
-  attribute \src "ls180.v:2623.12-2623.50"
+  attribute \src "ls180.v:2668.12-2668.50"
   wire width 22 $1\builder_comb_rhs_array_muxed21[21:0]
-  attribute \src "ls180.v:2624.5-2624.42"
+  attribute \src "ls180.v:2669.5-2669.42"
   wire $1\builder_comb_rhs_array_muxed22[0:0]
-  attribute \src "ls180.v:2625.5-2625.42"
+  attribute \src "ls180.v:2670.5-2670.42"
   wire $1\builder_comb_rhs_array_muxed23[0:0]
-  attribute \src "ls180.v:2626.12-2626.50"
+  attribute \src "ls180.v:2671.12-2671.50"
   wire width 32 $1\builder_comb_rhs_array_muxed24[31:0]
-  attribute \src "ls180.v:2627.12-2627.50"
+  attribute \src "ls180.v:2672.12-2672.50"
   wire width 32 $1\builder_comb_rhs_array_muxed25[31:0]
-  attribute \src "ls180.v:2628.11-2628.48"
+  attribute \src "ls180.v:2673.11-2673.48"
   wire width 4 $1\builder_comb_rhs_array_muxed26[3:0]
-  attribute \src "ls180.v:2629.5-2629.42"
+  attribute \src "ls180.v:2674.5-2674.42"
   wire $1\builder_comb_rhs_array_muxed27[0:0]
-  attribute \src "ls180.v:2630.5-2630.42"
+  attribute \src "ls180.v:2675.5-2675.42"
   wire $1\builder_comb_rhs_array_muxed28[0:0]
-  attribute \src "ls180.v:2631.5-2631.42"
+  attribute \src "ls180.v:2676.5-2676.42"
   wire $1\builder_comb_rhs_array_muxed29[0:0]
-  attribute \src "ls180.v:2598.11-2598.47"
+  attribute \src "ls180.v:2643.11-2643.47"
   wire width 2 $1\builder_comb_rhs_array_muxed2[1:0]
-  attribute \src "ls180.v:2632.11-2632.48"
+  attribute \src "ls180.v:2677.11-2677.48"
   wire width 3 $1\builder_comb_rhs_array_muxed30[2:0]
-  attribute \src "ls180.v:2633.11-2633.48"
+  attribute \src "ls180.v:2678.11-2678.48"
   wire width 2 $1\builder_comb_rhs_array_muxed31[1:0]
-  attribute \src "ls180.v:2599.5-2599.41"
+  attribute \src "ls180.v:2644.5-2644.41"
   wire $1\builder_comb_rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:2600.5-2600.41"
+  attribute \src "ls180.v:2645.5-2645.41"
   wire $1\builder_comb_rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:2601.5-2601.41"
+  attribute \src "ls180.v:2646.5-2646.41"
   wire $1\builder_comb_rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:2605.5-2605.41"
+  attribute \src "ls180.v:2650.5-2650.41"
   wire $1\builder_comb_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:2606.12-2606.49"
+  attribute \src "ls180.v:2651.12-2651.49"
   wire width 13 $1\builder_comb_rhs_array_muxed7[12:0]
-  attribute \src "ls180.v:2607.11-2607.47"
+  attribute \src "ls180.v:2652.11-2652.47"
   wire width 2 $1\builder_comb_rhs_array_muxed8[1:0]
-  attribute \src "ls180.v:2608.5-2608.41"
+  attribute \src "ls180.v:2653.5-2653.41"
   wire $1\builder_comb_rhs_array_muxed9[0:0]
-  attribute \src "ls180.v:2602.5-2602.39"
+  attribute \src "ls180.v:2647.5-2647.39"
   wire $1\builder_comb_t_array_muxed0[0:0]
-  attribute \src "ls180.v:2603.5-2603.39"
+  attribute \src "ls180.v:2648.5-2648.39"
   wire $1\builder_comb_t_array_muxed1[0:0]
-  attribute \src "ls180.v:2604.5-2604.39"
+  attribute \src "ls180.v:2649.5-2649.39"
   wire $1\builder_comb_t_array_muxed2[0:0]
-  attribute \src "ls180.v:2611.5-2611.39"
+  attribute \src "ls180.v:2656.5-2656.39"
   wire $1\builder_comb_t_array_muxed3[0:0]
-  attribute \src "ls180.v:2612.5-2612.39"
+  attribute \src "ls180.v:2657.5-2657.39"
   wire $1\builder_comb_t_array_muxed4[0:0]
-  attribute \src "ls180.v:2613.5-2613.39"
+  attribute \src "ls180.v:2658.5-2658.39"
   wire $1\builder_comb_t_array_muxed5[0:0]
-  attribute \src "ls180.v:1731.5-1731.41"
+  attribute \src "ls180.v:1776.5-1776.41"
   wire $1\builder_converter0_next_state[0:0]
-  attribute \src "ls180.v:1730.5-1730.36"
+  attribute \src "ls180.v:1775.5-1775.36"
   wire $1\builder_converter0_state[0:0]
-  attribute \src "ls180.v:1735.5-1735.41"
+  attribute \src "ls180.v:1780.5-1780.41"
   wire $1\builder_converter1_next_state[0:0]
-  attribute \src "ls180.v:1734.5-1734.36"
+  attribute \src "ls180.v:1779.5-1779.36"
   wire $1\builder_converter1_state[0:0]
-  attribute \src "ls180.v:1739.5-1739.41"
+  attribute \src "ls180.v:1784.5-1784.41"
   wire $1\builder_converter2_next_state[0:0]
-  attribute \src "ls180.v:1738.5-1738.36"
+  attribute \src "ls180.v:1783.5-1783.36"
   wire $1\builder_converter2_state[0:0]
-  attribute \src "ls180.v:1776.5-1776.40"
+  attribute \src "ls180.v:1821.5-1821.40"
   wire $1\builder_converter_next_state[0:0]
-  attribute \src "ls180.v:1775.5-1775.35"
+  attribute \src "ls180.v:1820.5-1820.35"
   wire $1\builder_converter_state[0:0]
-  attribute \src "ls180.v:1896.12-1896.39"
+  attribute \src "ls180.v:1941.12-1941.39"
   wire width 20 $1\builder_count[19:0]
-  attribute \src "ls180.v:1893.5-1893.25"
+  attribute \src "ls180.v:1938.5-1938.25"
   wire $1\builder_error[0:0]
-  attribute \src "ls180.v:1890.11-1890.31"
+  attribute \src "ls180.v:1935.11-1935.31"
   wire width 3 $1\builder_grant[2:0]
-  attribute \src "ls180.v:1900.11-1900.51"
+  attribute \src "ls180.v:1945.11-1945.51"
   wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2402.11-2402.52"
+  attribute \src "ls180.v:2447.11-2447.52"
   wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2435.11-2435.52"
+  attribute \src "ls180.v:2480.11-2480.52"
   wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2476.11-2476.52"
+  attribute \src "ls180.v:2521.11-2521.52"
   wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2541.11-2541.52"
+  attribute \src "ls180.v:2586.11-2586.52"
   wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2566.11-2566.52"
+  attribute \src "ls180.v:2611.11-2611.52"
   wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1941.11-1941.51"
+  attribute \src "ls180.v:1986.11-1986.51"
   wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1970.11-1970.51"
+  attribute \src "ls180.v:2015.11-2015.51"
   wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1983.11-1983.51"
+  attribute \src "ls180.v:2028.11-2028.51"
   wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2024.11-2024.51"
+  attribute \src "ls180.v:2069.11-2069.51"
   wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2065.11-2065.51"
+  attribute \src "ls180.v:2110.11-2110.51"
   wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2130.11-2130.51"
+  attribute \src "ls180.v:2175.11-2175.51"
   wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2263.11-2263.51"
+  attribute \src "ls180.v:2308.11-2308.51"
   wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2344.11-2344.51"
+  attribute \src "ls180.v:2389.11-2389.51"
   wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:2361.11-2361.51"
+  attribute \src "ls180.v:2406.11-2406.51"
   wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1863.12-1863.43"
+  attribute \src "ls180.v:1908.12-1908.43"
   wire width 14 $1\builder_libresocsim_adr[13:0]
-  attribute \src "ls180.v:2592.12-2592.55"
+  attribute \src "ls180.v:2637.12-2637.55"
   wire width 14 $1\builder_libresocsim_adr_next_value1[13:0]
-  attribute \src "ls180.v:2593.5-2593.50"
+  attribute \src "ls180.v:2638.5-2638.50"
   wire $1\builder_libresocsim_adr_next_value_ce1[0:0]
-  attribute \src "ls180.v:1865.11-1865.43"
+  attribute \src "ls180.v:1910.11-1910.43"
   wire width 8 $1\builder_libresocsim_dat_w[7:0]
-  attribute \src "ls180.v:2590.11-2590.55"
+  attribute \src "ls180.v:2635.11-2635.55"
   wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0]
-  attribute \src "ls180.v:2591.5-2591.52"
+  attribute \src "ls180.v:2636.5-2636.52"
   wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
-  attribute \src "ls180.v:1864.5-1864.34"
+  attribute \src "ls180.v:1909.5-1909.34"
   wire $1\builder_libresocsim_we[0:0]
-  attribute \src "ls180.v:2594.5-2594.46"
+  attribute \src "ls180.v:2639.5-2639.46"
   wire $1\builder_libresocsim_we_next_value2[0:0]
-  attribute \src "ls180.v:2595.5-2595.49"
+  attribute \src "ls180.v:2640.5-2640.49"
   wire $1\builder_libresocsim_we_next_value_ce2[0:0]
-  attribute \src "ls180.v:1873.5-1873.44"
+  attribute \src "ls180.v:1918.5-1918.44"
   wire $1\builder_libresocsim_wishbone_ack[0:0]
-  attribute \src "ls180.v:1869.12-1869.54"
+  attribute \src "ls180.v:1914.12-1914.54"
   wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0]
-  attribute \src "ls180.v:1753.11-1753.48"
+  attribute \src "ls180.v:1798.11-1798.48"
   wire width 3 $1\builder_multiplexer_next_state[2:0]
-  attribute \src "ls180.v:1752.11-1752.43"
+  attribute \src "ls180.v:1797.11-1797.43"
   wire width 3 $1\builder_multiplexer_state[2:0]
-  attribute \src "ls180.v:2699.32-2699.66"
+  attribute \src "ls180.v:2744.32-2744.66"
   wire $1\builder_multiregimpl0_regs0[0:0]
-  attribute \src "ls180.v:2700.32-2700.66"
+  attribute \src "ls180.v:2745.32-2745.66"
   wire $1\builder_multiregimpl0_regs1[0:0]
-  attribute \src "ls180.v:2719.32-2719.67"
+  attribute \src "ls180.v:2764.32-2764.67"
   wire $1\builder_multiregimpl10_regs0[0:0]
-  attribute \src "ls180.v:2720.32-2720.67"
+  attribute \src "ls180.v:2765.32-2765.67"
   wire $1\builder_multiregimpl10_regs1[0:0]
-  attribute \src "ls180.v:2721.32-2721.67"
+  attribute \src "ls180.v:2766.32-2766.67"
   wire $1\builder_multiregimpl11_regs0[0:0]
-  attribute \src "ls180.v:2722.32-2722.67"
+  attribute \src "ls180.v:2767.32-2767.67"
   wire $1\builder_multiregimpl11_regs1[0:0]
-  attribute \src "ls180.v:2723.32-2723.67"
+  attribute \src "ls180.v:2768.32-2768.67"
   wire $1\builder_multiregimpl12_regs0[0:0]
-  attribute \src "ls180.v:2724.32-2724.67"
+  attribute \src "ls180.v:2769.32-2769.67"
   wire $1\builder_multiregimpl12_regs1[0:0]
-  attribute \src "ls180.v:2725.32-2725.67"
+  attribute \src "ls180.v:2770.32-2770.67"
   wire $1\builder_multiregimpl13_regs0[0:0]
-  attribute \src "ls180.v:2726.32-2726.67"
+  attribute \src "ls180.v:2771.32-2771.67"
   wire $1\builder_multiregimpl13_regs1[0:0]
-  attribute \src "ls180.v:2727.32-2727.67"
+  attribute \src "ls180.v:2772.32-2772.67"
   wire $1\builder_multiregimpl14_regs0[0:0]
-  attribute \src "ls180.v:2728.32-2728.67"
+  attribute \src "ls180.v:2773.32-2773.67"
   wire $1\builder_multiregimpl14_regs1[0:0]
-  attribute \src "ls180.v:2729.32-2729.67"
+  attribute \src "ls180.v:2774.32-2774.67"
   wire $1\builder_multiregimpl15_regs0[0:0]
-  attribute \src "ls180.v:2730.32-2730.67"
+  attribute \src "ls180.v:2775.32-2775.67"
   wire $1\builder_multiregimpl15_regs1[0:0]
-  attribute \src "ls180.v:2731.32-2731.67"
+  attribute \src "ls180.v:2776.32-2776.67"
   wire $1\builder_multiregimpl16_regs0[0:0]
-  attribute \src "ls180.v:2732.32-2732.67"
+  attribute \src "ls180.v:2777.32-2777.67"
   wire $1\builder_multiregimpl16_regs1[0:0]
-  attribute \src "ls180.v:2701.32-2701.66"
+  attribute \src "ls180.v:2746.32-2746.66"
   wire $1\builder_multiregimpl1_regs0[0:0]
-  attribute \src "ls180.v:2702.32-2702.66"
+  attribute \src "ls180.v:2747.32-2747.66"
   wire $1\builder_multiregimpl1_regs1[0:0]
-  attribute \src "ls180.v:2703.32-2703.66"
+  attribute \src "ls180.v:2748.32-2748.66"
   wire $1\builder_multiregimpl2_regs0[0:0]
-  attribute \src "ls180.v:2704.32-2704.66"
+  attribute \src "ls180.v:2749.32-2749.66"
   wire $1\builder_multiregimpl2_regs1[0:0]
-  attribute \src "ls180.v:2705.32-2705.66"
+  attribute \src "ls180.v:2750.32-2750.66"
   wire $1\builder_multiregimpl3_regs0[0:0]
-  attribute \src "ls180.v:2706.32-2706.66"
+  attribute \src "ls180.v:2751.32-2751.66"
   wire $1\builder_multiregimpl3_regs1[0:0]
-  attribute \src "ls180.v:2707.32-2707.66"
+  attribute \src "ls180.v:2752.32-2752.66"
   wire $1\builder_multiregimpl4_regs0[0:0]
-  attribute \src "ls180.v:2708.32-2708.66"
+  attribute \src "ls180.v:2753.32-2753.66"
   wire $1\builder_multiregimpl4_regs1[0:0]
-  attribute \src "ls180.v:2709.32-2709.66"
+  attribute \src "ls180.v:2754.32-2754.66"
   wire $1\builder_multiregimpl5_regs0[0:0]
-  attribute \src "ls180.v:2710.32-2710.66"
+  attribute \src "ls180.v:2755.32-2755.66"
   wire $1\builder_multiregimpl5_regs1[0:0]
-  attribute \src "ls180.v:2711.32-2711.66"
+  attribute \src "ls180.v:2756.32-2756.66"
   wire $1\builder_multiregimpl6_regs0[0:0]
-  attribute \src "ls180.v:2712.32-2712.66"
+  attribute \src "ls180.v:2757.32-2757.66"
   wire $1\builder_multiregimpl6_regs1[0:0]
-  attribute \src "ls180.v:2713.32-2713.66"
+  attribute \src "ls180.v:2758.32-2758.66"
   wire $1\builder_multiregimpl7_regs0[0:0]
-  attribute \src "ls180.v:2714.32-2714.66"
+  attribute \src "ls180.v:2759.32-2759.66"
   wire $1\builder_multiregimpl7_regs1[0:0]
-  attribute \src "ls180.v:2715.32-2715.66"
+  attribute \src "ls180.v:2760.32-2760.66"
   wire $1\builder_multiregimpl8_regs0[0:0]
-  attribute \src "ls180.v:2716.32-2716.66"
+  attribute \src "ls180.v:2761.32-2761.66"
   wire $1\builder_multiregimpl8_regs1[0:0]
-  attribute \src "ls180.v:2717.32-2717.66"
+  attribute \src "ls180.v:2762.32-2762.66"
   wire $1\builder_multiregimpl9_regs0[0:0]
-  attribute \src "ls180.v:2718.32-2718.66"
+  attribute \src "ls180.v:2763.32-2763.66"
   wire $1\builder_multiregimpl9_regs1[0:0]
-  attribute \src "ls180.v:1771.5-1771.43"
+  attribute \src "ls180.v:1816.5-1816.43"
   wire $1\builder_new_master_rdata_valid0[0:0]
-  attribute \src "ls180.v:1772.5-1772.43"
+  attribute \src "ls180.v:1817.5-1817.43"
   wire $1\builder_new_master_rdata_valid1[0:0]
-  attribute \src "ls180.v:1773.5-1773.43"
+  attribute \src "ls180.v:1818.5-1818.43"
   wire $1\builder_new_master_rdata_valid2[0:0]
-  attribute \src "ls180.v:1774.5-1774.43"
+  attribute \src "ls180.v:1819.5-1819.43"
   wire $1\builder_new_master_rdata_valid3[0:0]
-  attribute \src "ls180.v:1770.5-1770.42"
+  attribute \src "ls180.v:1815.5-1815.42"
   wire $1\builder_new_master_wdata_ready[0:0]
-  attribute \src "ls180.v:2589.11-2589.36"
+  attribute \src "ls180.v:2634.11-2634.36"
   wire width 2 $1\builder_next_state[1:0]
-  attribute \src "ls180.v:1743.11-1743.46"
+  attribute \src "ls180.v:1788.11-1788.46"
   wire width 2 $1\builder_refresher_next_state[1:0]
-  attribute \src "ls180.v:1742.11-1742.41"
+  attribute \src "ls180.v:1787.11-1787.41"
   wire width 2 $1\builder_refresher_state[1:0]
-  attribute \src "ls180.v:1852.11-1852.51"
+  attribute \src "ls180.v:1897.11-1897.51"
   wire width 2 $1\builder_sdblock2memdma_next_state[1:0]
-  attribute \src "ls180.v:1851.11-1851.46"
+  attribute \src "ls180.v:1896.11-1896.46"
   wire width 2 $1\builder_sdblock2memdma_state[1:0]
-  attribute \src "ls180.v:1820.5-1820.57"
+  attribute \src "ls180.v:1865.5-1865.57"
   wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
-  attribute \src "ls180.v:1819.5-1819.52"
+  attribute \src "ls180.v:1864.5-1864.52"
   wire $1\builder_sdcore_crcupstreaminserter_state[0:0]
-  attribute \src "ls180.v:1832.11-1832.47"
+  attribute \src "ls180.v:1877.11-1877.47"
   wire width 3 $1\builder_sdcore_fsm_next_state[2:0]
-  attribute \src "ls180.v:1831.11-1831.42"
+  attribute \src "ls180.v:1876.11-1876.42"
   wire width 3 $1\builder_sdcore_fsm_state[2:0]
-  attribute \src "ls180.v:1856.5-1856.49"
+  attribute \src "ls180.v:1901.5-1901.49"
   wire $1\builder_sdmem2blockdma_fsm_next_state[0:0]
-  attribute \src "ls180.v:1855.5-1855.44"
+  attribute \src "ls180.v:1900.5-1900.44"
   wire $1\builder_sdmem2blockdma_fsm_state[0:0]
-  attribute \src "ls180.v:1860.11-1860.65"
+  attribute \src "ls180.v:1905.11-1905.65"
   wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
-  attribute \src "ls180.v:1859.11-1859.60"
+  attribute \src "ls180.v:1904.11-1904.60"
   wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0]
-  attribute \src "ls180.v:1808.11-1808.46"
+  attribute \src "ls180.v:1853.11-1853.46"
   wire width 3 $1\builder_sdphy_fsm_next_state[2:0]
-  attribute \src "ls180.v:1807.11-1807.41"
+  attribute \src "ls180.v:1852.11-1852.41"
   wire width 3 $1\builder_sdphy_fsm_state[2:0]
-  attribute \src "ls180.v:1796.11-1796.52"
+  attribute \src "ls180.v:1841.11-1841.52"
   wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0]
-  attribute \src "ls180.v:1795.11-1795.47"
+  attribute \src "ls180.v:1840.11-1840.47"
   wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0]
-  attribute \src "ls180.v:1792.11-1792.52"
+  attribute \src "ls180.v:1837.11-1837.52"
   wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0]
-  attribute \src "ls180.v:1791.11-1791.47"
+  attribute \src "ls180.v:1836.11-1836.47"
   wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0]
-  attribute \src "ls180.v:1804.5-1804.46"
+  attribute \src "ls180.v:1849.5-1849.46"
   wire $1\builder_sdphy_sdphycrcr_next_state[0:0]
-  attribute \src "ls180.v:1803.5-1803.41"
+  attribute \src "ls180.v:1848.5-1848.41"
   wire $1\builder_sdphy_sdphycrcr_state[0:0]
-  attribute \src "ls180.v:1812.11-1812.53"
+  attribute \src "ls180.v:1857.11-1857.53"
   wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0]
-  attribute \src "ls180.v:1811.11-1811.48"
+  attribute \src "ls180.v:1856.11-1856.48"
   wire width 3 $1\builder_sdphy_sdphydatar_state[2:0]
-  attribute \src "ls180.v:1788.5-1788.46"
+  attribute \src "ls180.v:1833.5-1833.46"
   wire $1\builder_sdphy_sdphyinit_next_state[0:0]
-  attribute \src "ls180.v:1787.5-1787.41"
+  attribute \src "ls180.v:1832.5-1832.41"
   wire $1\builder_sdphy_sdphyinit_state[0:0]
-  attribute \src "ls180.v:1884.5-1884.30"
+  attribute \src "ls180.v:1929.5-1929.30"
   wire $1\builder_shared_ack[0:0]
-  attribute \src "ls180.v:1880.12-1880.40"
+  attribute \src "ls180.v:1925.12-1925.40"
   wire width 32 $1\builder_shared_dat_r[31:0]
-  attribute \src "ls180.v:1891.11-1891.35"
-  wire width 5 $1\builder_slave_sel[4:0]
-  attribute \src "ls180.v:1892.11-1892.37"
-  wire width 5 $1\builder_slave_sel_r[4:0]
-  attribute \src "ls180.v:1780.11-1780.47"
+  attribute \src "ls180.v:1936.11-1936.35"
+  wire width 8 $1\builder_slave_sel[7:0]
+  attribute \src "ls180.v:1937.11-1937.37"
+  wire width 8 $1\builder_slave_sel_r[7:0]
+  attribute \src "ls180.v:1825.11-1825.47"
   wire width 2 $1\builder_spimaster0_next_state[1:0]
-  attribute \src "ls180.v:1779.11-1779.42"
+  attribute \src "ls180.v:1824.11-1824.42"
   wire width 2 $1\builder_spimaster0_state[1:0]
-  attribute \src "ls180.v:1784.11-1784.47"
+  attribute \src "ls180.v:1829.11-1829.47"
   wire width 2 $1\builder_spimaster1_next_state[1:0]
-  attribute \src "ls180.v:1783.11-1783.42"
+  attribute \src "ls180.v:1828.11-1828.42"
   wire width 2 $1\builder_spimaster1_state[1:0]
-  attribute \src "ls180.v:2588.11-2588.31"
+  attribute \src "ls180.v:2633.11-2633.31"
   wire width 2 $1\builder_state[1:0]
-  attribute \src "ls180.v:2641.5-2641.39"
+  attribute \src "ls180.v:2686.5-2686.39"
   wire $1\builder_sync_f_array_muxed0[0:0]
-  attribute \src "ls180.v:2642.5-2642.39"
+  attribute \src "ls180.v:2687.5-2687.39"
   wire $1\builder_sync_f_array_muxed1[0:0]
-  attribute \src "ls180.v:2634.11-2634.47"
+  attribute \src "ls180.v:2679.11-2679.47"
   wire width 2 $1\builder_sync_rhs_array_muxed0[1:0]
-  attribute \src "ls180.v:2635.12-2635.49"
+  attribute \src "ls180.v:2680.12-2680.49"
   wire width 13 $1\builder_sync_rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:2636.5-2636.41"
+  attribute \src "ls180.v:2681.5-2681.41"
   wire $1\builder_sync_rhs_array_muxed2[0:0]
-  attribute \src "ls180.v:2637.5-2637.41"
+  attribute \src "ls180.v:2682.5-2682.41"
   wire $1\builder_sync_rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:2638.5-2638.41"
+  attribute \src "ls180.v:2683.5-2683.41"
   wire $1\builder_sync_rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:2639.5-2639.41"
+  attribute \src "ls180.v:2684.5-2684.41"
   wire $1\builder_sync_rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:2640.5-2640.41"
+  attribute \src "ls180.v:2685.5-2685.41"
   wire $1\builder_sync_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:832.5-832.29"
+  attribute \src "ls180.v:877.5-877.29"
   wire $1\main_cmd_consumed[0:0]
-  attribute \src "ls180.v:829.5-829.34"
+  attribute \src "ls180.v:874.5-874.34"
   wire $1\main_converter_counter[0:0]
-  attribute \src "ls180.v:1777.5-1777.55"
+  attribute \src "ls180.v:1822.5-1822.55"
   wire $1\main_converter_counter_converter_next_value[0:0]
-  attribute \src "ls180.v:1778.5-1778.58"
+  attribute \src "ls180.v:1823.5-1823.58"
   wire $1\main_converter_counter_converter_next_value_ce[0:0]
-  attribute \src "ls180.v:831.12-831.40"
+  attribute \src "ls180.v:876.12-876.40"
   wire width 32 $1\main_converter_dat_r[31:0]
-  attribute \src "ls180.v:828.5-828.31"
+  attribute \src "ls180.v:873.5-873.31"
   wire $1\main_converter_skip[0:0]
-  attribute \src "ls180.v:263.12-263.38"
+  attribute \src "ls180.v:308.12-308.38"
   wire width 16 $1\main_dfi_p0_rddata[15:0]
-  attribute \src "ls180.v:264.5-264.36"
+  attribute \src "ls180.v:309.5-309.36"
   wire $1\main_dfi_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:1063.12-1063.30"
+  attribute \src "ls180.v:1108.12-1108.30"
   wire width 24 $1\main_dummy[23:0]
-  attribute \src "ls180.v:980.5-980.27"
+  attribute \src "ls180.v:1025.5-1025.27"
   wire $1\main_gpio_oe_re[0:0]
-  attribute \src "ls180.v:979.12-979.40"
+  attribute \src "ls180.v:1024.12-1024.40"
   wire width 16 $1\main_gpio_oe_storage[15:0]
-  attribute \src "ls180.v:984.5-984.28"
+  attribute \src "ls180.v:1029.5-1029.28"
   wire $1\main_gpio_out_re[0:0]
-  attribute \src "ls180.v:983.12-983.41"
+  attribute \src "ls180.v:1028.12-1028.41"
   wire width 16 $1\main_gpio_out_storage[15:0]
-  attribute \src "ls180.v:981.12-981.36"
+  attribute \src "ls180.v:1026.12-1026.36"
   wire width 16 $1\main_gpio_status[15:0]
-  attribute \src "ls180.v:1088.5-1088.23"
+  attribute \src "ls180.v:1133.5-1133.23"
   wire $1\main_i2c_re[0:0]
-  attribute \src "ls180.v:1087.11-1087.34"
+  attribute \src "ls180.v:1132.11-1132.34"
   wire width 3 $1\main_i2c_storage[2:0]
-  attribute \src "ls180.v:248.5-248.24"
+  attribute \src "ls180.v:293.5-293.24"
   wire $1\main_int_rst[0:0]
-  attribute \src "ls180.v:1636.12-1636.43"
+  attribute \src "ls180.v:251.5-251.39"
+  wire $1\main_interface0_ram_bus_ack[0:0]
+  attribute \src "ls180.v:1681.12-1681.43"
   wire width 32 $1\main_interface1_bus_adr[31:0]
-  attribute \src "ls180.v:1640.5-1640.35"
+  attribute \src "ls180.v:1685.5-1685.35"
   wire $1\main_interface1_bus_cyc[0:0]
-  attribute \src "ls180.v:1639.11-1639.41"
+  attribute \src "ls180.v:1684.11-1684.41"
   wire width 4 $1\main_interface1_bus_sel[3:0]
-  attribute \src "ls180.v:1641.5-1641.35"
+  attribute \src "ls180.v:1686.5-1686.35"
   wire $1\main_interface1_bus_stb[0:0]
-  attribute \src "ls180.v:1643.5-1643.34"
+  attribute \src "ls180.v:1688.5-1688.34"
   wire $1\main_interface1_bus_we[0:0]
+  attribute \src "ls180.v:266.5-266.39"
+  wire $1\main_interface1_ram_bus_ack[0:0]
+  attribute \src "ls180.v:281.5-281.39"
+  wire $1\main_interface2_ram_bus_ack[0:0]
   attribute \src "ls180.v:63.12-63.47"
   wire width 32 $1\main_libresocsim_bus_errors[31:0]
   attribute \src "ls180.v:170.5-170.47"
   wire $1\main_libresocsim_converter0_counter[0:0]
-  attribute \src "ls180.v:1732.5-1732.69"
+  attribute \src "ls180.v:1777.5-1777.69"
   wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
-  attribute \src "ls180.v:1733.5-1733.72"
+  attribute \src "ls180.v:1778.5-1778.72"
   wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
   attribute \src "ls180.v:172.12-172.53"
   wire width 64 $1\main_libresocsim_converter0_dat_r[63:0]
@@ -223123,9 +223225,9 @@ module \ls180
   wire $1\main_libresocsim_converter0_skip[0:0]
   attribute \src "ls180.v:185.5-185.47"
   wire $1\main_libresocsim_converter1_counter[0:0]
-  attribute \src "ls180.v:1736.5-1736.69"
+  attribute \src "ls180.v:1781.5-1781.69"
   wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
-  attribute \src "ls180.v:1737.5-1737.72"
+  attribute \src "ls180.v:1782.5-1782.72"
   wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
   attribute \src "ls180.v:187.12-187.53"
   wire width 64 $1\main_libresocsim_converter1_dat_r[63:0]
@@ -223133,9 +223235,9 @@ module \ls180
   wire $1\main_libresocsim_converter1_skip[0:0]
   attribute \src "ls180.v:200.5-200.47"
   wire $1\main_libresocsim_converter2_counter[0:0]
-  attribute \src "ls180.v:1740.5-1740.69"
+  attribute \src "ls180.v:1785.5-1785.69"
   wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
-  attribute \src "ls180.v:1741.5-1741.72"
+  attribute \src "ls180.v:1786.5-1786.72"
   wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
   attribute \src "ls180.v:202.12-202.53"
   wire width 64 $1\main_libresocsim_converter2_dat_r[63:0]
@@ -223227,8132 +223329,8342 @@ module \ls180
   wire $1\main_libresocsim_zero_old_trigger[0:0]
   attribute \src "ls180.v:230.5-230.41"
   wire $1\main_libresocsim_zero_pending[0:0]
-  attribute \src "ls180.v:820.12-820.40"
+  attribute \src "ls180.v:865.12-865.40"
   wire width 30 $1\main_litedram_wb_adr[29:0]
-  attribute \src "ls180.v:824.5-824.32"
+  attribute \src "ls180.v:869.5-869.32"
   wire $1\main_litedram_wb_cyc[0:0]
-  attribute \src "ls180.v:821.12-821.42"
+  attribute \src "ls180.v:866.12-866.42"
   wire width 16 $1\main_litedram_wb_dat_w[15:0]
-  attribute \src "ls180.v:823.11-823.38"
+  attribute \src "ls180.v:868.11-868.38"
   wire width 2 $1\main_litedram_wb_sel[1:0]
-  attribute \src "ls180.v:825.5-825.32"
+  attribute \src "ls180.v:870.5-870.32"
   wire $1\main_litedram_wb_stb[0:0]
-  attribute \src "ls180.v:827.5-827.31"
+  attribute \src "ls180.v:872.5-872.31"
   wire $1\main_litedram_wb_we[0:0]
-  attribute \src "ls180.v:1067.12-1067.37"
+  attribute \src "ls180.v:1112.12-1112.37"
   wire width 32 $1\main_pwm0_counter[31:0]
-  attribute \src "ls180.v:1069.5-1069.31"
+  attribute \src "ls180.v:1114.5-1114.31"
   wire $1\main_pwm0_enable_re[0:0]
-  attribute \src "ls180.v:1068.5-1068.36"
+  attribute \src "ls180.v:1113.5-1113.36"
   wire $1\main_pwm0_enable_storage[0:0]
-  attribute \src "ls180.v:1073.5-1073.31"
+  attribute \src "ls180.v:1118.5-1118.31"
   wire $1\main_pwm0_period_re[0:0]
-  attribute \src "ls180.v:1072.12-1072.44"
+  attribute \src "ls180.v:1117.12-1117.44"
   wire width 32 $1\main_pwm0_period_storage[31:0]
-  attribute \src "ls180.v:1071.5-1071.30"
+  attribute \src "ls180.v:1116.5-1116.30"
   wire $1\main_pwm0_width_re[0:0]
-  attribute \src "ls180.v:1070.12-1070.43"
+  attribute \src "ls180.v:1115.12-1115.43"
   wire width 32 $1\main_pwm0_width_storage[31:0]
-  attribute \src "ls180.v:1077.12-1077.37"
+  attribute \src "ls180.v:1122.12-1122.37"
   wire width 32 $1\main_pwm1_counter[31:0]
-  attribute \src "ls180.v:1079.5-1079.31"
+  attribute \src "ls180.v:1124.5-1124.31"
   wire $1\main_pwm1_enable_re[0:0]
-  attribute \src "ls180.v:1078.5-1078.36"
+  attribute \src "ls180.v:1123.5-1123.36"
   wire $1\main_pwm1_enable_storage[0:0]
-  attribute \src "ls180.v:1083.5-1083.31"
+  attribute \src "ls180.v:1128.5-1128.31"
   wire $1\main_pwm1_period_re[0:0]
-  attribute \src "ls180.v:1082.12-1082.44"
+  attribute \src "ls180.v:1127.12-1127.44"
   wire width 32 $1\main_pwm1_period_storage[31:0]
-  attribute \src "ls180.v:1081.5-1081.30"
+  attribute \src "ls180.v:1126.5-1126.30"
   wire $1\main_pwm1_width_re[0:0]
-  attribute \src "ls180.v:1080.12-1080.43"
+  attribute \src "ls180.v:1125.12-1125.43"
   wire width 32 $1\main_pwm1_width_storage[31:0]
-  attribute \src "ls180.v:265.11-265.32"
+  attribute \src "ls180.v:310.11-310.32"
   wire width 3 $1\main_rddata_en[2:0]
-  attribute \src "ls180.v:1605.11-1605.50"
+  attribute \src "ls180.v:1650.11-1650.50"
   wire width 2 $1\main_sdblock2mem_converter_demux[1:0]
-  attribute \src "ls180.v:1601.5-1601.51"
+  attribute \src "ls180.v:1646.5-1646.51"
   wire $1\main_sdblock2mem_converter_source_first[0:0]
-  attribute \src "ls180.v:1602.5-1602.50"
+  attribute \src "ls180.v:1647.5-1647.50"
   wire $1\main_sdblock2mem_converter_source_last[0:0]
-  attribute \src "ls180.v:1603.12-1603.66"
+  attribute \src "ls180.v:1648.12-1648.66"
   wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0]
-  attribute \src "ls180.v:1604.11-1604.77"
+  attribute \src "ls180.v:1649.11-1649.77"
   wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
-  attribute \src "ls180.v:1607.5-1607.49"
+  attribute \src "ls180.v:1652.5-1652.49"
   wire $1\main_sdblock2mem_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1580.11-1580.47"
+  attribute \src "ls180.v:1625.11-1625.47"
   wire width 5 $1\main_sdblock2mem_fifo_consume[4:0]
-  attribute \src "ls180.v:1577.11-1577.45"
+  attribute \src "ls180.v:1622.11-1622.45"
   wire width 6 $1\main_sdblock2mem_fifo_level[5:0]
-  attribute \src "ls180.v:1579.11-1579.47"
+  attribute \src "ls180.v:1624.11-1624.47"
   wire width 5 $1\main_sdblock2mem_fifo_produce[4:0]
-  attribute \src "ls180.v:1581.11-1581.50"
+  attribute \src "ls180.v:1626.11-1626.50"
   wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0]
-  attribute \src "ls180.v:1615.12-1615.62"
+  attribute \src "ls180.v:1660.12-1660.62"
   wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0]
-  attribute \src "ls180.v:1616.12-1616.60"
+  attribute \src "ls180.v:1661.12-1661.60"
   wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
-  attribute \src "ls180.v:1613.5-1613.45"
+  attribute \src "ls180.v:1658.5-1658.45"
   wire $1\main_sdblock2mem_sink_sink_valid1[0:0]
-  attribute \src "ls180.v:1623.5-1623.54"
+  attribute \src "ls180.v:1668.5-1668.54"
   wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
-  attribute \src "ls180.v:1622.12-1622.67"
+  attribute \src "ls180.v:1667.12-1667.67"
   wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
-  attribute \src "ls180.v:1627.5-1627.56"
+  attribute \src "ls180.v:1672.5-1672.56"
   wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
-  attribute \src "ls180.v:1626.5-1626.61"
+  attribute \src "ls180.v:1671.5-1671.61"
   wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
-  attribute \src "ls180.v:1625.5-1625.56"
+  attribute \src "ls180.v:1670.5-1670.56"
   wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
-  attribute \src "ls180.v:1624.12-1624.69"
+  attribute \src "ls180.v:1669.12-1669.69"
   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
-  attribute \src "ls180.v:1631.5-1631.54"
+  attribute \src "ls180.v:1676.5-1676.54"
   wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
-  attribute \src "ls180.v:1630.5-1630.59"
+  attribute \src "ls180.v:1675.5-1675.59"
   wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
-  attribute \src "ls180.v:1633.12-1633.61"
+  attribute \src "ls180.v:1678.12-1678.61"
   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
-  attribute \src "ls180.v:1853.12-1853.87"
+  attribute \src "ls180.v:1898.12-1898.87"
   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
-  attribute \src "ls180.v:1854.5-1854.82"
+  attribute \src "ls180.v:1899.5-1899.82"
   wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
-  attribute \src "ls180.v:1618.5-1618.57"
+  attribute \src "ls180.v:1663.5-1663.57"
   wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
-  attribute \src "ls180.v:1628.5-1628.53"
+  attribute \src "ls180.v:1673.5-1673.53"
   wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
-  attribute \src "ls180.v:1397.5-1397.38"
+  attribute \src "ls180.v:1442.5-1442.38"
   wire $1\main_sdcore_block_count_re[0:0]
-  attribute \src "ls180.v:1396.12-1396.51"
+  attribute \src "ls180.v:1441.12-1441.51"
   wire width 32 $1\main_sdcore_block_count_storage[31:0]
-  attribute \src "ls180.v:1395.5-1395.39"
+  attribute \src "ls180.v:1440.5-1440.39"
   wire $1\main_sdcore_block_length_re[0:0]
-  attribute \src "ls180.v:1394.11-1394.51"
+  attribute \src "ls180.v:1439.11-1439.51"
   wire width 10 $1\main_sdcore_block_length_storage[9:0]
-  attribute \src "ls180.v:1381.5-1381.39"
+  attribute \src "ls180.v:1426.5-1426.39"
   wire $1\main_sdcore_cmd_argument_re[0:0]
-  attribute \src "ls180.v:1380.12-1380.52"
+  attribute \src "ls180.v:1425.12-1425.52"
   wire width 32 $1\main_sdcore_cmd_argument_storage[31:0]
-  attribute \src "ls180.v:1383.5-1383.38"
+  attribute \src "ls180.v:1428.5-1428.38"
   wire $1\main_sdcore_cmd_command_re[0:0]
-  attribute \src "ls180.v:1382.12-1382.51"
+  attribute \src "ls180.v:1427.12-1427.51"
   wire width 32 $1\main_sdcore_cmd_command_storage[31:0]
-  attribute \src "ls180.v:1536.11-1536.39"
+  attribute \src "ls180.v:1581.11-1581.39"
   wire width 3 $1\main_sdcore_cmd_count[2:0]
-  attribute \src "ls180.v:1837.11-1837.62"
+  attribute \src "ls180.v:1882.11-1882.62"
   wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
-  attribute \src "ls180.v:1838.5-1838.59"
+  attribute \src "ls180.v:1883.5-1883.59"
   wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
-  attribute \src "ls180.v:1537.5-1537.32"
+  attribute \src "ls180.v:1582.5-1582.32"
   wire $1\main_sdcore_cmd_done[0:0]
-  attribute \src "ls180.v:1833.5-1833.55"
+  attribute \src "ls180.v:1878.5-1878.55"
   wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
-  attribute \src "ls180.v:1834.5-1834.58"
+  attribute \src "ls180.v:1879.5-1879.58"
   wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
-  attribute \src "ls180.v:1538.5-1538.33"
+  attribute \src "ls180.v:1583.5-1583.33"
   wire $1\main_sdcore_cmd_error[0:0]
-  attribute \src "ls180.v:1841.5-1841.56"
+  attribute \src "ls180.v:1886.5-1886.56"
   wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
-  attribute \src "ls180.v:1842.5-1842.59"
+  attribute \src "ls180.v:1887.5-1887.59"
   wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
-  attribute \src "ls180.v:1388.13-1388.53"
+  attribute \src "ls180.v:1433.13-1433.53"
   wire width 128 $1\main_sdcore_cmd_response_status[127:0]
-  attribute \src "ls180.v:1849.13-1849.76"
+  attribute \src "ls180.v:1894.13-1894.76"
   wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
-  attribute \src "ls180.v:1850.5-1850.69"
+  attribute \src "ls180.v:1895.5-1895.69"
   wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
-  attribute \src "ls180.v:1539.5-1539.35"
+  attribute \src "ls180.v:1584.5-1584.35"
   wire $1\main_sdcore_cmd_timeout[0:0]
-  attribute \src "ls180.v:1843.5-1843.58"
+  attribute \src "ls180.v:1888.5-1888.58"
   wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
-  attribute \src "ls180.v:1844.5-1844.61"
+  attribute \src "ls180.v:1889.5-1889.61"
   wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
-  attribute \src "ls180.v:1497.11-1497.47"
+  attribute \src "ls180.v:1542.11-1542.47"
   wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0]
-  attribute \src "ls180.v:1503.5-1503.46"
+  attribute \src "ls180.v:1548.5-1548.46"
   wire $1\main_sdcore_crc16_checker_crc0_clr[0:0]
-  attribute \src "ls180.v:1502.12-1502.54"
+  attribute \src "ls180.v:1547.12-1547.54"
   wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0]
-  attribute \src "ls180.v:1498.12-1498.58"
+  attribute \src "ls180.v:1543.12-1543.58"
   wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
-  attribute \src "ls180.v:1510.5-1510.46"
+  attribute \src "ls180.v:1555.5-1555.46"
   wire $1\main_sdcore_crc16_checker_crc1_clr[0:0]
-  attribute \src "ls180.v:1509.12-1509.54"
+  attribute \src "ls180.v:1554.12-1554.54"
   wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0]
-  attribute \src "ls180.v:1505.12-1505.58"
+  attribute \src "ls180.v:1550.12-1550.58"
   wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
-  attribute \src "ls180.v:1517.5-1517.46"
+  attribute \src "ls180.v:1562.5-1562.46"
   wire $1\main_sdcore_crc16_checker_crc2_clr[0:0]
-  attribute \src "ls180.v:1516.12-1516.54"
+  attribute \src "ls180.v:1561.12-1561.54"
   wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0]
-  attribute \src "ls180.v:1512.12-1512.58"
+  attribute \src "ls180.v:1557.12-1557.58"
   wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
-  attribute \src "ls180.v:1524.5-1524.46"
+  attribute \src "ls180.v:1569.5-1569.46"
   wire $1\main_sdcore_crc16_checker_crc3_clr[0:0]
-  attribute \src "ls180.v:1523.12-1523.54"
+  attribute \src "ls180.v:1568.12-1568.54"
   wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0]
-  attribute \src "ls180.v:1519.12-1519.58"
+  attribute \src "ls180.v:1564.12-1564.58"
   wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:1526.12-1526.53"
+  attribute \src "ls180.v:1571.12-1571.53"
   wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0]
-  attribute \src "ls180.v:1527.12-1527.53"
+  attribute \src "ls180.v:1572.12-1572.53"
   wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0]
-  attribute \src "ls180.v:1528.12-1528.53"
+  attribute \src "ls180.v:1573.12-1573.53"
   wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0]
-  attribute \src "ls180.v:1529.12-1529.53"
+  attribute \src "ls180.v:1574.12-1574.53"
   wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0]
-  attribute \src "ls180.v:1531.12-1531.51"
+  attribute \src "ls180.v:1576.12-1576.51"
   wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0]
-  attribute \src "ls180.v:1532.12-1532.51"
+  attribute \src "ls180.v:1577.12-1577.51"
   wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0]
-  attribute \src "ls180.v:1533.12-1533.51"
+  attribute \src "ls180.v:1578.12-1578.51"
   wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0]
-  attribute \src "ls180.v:1534.12-1534.51"
+  attribute \src "ls180.v:1579.12-1579.51"
   wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0]
-  attribute \src "ls180.v:1488.5-1488.48"
+  attribute \src "ls180.v:1533.5-1533.48"
   wire $1\main_sdcore_crc16_checker_sink_first[0:0]
-  attribute \src "ls180.v:1489.5-1489.47"
+  attribute \src "ls180.v:1534.5-1534.47"
   wire $1\main_sdcore_crc16_checker_sink_last[0:0]
-  attribute \src "ls180.v:1490.11-1490.61"
+  attribute \src "ls180.v:1535.11-1535.61"
   wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
-  attribute \src "ls180.v:1487.5-1487.48"
+  attribute \src "ls180.v:1532.5-1532.48"
   wire $1\main_sdcore_crc16_checker_sink_ready[0:0]
-  attribute \src "ls180.v:1486.5-1486.48"
+  attribute \src "ls180.v:1531.5-1531.48"
   wire $1\main_sdcore_crc16_checker_sink_valid[0:0]
-  attribute \src "ls180.v:1491.5-1491.50"
+  attribute \src "ls180.v:1536.5-1536.50"
   wire $1\main_sdcore_crc16_checker_source_valid[0:0]
-  attribute \src "ls180.v:1496.11-1496.47"
+  attribute \src "ls180.v:1541.11-1541.47"
   wire width 8 $1\main_sdcore_crc16_checker_val[7:0]
-  attribute \src "ls180.v:1530.5-1530.43"
+  attribute \src "ls180.v:1575.5-1575.43"
   wire $1\main_sdcore_crc16_checker_valid[0:0]
-  attribute \src "ls180.v:1453.11-1453.48"
+  attribute \src "ls180.v:1498.11-1498.48"
   wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0]
-  attribute \src "ls180.v:1829.11-1829.87"
+  attribute \src "ls180.v:1874.11-1874.87"
   wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
-  attribute \src "ls180.v:1830.5-1830.84"
+  attribute \src "ls180.v:1875.5-1875.84"
   wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
-  attribute \src "ls180.v:1458.12-1458.55"
+  attribute \src "ls180.v:1503.12-1503.55"
   wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
-  attribute \src "ls180.v:1454.12-1454.59"
+  attribute \src "ls180.v:1499.12-1499.59"
   wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
-  attribute \src "ls180.v:1465.12-1465.55"
+  attribute \src "ls180.v:1510.12-1510.55"
   wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
-  attribute \src "ls180.v:1461.12-1461.59"
+  attribute \src "ls180.v:1506.12-1506.59"
   wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
-  attribute \src "ls180.v:1472.12-1472.55"
+  attribute \src "ls180.v:1517.12-1517.55"
   wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
-  attribute \src "ls180.v:1468.12-1468.59"
+  attribute \src "ls180.v:1513.12-1513.59"
   wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
-  attribute \src "ls180.v:1479.12-1479.55"
+  attribute \src "ls180.v:1524.12-1524.55"
   wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
-  attribute \src "ls180.v:1475.12-1475.59"
+  attribute \src "ls180.v:1520.12-1520.59"
   wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:1482.12-1482.54"
+  attribute \src "ls180.v:1527.12-1527.54"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
-  attribute \src "ls180.v:1821.12-1821.93"
+  attribute \src "ls180.v:1866.12-1866.93"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
-  attribute \src "ls180.v:1822.5-1822.88"
+  attribute \src "ls180.v:1867.5-1867.88"
   wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
-  attribute \src "ls180.v:1483.12-1483.54"
+  attribute \src "ls180.v:1528.12-1528.54"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
-  attribute \src "ls180.v:1823.12-1823.93"
+  attribute \src "ls180.v:1868.12-1868.93"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
-  attribute \src "ls180.v:1824.5-1824.88"
+  attribute \src "ls180.v:1869.5-1869.88"
   wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
-  attribute \src "ls180.v:1484.12-1484.54"
+  attribute \src "ls180.v:1529.12-1529.54"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
-  attribute \src "ls180.v:1825.12-1825.93"
+  attribute \src "ls180.v:1870.12-1870.93"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
-  attribute \src "ls180.v:1826.5-1826.88"
+  attribute \src "ls180.v:1871.5-1871.88"
   wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
-  attribute \src "ls180.v:1485.12-1485.54"
+  attribute \src "ls180.v:1530.12-1530.54"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
-  attribute \src "ls180.v:1827.12-1827.93"
+  attribute \src "ls180.v:1872.12-1872.93"
   wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
-  attribute \src "ls180.v:1828.5-1828.88"
+  attribute \src "ls180.v:1873.5-1873.88"
   wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
-  attribute \src "ls180.v:1444.5-1444.49"
+  attribute \src "ls180.v:1489.5-1489.49"
   wire $1\main_sdcore_crc16_inserter_sink_ready[0:0]
-  attribute \src "ls180.v:1451.5-1451.50"
+  attribute \src "ls180.v:1496.5-1496.50"
   wire $1\main_sdcore_crc16_inserter_source_last[0:0]
-  attribute \src "ls180.v:1452.11-1452.64"
+  attribute \src "ls180.v:1497.11-1497.64"
   wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
-  attribute \src "ls180.v:1449.5-1449.51"
+  attribute \src "ls180.v:1494.5-1494.51"
   wire $1\main_sdcore_crc16_inserter_source_ready[0:0]
-  attribute \src "ls180.v:1448.5-1448.51"
+  attribute \src "ls180.v:1493.5-1493.51"
   wire $1\main_sdcore_crc16_inserter_source_valid[0:0]
-  attribute \src "ls180.v:1440.11-1440.47"
+  attribute \src "ls180.v:1485.11-1485.47"
   wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0]
-  attribute \src "ls180.v:1398.11-1398.51"
+  attribute \src "ls180.v:1443.11-1443.51"
   wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
-  attribute \src "ls180.v:1541.12-1541.42"
+  attribute \src "ls180.v:1586.12-1586.42"
   wire width 32 $1\main_sdcore_data_count[31:0]
-  attribute \src "ls180.v:1839.12-1839.65"
+  attribute \src "ls180.v:1884.12-1884.65"
   wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
-  attribute \src "ls180.v:1840.5-1840.60"
+  attribute \src "ls180.v:1885.5-1885.60"
   wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
-  attribute \src "ls180.v:1542.5-1542.33"
+  attribute \src "ls180.v:1587.5-1587.33"
   wire $1\main_sdcore_data_done[0:0]
-  attribute \src "ls180.v:1835.5-1835.56"
+  attribute \src "ls180.v:1880.5-1880.56"
   wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
-  attribute \src "ls180.v:1836.5-1836.59"
+  attribute \src "ls180.v:1881.5-1881.59"
   wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
-  attribute \src "ls180.v:1543.5-1543.34"
+  attribute \src "ls180.v:1588.5-1588.34"
   wire $1\main_sdcore_data_error[0:0]
-  attribute \src "ls180.v:1845.5-1845.57"
+  attribute \src "ls180.v:1890.5-1890.57"
   wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
-  attribute \src "ls180.v:1846.5-1846.60"
+  attribute \src "ls180.v:1891.5-1891.60"
   wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
-  attribute \src "ls180.v:1544.5-1544.36"
+  attribute \src "ls180.v:1589.5-1589.36"
   wire $1\main_sdcore_data_timeout[0:0]
-  attribute \src "ls180.v:1847.5-1847.59"
+  attribute \src "ls180.v:1892.5-1892.59"
   wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
-  attribute \src "ls180.v:1848.5-1848.62"
+  attribute \src "ls180.v:1893.5-1893.62"
   wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
-  attribute \src "ls180.v:1689.11-1689.48"
+  attribute \src "ls180.v:1734.11-1734.48"
   wire width 2 $1\main_sdmem2block_converter_mux[1:0]
-  attribute \src "ls180.v:1687.11-1687.64"
+  attribute \src "ls180.v:1732.11-1732.64"
   wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:1663.5-1663.40"
+  attribute \src "ls180.v:1708.5-1708.40"
   wire $1\main_sdmem2block_dma_base_re[0:0]
-  attribute \src "ls180.v:1662.12-1662.53"
+  attribute \src "ls180.v:1707.12-1707.53"
   wire width 64 $1\main_sdmem2block_dma_base_storage[63:0]
-  attribute \src "ls180.v:1661.12-1661.45"
+  attribute \src "ls180.v:1706.12-1706.45"
   wire width 32 $1\main_sdmem2block_dma_data[31:0]
-  attribute \src "ls180.v:1857.12-1857.75"
+  attribute \src "ls180.v:1902.12-1902.75"
   wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
-  attribute \src "ls180.v:1858.5-1858.70"
+  attribute \src "ls180.v:1903.5-1903.70"
   wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
-  attribute \src "ls180.v:1668.5-1668.44"
+  attribute \src "ls180.v:1713.5-1713.44"
   wire $1\main_sdmem2block_dma_done_status[0:0]
-  attribute \src "ls180.v:1667.5-1667.42"
+  attribute \src "ls180.v:1712.5-1712.42"
   wire $1\main_sdmem2block_dma_enable_re[0:0]
-  attribute \src "ls180.v:1666.5-1666.47"
+  attribute \src "ls180.v:1711.5-1711.47"
   wire $1\main_sdmem2block_dma_enable_storage[0:0]
-  attribute \src "ls180.v:1665.5-1665.42"
+  attribute \src "ls180.v:1710.5-1710.42"
   wire $1\main_sdmem2block_dma_length_re[0:0]
-  attribute \src "ls180.v:1664.12-1664.55"
+  attribute \src "ls180.v:1709.12-1709.55"
   wire width 32 $1\main_sdmem2block_dma_length_storage[31:0]
-  attribute \src "ls180.v:1671.5-1671.40"
+  attribute \src "ls180.v:1716.5-1716.40"
   wire $1\main_sdmem2block_dma_loop_re[0:0]
-  attribute \src "ls180.v:1670.5-1670.45"
+  attribute \src "ls180.v:1715.5-1715.45"
   wire $1\main_sdmem2block_dma_loop_storage[0:0]
-  attribute \src "ls180.v:1675.12-1675.47"
+  attribute \src "ls180.v:1720.12-1720.47"
   wire width 32 $1\main_sdmem2block_dma_offset[31:0]
-  attribute \src "ls180.v:1861.12-1861.87"
+  attribute \src "ls180.v:1906.12-1906.87"
   wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
-  attribute \src "ls180.v:1862.5-1862.82"
+  attribute \src "ls180.v:1907.5-1907.82"
   wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
-  attribute \src "ls180.v:1654.5-1654.42"
+  attribute \src "ls180.v:1699.5-1699.42"
   wire $1\main_sdmem2block_dma_sink_last[0:0]
-  attribute \src "ls180.v:1655.12-1655.61"
+  attribute \src "ls180.v:1700.12-1700.61"
   wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0]
-  attribute \src "ls180.v:1653.5-1653.43"
+  attribute \src "ls180.v:1698.5-1698.43"
   wire $1\main_sdmem2block_dma_sink_ready[0:0]
-  attribute \src "ls180.v:1652.5-1652.43"
+  attribute \src "ls180.v:1697.5-1697.43"
   wire $1\main_sdmem2block_dma_sink_valid[0:0]
-  attribute \src "ls180.v:1659.5-1659.44"
+  attribute \src "ls180.v:1704.5-1704.44"
   wire $1\main_sdmem2block_dma_source_last[0:0]
-  attribute \src "ls180.v:1660.12-1660.60"
+  attribute \src "ls180.v:1705.12-1705.60"
   wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0]
-  attribute \src "ls180.v:1656.5-1656.45"
+  attribute \src "ls180.v:1701.5-1701.45"
   wire $1\main_sdmem2block_dma_source_valid[0:0]
-  attribute \src "ls180.v:1716.11-1716.47"
+  attribute \src "ls180.v:1761.11-1761.47"
   wire width 5 $1\main_sdmem2block_fifo_consume[4:0]
-  attribute \src "ls180.v:1713.11-1713.45"
+  attribute \src "ls180.v:1758.11-1758.45"
   wire width 6 $1\main_sdmem2block_fifo_level[5:0]
-  attribute \src "ls180.v:1715.11-1715.47"
+  attribute \src "ls180.v:1760.11-1760.47"
   wire width 5 $1\main_sdmem2block_fifo_produce[4:0]
-  attribute \src "ls180.v:1717.11-1717.50"
+  attribute \src "ls180.v:1762.11-1762.50"
   wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0]
-  attribute \src "ls180.v:1097.5-1097.35"
+  attribute \src "ls180.v:1142.5-1142.35"
   wire $1\main_sdphy_clocker_clk0[0:0]
-  attribute \src "ls180.v:1100.5-1100.35"
+  attribute \src "ls180.v:1145.5-1145.35"
   wire $1\main_sdphy_clocker_clk1[0:0]
-  attribute \src "ls180.v:1101.5-1101.36"
+  attribute \src "ls180.v:1146.5-1146.36"
   wire $1\main_sdphy_clocker_clk_d[0:0]
-  attribute \src "ls180.v:1099.11-1099.41"
+  attribute \src "ls180.v:1144.11-1144.41"
   wire width 9 $1\main_sdphy_clocker_clks[8:0]
-  attribute \src "ls180.v:1095.5-1095.33"
+  attribute \src "ls180.v:1140.5-1140.33"
   wire $1\main_sdphy_clocker_re[0:0]
-  attribute \src "ls180.v:1094.11-1094.46"
+  attribute \src "ls180.v:1139.11-1139.46"
   wire width 9 $1\main_sdphy_clocker_storage[8:0]
-  attribute \src "ls180.v:1203.5-1203.49"
+  attribute \src "ls180.v:1248.5-1248.49"
   wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
-  attribute \src "ls180.v:1204.5-1204.48"
+  attribute \src "ls180.v:1249.5-1249.48"
   wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
-  attribute \src "ls180.v:1205.11-1205.62"
+  attribute \src "ls180.v:1250.11-1250.62"
   wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:1201.5-1201.49"
+  attribute \src "ls180.v:1246.5-1246.49"
   wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
-  attribute \src "ls180.v:1188.11-1188.54"
+  attribute \src "ls180.v:1233.11-1233.54"
   wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
-  attribute \src "ls180.v:1184.5-1184.55"
+  attribute \src "ls180.v:1229.5-1229.55"
   wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
-  attribute \src "ls180.v:1185.5-1185.54"
+  attribute \src "ls180.v:1230.5-1230.54"
   wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
-  attribute \src "ls180.v:1186.11-1186.68"
+  attribute \src "ls180.v:1231.11-1231.68"
   wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:1187.11-1187.81"
+  attribute \src "ls180.v:1232.11-1232.81"
   wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:1190.5-1190.53"
+  attribute \src "ls180.v:1235.5-1235.53"
   wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1206.5-1206.38"
+  attribute \src "ls180.v:1251.5-1251.38"
   wire $1\main_sdphy_cmdr_cmdr_reset[0:0]
-  attribute \src "ls180.v:1801.5-1801.66"
+  attribute \src "ls180.v:1846.5-1846.66"
   wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
-  attribute \src "ls180.v:1802.5-1802.69"
+  attribute \src "ls180.v:1847.5-1847.69"
   wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
-  attribute \src "ls180.v:1176.5-1176.36"
+  attribute \src "ls180.v:1221.5-1221.36"
   wire $1\main_sdphy_cmdr_cmdr_run[0:0]
-  attribute \src "ls180.v:1171.5-1171.53"
+  attribute \src "ls180.v:1216.5-1216.53"
   wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
-  attribute \src "ls180.v:1158.11-1158.39"
+  attribute \src "ls180.v:1203.11-1203.39"
   wire width 8 $1\main_sdphy_cmdr_count[7:0]
-  attribute \src "ls180.v:1797.11-1797.67"
+  attribute \src "ls180.v:1842.11-1842.67"
   wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
-  attribute \src "ls180.v:1798.5-1798.64"
+  attribute \src "ls180.v:1843.5-1843.64"
   wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
-  attribute \src "ls180.v:1143.5-1143.48"
+  attribute \src "ls180.v:1188.5-1188.48"
   wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1144.5-1144.50"
+  attribute \src "ls180.v:1189.5-1189.50"
   wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1145.5-1145.51"
+  attribute \src "ls180.v:1190.5-1190.51"
   wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1150.5-1150.37"
+  attribute \src "ls180.v:1195.5-1195.37"
   wire $1\main_sdphy_cmdr_sink_last[0:0]
-  attribute \src "ls180.v:1151.11-1151.53"
+  attribute \src "ls180.v:1196.11-1196.53"
   wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0]
-  attribute \src "ls180.v:1149.5-1149.38"
+  attribute \src "ls180.v:1194.5-1194.38"
   wire $1\main_sdphy_cmdr_sink_ready[0:0]
-  attribute \src "ls180.v:1148.5-1148.38"
+  attribute \src "ls180.v:1193.5-1193.38"
   wire $1\main_sdphy_cmdr_sink_valid[0:0]
-  attribute \src "ls180.v:1154.5-1154.39"
+  attribute \src "ls180.v:1199.5-1199.39"
   wire $1\main_sdphy_cmdr_source_last[0:0]
-  attribute \src "ls180.v:1155.11-1155.53"
+  attribute \src "ls180.v:1200.11-1200.53"
   wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0]
-  attribute \src "ls180.v:1156.11-1156.55"
+  attribute \src "ls180.v:1201.11-1201.55"
   wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0]
-  attribute \src "ls180.v:1153.5-1153.40"
+  attribute \src "ls180.v:1198.5-1198.40"
   wire $1\main_sdphy_cmdr_source_ready[0:0]
-  attribute \src "ls180.v:1152.5-1152.40"
+  attribute \src "ls180.v:1197.5-1197.40"
   wire $1\main_sdphy_cmdr_source_valid[0:0]
-  attribute \src "ls180.v:1157.12-1157.48"
+  attribute \src "ls180.v:1202.12-1202.48"
   wire width 32 $1\main_sdphy_cmdr_timeout[31:0]
-  attribute \src "ls180.v:1799.12-1799.71"
+  attribute \src "ls180.v:1844.12-1844.71"
   wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
-  attribute \src "ls180.v:1800.5-1800.66"
+  attribute \src "ls180.v:1845.5-1845.66"
   wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
-  attribute \src "ls180.v:1130.11-1130.39"
+  attribute \src "ls180.v:1175.11-1175.39"
   wire width 8 $1\main_sdphy_cmdw_count[7:0]
-  attribute \src "ls180.v:1793.11-1793.66"
+  attribute \src "ls180.v:1838.11-1838.66"
   wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
-  attribute \src "ls180.v:1794.5-1794.63"
+  attribute \src "ls180.v:1839.5-1839.63"
   wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
-  attribute \src "ls180.v:1129.5-1129.32"
+  attribute \src "ls180.v:1174.5-1174.32"
   wire $1\main_sdphy_cmdw_done[0:0]
-  attribute \src "ls180.v:1120.5-1120.48"
+  attribute \src "ls180.v:1165.5-1165.48"
   wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1121.5-1121.50"
+  attribute \src "ls180.v:1166.5-1166.50"
   wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1122.5-1122.51"
+  attribute \src "ls180.v:1167.5-1167.51"
   wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1127.5-1127.37"
+  attribute \src "ls180.v:1172.5-1172.37"
   wire $1\main_sdphy_cmdw_sink_last[0:0]
-  attribute \src "ls180.v:1128.11-1128.51"
+  attribute \src "ls180.v:1173.11-1173.51"
   wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0]
-  attribute \src "ls180.v:1126.5-1126.38"
+  attribute \src "ls180.v:1171.5-1171.38"
   wire $1\main_sdphy_cmdw_sink_ready[0:0]
-  attribute \src "ls180.v:1125.5-1125.38"
+  attribute \src "ls180.v:1170.5-1170.38"
   wire $1\main_sdphy_cmdw_sink_valid[0:0]
-  attribute \src "ls180.v:1314.11-1314.41"
+  attribute \src "ls180.v:1359.11-1359.41"
   wire width 10 $1\main_sdphy_datar_count[9:0]
-  attribute \src "ls180.v:1813.11-1813.70"
+  attribute \src "ls180.v:1858.11-1858.70"
   wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
-  attribute \src "ls180.v:1814.5-1814.66"
+  attribute \src "ls180.v:1859.5-1859.66"
   wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
-  attribute \src "ls180.v:1359.5-1359.51"
+  attribute \src "ls180.v:1404.5-1404.51"
   wire $1\main_sdphy_datar_datar_buf_source_first[0:0]
-  attribute \src "ls180.v:1360.5-1360.50"
+  attribute \src "ls180.v:1405.5-1405.50"
   wire $1\main_sdphy_datar_datar_buf_source_last[0:0]
-  attribute \src "ls180.v:1361.11-1361.64"
+  attribute \src "ls180.v:1406.11-1406.64"
   wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:1357.5-1357.51"
+  attribute \src "ls180.v:1402.5-1402.51"
   wire $1\main_sdphy_datar_datar_buf_source_valid[0:0]
-  attribute \src "ls180.v:1344.5-1344.50"
+  attribute \src "ls180.v:1389.5-1389.50"
   wire $1\main_sdphy_datar_datar_converter_demux[0:0]
-  attribute \src "ls180.v:1340.5-1340.57"
+  attribute \src "ls180.v:1385.5-1385.57"
   wire $1\main_sdphy_datar_datar_converter_source_first[0:0]
-  attribute \src "ls180.v:1341.5-1341.56"
+  attribute \src "ls180.v:1386.5-1386.56"
   wire $1\main_sdphy_datar_datar_converter_source_last[0:0]
-  attribute \src "ls180.v:1342.11-1342.70"
+  attribute \src "ls180.v:1387.11-1387.70"
   wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:1343.11-1343.83"
+  attribute \src "ls180.v:1388.11-1388.83"
   wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
-  attribute \src "ls180.v:1346.5-1346.55"
+  attribute \src "ls180.v:1391.5-1391.55"
   wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1362.5-1362.40"
+  attribute \src "ls180.v:1407.5-1407.40"
   wire $1\main_sdphy_datar_datar_reset[0:0]
-  attribute \src "ls180.v:1817.5-1817.69"
+  attribute \src "ls180.v:1862.5-1862.69"
   wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
-  attribute \src "ls180.v:1818.5-1818.72"
+  attribute \src "ls180.v:1863.5-1863.72"
   wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
-  attribute \src "ls180.v:1332.5-1332.38"
+  attribute \src "ls180.v:1377.5-1377.38"
   wire $1\main_sdphy_datar_datar_run[0:0]
-  attribute \src "ls180.v:1327.5-1327.55"
+  attribute \src "ls180.v:1372.5-1372.55"
   wire $1\main_sdphy_datar_datar_source_source_ready0[0:0]
-  attribute \src "ls180.v:1297.5-1297.49"
+  attribute \src "ls180.v:1342.5-1342.49"
   wire $1\main_sdphy_datar_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1304.5-1304.38"
+  attribute \src "ls180.v:1349.5-1349.38"
   wire $1\main_sdphy_datar_sink_last[0:0]
-  attribute \src "ls180.v:1305.11-1305.61"
+  attribute \src "ls180.v:1350.11-1350.61"
   wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0]
-  attribute \src "ls180.v:1303.5-1303.39"
+  attribute \src "ls180.v:1348.5-1348.39"
   wire $1\main_sdphy_datar_sink_ready[0:0]
-  attribute \src "ls180.v:1302.5-1302.39"
+  attribute \src "ls180.v:1347.5-1347.39"
   wire $1\main_sdphy_datar_sink_valid[0:0]
-  attribute \src "ls180.v:1309.5-1309.40"
+  attribute \src "ls180.v:1354.5-1354.40"
   wire $1\main_sdphy_datar_source_last[0:0]
-  attribute \src "ls180.v:1310.11-1310.54"
+  attribute \src "ls180.v:1355.11-1355.54"
   wire width 8 $1\main_sdphy_datar_source_payload_data[7:0]
-  attribute \src "ls180.v:1311.11-1311.56"
+  attribute \src "ls180.v:1356.11-1356.56"
   wire width 3 $1\main_sdphy_datar_source_payload_status[2:0]
-  attribute \src "ls180.v:1307.5-1307.41"
+  attribute \src "ls180.v:1352.5-1352.41"
   wire $1\main_sdphy_datar_source_ready[0:0]
-  attribute \src "ls180.v:1306.5-1306.41"
+  attribute \src "ls180.v:1351.5-1351.41"
   wire $1\main_sdphy_datar_source_valid[0:0]
-  attribute \src "ls180.v:1312.5-1312.33"
+  attribute \src "ls180.v:1357.5-1357.33"
   wire $1\main_sdphy_datar_stop[0:0]
-  attribute \src "ls180.v:1313.12-1313.49"
+  attribute \src "ls180.v:1358.12-1358.49"
   wire width 32 $1\main_sdphy_datar_timeout[31:0]
-  attribute \src "ls180.v:1815.12-1815.73"
+  attribute \src "ls180.v:1860.12-1860.73"
   wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
-  attribute \src "ls180.v:1816.5-1816.68"
+  attribute \src "ls180.v:1861.5-1861.68"
   wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
-  attribute \src "ls180.v:1222.11-1222.40"
+  attribute \src "ls180.v:1267.11-1267.40"
   wire width 8 $1\main_sdphy_dataw_count[7:0]
-  attribute \src "ls180.v:1809.11-1809.61"
+  attribute \src "ls180.v:1854.11-1854.61"
   wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
-  attribute \src "ls180.v:1810.5-1810.58"
+  attribute \src "ls180.v:1855.5-1855.58"
   wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
-  attribute \src "ls180.v:1281.5-1281.50"
+  attribute \src "ls180.v:1326.5-1326.50"
   wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
-  attribute \src "ls180.v:1282.5-1282.49"
+  attribute \src "ls180.v:1327.5-1327.49"
   wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
-  attribute \src "ls180.v:1283.11-1283.63"
+  attribute \src "ls180.v:1328.11-1328.63"
   wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:1279.5-1279.50"
+  attribute \src "ls180.v:1324.5-1324.50"
   wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
-  attribute \src "ls180.v:1266.11-1266.55"
+  attribute \src "ls180.v:1311.11-1311.55"
   wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0]
-  attribute \src "ls180.v:1262.5-1262.56"
+  attribute \src "ls180.v:1307.5-1307.56"
   wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
-  attribute \src "ls180.v:1263.5-1263.55"
+  attribute \src "ls180.v:1308.5-1308.55"
   wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
-  attribute \src "ls180.v:1264.11-1264.69"
+  attribute \src "ls180.v:1309.11-1309.69"
   wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:1265.11-1265.82"
+  attribute \src "ls180.v:1310.11-1310.82"
   wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:1268.5-1268.54"
+  attribute \src "ls180.v:1313.5-1313.54"
   wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
-  attribute \src "ls180.v:1284.5-1284.39"
+  attribute \src "ls180.v:1329.5-1329.39"
   wire $1\main_sdphy_dataw_crcr_reset[0:0]
-  attribute \src "ls180.v:1805.5-1805.66"
+  attribute \src "ls180.v:1850.5-1850.66"
   wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
-  attribute \src "ls180.v:1806.5-1806.69"
+  attribute \src "ls180.v:1851.5-1851.69"
   wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
-  attribute \src "ls180.v:1254.5-1254.37"
+  attribute \src "ls180.v:1299.5-1299.37"
   wire $1\main_sdphy_dataw_crcr_run[0:0]
-  attribute \src "ls180.v:1249.5-1249.54"
+  attribute \src "ls180.v:1294.5-1294.54"
   wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
-  attribute \src "ls180.v:1236.5-1236.34"
+  attribute \src "ls180.v:1281.5-1281.34"
   wire $1\main_sdphy_dataw_error[0:0]
-  attribute \src "ls180.v:1211.5-1211.49"
+  attribute \src "ls180.v:1256.5-1256.49"
   wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1214.11-1214.58"
+  attribute \src "ls180.v:1259.11-1259.58"
   wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:1215.5-1215.53"
+  attribute \src "ls180.v:1260.5-1260.53"
   wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:1218.5-1218.39"
+  attribute \src "ls180.v:1263.5-1263.39"
   wire $1\main_sdphy_dataw_sink_first[0:0]
-  attribute \src "ls180.v:1219.5-1219.38"
+  attribute \src "ls180.v:1264.5-1264.38"
   wire $1\main_sdphy_dataw_sink_last[0:0]
-  attribute \src "ls180.v:1220.11-1220.52"
+  attribute \src "ls180.v:1265.11-1265.52"
   wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0]
-  attribute \src "ls180.v:1217.5-1217.39"
+  attribute \src "ls180.v:1262.5-1262.39"
   wire $1\main_sdphy_dataw_sink_ready[0:0]
-  attribute \src "ls180.v:1216.5-1216.39"
+  attribute \src "ls180.v:1261.5-1261.39"
   wire $1\main_sdphy_dataw_sink_valid[0:0]
-  attribute \src "ls180.v:1234.5-1234.34"
+  attribute \src "ls180.v:1279.5-1279.34"
   wire $1\main_sdphy_dataw_start[0:0]
-  attribute \src "ls180.v:1221.5-1221.33"
+  attribute \src "ls180.v:1266.5-1266.33"
   wire $1\main_sdphy_dataw_stop[0:0]
-  attribute \src "ls180.v:1235.5-1235.34"
+  attribute \src "ls180.v:1280.5-1280.34"
   wire $1\main_sdphy_dataw_valid[0:0]
-  attribute \src "ls180.v:1115.11-1115.39"
+  attribute \src "ls180.v:1160.11-1160.39"
   wire width 8 $1\main_sdphy_init_count[7:0]
-  attribute \src "ls180.v:1789.11-1789.66"
+  attribute \src "ls180.v:1834.11-1834.66"
   wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
-  attribute \src "ls180.v:1790.5-1790.63"
+  attribute \src "ls180.v:1835.5-1835.63"
   wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
-  attribute \src "ls180.v:1110.5-1110.48"
+  attribute \src "ls180.v:1155.5-1155.48"
   wire $1\main_sdphy_init_pads_out_payload_clk[0:0]
-  attribute \src "ls180.v:1111.5-1111.50"
+  attribute \src "ls180.v:1156.5-1156.50"
   wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
-  attribute \src "ls180.v:1112.5-1112.51"
+  attribute \src "ls180.v:1157.5-1157.51"
   wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
-  attribute \src "ls180.v:1113.11-1113.57"
+  attribute \src "ls180.v:1158.11-1158.57"
   wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0]
-  attribute \src "ls180.v:1114.5-1114.52"
+  attribute \src "ls180.v:1159.5-1159.52"
   wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
-  attribute \src "ls180.v:1364.5-1364.35"
+  attribute \src "ls180.v:1409.5-1409.35"
   wire $1\main_sdphy_sdpads_cmd_i[0:0]
-  attribute \src "ls180.v:1367.11-1367.42"
+  attribute \src "ls180.v:1412.11-1412.42"
   wire width 4 $1\main_sdphy_sdpads_data_i[3:0]
-  attribute \src "ls180.v:327.5-327.33"
+  attribute \src "ls180.v:372.5-372.33"
   wire $1\main_sdram_address_re[0:0]
-  attribute \src "ls180.v:326.12-326.46"
+  attribute \src "ls180.v:371.12-371.46"
   wire width 13 $1\main_sdram_address_storage[12:0]
-  attribute \src "ls180.v:329.5-329.34"
+  attribute \src "ls180.v:374.5-374.34"
   wire $1\main_sdram_baddress_re[0:0]
-  attribute \src "ls180.v:328.11-328.45"
+  attribute \src "ls180.v:373.11-373.45"
   wire width 2 $1\main_sdram_baddress_storage[1:0]
-  attribute \src "ls180.v:425.5-425.50"
+  attribute \src "ls180.v:470.5-470.50"
   wire $1\main_sdram_bankmachine0_auto_precharge[0:0]
-  attribute \src "ls180.v:447.11-447.70"
+  attribute \src "ls180.v:492.11-492.70"
   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:444.11-444.68"
+  attribute \src "ls180.v:489.11-489.68"
   wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:446.11-446.70"
+  attribute \src "ls180.v:491.11-491.70"
   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:448.11-448.73"
+  attribute \src "ls180.v:493.11-493.73"
   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:471.5-471.59"
+  attribute \src "ls180.v:516.5-516.59"
   wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:472.5-472.58"
+  attribute \src "ls180.v:517.5-517.58"
   wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:474.12-474.74"
+  attribute \src "ls180.v:519.12-519.74"
   wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:473.5-473.64"
+  attribute \src "ls180.v:518.5-518.64"
   wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:469.5-469.59"
+  attribute \src "ls180.v:514.5-514.59"
   wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:417.12-417.57"
+  attribute \src "ls180.v:462.12-462.57"
   wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
-  attribute \src "ls180.v:419.5-419.51"
+  attribute \src "ls180.v:464.5-464.51"
   wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:422.5-422.54"
+  attribute \src "ls180.v:467.5-467.54"
   wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:423.5-423.55"
+  attribute \src "ls180.v:468.5-468.55"
   wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:424.5-424.56"
+  attribute \src "ls180.v:469.5-469.56"
   wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:420.5-420.51"
+  attribute \src "ls180.v:465.5-465.51"
   wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:421.5-421.50"
+  attribute \src "ls180.v:466.5-466.50"
   wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
-  attribute \src "ls180.v:416.5-416.45"
+  attribute \src "ls180.v:461.5-461.45"
   wire $1\main_sdram_bankmachine0_cmd_ready[0:0]
-  attribute \src "ls180.v:415.5-415.45"
+  attribute \src "ls180.v:460.5-460.45"
   wire $1\main_sdram_bankmachine0_cmd_valid[0:0]
-  attribute \src "ls180.v:414.5-414.47"
+  attribute \src "ls180.v:459.5-459.47"
   wire $1\main_sdram_bankmachine0_refresh_gnt[0:0]
-  attribute \src "ls180.v:412.5-412.51"
+  attribute \src "ls180.v:457.5-457.51"
   wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
-  attribute \src "ls180.v:411.5-411.51"
+  attribute \src "ls180.v:456.5-456.51"
   wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
-  attribute \src "ls180.v:475.12-475.47"
+  attribute \src "ls180.v:520.12-520.47"
   wire width 13 $1\main_sdram_bankmachine0_row[12:0]
-  attribute \src "ls180.v:479.5-479.45"
+  attribute \src "ls180.v:524.5-524.45"
   wire $1\main_sdram_bankmachine0_row_close[0:0]
-  attribute \src "ls180.v:480.5-480.54"
+  attribute \src "ls180.v:525.5-525.54"
   wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:478.5-478.44"
+  attribute \src "ls180.v:523.5-523.44"
   wire $1\main_sdram_bankmachine0_row_open[0:0]
-  attribute \src "ls180.v:476.5-476.46"
+  attribute \src "ls180.v:521.5-521.46"
   wire $1\main_sdram_bankmachine0_row_opened[0:0]
-  attribute \src "ls180.v:483.11-483.55"
+  attribute \src "ls180.v:528.11-528.55"
   wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0]
-  attribute \src "ls180.v:482.32-482.76"
+  attribute \src "ls180.v:527.32-527.76"
   wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
-  attribute \src "ls180.v:507.5-507.50"
+  attribute \src "ls180.v:552.5-552.50"
   wire $1\main_sdram_bankmachine1_auto_precharge[0:0]
-  attribute \src "ls180.v:529.11-529.70"
+  attribute \src "ls180.v:574.11-574.70"
   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:526.11-526.68"
+  attribute \src "ls180.v:571.11-571.68"
   wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:528.11-528.70"
+  attribute \src "ls180.v:573.11-573.70"
   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:530.11-530.73"
+  attribute \src "ls180.v:575.11-575.73"
   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:553.5-553.59"
+  attribute \src "ls180.v:598.5-598.59"
   wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:554.5-554.58"
+  attribute \src "ls180.v:599.5-599.58"
   wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:556.12-556.74"
+  attribute \src "ls180.v:601.12-601.74"
   wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:555.5-555.64"
+  attribute \src "ls180.v:600.5-600.64"
   wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:551.5-551.59"
+  attribute \src "ls180.v:596.5-596.59"
   wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:499.12-499.57"
+  attribute \src "ls180.v:544.12-544.57"
   wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
-  attribute \src "ls180.v:501.5-501.51"
+  attribute \src "ls180.v:546.5-546.51"
   wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:504.5-504.54"
+  attribute \src "ls180.v:549.5-549.54"
   wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:505.5-505.55"
+  attribute \src "ls180.v:550.5-550.55"
   wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:506.5-506.56"
+  attribute \src "ls180.v:551.5-551.56"
   wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:502.5-502.51"
+  attribute \src "ls180.v:547.5-547.51"
   wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:503.5-503.50"
+  attribute \src "ls180.v:548.5-548.50"
   wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
-  attribute \src "ls180.v:498.5-498.45"
+  attribute \src "ls180.v:543.5-543.45"
   wire $1\main_sdram_bankmachine1_cmd_ready[0:0]
-  attribute \src "ls180.v:497.5-497.45"
+  attribute \src "ls180.v:542.5-542.45"
   wire $1\main_sdram_bankmachine1_cmd_valid[0:0]
-  attribute \src "ls180.v:496.5-496.47"
+  attribute \src "ls180.v:541.5-541.47"
   wire $1\main_sdram_bankmachine1_refresh_gnt[0:0]
-  attribute \src "ls180.v:494.5-494.51"
+  attribute \src "ls180.v:539.5-539.51"
   wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
-  attribute \src "ls180.v:493.5-493.51"
+  attribute \src "ls180.v:538.5-538.51"
   wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
-  attribute \src "ls180.v:557.12-557.47"
+  attribute \src "ls180.v:602.12-602.47"
   wire width 13 $1\main_sdram_bankmachine1_row[12:0]
-  attribute \src "ls180.v:561.5-561.45"
+  attribute \src "ls180.v:606.5-606.45"
   wire $1\main_sdram_bankmachine1_row_close[0:0]
-  attribute \src "ls180.v:562.5-562.54"
+  attribute \src "ls180.v:607.5-607.54"
   wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:560.5-560.44"
+  attribute \src "ls180.v:605.5-605.44"
   wire $1\main_sdram_bankmachine1_row_open[0:0]
-  attribute \src "ls180.v:558.5-558.46"
+  attribute \src "ls180.v:603.5-603.46"
   wire $1\main_sdram_bankmachine1_row_opened[0:0]
-  attribute \src "ls180.v:565.11-565.55"
+  attribute \src "ls180.v:610.11-610.55"
   wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0]
-  attribute \src "ls180.v:564.32-564.76"
+  attribute \src "ls180.v:609.32-609.76"
   wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
-  attribute \src "ls180.v:589.5-589.50"
+  attribute \src "ls180.v:634.5-634.50"
   wire $1\main_sdram_bankmachine2_auto_precharge[0:0]
-  attribute \src "ls180.v:611.11-611.70"
+  attribute \src "ls180.v:656.11-656.70"
   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:608.11-608.68"
+  attribute \src "ls180.v:653.11-653.68"
   wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:610.11-610.70"
+  attribute \src "ls180.v:655.11-655.70"
   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:612.11-612.73"
+  attribute \src "ls180.v:657.11-657.73"
   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:635.5-635.59"
+  attribute \src "ls180.v:680.5-680.59"
   wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:636.5-636.58"
+  attribute \src "ls180.v:681.5-681.58"
   wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:638.12-638.74"
+  attribute \src "ls180.v:683.12-683.74"
   wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:637.5-637.64"
+  attribute \src "ls180.v:682.5-682.64"
   wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:633.5-633.59"
+  attribute \src "ls180.v:678.5-678.59"
   wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:581.12-581.57"
+  attribute \src "ls180.v:626.12-626.57"
   wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
-  attribute \src "ls180.v:583.5-583.51"
+  attribute \src "ls180.v:628.5-628.51"
   wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:586.5-586.54"
+  attribute \src "ls180.v:631.5-631.54"
   wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:587.5-587.55"
+  attribute \src "ls180.v:632.5-632.55"
   wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:588.5-588.56"
+  attribute \src "ls180.v:633.5-633.56"
   wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:584.5-584.51"
+  attribute \src "ls180.v:629.5-629.51"
   wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:585.5-585.50"
+  attribute \src "ls180.v:630.5-630.50"
   wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
-  attribute \src "ls180.v:580.5-580.45"
+  attribute \src "ls180.v:625.5-625.45"
   wire $1\main_sdram_bankmachine2_cmd_ready[0:0]
-  attribute \src "ls180.v:579.5-579.45"
+  attribute \src "ls180.v:624.5-624.45"
   wire $1\main_sdram_bankmachine2_cmd_valid[0:0]
-  attribute \src "ls180.v:578.5-578.47"
+  attribute \src "ls180.v:623.5-623.47"
   wire $1\main_sdram_bankmachine2_refresh_gnt[0:0]
-  attribute \src "ls180.v:576.5-576.51"
+  attribute \src "ls180.v:621.5-621.51"
   wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
-  attribute \src "ls180.v:575.5-575.51"
+  attribute \src "ls180.v:620.5-620.51"
   wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
-  attribute \src "ls180.v:639.12-639.47"
+  attribute \src "ls180.v:684.12-684.47"
   wire width 13 $1\main_sdram_bankmachine2_row[12:0]
-  attribute \src "ls180.v:643.5-643.45"
+  attribute \src "ls180.v:688.5-688.45"
   wire $1\main_sdram_bankmachine2_row_close[0:0]
-  attribute \src "ls180.v:644.5-644.54"
+  attribute \src "ls180.v:689.5-689.54"
   wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:642.5-642.44"
+  attribute \src "ls180.v:687.5-687.44"
   wire $1\main_sdram_bankmachine2_row_open[0:0]
-  attribute \src "ls180.v:640.5-640.46"
+  attribute \src "ls180.v:685.5-685.46"
   wire $1\main_sdram_bankmachine2_row_opened[0:0]
-  attribute \src "ls180.v:647.11-647.55"
+  attribute \src "ls180.v:692.11-692.55"
   wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0]
-  attribute \src "ls180.v:646.32-646.76"
+  attribute \src "ls180.v:691.32-691.76"
   wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
-  attribute \src "ls180.v:671.5-671.50"
+  attribute \src "ls180.v:716.5-716.50"
   wire $1\main_sdram_bankmachine3_auto_precharge[0:0]
-  attribute \src "ls180.v:693.11-693.70"
+  attribute \src "ls180.v:738.11-738.70"
   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:690.11-690.68"
+  attribute \src "ls180.v:735.11-735.68"
   wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:692.11-692.70"
+  attribute \src "ls180.v:737.11-737.70"
   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:694.11-694.73"
+  attribute \src "ls180.v:739.11-739.73"
   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:717.5-717.59"
+  attribute \src "ls180.v:762.5-762.59"
   wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:718.5-718.58"
+  attribute \src "ls180.v:763.5-763.58"
   wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:720.12-720.74"
+  attribute \src "ls180.v:765.12-765.74"
   wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:719.5-719.64"
+  attribute \src "ls180.v:764.5-764.64"
   wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:715.5-715.59"
+  attribute \src "ls180.v:760.5-760.59"
   wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:663.12-663.57"
+  attribute \src "ls180.v:708.12-708.57"
   wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
-  attribute \src "ls180.v:665.5-665.51"
+  attribute \src "ls180.v:710.5-710.51"
   wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:668.5-668.54"
+  attribute \src "ls180.v:713.5-713.54"
   wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:669.5-669.55"
+  attribute \src "ls180.v:714.5-714.55"
   wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:670.5-670.56"
+  attribute \src "ls180.v:715.5-715.56"
   wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:666.5-666.51"
+  attribute \src "ls180.v:711.5-711.51"
   wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:667.5-667.50"
+  attribute \src "ls180.v:712.5-712.50"
   wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
-  attribute \src "ls180.v:662.5-662.45"
+  attribute \src "ls180.v:707.5-707.45"
   wire $1\main_sdram_bankmachine3_cmd_ready[0:0]
-  attribute \src "ls180.v:661.5-661.45"
+  attribute \src "ls180.v:706.5-706.45"
   wire $1\main_sdram_bankmachine3_cmd_valid[0:0]
-  attribute \src "ls180.v:660.5-660.47"
+  attribute \src "ls180.v:705.5-705.47"
   wire $1\main_sdram_bankmachine3_refresh_gnt[0:0]
-  attribute \src "ls180.v:658.5-658.51"
+  attribute \src "ls180.v:703.5-703.51"
   wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
-  attribute \src "ls180.v:657.5-657.51"
+  attribute \src "ls180.v:702.5-702.51"
   wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
-  attribute \src "ls180.v:721.12-721.47"
+  attribute \src "ls180.v:766.12-766.47"
   wire width 13 $1\main_sdram_bankmachine3_row[12:0]
-  attribute \src "ls180.v:725.5-725.45"
+  attribute \src "ls180.v:770.5-770.45"
   wire $1\main_sdram_bankmachine3_row_close[0:0]
-  attribute \src "ls180.v:726.5-726.54"
+  attribute \src "ls180.v:771.5-771.54"
   wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:724.5-724.44"
+  attribute \src "ls180.v:769.5-769.44"
   wire $1\main_sdram_bankmachine3_row_open[0:0]
-  attribute \src "ls180.v:722.5-722.46"
+  attribute \src "ls180.v:767.5-767.46"
   wire $1\main_sdram_bankmachine3_row_opened[0:0]
-  attribute \src "ls180.v:729.11-729.55"
+  attribute \src "ls180.v:774.11-774.55"
   wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0]
-  attribute \src "ls180.v:728.32-728.76"
+  attribute \src "ls180.v:773.32-773.76"
   wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
-  attribute \src "ls180.v:744.5-744.49"
+  attribute \src "ls180.v:789.5-789.49"
   wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:745.5-745.49"
+  attribute \src "ls180.v:790.5-790.49"
   wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:746.5-746.48"
+  attribute \src "ls180.v:791.5-791.48"
   wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
-  attribute \src "ls180.v:752.11-752.45"
+  attribute \src "ls180.v:797.11-797.45"
   wire width 2 $1\main_sdram_choose_cmd_grant[1:0]
-  attribute \src "ls180.v:750.11-750.46"
+  attribute \src "ls180.v:795.11-795.46"
   wire width 4 $1\main_sdram_choose_cmd_valids[3:0]
-  attribute \src "ls180.v:762.5-762.49"
+  attribute \src "ls180.v:807.5-807.49"
   wire $1\main_sdram_choose_req_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:763.5-763.49"
+  attribute \src "ls180.v:808.5-808.49"
   wire $1\main_sdram_choose_req_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:764.5-764.48"
+  attribute \src "ls180.v:809.5-809.48"
   wire $1\main_sdram_choose_req_cmd_payload_we[0:0]
-  attribute \src "ls180.v:759.5-759.43"
+  attribute \src "ls180.v:804.5-804.43"
   wire $1\main_sdram_choose_req_cmd_ready[0:0]
-  attribute \src "ls180.v:770.11-770.45"
+  attribute \src "ls180.v:815.11-815.45"
   wire width 2 $1\main_sdram_choose_req_grant[1:0]
-  attribute \src "ls180.v:768.11-768.46"
+  attribute \src "ls180.v:813.11-813.46"
   wire width 4 $1\main_sdram_choose_req_valids[3:0]
-  attribute \src "ls180.v:757.5-757.48"
+  attribute \src "ls180.v:802.5-802.48"
   wire $1\main_sdram_choose_req_want_activates[0:0]
-  attribute \src "ls180.v:754.5-754.44"
+  attribute \src "ls180.v:799.5-799.44"
   wire $1\main_sdram_choose_req_want_reads[0:0]
-  attribute \src "ls180.v:755.5-755.45"
+  attribute \src "ls180.v:800.5-800.45"
   wire $1\main_sdram_choose_req_want_writes[0:0]
-  attribute \src "ls180.v:383.5-383.31"
+  attribute \src "ls180.v:428.5-428.31"
   wire $1\main_sdram_cmd_last[0:0]
-  attribute \src "ls180.v:384.12-384.44"
+  attribute \src "ls180.v:429.12-429.44"
   wire width 13 $1\main_sdram_cmd_payload_a[12:0]
-  attribute \src "ls180.v:385.11-385.43"
+  attribute \src "ls180.v:430.11-430.43"
   wire width 2 $1\main_sdram_cmd_payload_ba[1:0]
-  attribute \src "ls180.v:386.5-386.38"
+  attribute \src "ls180.v:431.5-431.38"
   wire $1\main_sdram_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:387.5-387.38"
+  attribute \src "ls180.v:432.5-432.38"
   wire $1\main_sdram_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:388.5-388.37"
+  attribute \src "ls180.v:433.5-433.37"
   wire $1\main_sdram_cmd_payload_we[0:0]
-  attribute \src "ls180.v:382.5-382.32"
+  attribute \src "ls180.v:427.5-427.32"
   wire $1\main_sdram_cmd_ready[0:0]
-  attribute \src "ls180.v:381.5-381.32"
+  attribute \src "ls180.v:426.5-426.32"
   wire $1\main_sdram_cmd_valid[0:0]
-  attribute \src "ls180.v:321.5-321.33"
+  attribute \src "ls180.v:366.5-366.33"
   wire $1\main_sdram_command_re[0:0]
-  attribute \src "ls180.v:320.11-320.44"
+  attribute \src "ls180.v:365.11-365.44"
   wire width 6 $1\main_sdram_command_storage[5:0]
-  attribute \src "ls180.v:365.12-365.45"
+  attribute \src "ls180.v:410.12-410.45"
   wire width 13 $1\main_sdram_dfi_p0_address[12:0]
-  attribute \src "ls180.v:366.11-366.40"
+  attribute \src "ls180.v:411.11-411.40"
   wire width 2 $1\main_sdram_dfi_p0_bank[1:0]
-  attribute \src "ls180.v:367.5-367.35"
+  attribute \src "ls180.v:412.5-412.35"
   wire $1\main_sdram_dfi_p0_cas_n[0:0]
-  attribute \src "ls180.v:368.5-368.34"
+  attribute \src "ls180.v:413.5-413.34"
   wire $1\main_sdram_dfi_p0_cs_n[0:0]
-  attribute \src "ls180.v:369.5-369.35"
+  attribute \src "ls180.v:414.5-414.35"
   wire $1\main_sdram_dfi_p0_ras_n[0:0]
-  attribute \src "ls180.v:378.5-378.39"
+  attribute \src "ls180.v:423.5-423.39"
   wire $1\main_sdram_dfi_p0_rddata_en[0:0]
-  attribute \src "ls180.v:370.5-370.34"
+  attribute \src "ls180.v:415.5-415.34"
   wire $1\main_sdram_dfi_p0_we_n[0:0]
-  attribute \src "ls180.v:376.5-376.39"
+  attribute \src "ls180.v:421.5-421.39"
   wire $1\main_sdram_dfi_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:789.5-789.26"
+  attribute \src "ls180.v:834.5-834.26"
   wire $1\main_sdram_en0[0:0]
-  attribute \src "ls180.v:792.5-792.26"
+  attribute \src "ls180.v:837.5-837.26"
   wire $1\main_sdram_en1[0:0]
-  attribute \src "ls180.v:362.12-362.46"
+  attribute \src "ls180.v:407.12-407.46"
   wire width 16 $1\main_sdram_interface_wdata[15:0]
-  attribute \src "ls180.v:363.11-363.47"
+  attribute \src "ls180.v:408.11-408.47"
   wire width 2 $1\main_sdram_interface_wdata_we[1:0]
-  attribute \src "ls180.v:268.5-268.36"
+  attribute \src "ls180.v:313.5-313.36"
   wire $1\main_sdram_inti_p0_cas_n[0:0]
-  attribute \src "ls180.v:269.5-269.35"
+  attribute \src "ls180.v:314.5-314.35"
   wire $1\main_sdram_inti_p0_cs_n[0:0]
-  attribute \src "ls180.v:270.5-270.36"
+  attribute \src "ls180.v:315.5-315.36"
   wire $1\main_sdram_inti_p0_ras_n[0:0]
-  attribute \src "ls180.v:280.12-280.45"
+  attribute \src "ls180.v:325.12-325.45"
   wire width 16 $1\main_sdram_inti_p0_rddata[15:0]
-  attribute \src "ls180.v:281.5-281.43"
+  attribute \src "ls180.v:326.5-326.43"
   wire $1\main_sdram_inti_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:271.5-271.35"
+  attribute \src "ls180.v:316.5-316.35"
   wire $1\main_sdram_inti_p0_we_n[0:0]
-  attribute \src "ls180.v:307.5-307.38"
+  attribute \src "ls180.v:352.5-352.38"
   wire $1\main_sdram_master_p0_act_n[0:0]
-  attribute \src "ls180.v:298.12-298.48"
+  attribute \src "ls180.v:343.12-343.48"
   wire width 13 $1\main_sdram_master_p0_address[12:0]
-  attribute \src "ls180.v:299.11-299.43"
+  attribute \src "ls180.v:344.11-344.43"
   wire width 2 $1\main_sdram_master_p0_bank[1:0]
-  attribute \src "ls180.v:300.5-300.38"
+  attribute \src "ls180.v:345.5-345.38"
   wire $1\main_sdram_master_p0_cas_n[0:0]
-  attribute \src "ls180.v:304.5-304.36"
+  attribute \src "ls180.v:349.5-349.36"
   wire $1\main_sdram_master_p0_cke[0:0]
-  attribute \src "ls180.v:301.5-301.37"
+  attribute \src "ls180.v:346.5-346.37"
   wire $1\main_sdram_master_p0_cs_n[0:0]
-  attribute \src "ls180.v:305.5-305.36"
+  attribute \src "ls180.v:350.5-350.36"
   wire $1\main_sdram_master_p0_odt[0:0]
-  attribute \src "ls180.v:302.5-302.38"
+  attribute \src "ls180.v:347.5-347.38"
   wire $1\main_sdram_master_p0_ras_n[0:0]
-  attribute \src "ls180.v:311.5-311.42"
+  attribute \src "ls180.v:356.5-356.42"
   wire $1\main_sdram_master_p0_rddata_en[0:0]
-  attribute \src "ls180.v:306.5-306.40"
+  attribute \src "ls180.v:351.5-351.40"
   wire $1\main_sdram_master_p0_reset_n[0:0]
-  attribute \src "ls180.v:303.5-303.37"
+  attribute \src "ls180.v:348.5-348.37"
   wire $1\main_sdram_master_p0_we_n[0:0]
-  attribute \src "ls180.v:308.12-308.47"
+  attribute \src "ls180.v:353.12-353.47"
   wire width 16 $1\main_sdram_master_p0_wrdata[15:0]
-  attribute \src "ls180.v:309.5-309.42"
+  attribute \src "ls180.v:354.5-354.42"
   wire $1\main_sdram_master_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:310.11-310.50"
+  attribute \src "ls180.v:355.11-355.50"
   wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0]
-  attribute \src "ls180.v:399.5-399.38"
+  attribute \src "ls180.v:444.5-444.38"
   wire $1\main_sdram_postponer_count[0:0]
-  attribute \src "ls180.v:398.5-398.38"
+  attribute \src "ls180.v:443.5-443.38"
   wire $1\main_sdram_postponer_req_o[0:0]
-  attribute \src "ls180.v:319.5-319.25"
+  attribute \src "ls180.v:364.5-364.25"
   wire $1\main_sdram_re[0:0]
-  attribute \src "ls180.v:405.5-405.38"
+  attribute \src "ls180.v:450.5-450.38"
   wire $1\main_sdram_sequencer_count[0:0]
-  attribute \src "ls180.v:404.11-404.46"
+  attribute \src "ls180.v:449.11-449.46"
   wire width 4 $1\main_sdram_sequencer_counter[3:0]
-  attribute \src "ls180.v:403.5-403.38"
+  attribute \src "ls180.v:448.5-448.38"
   wire $1\main_sdram_sequencer_done1[0:0]
-  attribute \src "ls180.v:400.5-400.39"
+  attribute \src "ls180.v:445.5-445.39"
   wire $1\main_sdram_sequencer_start0[0:0]
-  attribute \src "ls180.v:296.12-296.46"
+  attribute \src "ls180.v:341.12-341.46"
   wire width 16 $1\main_sdram_slave_p0_rddata[15:0]
-  attribute \src "ls180.v:297.5-297.44"
+  attribute \src "ls180.v:342.5-342.44"
   wire $1\main_sdram_slave_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:332.12-332.37"
+  attribute \src "ls180.v:377.12-377.37"
   wire width 16 $1\main_sdram_status[15:0]
-  attribute \src "ls180.v:774.11-774.40"
+  attribute \src "ls180.v:819.11-819.40"
   wire width 2 $1\main_sdram_steerer_sel[1:0]
-  attribute \src "ls180.v:318.11-318.36"
+  attribute \src "ls180.v:363.11-363.36"
   wire width 4 $1\main_sdram_storage[3:0]
-  attribute \src "ls180.v:783.5-783.36"
+  attribute \src "ls180.v:828.5-828.36"
   wire $1\main_sdram_tccdcon_count[0:0]
-  attribute \src "ls180.v:782.32-782.63"
+  attribute \src "ls180.v:827.32-827.63"
   wire $1\main_sdram_tccdcon_ready[0:0]
-  attribute \src "ls180.v:791.11-791.34"
+  attribute \src "ls180.v:836.11-836.34"
   wire width 5 $1\main_sdram_time0[4:0]
-  attribute \src "ls180.v:794.11-794.34"
+  attribute \src "ls180.v:839.11-839.34"
   wire width 4 $1\main_sdram_time1[3:0]
-  attribute \src "ls180.v:396.11-396.44"
+  attribute \src "ls180.v:441.11-441.44"
   wire width 10 $1\main_sdram_timer_count1[9:0]
-  attribute \src "ls180.v:786.11-786.42"
+  attribute \src "ls180.v:831.11-831.42"
   wire width 3 $1\main_sdram_twtrcon_count[2:0]
-  attribute \src "ls180.v:785.32-785.63"
+  attribute \src "ls180.v:830.32-830.63"
   wire $1\main_sdram_twtrcon_ready[0:0]
-  attribute \src "ls180.v:331.5-331.32"
+  attribute \src "ls180.v:376.5-376.32"
   wire $1\main_sdram_wrdata_re[0:0]
-  attribute \src "ls180.v:330.12-330.45"
+  attribute \src "ls180.v:375.12-375.45"
   wire width 16 $1\main_sdram_wrdata_storage[15:0]
-  attribute \src "ls180.v:999.12-999.44"
+  attribute \src "ls180.v:1044.12-1044.44"
   wire width 16 $1\main_spimaster11_storage[15:0]
-  attribute \src "ls180.v:1000.5-1000.31"
+  attribute \src "ls180.v:1045.5-1045.31"
   wire $1\main_spimaster12_re[0:0]
-  attribute \src "ls180.v:1004.11-1004.42"
+  attribute \src "ls180.v:1049.11-1049.42"
   wire width 8 $1\main_spimaster16_storage[7:0]
-  attribute \src "ls180.v:1005.5-1005.31"
+  attribute \src "ls180.v:1050.5-1050.31"
   wire $1\main_spimaster17_re[0:0]
-  attribute \src "ls180.v:1061.5-1061.30"
+  attribute \src "ls180.v:1106.5-1106.30"
   wire $1\main_spimaster1_re[0:0]
-  attribute \src "ls180.v:1060.12-1060.45"
+  attribute \src "ls180.v:1105.12-1105.45"
   wire width 16 $1\main_spimaster1_storage[15:0]
-  attribute \src "ls180.v:1009.5-1009.36"
+  attribute \src "ls180.v:1054.5-1054.36"
   wire $1\main_spimaster21_storage[0:0]
-  attribute \src "ls180.v:1010.5-1010.31"
+  attribute \src "ls180.v:1055.5-1055.31"
   wire $1\main_spimaster22_re[0:0]
-  attribute \src "ls180.v:1011.5-1011.36"
+  attribute \src "ls180.v:1056.5-1056.36"
   wire $1\main_spimaster23_storage[0:0]
-  attribute \src "ls180.v:1012.5-1012.31"
+  attribute \src "ls180.v:1057.5-1057.31"
   wire $1\main_spimaster24_re[0:0]
-  attribute \src "ls180.v:1013.5-1013.39"
+  attribute \src "ls180.v:1058.5-1058.39"
   wire $1\main_spimaster25_clk_enable[0:0]
-  attribute \src "ls180.v:1014.5-1014.38"
+  attribute \src "ls180.v:1059.5-1059.38"
   wire $1\main_spimaster26_cs_enable[0:0]
-  attribute \src "ls180.v:1015.11-1015.40"
+  attribute \src "ls180.v:1060.11-1060.40"
   wire width 3 $1\main_spimaster27_count[2:0]
-  attribute \src "ls180.v:1781.11-1781.62"
+  attribute \src "ls180.v:1826.11-1826.62"
   wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0]
-  attribute \src "ls180.v:1782.5-1782.59"
+  attribute \src "ls180.v:1827.5-1827.59"
   wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
-  attribute \src "ls180.v:1016.5-1016.39"
+  attribute \src "ls180.v:1061.5-1061.39"
   wire $1\main_spimaster28_mosi_latch[0:0]
-  attribute \src "ls180.v:1017.5-1017.39"
+  attribute \src "ls180.v:1062.5-1062.39"
   wire $1\main_spimaster29_miso_latch[0:0]
-  attribute \src "ls180.v:990.5-990.32"
+  attribute \src "ls180.v:1035.5-1035.32"
   wire $1\main_spimaster2_done[0:0]
-  attribute \src "ls180.v:1018.12-1018.48"
+  attribute \src "ls180.v:1063.12-1063.48"
   wire width 16 $1\main_spimaster30_clk_divider[15:0]
-  attribute \src "ls180.v:1021.11-1021.44"
+  attribute \src "ls180.v:1066.11-1066.44"
   wire width 8 $1\main_spimaster33_mosi_data[7:0]
-  attribute \src "ls180.v:1022.11-1022.43"
+  attribute \src "ls180.v:1067.11-1067.43"
   wire width 3 $1\main_spimaster34_mosi_sel[2:0]
-  attribute \src "ls180.v:1023.11-1023.44"
+  attribute \src "ls180.v:1068.11-1068.44"
   wire width 8 $1\main_spimaster35_miso_data[7:0]
-  attribute \src "ls180.v:991.5-991.31"
+  attribute \src "ls180.v:1036.5-1036.31"
   wire $1\main_spimaster3_irq[0:0]
-  attribute \src "ls180.v:993.11-993.38"
+  attribute \src "ls180.v:1038.11-1038.38"
   wire width 8 $1\main_spimaster5_miso[7:0]
-  attribute \src "ls180.v:997.5-997.33"
+  attribute \src "ls180.v:1042.5-1042.33"
   wire $1\main_spimaster9_start[0:0]
-  attribute \src "ls180.v:1054.12-1054.47"
+  attribute \src "ls180.v:1099.12-1099.47"
   wire width 16 $1\main_spisdcard_clk_divider1[15:0]
-  attribute \src "ls180.v:1049.5-1049.37"
+  attribute \src "ls180.v:1094.5-1094.37"
   wire $1\main_spisdcard_clk_enable[0:0]
-  attribute \src "ls180.v:1036.5-1036.37"
+  attribute \src "ls180.v:1081.5-1081.37"
   wire $1\main_spisdcard_control_re[0:0]
-  attribute \src "ls180.v:1035.12-1035.50"
+  attribute \src "ls180.v:1080.12-1080.50"
   wire width 16 $1\main_spisdcard_control_storage[15:0]
-  attribute \src "ls180.v:1051.11-1051.38"
+  attribute \src "ls180.v:1096.11-1096.38"
   wire width 3 $1\main_spisdcard_count[2:0]
-  attribute \src "ls180.v:1785.11-1785.60"
+  attribute \src "ls180.v:1830.11-1830.60"
   wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0]
-  attribute \src "ls180.v:1786.5-1786.57"
+  attribute \src "ls180.v:1831.5-1831.57"
   wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
-  attribute \src "ls180.v:1050.5-1050.36"
+  attribute \src "ls180.v:1095.5-1095.36"
   wire $1\main_spisdcard_cs_enable[0:0]
-  attribute \src "ls180.v:1046.5-1046.32"
+  attribute \src "ls180.v:1091.5-1091.32"
   wire $1\main_spisdcard_cs_re[0:0]
-  attribute \src "ls180.v:1045.5-1045.37"
+  attribute \src "ls180.v:1090.5-1090.37"
   wire $1\main_spisdcard_cs_storage[0:0]
-  attribute \src "ls180.v:1026.5-1026.32"
+  attribute \src "ls180.v:1071.5-1071.32"
   wire $1\main_spisdcard_done0[0:0]
-  attribute \src "ls180.v:1027.5-1027.30"
+  attribute \src "ls180.v:1072.5-1072.30"
   wire $1\main_spisdcard_irq[0:0]
-  attribute \src "ls180.v:1048.5-1048.38"
+  attribute \src "ls180.v:1093.5-1093.38"
   wire $1\main_spisdcard_loopback_re[0:0]
-  attribute \src "ls180.v:1047.5-1047.43"
+  attribute \src "ls180.v:1092.5-1092.43"
   wire $1\main_spisdcard_loopback_storage[0:0]
-  attribute \src "ls180.v:1029.11-1029.37"
+  attribute \src "ls180.v:1074.11-1074.37"
   wire width 8 $1\main_spisdcard_miso[7:0]
-  attribute \src "ls180.v:1059.11-1059.42"
+  attribute \src "ls180.v:1104.11-1104.42"
   wire width 8 $1\main_spisdcard_miso_data[7:0]
-  attribute \src "ls180.v:1053.5-1053.37"
+  attribute \src "ls180.v:1098.5-1098.37"
   wire $1\main_spisdcard_miso_latch[0:0]
-  attribute \src "ls180.v:1057.11-1057.42"
+  attribute \src "ls180.v:1102.11-1102.42"
   wire width 8 $1\main_spisdcard_mosi_data[7:0]
-  attribute \src "ls180.v:1052.5-1052.37"
+  attribute \src "ls180.v:1097.5-1097.37"
   wire $1\main_spisdcard_mosi_latch[0:0]
-  attribute \src "ls180.v:1041.5-1041.34"
+  attribute \src "ls180.v:1086.5-1086.34"
   wire $1\main_spisdcard_mosi_re[0:0]
-  attribute \src "ls180.v:1058.11-1058.41"
+  attribute \src "ls180.v:1103.11-1103.41"
   wire width 3 $1\main_spisdcard_mosi_sel[2:0]
-  attribute \src "ls180.v:1040.11-1040.45"
+  attribute \src "ls180.v:1085.11-1085.45"
   wire width 8 $1\main_spisdcard_mosi_storage[7:0]
-  attribute \src "ls180.v:1033.5-1033.33"
+  attribute \src "ls180.v:1078.5-1078.33"
   wire $1\main_spisdcard_start1[0:0]
-  attribute \src "ls180.v:887.11-887.50"
+  attribute \src "ls180.v:258.11-258.31"
+  wire width 4 $1\main_sram0_we[3:0]
+  attribute \src "ls180.v:273.11-273.31"
+  wire width 4 $1\main_sram1_we[3:0]
+  attribute \src "ls180.v:288.11-288.31"
+  wire width 4 $1\main_sram2_we[3:0]
+  attribute \src "ls180.v:932.11-932.50"
   wire width 2 $1\main_uart_eventmanager_pending_w[1:0]
-  attribute \src "ls180.v:889.5-889.37"
+  attribute \src "ls180.v:934.5-934.37"
   wire $1\main_uart_eventmanager_re[0:0]
-  attribute \src "ls180.v:883.11-883.49"
+  attribute \src "ls180.v:928.11-928.49"
   wire width 2 $1\main_uart_eventmanager_status_w[1:0]
-  attribute \src "ls180.v:888.11-888.48"
+  attribute \src "ls180.v:933.11-933.48"
   wire width 2 $1\main_uart_eventmanager_storage[1:0]
-  attribute \src "ls180.v:855.12-855.54"
+  attribute \src "ls180.v:900.12-900.54"
   wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0]
-  attribute \src "ls180.v:845.12-845.54"
+  attribute \src "ls180.v:890.12-890.54"
   wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0]
-  attribute \src "ls180.v:838.5-838.28"
+  attribute \src "ls180.v:883.5-883.28"
   wire $1\main_uart_phy_re[0:0]
-  attribute \src "ls180.v:859.11-859.43"
+  attribute \src "ls180.v:904.11-904.43"
   wire width 4 $1\main_uart_phy_rx_bitcount[3:0]
-  attribute \src "ls180.v:860.5-860.33"
+  attribute \src "ls180.v:905.5-905.33"
   wire $1\main_uart_phy_rx_busy[0:0]
-  attribute \src "ls180.v:857.5-857.30"
+  attribute \src "ls180.v:902.5-902.30"
   wire $1\main_uart_phy_rx_r[0:0]
-  attribute \src "ls180.v:858.11-858.38"
+  attribute \src "ls180.v:903.11-903.38"
   wire width 8 $1\main_uart_phy_rx_reg[7:0]
-  attribute \src "ls180.v:840.5-840.36"
+  attribute \src "ls180.v:885.5-885.36"
   wire $1\main_uart_phy_sink_ready[0:0]
-  attribute \src "ls180.v:853.11-853.51"
+  attribute \src "ls180.v:898.11-898.51"
   wire width 8 $1\main_uart_phy_source_payload_data[7:0]
-  attribute \src "ls180.v:849.5-849.38"
+  attribute \src "ls180.v:894.5-894.38"
   wire $1\main_uart_phy_source_valid[0:0]
-  attribute \src "ls180.v:837.12-837.47"
+  attribute \src "ls180.v:882.12-882.47"
   wire width 32 $1\main_uart_phy_storage[31:0]
-  attribute \src "ls180.v:847.11-847.43"
+  attribute \src "ls180.v:892.11-892.43"
   wire width 4 $1\main_uart_phy_tx_bitcount[3:0]
-  attribute \src "ls180.v:848.5-848.33"
+  attribute \src "ls180.v:893.5-893.33"
   wire $1\main_uart_phy_tx_busy[0:0]
-  attribute \src "ls180.v:846.11-846.38"
+  attribute \src "ls180.v:891.11-891.38"
   wire width 8 $1\main_uart_phy_tx_reg[7:0]
-  attribute \src "ls180.v:854.5-854.39"
+  attribute \src "ls180.v:899.5-899.39"
   wire $1\main_uart_phy_uart_clk_rxen[0:0]
-  attribute \src "ls180.v:844.5-844.39"
+  attribute \src "ls180.v:889.5-889.39"
   wire $1\main_uart_phy_uart_clk_txen[0:0]
-  attribute \src "ls180.v:878.5-878.30"
+  attribute \src "ls180.v:923.5-923.30"
   wire $1\main_uart_rx_clear[0:0]
-  attribute \src "ls180.v:962.11-962.43"
+  attribute \src "ls180.v:1007.11-1007.43"
   wire width 4 $1\main_uart_rx_fifo_consume[3:0]
-  attribute \src "ls180.v:959.11-959.42"
+  attribute \src "ls180.v:1004.11-1004.42"
   wire width 5 $1\main_uart_rx_fifo_level0[4:0]
-  attribute \src "ls180.v:961.11-961.43"
+  attribute \src "ls180.v:1006.11-1006.43"
   wire width 4 $1\main_uart_rx_fifo_produce[3:0]
-  attribute \src "ls180.v:952.5-952.38"
+  attribute \src "ls180.v:997.5-997.38"
   wire $1\main_uart_rx_fifo_readable[0:0]
-  attribute \src "ls180.v:963.11-963.46"
+  attribute \src "ls180.v:1008.11-1008.46"
   wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:879.5-879.36"
+  attribute \src "ls180.v:924.5-924.36"
   wire $1\main_uart_rx_old_trigger[0:0]
-  attribute \src "ls180.v:876.5-876.32"
+  attribute \src "ls180.v:921.5-921.32"
   wire $1\main_uart_rx_pending[0:0]
-  attribute \src "ls180.v:873.5-873.30"
+  attribute \src "ls180.v:918.5-918.30"
   wire $1\main_uart_tx_clear[0:0]
-  attribute \src "ls180.v:925.11-925.43"
+  attribute \src "ls180.v:970.11-970.43"
   wire width 4 $1\main_uart_tx_fifo_consume[3:0]
-  attribute \src "ls180.v:922.11-922.42"
+  attribute \src "ls180.v:967.11-967.42"
   wire width 5 $1\main_uart_tx_fifo_level0[4:0]
-  attribute \src "ls180.v:924.11-924.43"
+  attribute \src "ls180.v:969.11-969.43"
   wire width 4 $1\main_uart_tx_fifo_produce[3:0]
-  attribute \src "ls180.v:915.5-915.38"
+  attribute \src "ls180.v:960.5-960.38"
   wire $1\main_uart_tx_fifo_readable[0:0]
-  attribute \src "ls180.v:926.11-926.46"
+  attribute \src "ls180.v:971.11-971.46"
   wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:874.5-874.36"
+  attribute \src "ls180.v:919.5-919.36"
   wire $1\main_uart_tx_old_trigger[0:0]
-  attribute \src "ls180.v:871.5-871.32"
+  attribute \src "ls180.v:916.5-916.32"
   wire $1\main_uart_tx_pending[0:0]
-  attribute \src "ls180.v:815.5-815.29"
+  attribute \src "ls180.v:860.5-860.29"
   wire $1\main_wb_sdram_ack[0:0]
-  attribute \src "ls180.v:833.5-833.31"
+  attribute \src "ls180.v:878.5-878.31"
   wire $1\main_wdata_consumed[0:0]
-  attribute \src "ls180.v:2815.68-2815.110"
-  wire $add$ls180.v:2815$22_Y
-  attribute \src "ls180.v:2875.68-2875.110"
-  wire $add$ls180.v:2875$33_Y
-  attribute \src "ls180.v:2935.68-2935.110"
-  wire $add$ls180.v:2935$44_Y
-  attribute \src "ls180.v:4068.54-4068.83"
-  wire $add$ls180.v:4068$537_Y
-  attribute \src "ls180.v:4168.36-4168.89"
-  wire width 5 $add$ls180.v:4168$583_Y
-  attribute \src "ls180.v:4198.36-4198.89"
-  wire width 5 $add$ls180.v:4198$594_Y
-  attribute \src "ls180.v:4253.54-4253.83"
-  wire width 3 $add$ls180.v:4253$607_Y
-  attribute \src "ls180.v:4312.52-4312.79"
-  wire width 3 $add$ls180.v:4312$615_Y
-  attribute \src "ls180.v:4416.58-4416.86"
-  wire width 8 $add$ls180.v:4416$643_Y
-  attribute \src "ls180.v:4473.58-4473.86"
-  wire width 8 $add$ls180.v:4473$646_Y
-  attribute \src "ls180.v:4490.58-4490.86"
-  wire width 8 $add$ls180.v:4490$648_Y
-  attribute \src "ls180.v:4583.59-4583.87"
-  wire width 8 $add$ls180.v:4583$665_Y
-  attribute \src "ls180.v:4608.59-4608.87"
-  wire width 8 $add$ls180.v:4608$668_Y
-  attribute \src "ls180.v:4730.53-4730.82"
-  wire width 8 $add$ls180.v:4730$685_Y
-  attribute \src "ls180.v:4841.65-4841.114"
-  wire width 10 $add$ls180.v:4841$699_Y
-  attribute \src "ls180.v:4846.62-4846.91"
-  wire width 10 $add$ls180.v:4846$702_Y
-  attribute \src "ls180.v:4872.61-4872.90"
-  wire width 10 $add$ls180.v:4872$705_Y
-  attribute \src "ls180.v:5076.80-5076.117"
-  wire width 3 $add$ls180.v:5076$890_Y
-  attribute \src "ls180.v:5270.54-5270.82"
-  wire width 3 $add$ls180.v:5270$965_Y
-  attribute \src "ls180.v:5322.55-5322.84"
-  wire width 32 $add$ls180.v:5322$975_Y
-  attribute \src "ls180.v:5348.57-5348.86"
-  wire width 32 $add$ls180.v:5348$983_Y
-  attribute \src "ls180.v:5469.51-5469.134"
-  wire width 32 $add$ls180.v:5469$999_Y
-  attribute \src "ls180.v:5472.77-5472.125"
-  wire width 32 $add$ls180.v:5472$1001_Y
-  attribute \src "ls180.v:5565.50-5565.105"
-  wire width 32 $add$ls180.v:5565$1010_Y
-  attribute \src "ls180.v:5567.77-5567.111"
-  wire width 32 $add$ls180.v:5567$1011_Y
-  attribute \src "ls180.v:7487.36-7487.70"
-  wire width 32 $add$ls180.v:7487$2403_Y
-  attribute \src "ls180.v:7572.37-7572.72"
-  wire width 4 $add$ls180.v:7572$2424_Y
-  attribute \src "ls180.v:7589.60-7589.119"
-  wire width 3 $add$ls180.v:7589$2428_Y
-  attribute \src "ls180.v:7592.60-7592.119"
-  wire width 3 $add$ls180.v:7592$2429_Y
-  attribute \src "ls180.v:7596.59-7596.116"
-  wire width 4 $add$ls180.v:7596$2434_Y
-  attribute \src "ls180.v:7635.60-7635.119"
-  wire width 3 $add$ls180.v:7635$2444_Y
-  attribute \src "ls180.v:7638.60-7638.119"
-  wire width 3 $add$ls180.v:7638$2445_Y
-  attribute \src "ls180.v:7642.59-7642.116"
-  wire width 4 $add$ls180.v:7642$2450_Y
-  attribute \src "ls180.v:7681.60-7681.119"
-  wire width 3 $add$ls180.v:7681$2460_Y
-  attribute \src "ls180.v:7684.60-7684.119"
-  wire width 3 $add$ls180.v:7684$2461_Y
-  attribute \src "ls180.v:7688.59-7688.116"
-  wire width 4 $add$ls180.v:7688$2466_Y
-  attribute \src "ls180.v:7727.60-7727.119"
-  wire width 3 $add$ls180.v:7727$2476_Y
-  attribute \src "ls180.v:7730.60-7730.119"
-  wire width 3 $add$ls180.v:7730$2477_Y
-  attribute \src "ls180.v:7734.59-7734.116"
-  wire width 4 $add$ls180.v:7734$2482_Y
-  attribute \src "ls180.v:7964.34-7964.66"
-  wire width 4 $add$ls180.v:7964$2536_Y
-  attribute \src "ls180.v:7980.73-7980.131"
-  wire width 33 $add$ls180.v:7980$2539_Y
-  attribute \src "ls180.v:7993.34-7993.66"
-  wire width 4 $add$ls180.v:7993$2543_Y
-  attribute \src "ls180.v:8012.73-8012.131"
-  wire width 33 $add$ls180.v:8012$2546_Y
-  attribute \src "ls180.v:8038.33-8038.65"
-  wire width 4 $add$ls180.v:8038$2554_Y
-  attribute \src "ls180.v:8041.33-8041.65"
-  wire width 4 $add$ls180.v:8041$2555_Y
-  attribute \src "ls180.v:8045.33-8045.64"
-  wire width 5 $add$ls180.v:8045$2560_Y
-  attribute \src "ls180.v:8060.33-8060.65"
-  wire width 4 $add$ls180.v:8060$2565_Y
-  attribute \src "ls180.v:8063.33-8063.65"
-  wire width 4 $add$ls180.v:8063$2566_Y
-  attribute \src "ls180.v:8067.33-8067.64"
-  wire width 5 $add$ls180.v:8067$2571_Y
-  attribute \src "ls180.v:8088.35-8088.70"
-  wire width 16 $add$ls180.v:8088$2573_Y
-  attribute \src "ls180.v:8123.34-8123.68"
-  wire width 16 $add$ls180.v:8123$2578_Y
-  attribute \src "ls180.v:8159.25-8159.49"
-  wire width 32 $add$ls180.v:8159$2583_Y
-  attribute \src "ls180.v:8173.25-8173.49"
-  wire width 32 $add$ls180.v:8173$2587_Y
-  attribute \src "ls180.v:8187.31-8187.61"
-  wire width 9 $add$ls180.v:8187$2592_Y
-  attribute \src "ls180.v:8210.45-8210.88"
-  wire width 3 $add$ls180.v:8210$2596_Y
-  attribute \src "ls180.v:8256.71-8256.114"
-  wire width 4 $add$ls180.v:8256$2602_Y
-  attribute \src "ls180.v:8291.46-8291.90"
-  wire width 3 $add$ls180.v:8291$2608_Y
-  attribute \src "ls180.v:8337.72-8337.116"
-  wire width 4 $add$ls180.v:8337$2614_Y
-  attribute \src "ls180.v:8370.47-8370.92"
-  wire $add$ls180.v:8370$2620_Y
-  attribute \src "ls180.v:8398.73-8398.118"
-  wire width 2 $add$ls180.v:8398$2626_Y
-  attribute \src "ls180.v:8510.39-8510.75"
-  wire width 4 $add$ls180.v:8510$2639_Y
-  attribute \src "ls180.v:8571.37-8571.73"
-  wire width 5 $add$ls180.v:8571$2643_Y
-  attribute \src "ls180.v:8574.37-8574.73"
-  wire width 5 $add$ls180.v:8574$2644_Y
-  attribute \src "ls180.v:8578.36-8578.70"
-  wire width 6 $add$ls180.v:8578$2649_Y
-  attribute \src "ls180.v:8593.41-8593.80"
-  wire width 2 $add$ls180.v:8593$2653_Y
-  attribute \src "ls180.v:8627.67-8627.106"
-  wire width 3 $add$ls180.v:8627$2659_Y
-  attribute \src "ls180.v:8653.39-8653.76"
-  wire width 2 $add$ls180.v:8653$2661_Y
-  attribute \src "ls180.v:8657.37-8657.73"
-  wire width 5 $add$ls180.v:8657$2665_Y
-  attribute \src "ls180.v:8660.37-8660.73"
-  wire width 5 $add$ls180.v:8660$2666_Y
-  attribute \src "ls180.v:8664.36-8664.70"
-  wire width 6 $add$ls180.v:8664$2671_Y
-  attribute \src "ls180.v:2809.9-2809.80"
-  wire $and$ls180.v:2809$17_Y
-  attribute \src "ls180.v:2827.9-2827.80"
-  wire $and$ls180.v:2827$24_Y
-  attribute \src "ls180.v:2869.9-2869.80"
-  wire $and$ls180.v:2869$28_Y
-  attribute \src "ls180.v:2887.9-2887.80"
-  wire $and$ls180.v:2887$35_Y
-  attribute \src "ls180.v:2929.9-2929.86"
-  wire $and$ls180.v:2929$39_Y
-  attribute \src "ls180.v:2947.9-2947.86"
-  wire $and$ls180.v:2947$46_Y
-  attribute \src "ls180.v:2957.31-2957.90"
-  wire $and$ls180.v:2957$48_Y
-  attribute \src "ls180.v:2957.30-2957.121"
-  wire $and$ls180.v:2957$49_Y
-  attribute \src "ls180.v:2957.29-2957.156"
-  wire $and$ls180.v:2957$50_Y
-  attribute \src "ls180.v:2958.31-2958.90"
-  wire $and$ls180.v:2958$51_Y
-  attribute \src "ls180.v:2958.30-2958.121"
-  wire $and$ls180.v:2958$52_Y
-  attribute \src "ls180.v:2958.29-2958.156"
-  wire $and$ls180.v:2958$53_Y
-  attribute \src "ls180.v:2959.31-2959.90"
-  wire $and$ls180.v:2959$54_Y
-  attribute \src "ls180.v:2959.30-2959.121"
-  wire $and$ls180.v:2959$55_Y
-  attribute \src "ls180.v:2959.29-2959.156"
-  wire $and$ls180.v:2959$56_Y
-  attribute \src "ls180.v:2960.31-2960.90"
-  wire $and$ls180.v:2960$57_Y
-  attribute \src "ls180.v:2960.30-2960.121"
-  wire $and$ls180.v:2960$58_Y
-  attribute \src "ls180.v:2960.29-2960.156"
-  wire $and$ls180.v:2960$59_Y
-  attribute \src "ls180.v:2969.7-2969.89"
-  wire $and$ls180.v:2969$62_Y
-  attribute \src "ls180.v:2974.32-2974.111"
-  wire $and$ls180.v:2974$63_Y
-  attribute \src "ls180.v:3088.40-3088.99"
-  wire $and$ls180.v:3088$70_Y
-  attribute \src "ls180.v:3089.40-3089.99"
-  wire $and$ls180.v:3089$71_Y
-  attribute \src "ls180.v:3127.38-3127.103"
-  wire $and$ls180.v:3127$77_Y
-  attribute \src "ls180.v:3181.50-3181.119"
-  wire $and$ls180.v:3181$85_Y
-  attribute \src "ls180.v:3181.49-3181.167"
-  wire $and$ls180.v:3181$86_Y
-  attribute \src "ls180.v:3182.49-3182.118"
-  wire $and$ls180.v:3182$87_Y
-  attribute \src "ls180.v:3182.48-3182.154"
-  wire $and$ls180.v:3182$88_Y
-  attribute \src "ls180.v:3183.50-3183.119"
-  wire $and$ls180.v:3183$89_Y
-  attribute \src "ls180.v:3183.49-3183.155"
-  wire $and$ls180.v:3183$90_Y
-  attribute \src "ls180.v:3186.7-3186.114"
-  wire $and$ls180.v:3186$92_Y
-  attribute \src "ls180.v:3215.66-3215.246"
-  wire $and$ls180.v:3215$98_Y
-  attribute \src "ls180.v:3216.64-3216.187"
-  wire $and$ls180.v:3216$99_Y
-  attribute \src "ls180.v:3240.9-3240.86"
-  wire $and$ls180.v:3240$105_Y
-  attribute \src "ls180.v:3252.9-3252.86"
-  wire $and$ls180.v:3252$106_Y
-  attribute \src "ls180.v:3302.13-3302.87"
-  wire $and$ls180.v:3302$108_Y
-  attribute \src "ls180.v:3338.50-3338.119"
-  wire $and$ls180.v:3338$115_Y
-  attribute \src "ls180.v:3338.49-3338.167"
-  wire $and$ls180.v:3338$116_Y
-  attribute \src "ls180.v:3339.49-3339.118"
-  wire $and$ls180.v:3339$117_Y
-  attribute \src "ls180.v:3339.48-3339.154"
-  wire $and$ls180.v:3339$118_Y
-  attribute \src "ls180.v:3340.50-3340.119"
-  wire $and$ls180.v:3340$119_Y
-  attribute \src "ls180.v:3340.49-3340.155"
-  wire $and$ls180.v:3340$120_Y
-  attribute \src "ls180.v:3343.7-3343.114"
-  wire $and$ls180.v:3343$122_Y
-  attribute \src "ls180.v:3372.66-3372.246"
-  wire $and$ls180.v:3372$128_Y
-  attribute \src "ls180.v:3373.64-3373.187"
-  wire $and$ls180.v:3373$129_Y
-  attribute \src "ls180.v:3397.9-3397.86"
-  wire $and$ls180.v:3397$135_Y
-  attribute \src "ls180.v:3409.9-3409.86"
-  wire $and$ls180.v:3409$136_Y
-  attribute \src "ls180.v:3459.13-3459.87"
-  wire $and$ls180.v:3459$138_Y
-  attribute \src "ls180.v:3495.50-3495.119"
-  wire $and$ls180.v:3495$145_Y
-  attribute \src "ls180.v:3495.49-3495.167"
-  wire $and$ls180.v:3495$146_Y
-  attribute \src "ls180.v:3496.49-3496.118"
-  wire $and$ls180.v:3496$147_Y
-  attribute \src "ls180.v:3496.48-3496.154"
-  wire $and$ls180.v:3496$148_Y
-  attribute \src "ls180.v:3497.50-3497.119"
-  wire $and$ls180.v:3497$149_Y
-  attribute \src "ls180.v:3497.49-3497.155"
-  wire $and$ls180.v:3497$150_Y
-  attribute \src "ls180.v:3500.7-3500.114"
-  wire $and$ls180.v:3500$152_Y
-  attribute \src "ls180.v:3529.66-3529.246"
-  wire $and$ls180.v:3529$158_Y
-  attribute \src "ls180.v:3530.64-3530.187"
-  wire $and$ls180.v:3530$159_Y
-  attribute \src "ls180.v:3554.9-3554.86"
-  wire $and$ls180.v:3554$165_Y
-  attribute \src "ls180.v:3566.9-3566.86"
-  wire $and$ls180.v:3566$166_Y
-  attribute \src "ls180.v:3616.13-3616.87"
-  wire $and$ls180.v:3616$168_Y
-  attribute \src "ls180.v:3652.50-3652.119"
-  wire $and$ls180.v:3652$175_Y
-  attribute \src "ls180.v:3652.49-3652.167"
-  wire $and$ls180.v:3652$176_Y
-  attribute \src "ls180.v:3653.49-3653.118"
-  wire $and$ls180.v:3653$177_Y
-  attribute \src "ls180.v:3653.48-3653.154"
-  wire $and$ls180.v:3653$178_Y
-  attribute \src "ls180.v:3654.50-3654.119"
-  wire $and$ls180.v:3654$179_Y
-  attribute \src "ls180.v:3654.49-3654.155"
-  wire $and$ls180.v:3654$180_Y
-  attribute \src "ls180.v:3657.7-3657.114"
-  wire $and$ls180.v:3657$182_Y
-  attribute \src "ls180.v:3686.66-3686.246"
-  wire $and$ls180.v:3686$188_Y
-  attribute \src "ls180.v:3687.64-3687.187"
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+  wire $and$ls180.v:3258$141_Y
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+  attribute \src "ls180.v:3290.66-3290.246"
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+  wire $and$ls180.v:3291$150_Y
+  attribute \src "ls180.v:3315.9-3315.86"
+  wire $and$ls180.v:3315$156_Y
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+  wire $and$ls180.v:3327$157_Y
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+  wire $and$ls180.v:3377$159_Y
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+  wire $and$ls180.v:3413$167_Y
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+  wire $and$ls180.v:3484$187_Y
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+  wire $and$ls180.v:5966$1309_Y
+  attribute \src "ls180.v:5966.39-5966.143"
+  wire $and$ls180.v:5966$1311_Y
+  attribute \src "ls180.v:5967.40-5967.96"
+  wire $and$ls180.v:5967$1313_Y
+  attribute \src "ls180.v:5967.39-5967.146"
+  wire $and$ls180.v:5967$1315_Y
+  attribute \src "ls180.v:5969.40-5969.93"
+  wire $and$ls180.v:5969$1316_Y
+  attribute \src "ls180.v:5969.39-5969.143"
+  wire $and$ls180.v:5969$1318_Y
+  attribute \src "ls180.v:5970.40-5970.96"
+  wire $and$ls180.v:5970$1320_Y
+  attribute \src "ls180.v:5970.39-5970.146"
+  wire $and$ls180.v:5970$1322_Y
+  attribute \src "ls180.v:5972.40-5972.93"
+  wire $and$ls180.v:5972$1323_Y
+  attribute \src "ls180.v:5972.39-5972.143"
+  wire $and$ls180.v:5972$1325_Y
+  attribute \src "ls180.v:5973.40-5973.96"
+  wire $and$ls180.v:5973$1327_Y
+  attribute \src "ls180.v:5973.39-5973.146"
+  wire $and$ls180.v:5973$1329_Y
+  attribute \src "ls180.v:5975.40-5975.93"
+  wire $and$ls180.v:5975$1330_Y
+  attribute \src "ls180.v:5975.39-5975.143"
+  wire $and$ls180.v:5975$1332_Y
+  attribute \src "ls180.v:5976.40-5976.96"
+  wire $and$ls180.v:5976$1334_Y
+  attribute \src "ls180.v:5976.39-5976.146"
+  wire $and$ls180.v:5976$1336_Y
+  attribute \src "ls180.v:5988.40-5988.93"
+  wire $and$ls180.v:5988$1338_Y
+  attribute \src "ls180.v:5988.39-5988.143"
+  wire $and$ls180.v:5988$1340_Y
+  attribute \src "ls180.v:5989.40-5989.96"
+  wire $and$ls180.v:5989$1342_Y
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+  wire $and$ls180.v:5989$1344_Y
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+  wire $and$ls180.v:5991$1347_Y
+  attribute \src "ls180.v:5992.39-5992.95"
+  wire $and$ls180.v:5992$1349_Y
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+  wire $and$ls180.v:5995$1358_Y
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+  wire $and$ls180.v:5998$1365_Y
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+  wire $and$ls180.v:6000$1368_Y
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+  attribute \src "ls180.v:6013.39-6013.146"
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+  attribute \src "ls180.v:6028.41-6028.145"
+  wire $and$ls180.v:6028$1411_Y
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+  attribute \src "ls180.v:6029.41-6029.148"
+  wire $and$ls180.v:6029$1415_Y
+  attribute \src "ls180.v:6031.42-6031.95"
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+  wire $and$ls180.v:6031$1418_Y
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+  attribute \src "ls180.v:6032.41-6032.148"
+  wire $and$ls180.v:6032$1422_Y
+  attribute \src "ls180.v:6034.42-6034.95"
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+  attribute \src "ls180.v:6034.41-6034.145"
+  wire $and$ls180.v:6034$1425_Y
+  attribute \src "ls180.v:6035.42-6035.98"
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+  wire $and$ls180.v:6037$1430_Y
+  attribute \src "ls180.v:6037.41-6037.145"
+  wire $and$ls180.v:6037$1432_Y
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+  wire $and$ls180.v:6038$1436_Y
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+  wire $and$ls180.v:6040$1439_Y
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+  attribute \src "ls180.v:6041.41-6041.148"
+  wire $and$ls180.v:6041$1443_Y
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+  wire $and$ls180.v:6043$1446_Y
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+  wire $and$ls180.v:6044$1450_Y
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+  wire $and$ls180.v:6046$1453_Y
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+  wire $and$ls180.v:6047$1455_Y
+  attribute \src "ls180.v:6047.41-6047.148"
+  wire $and$ls180.v:6047$1457_Y
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+  wire $and$ls180.v:6049$1460_Y
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+  wire $and$ls180.v:6050$1462_Y
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+  wire $and$ls180.v:6050$1464_Y
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+  attribute \src "ls180.v:6052.43-6052.147"
+  wire $and$ls180.v:6052$1467_Y
+  attribute \src "ls180.v:6053.44-6053.100"
+  wire $and$ls180.v:6053$1469_Y
+  attribute \src "ls180.v:6053.43-6053.150"
+  wire $and$ls180.v:6053$1471_Y
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+  wire $and$ls180.v:6055$1472_Y
+  attribute \src "ls180.v:6055.43-6055.148"
+  wire $and$ls180.v:6055$1474_Y
+  attribute \src "ls180.v:6056.44-6056.100"
+  wire $and$ls180.v:6056$1476_Y
+  attribute \src "ls180.v:6056.43-6056.151"
+  wire $and$ls180.v:6056$1478_Y
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+  wire $and$ls180.v:6058$1481_Y
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+  wire $and$ls180.v:6059$1485_Y
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+  wire $and$ls180.v:6061$1488_Y
+  attribute \src "ls180.v:6062.44-6062.100"
+  wire $and$ls180.v:6062$1490_Y
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+  wire $and$ls180.v:6062$1492_Y
+  attribute \src "ls180.v:6064.41-6064.94"
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+  attribute \src "ls180.v:6064.40-6064.145"
+  wire $and$ls180.v:6064$1495_Y
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+  wire $and$ls180.v:6065$1497_Y
+  attribute \src "ls180.v:6065.40-6065.148"
+  wire $and$ls180.v:6065$1499_Y
+  attribute \src "ls180.v:6067.42-6067.95"
+  wire $and$ls180.v:6067$1500_Y
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+  wire $and$ls180.v:6067$1502_Y
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+  wire $and$ls180.v:6068$1506_Y
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+  wire $and$ls180.v:6087$1510_Y
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+  wire $and$ls180.v:6088$1512_Y
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+  wire $and$ls180.v:6088$1514_Y
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+  wire $and$ls180.v:6090$1517_Y
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+  wire $and$ls180.v:6091$1521_Y
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+  wire $and$ls180.v:6093$1524_Y
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+  wire $and$ls180.v:6094$1528_Y
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+  wire $and$ls180.v:6096$1531_Y
+  attribute \src "ls180.v:6097.46-6097.102"
+  wire $and$ls180.v:6097$1533_Y
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+  wire $and$ls180.v:6097$1535_Y
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+  wire $and$ls180.v:6099$1538_Y
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+  wire $and$ls180.v:6109$1563_Y
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+  attribute \src "ls180.v:6111.35-6111.139"
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-  attribute \src "ls180.v:8295.8-8295.95"
-  wire $and$ls180.v:8295$2610_Y
-  attribute \src "ls180.v:8303.8-8303.95"
-  wire $and$ls180.v:8303$2611_Y
-  attribute \src "ls180.v:8373.7-8373.100"
-  wire $and$ls180.v:8373$2621_Y
-  attribute \src "ls180.v:8374.8-8374.97"
-  wire $and$ls180.v:8374$2622_Y
-  attribute \src "ls180.v:8382.8-8382.97"
-  wire $and$ls180.v:8382$2623_Y
-  attribute \src "ls180.v:8473.7-8473.82"
-  wire $and$ls180.v:8473$2629_Y
-  attribute \src "ls180.v:8476.7-8476.82"
-  wire $and$ls180.v:8476$2630_Y
-  attribute \src "ls180.v:8479.7-8479.82"
-  wire $and$ls180.v:8479$2631_Y
-  attribute \src "ls180.v:8482.7-8482.82"
-  wire $and$ls180.v:8482$2632_Y
-  attribute \src "ls180.v:8485.7-8485.82"
-  wire $and$ls180.v:8485$2633_Y
-  attribute \src "ls180.v:8490.7-8490.82"
-  wire $and$ls180.v:8490$2634_Y
-  attribute \src "ls180.v:8495.7-8495.82"
-  wire $and$ls180.v:8495$2635_Y
-  attribute \src "ls180.v:8500.7-8500.82"
-  wire $and$ls180.v:8500$2636_Y
-  attribute \src "ls180.v:8505.7-8505.82"
-  wire $and$ls180.v:8505$2637_Y
-  attribute \src "ls180.v:8570.8-8570.83"
-  wire $and$ls180.v:8570$2640_Y
-  attribute \src "ls180.v:8570.7-8570.119"
-  wire $and$ls180.v:8570$2642_Y
-  attribute \src "ls180.v:8576.8-8576.83"
-  wire $and$ls180.v:8576$2645_Y
-  attribute \src "ls180.v:8576.7-8576.119"
-  wire $and$ls180.v:8576$2647_Y
-  attribute \src "ls180.v:8596.7-8596.88"
-  wire $and$ls180.v:8596$2654_Y
-  attribute \src "ls180.v:8597.8-8597.85"
-  wire $and$ls180.v:8597$2655_Y
-  attribute \src "ls180.v:8605.8-8605.85"
-  wire $and$ls180.v:8605$2656_Y
-  attribute \src "ls180.v:8649.7-8649.88"
-  wire $and$ls180.v:8649$2660_Y
-  attribute \src "ls180.v:8656.8-8656.83"
-  wire $and$ls180.v:8656$2662_Y
-  attribute \src "ls180.v:8656.7-8656.119"
-  wire $and$ls180.v:8656$2664_Y
-  attribute \src "ls180.v:8662.8-8662.83"
-  wire $and$ls180.v:8662$2667_Y
-  attribute \src "ls180.v:8662.7-8662.119"
-  wire $and$ls180.v:8662$2669_Y
-  attribute \src "ls180.v:2810.42-2810.101"
-  wire $eq$ls180.v:2810$18_Y
-  attribute \src "ls180.v:2817.11-2817.54"
-  wire $eq$ls180.v:2817$23_Y
-  attribute \src "ls180.v:2870.42-2870.101"
-  wire $eq$ls180.v:2870$29_Y
-  attribute \src "ls180.v:2877.11-2877.54"
-  wire $eq$ls180.v:2877$34_Y
-  attribute \src "ls180.v:2930.42-2930.101"
-  wire $eq$ls180.v:2930$40_Y
-  attribute \src "ls180.v:2937.11-2937.54"
-  wire $eq$ls180.v:2937$45_Y
-  attribute \src "ls180.v:3123.34-3123.65"
-  wire $eq$ls180.v:3123$73_Y
-  attribute \src "ls180.v:3127.68-3127.102"
-  wire $eq$ls180.v:3127$76_Y
-  attribute \src "ls180.v:3171.43-3171.134"
-  wire $eq$ls180.v:3171$81_Y
-  attribute \src "ls180.v:3188.47-3188.88"
-  wire $eq$ls180.v:3188$94_Y
-  attribute \src "ls180.v:3328.43-3328.134"
-  wire $eq$ls180.v:3328$111_Y
-  attribute \src "ls180.v:3345.47-3345.88"
-  wire $eq$ls180.v:3345$124_Y
-  attribute \src "ls180.v:3485.43-3485.134"
-  wire $eq$ls180.v:3485$141_Y
-  attribute \src "ls180.v:3502.47-3502.88"
-  wire $eq$ls180.v:3502$154_Y
-  attribute \src "ls180.v:3642.43-3642.134"
-  wire $eq$ls180.v:3642$171_Y
-  attribute \src "ls180.v:3659.47-3659.88"
-  wire $eq$ls180.v:3659$184_Y
-  attribute \src "ls180.v:3796.32-3796.56"
-  wire $eq$ls180.v:3796$231_Y
-  attribute \src "ls180.v:3797.32-3797.56"
-  wire $eq$ls180.v:3797$232_Y
-  attribute \src "ls180.v:3808.339-3808.418"
-  wire $eq$ls180.v:3808$246_Y
-  attribute \src "ls180.v:3808.423-3808.504"
-  wire $eq$ls180.v:3808$247_Y
-  attribute \src "ls180.v:3809.339-3809.418"
-  wire $eq$ls180.v:3809$259_Y
-  attribute \src "ls180.v:3809.423-3809.504"
-  wire $eq$ls180.v:3809$260_Y
-  attribute \src "ls180.v:3810.339-3810.418"
-  wire $eq$ls180.v:3810$272_Y
-  attribute \src "ls180.v:3810.423-3810.504"
-  wire $eq$ls180.v:3810$273_Y
-  attribute \src "ls180.v:3811.339-3811.418"
-  wire $eq$ls180.v:3811$285_Y
-  attribute \src "ls180.v:3811.423-3811.504"
-  wire $eq$ls180.v:3811$286_Y
-  attribute \src "ls180.v:3841.339-3841.418"
-  wire $eq$ls180.v:3841$304_Y
-  attribute \src "ls180.v:3841.423-3841.504"
-  wire $eq$ls180.v:3841$305_Y
-  attribute \src "ls180.v:3842.339-3842.418"
-  wire $eq$ls180.v:3842$317_Y
-  attribute \src "ls180.v:3842.423-3842.504"
-  wire $eq$ls180.v:3842$318_Y
-  attribute \src "ls180.v:3843.339-3843.418"
-  wire $eq$ls180.v:3843$330_Y
-  attribute \src "ls180.v:3843.423-3843.504"
-  wire $eq$ls180.v:3843$331_Y
-  attribute \src "ls180.v:3844.339-3844.418"
-  wire $eq$ls180.v:3844$343_Y
-  attribute \src "ls180.v:3844.423-3844.504"
-  wire $eq$ls180.v:3844$344_Y
-  attribute \src "ls180.v:3873.78-3873.113"
-  wire $eq$ls180.v:3873$353_Y
-  attribute \src "ls180.v:3876.78-3876.113"
-  wire $eq$ls180.v:3876$356_Y
-  attribute \src "ls180.v:3882.78-3882.113"
-  wire $eq$ls180.v:3882$360_Y
-  attribute \src "ls180.v:3885.78-3885.113"
-  wire $eq$ls180.v:3885$363_Y
-  attribute \src "ls180.v:3891.78-3891.113"
-  wire $eq$ls180.v:3891$367_Y
-  attribute \src "ls180.v:3894.78-3894.113"
-  wire $eq$ls180.v:3894$370_Y
-  attribute \src "ls180.v:3900.78-3900.113"
-  wire $eq$ls180.v:3900$374_Y
-  attribute \src "ls180.v:3903.78-3903.113"
-  wire $eq$ls180.v:3903$377_Y
-  attribute \src "ls180.v:3984.42-3984.82"
-  wire $eq$ls180.v:3984$400_Y
-  attribute \src "ls180.v:3984.145-3984.178"
-  wire $eq$ls180.v:3984$401_Y
-  attribute \src "ls180.v:3984.220-3984.253"
-  wire $eq$ls180.v:3984$404_Y
-  attribute \src "ls180.v:3984.295-3984.328"
-  wire $eq$ls180.v:3984$407_Y
-  attribute \src "ls180.v:3989.42-3989.82"
-  wire $eq$ls180.v:3989$416_Y
-  attribute \src "ls180.v:3989.145-3989.178"
-  wire $eq$ls180.v:3989$417_Y
-  attribute \src "ls180.v:3989.220-3989.253"
-  wire $eq$ls180.v:3989$420_Y
-  attribute \src "ls180.v:3989.295-3989.328"
-  wire $eq$ls180.v:3989$423_Y
-  attribute \src "ls180.v:3994.42-3994.82"
-  wire $eq$ls180.v:3994$432_Y
-  attribute \src "ls180.v:3994.145-3994.178"
-  wire $eq$ls180.v:3994$433_Y
-  attribute \src "ls180.v:3994.220-3994.253"
-  wire $eq$ls180.v:3994$436_Y
-  attribute \src "ls180.v:3994.295-3994.328"
-  wire $eq$ls180.v:3994$439_Y
-  attribute \src "ls180.v:3999.42-3999.82"
-  wire $eq$ls180.v:3999$448_Y
-  attribute \src "ls180.v:3999.145-3999.178"
-  wire $eq$ls180.v:3999$449_Y
-  attribute \src "ls180.v:3999.220-3999.253"
-  wire $eq$ls180.v:3999$452_Y
-  attribute \src "ls180.v:3999.295-3999.328"
-  wire $eq$ls180.v:3999$455_Y
-  attribute \src "ls180.v:4004.44-4004.77"
-  wire $eq$ls180.v:4004$464_Y
-  attribute \src "ls180.v:4004.83-4004.123"
-  wire $eq$ls180.v:4004$465_Y
-  attribute \src "ls180.v:4004.186-4004.219"
-  wire $eq$ls180.v:4004$466_Y
-  attribute \src "ls180.v:4004.261-4004.294"
-  wire $eq$ls180.v:4004$469_Y
-  attribute \src "ls180.v:4004.336-4004.369"
-  wire $eq$ls180.v:4004$472_Y
-  attribute \src "ls180.v:4004.418-4004.451"
-  wire $eq$ls180.v:4004$480_Y
-  attribute \src "ls180.v:4004.457-4004.497"
-  wire $eq$ls180.v:4004$481_Y
-  attribute \src "ls180.v:4004.560-4004.593"
-  wire $eq$ls180.v:4004$482_Y
-  attribute \src "ls180.v:4004.635-4004.668"
-  wire $eq$ls180.v:4004$485_Y
-  attribute \src "ls180.v:4004.710-4004.743"
-  wire $eq$ls180.v:4004$488_Y
-  attribute \src "ls180.v:4004.792-4004.825"
-  wire $eq$ls180.v:4004$496_Y
-  attribute \src "ls180.v:4004.831-4004.871"
-  wire $eq$ls180.v:4004$497_Y
-  attribute \src "ls180.v:4004.934-4004.967"
-  wire $eq$ls180.v:4004$498_Y
-  attribute \src "ls180.v:4004.1009-4004.1042"
-  wire $eq$ls180.v:4004$501_Y
-  attribute \src "ls180.v:4004.1084-4004.1117"
-  wire $eq$ls180.v:4004$504_Y
-  attribute \src "ls180.v:4004.1166-4004.1199"
-  wire $eq$ls180.v:4004$512_Y
-  attribute \src "ls180.v:4004.1205-4004.1245"
-  wire $eq$ls180.v:4004$513_Y
-  attribute \src "ls180.v:4004.1308-4004.1341"
-  wire $eq$ls180.v:4004$514_Y
-  attribute \src "ls180.v:4004.1383-4004.1416"
-  wire $eq$ls180.v:4004$517_Y
-  attribute \src "ls180.v:4004.1458-4004.1491"
-  wire $eq$ls180.v:4004$520_Y
-  attribute \src "ls180.v:4063.29-4063.57"
-  wire $eq$ls180.v:4063$533_Y
-  attribute \src "ls180.v:4070.11-4070.41"
-  wire $eq$ls180.v:4070$538_Y
-  attribute \src "ls180.v:4227.37-4227.111"
-  wire $eq$ls180.v:4227$603_Y
-  attribute \src "ls180.v:4228.37-4228.105"
-  wire $eq$ls180.v:4228$605_Y
-  attribute \src "ls180.v:4255.10-4255.67"
-  wire $eq$ls180.v:4255$609_Y
-  attribute \src "ls180.v:4285.35-4285.108"
-  wire $eq$ls180.v:4285$611_Y
-  attribute \src "ls180.v:4286.35-4286.102"
-  wire $eq$ls180.v:4286$613_Y
-  attribute \src "ls180.v:4314.10-4314.65"
-  wire $eq$ls180.v:4314$617_Y
-  attribute \src "ls180.v:4418.10-4418.40"
-  wire $eq$ls180.v:4418$644_Y
-  attribute \src "ls180.v:4475.10-4475.39"
-  wire $eq$ls180.v:4475$647_Y
-  attribute \src "ls180.v:4492.10-4492.39"
-  wire $eq$ls180.v:4492$649_Y
-  attribute \src "ls180.v:4520.38-4520.88"
-  wire $eq$ls180.v:4520$651_Y
-  attribute \src "ls180.v:4570.9-4570.40"
-  wire $eq$ls180.v:4570$661_Y
-  attribute \src "ls180.v:4579.36-4579.105"
-  wire $eq$ls180.v:4579$663_Y
-  attribute \src "ls180.v:4598.9-4598.40"
-  wire $eq$ls180.v:4598$667_Y
-  attribute \src "ls180.v:4610.10-4610.39"
-  wire $eq$ls180.v:4610$669_Y
-  attribute \src "ls180.v:4647.39-4647.94"
-  wire $eq$ls180.v:4647$673_Y
-  attribute \src "ls180.v:4684.32-4684.89"
-  wire $eq$ls180.v:4684$682_Y
-  attribute \src "ls180.v:4732.10-4732.40"
-  wire $eq$ls180.v:4732$686_Y
-  attribute \src "ls180.v:4781.40-4781.98"
-  wire $eq$ls180.v:4781$688_Y
-  attribute \src "ls180.v:4832.9-4832.41"
-  wire $eq$ls180.v:4832$698_Y
-  attribute \src "ls180.v:4841.37-4841.123"
-  wire $eq$ls180.v:4841$701_Y
-  attribute \src "ls180.v:4864.9-4864.41"
-  wire $eq$ls180.v:4864$704_Y
-  attribute \src "ls180.v:4874.10-4874.41"
-  wire $eq$ls180.v:4874$706_Y
-  attribute \src "ls180.v:5043.9-5043.47"
-  wire $eq$ls180.v:5043$888_Y
-  attribute \src "ls180.v:5073.10-5073.48"
-  wire $eq$ls180.v:5073$889_Y
-  attribute \src "ls180.v:5104.10-5104.78"
-  wire $eq$ls180.v:5104$894_Y
-  attribute \src "ls180.v:5104.83-5104.151"
-  wire $eq$ls180.v:5104$895_Y
-  attribute \src "ls180.v:5104.157-5104.225"
-  wire $eq$ls180.v:5104$897_Y
-  attribute \src "ls180.v:5104.231-5104.299"
-  wire $eq$ls180.v:5104$899_Y
-  attribute \src "ls180.v:5112.7-5112.44"
-  wire $eq$ls180.v:5112$903_Y
-  attribute \src "ls180.v:5122.7-5122.44"
-  wire $eq$ls180.v:5122$906_Y
-  attribute \src "ls180.v:5132.7-5132.44"
-  wire $eq$ls180.v:5132$909_Y
-  attribute \src "ls180.v:5142.7-5142.44"
-  wire $eq$ls180.v:5142$912_Y
-  attribute \src "ls180.v:5266.36-5266.64"
-  wire $eq$ls180.v:5266$963_Y
-  attribute \src "ls180.v:5272.10-5272.39"
-  wire $eq$ls180.v:5272$966_Y
-  attribute \src "ls180.v:5273.11-5273.39"
-  wire $eq$ls180.v:5273$967_Y
-  attribute \src "ls180.v:5285.34-5285.63"
-  wire $eq$ls180.v:5285$968_Y
-  attribute \src "ls180.v:5286.9-5286.37"
-  wire $eq$ls180.v:5286$969_Y
-  attribute \src "ls180.v:5293.10-5293.55"
-  wire $eq$ls180.v:5293$970_Y
-  attribute \src "ls180.v:5299.12-5299.41"
-  wire $eq$ls180.v:5299$971_Y
-  attribute \src "ls180.v:5302.13-5302.42"
-  wire $eq$ls180.v:5302$972_Y
-  attribute \src "ls180.v:5324.10-5324.76"
-  wire $eq$ls180.v:5324$977_Y
-  attribute \src "ls180.v:5339.35-5339.101"
-  wire $eq$ls180.v:5339$980_Y
-  attribute \src "ls180.v:5341.10-5341.56"
-  wire $eq$ls180.v:5341$981_Y
-  attribute \src "ls180.v:5350.12-5350.78"
-  wire $eq$ls180.v:5350$985_Y
-  attribute \src "ls180.v:5357.11-5357.57"
-  wire $eq$ls180.v:5357$986_Y
-  attribute \src "ls180.v:5474.10-5474.105"
-  wire $eq$ls180.v:5474$1003_Y
-  attribute \src "ls180.v:5564.39-5564.106"
-  wire $eq$ls180.v:5564$1009_Y
-  attribute \src "ls180.v:5594.44-5594.82"
-  wire $eq$ls180.v:5594$1012_Y
-  attribute \src "ls180.v:5595.43-5595.81"
-  wire $eq$ls180.v:5595$1013_Y
-  attribute \src "ls180.v:5695.85-5695.106"
-  wire $eq$ls180.v:5695$1029_Y
-  attribute \src "ls180.v:5696.85-5696.106"
-  wire $eq$ls180.v:5696$1031_Y
-  attribute \src "ls180.v:5697.85-5697.106"
-  wire $eq$ls180.v:5697$1033_Y
-  attribute \src "ls180.v:5698.57-5698.78"
-  wire $eq$ls180.v:5698$1035_Y
-  attribute \src "ls180.v:5699.57-5699.78"
-  wire $eq$ls180.v:5699$1037_Y
-  attribute \src "ls180.v:5700.85-5700.106"
-  wire $eq$ls180.v:5700$1039_Y
-  attribute \src "ls180.v:5701.85-5701.106"
-  wire $eq$ls180.v:5701$1041_Y
-  attribute \src "ls180.v:5702.85-5702.106"
-  wire $eq$ls180.v:5702$1043_Y
-  attribute \src "ls180.v:5703.57-5703.78"
-  wire $eq$ls180.v:5703$1045_Y
-  attribute \src "ls180.v:5704.57-5704.78"
-  wire $eq$ls180.v:5704$1047_Y
-  attribute \src "ls180.v:5708.27-5708.59"
-  wire $eq$ls180.v:5708$1050_Y
-  attribute \src "ls180.v:5709.27-5709.68"
-  wire $eq$ls180.v:5709$1051_Y
-  attribute \src "ls180.v:5710.27-5710.66"
-  wire $eq$ls180.v:5710$1052_Y
-  attribute \src "ls180.v:5711.27-5711.61"
-  wire $eq$ls180.v:5711$1053_Y
-  attribute \src "ls180.v:5712.27-5712.65"
-  wire $eq$ls180.v:5712$1054_Y
-  attribute \src "ls180.v:5768.24-5768.45"
-  wire $eq$ls180.v:5768$1081_Y
-  attribute \src "ls180.v:5769.32-5769.77"
-  wire $eq$ls180.v:5769$1082_Y
-  attribute \src "ls180.v:5771.97-5771.141"
-  wire $eq$ls180.v:5771$1084_Y
-  attribute \src "ls180.v:5772.100-5772.144"
-  wire $eq$ls180.v:5772$1088_Y
-  attribute \src "ls180.v:5774.99-5774.143"
-  wire $eq$ls180.v:5774$1091_Y
-  attribute \src "ls180.v:5775.102-5775.146"
-  wire $eq$ls180.v:5775$1095_Y
-  attribute \src "ls180.v:5777.99-5777.143"
-  wire $eq$ls180.v:5777$1098_Y
-  attribute \src "ls180.v:5778.102-5778.146"
-  wire $eq$ls180.v:5778$1102_Y
-  attribute \src "ls180.v:5780.99-5780.143"
-  wire $eq$ls180.v:5780$1105_Y
-  attribute \src "ls180.v:5781.102-5781.146"
-  wire $eq$ls180.v:5781$1109_Y
-  attribute \src "ls180.v:5783.99-5783.143"
-  wire $eq$ls180.v:5783$1112_Y
-  attribute \src "ls180.v:5784.102-5784.146"
-  wire $eq$ls180.v:5784$1116_Y
-  attribute \src "ls180.v:5786.102-5786.146"
-  wire $eq$ls180.v:5786$1119_Y
-  attribute \src "ls180.v:5787.105-5787.149"
-  wire $eq$ls180.v:5787$1123_Y
-  attribute \src "ls180.v:5789.102-5789.146"
-  wire $eq$ls180.v:5789$1126_Y
-  attribute \src "ls180.v:5790.105-5790.149"
-  wire $eq$ls180.v:5790$1130_Y
-  attribute \src "ls180.v:5792.102-5792.146"
-  wire $eq$ls180.v:5792$1133_Y
-  attribute \src "ls180.v:5793.105-5793.149"
-  wire $eq$ls180.v:5793$1137_Y
-  attribute \src "ls180.v:5795.102-5795.146"
-  wire $eq$ls180.v:5795$1140_Y
-  attribute \src "ls180.v:5796.105-5796.149"
-  wire $eq$ls180.v:5796$1144_Y
-  attribute \src "ls180.v:5807.32-5807.77"
-  wire $eq$ls180.v:5807$1146_Y
-  attribute \src "ls180.v:5809.94-5809.138"
-  wire $eq$ls180.v:5809$1148_Y
-  attribute \src "ls180.v:5810.97-5810.141"
-  wire $eq$ls180.v:5810$1152_Y
-  attribute \src "ls180.v:5812.94-5812.138"
-  wire $eq$ls180.v:5812$1155_Y
-  attribute \src "ls180.v:5813.97-5813.141"
-  wire $eq$ls180.v:5813$1159_Y
-  attribute \src "ls180.v:5815.94-5815.138"
-  wire $eq$ls180.v:5815$1162_Y
-  attribute \src "ls180.v:5816.97-5816.141"
-  wire $eq$ls180.v:5816$1166_Y
-  attribute \src "ls180.v:5818.94-5818.138"
-  wire $eq$ls180.v:5818$1169_Y
-  attribute \src "ls180.v:5819.97-5819.141"
-  wire $eq$ls180.v:5819$1173_Y
-  attribute \src "ls180.v:5821.95-5821.139"
-  wire $eq$ls180.v:5821$1176_Y
-  attribute \src "ls180.v:5822.98-5822.142"
-  wire $eq$ls180.v:5822$1180_Y
-  attribute \src "ls180.v:5824.95-5824.139"
-  wire $eq$ls180.v:5824$1183_Y
-  attribute \src "ls180.v:5825.98-5825.142"
-  wire $eq$ls180.v:5825$1187_Y
-  attribute \src "ls180.v:5833.32-5833.78"
-  wire $eq$ls180.v:5833$1189_Y
-  attribute \src "ls180.v:5835.93-5835.135"
-  wire $eq$ls180.v:5835$1191_Y
-  attribute \src "ls180.v:5836.96-5836.138"
-  wire $eq$ls180.v:5836$1195_Y
-  attribute \src "ls180.v:5838.92-5838.134"
-  wire $eq$ls180.v:5838$1198_Y
-  attribute \src "ls180.v:5839.95-5839.137"
-  wire $eq$ls180.v:5839$1202_Y
-  attribute \src "ls180.v:5847.32-5847.77"
-  wire $eq$ls180.v:5847$1204_Y
-  attribute \src "ls180.v:5849.98-5849.142"
-  wire $eq$ls180.v:5849$1206_Y
-  attribute \src "ls180.v:5850.101-5850.145"
-  wire $eq$ls180.v:5850$1210_Y
-  attribute \src "ls180.v:5852.97-5852.141"
-  wire $eq$ls180.v:5852$1213_Y
-  attribute \src "ls180.v:5853.100-5853.144"
-  wire $eq$ls180.v:5853$1217_Y
-  attribute \src "ls180.v:5855.97-5855.141"
-  wire $eq$ls180.v:5855$1220_Y
-  attribute \src "ls180.v:5856.100-5856.144"
-  wire $eq$ls180.v:5856$1224_Y
-  attribute \src "ls180.v:5858.97-5858.141"
-  wire $eq$ls180.v:5858$1227_Y
-  attribute \src "ls180.v:5859.100-5859.144"
-  wire $eq$ls180.v:5859$1231_Y
-  attribute \src "ls180.v:5861.97-5861.141"
-  wire $eq$ls180.v:5861$1234_Y
-  attribute \src "ls180.v:5862.100-5862.144"
-  wire $eq$ls180.v:5862$1238_Y
-  attribute \src "ls180.v:5864.98-5864.142"
-  wire $eq$ls180.v:5864$1241_Y
-  attribute \src "ls180.v:5865.101-5865.145"
-  wire $eq$ls180.v:5865$1245_Y
-  attribute \src "ls180.v:5867.98-5867.142"
-  wire $eq$ls180.v:5867$1248_Y
-  attribute \src "ls180.v:5868.101-5868.145"
-  wire $eq$ls180.v:5868$1252_Y
-  attribute \src "ls180.v:5870.98-5870.142"
-  wire $eq$ls180.v:5870$1255_Y
-  attribute \src "ls180.v:5871.101-5871.145"
-  wire $eq$ls180.v:5871$1259_Y
-  attribute \src "ls180.v:5873.98-5873.142"
-  wire $eq$ls180.v:5873$1262_Y
-  attribute \src "ls180.v:5874.101-5874.145"
-  wire $eq$ls180.v:5874$1266_Y
-  attribute \src "ls180.v:5884.32-5884.78"
-  wire $eq$ls180.v:5884$1268_Y
-  attribute \src "ls180.v:5886.98-5886.142"
-  wire $eq$ls180.v:5886$1270_Y
-  attribute \src "ls180.v:5887.101-5887.145"
-  wire $eq$ls180.v:5887$1274_Y
-  attribute \src "ls180.v:5889.97-5889.141"
-  wire $eq$ls180.v:5889$1277_Y
-  attribute \src "ls180.v:5890.100-5890.144"
-  wire $eq$ls180.v:5890$1281_Y
-  attribute \src "ls180.v:5892.97-5892.141"
-  wire $eq$ls180.v:5892$1284_Y
-  attribute \src "ls180.v:5893.100-5893.144"
-  wire $eq$ls180.v:5893$1288_Y
-  attribute \src "ls180.v:5895.97-5895.141"
-  wire $eq$ls180.v:5895$1291_Y
-  attribute \src "ls180.v:5896.100-5896.144"
-  wire $eq$ls180.v:5896$1295_Y
-  attribute \src "ls180.v:5898.97-5898.141"
-  wire $eq$ls180.v:5898$1298_Y
-  attribute \src "ls180.v:5899.100-5899.144"
-  wire $eq$ls180.v:5899$1302_Y
-  attribute \src "ls180.v:5901.98-5901.142"
-  wire $eq$ls180.v:5901$1305_Y
-  attribute \src "ls180.v:5902.101-5902.145"
-  wire $eq$ls180.v:5902$1309_Y
-  attribute \src "ls180.v:5904.98-5904.142"
-  wire $eq$ls180.v:5904$1312_Y
-  attribute \src "ls180.v:5905.101-5905.145"
-  wire $eq$ls180.v:5905$1316_Y
-  attribute \src "ls180.v:5907.98-5907.142"
-  wire $eq$ls180.v:5907$1319_Y
-  attribute \src "ls180.v:5908.101-5908.145"
-  wire $eq$ls180.v:5908$1323_Y
-  attribute \src "ls180.v:5910.98-5910.142"
-  wire $eq$ls180.v:5910$1326_Y
-  attribute \src "ls180.v:5911.101-5911.145"
-  wire $eq$ls180.v:5911$1330_Y
-  attribute \src "ls180.v:5921.32-5921.78"
-  wire $eq$ls180.v:5921$1332_Y
-  attribute \src "ls180.v:5923.100-5923.144"
-  wire $eq$ls180.v:5923$1334_Y
-  attribute \src "ls180.v:5924.103-5924.147"
-  wire $eq$ls180.v:5924$1338_Y
-  attribute \src "ls180.v:5926.100-5926.144"
-  wire $eq$ls180.v:5926$1341_Y
-  attribute \src "ls180.v:5927.103-5927.147"
-  wire $eq$ls180.v:5927$1345_Y
-  attribute \src "ls180.v:5929.100-5929.144"
-  wire $eq$ls180.v:5929$1348_Y
-  attribute \src "ls180.v:5930.103-5930.147"
-  wire $eq$ls180.v:5930$1352_Y
-  attribute \src "ls180.v:5932.100-5932.144"
-  wire $eq$ls180.v:5932$1355_Y
-  attribute \src "ls180.v:5933.103-5933.147"
-  wire $eq$ls180.v:5933$1359_Y
-  attribute \src "ls180.v:5935.100-5935.144"
-  wire $eq$ls180.v:5935$1362_Y
-  attribute \src "ls180.v:5936.103-5936.147"
-  wire $eq$ls180.v:5936$1366_Y
-  attribute \src "ls180.v:5938.100-5938.144"
-  wire $eq$ls180.v:5938$1369_Y
-  attribute \src "ls180.v:5939.103-5939.147"
-  wire $eq$ls180.v:5939$1373_Y
-  attribute \src "ls180.v:5941.100-5941.144"
-  wire $eq$ls180.v:5941$1376_Y
-  attribute \src "ls180.v:5942.103-5942.147"
-  wire $eq$ls180.v:5942$1380_Y
-  attribute \src "ls180.v:5944.100-5944.144"
-  wire $eq$ls180.v:5944$1383_Y
-  attribute \src "ls180.v:5945.103-5945.147"
-  wire $eq$ls180.v:5945$1387_Y
-  attribute \src "ls180.v:5947.102-5947.146"
-  wire $eq$ls180.v:5947$1390_Y
-  attribute \src "ls180.v:5948.105-5948.149"
-  wire $eq$ls180.v:5948$1394_Y
-  attribute \src "ls180.v:5950.102-5950.146"
-  wire $eq$ls180.v:5950$1397_Y
-  attribute \src "ls180.v:5951.105-5951.149"
-  wire $eq$ls180.v:5951$1401_Y
-  attribute \src "ls180.v:5953.102-5953.147"
-  wire $eq$ls180.v:5953$1404_Y
-  attribute \src "ls180.v:5954.105-5954.150"
-  wire $eq$ls180.v:5954$1408_Y
-  attribute \src "ls180.v:5956.102-5956.147"
-  wire $eq$ls180.v:5956$1411_Y
-  attribute \src "ls180.v:5957.105-5957.150"
-  wire $eq$ls180.v:5957$1415_Y
-  attribute \src "ls180.v:5959.102-5959.147"
-  wire $eq$ls180.v:5959$1418_Y
-  attribute \src "ls180.v:5960.105-5960.150"
-  wire $eq$ls180.v:5960$1422_Y
-  attribute \src "ls180.v:5962.99-5962.144"
-  wire $eq$ls180.v:5962$1425_Y
-  attribute \src "ls180.v:5963.102-5963.147"
-  wire $eq$ls180.v:5963$1429_Y
-  attribute \src "ls180.v:5965.100-5965.145"
-  wire $eq$ls180.v:5965$1432_Y
-  attribute \src "ls180.v:5966.103-5966.148"
-  wire $eq$ls180.v:5966$1436_Y
-  attribute \src "ls180.v:5983.32-5983.78"
-  wire $eq$ls180.v:5983$1438_Y
-  attribute \src "ls180.v:5985.104-5985.148"
-  wire $eq$ls180.v:5985$1440_Y
-  attribute \src "ls180.v:5986.107-5986.151"
-  wire $eq$ls180.v:5986$1444_Y
-  attribute \src "ls180.v:5988.104-5988.148"
-  wire $eq$ls180.v:5988$1447_Y
-  attribute \src "ls180.v:5989.107-5989.151"
-  wire $eq$ls180.v:5989$1451_Y
-  attribute \src "ls180.v:5991.104-5991.148"
-  wire $eq$ls180.v:5991$1454_Y
-  attribute \src "ls180.v:5992.107-5992.151"
-  wire $eq$ls180.v:5992$1458_Y
-  attribute \src "ls180.v:5994.104-5994.148"
-  wire $eq$ls180.v:5994$1461_Y
-  attribute \src "ls180.v:5995.107-5995.151"
-  wire $eq$ls180.v:5995$1465_Y
-  attribute \src "ls180.v:5997.103-5997.147"
-  wire $eq$ls180.v:5997$1468_Y
-  attribute \src "ls180.v:5998.106-5998.150"
-  wire $eq$ls180.v:5998$1472_Y
-  attribute \src "ls180.v:6000.103-6000.147"
-  wire $eq$ls180.v:6000$1475_Y
-  attribute \src "ls180.v:6001.106-6001.150"
-  wire $eq$ls180.v:6001$1479_Y
-  attribute \src "ls180.v:6003.103-6003.147"
-  wire $eq$ls180.v:6003$1482_Y
-  attribute \src "ls180.v:6004.106-6004.150"
-  wire $eq$ls180.v:6004$1486_Y
-  attribute \src "ls180.v:6006.103-6006.147"
-  wire $eq$ls180.v:6006$1489_Y
-  attribute \src "ls180.v:6007.106-6007.150"
-  wire $eq$ls180.v:6007$1493_Y
-  attribute \src "ls180.v:6009.94-6009.138"
-  wire $eq$ls180.v:6009$1496_Y
-  attribute \src "ls180.v:6010.97-6010.141"
-  wire $eq$ls180.v:6010$1500_Y
-  attribute \src "ls180.v:6012.105-6012.149"
-  wire $eq$ls180.v:6012$1503_Y
-  attribute \src "ls180.v:6013.108-6013.152"
-  wire $eq$ls180.v:6013$1507_Y
-  attribute \src "ls180.v:6015.105-6015.150"
-  wire $eq$ls180.v:6015$1510_Y
-  attribute \src "ls180.v:6016.108-6016.153"
-  wire $eq$ls180.v:6016$1514_Y
-  attribute \src "ls180.v:6018.105-6018.150"
-  wire $eq$ls180.v:6018$1517_Y
-  attribute \src "ls180.v:6019.108-6019.153"
-  wire $eq$ls180.v:6019$1521_Y
-  attribute \src "ls180.v:6021.105-6021.150"
-  wire $eq$ls180.v:6021$1524_Y
-  attribute \src "ls180.v:6022.108-6022.153"
-  wire $eq$ls180.v:6022$1528_Y
-  attribute \src "ls180.v:6024.105-6024.150"
-  wire $eq$ls180.v:6024$1531_Y
-  attribute \src "ls180.v:6025.108-6025.153"
-  wire $eq$ls180.v:6025$1535_Y
-  attribute \src "ls180.v:6027.105-6027.150"
-  wire $eq$ls180.v:6027$1538_Y
-  attribute \src "ls180.v:6028.108-6028.153"
-  wire $eq$ls180.v:6028$1542_Y
-  attribute \src "ls180.v:6030.104-6030.149"
-  wire $eq$ls180.v:6030$1545_Y
-  attribute \src "ls180.v:6031.107-6031.152"
-  wire $eq$ls180.v:6031$1549_Y
-  attribute \src "ls180.v:6033.104-6033.149"
-  wire $eq$ls180.v:6033$1552_Y
-  attribute \src "ls180.v:6034.107-6034.152"
-  wire $eq$ls180.v:6034$1556_Y
-  attribute \src "ls180.v:6036.104-6036.149"
-  wire $eq$ls180.v:6036$1559_Y
-  attribute \src "ls180.v:6037.107-6037.152"
-  wire $eq$ls180.v:6037$1563_Y
-  attribute \src "ls180.v:6039.104-6039.149"
-  wire $eq$ls180.v:6039$1566_Y
-  attribute \src "ls180.v:6040.107-6040.152"
-  wire $eq$ls180.v:6040$1570_Y
-  attribute \src "ls180.v:6042.104-6042.149"
-  wire $eq$ls180.v:6042$1573_Y
-  attribute \src "ls180.v:6043.107-6043.152"
-  wire $eq$ls180.v:6043$1577_Y
-  attribute \src "ls180.v:6045.104-6045.149"
-  wire $eq$ls180.v:6045$1580_Y
-  attribute \src "ls180.v:6046.107-6046.152"
-  wire $eq$ls180.v:6046$1584_Y
-  attribute \src "ls180.v:6048.104-6048.149"
-  wire $eq$ls180.v:6048$1587_Y
-  attribute \src "ls180.v:6049.107-6049.152"
-  wire $eq$ls180.v:6049$1591_Y
-  attribute \src "ls180.v:6051.104-6051.149"
-  wire $eq$ls180.v:6051$1594_Y
-  attribute \src "ls180.v:6052.107-6052.152"
-  wire $eq$ls180.v:6052$1598_Y
-  attribute \src "ls180.v:6054.104-6054.149"
-  wire $eq$ls180.v:6054$1601_Y
-  attribute \src "ls180.v:6055.107-6055.152"
-  wire $eq$ls180.v:6055$1605_Y
-  attribute \src "ls180.v:6057.104-6057.149"
-  wire $eq$ls180.v:6057$1608_Y
-  attribute \src "ls180.v:6058.107-6058.152"
-  wire $eq$ls180.v:6058$1612_Y
-  attribute \src "ls180.v:6060.100-6060.145"
-  wire $eq$ls180.v:6060$1615_Y
-  attribute \src "ls180.v:6061.103-6061.148"
-  wire $eq$ls180.v:6061$1619_Y
-  attribute \src "ls180.v:6063.101-6063.146"
-  wire $eq$ls180.v:6063$1622_Y
-  attribute \src "ls180.v:6064.104-6064.149"
-  wire $eq$ls180.v:6064$1626_Y
-  attribute \src "ls180.v:6066.104-6066.149"
-  wire $eq$ls180.v:6066$1629_Y
-  attribute \src "ls180.v:6067.107-6067.152"
-  wire $eq$ls180.v:6067$1633_Y
-  attribute \src "ls180.v:6069.104-6069.149"
-  wire $eq$ls180.v:6069$1636_Y
-  attribute \src "ls180.v:6070.107-6070.152"
-  wire $eq$ls180.v:6070$1640_Y
-  attribute \src "ls180.v:6072.103-6072.148"
-  wire $eq$ls180.v:6072$1643_Y
-  attribute \src "ls180.v:6073.106-6073.151"
-  wire $eq$ls180.v:6073$1647_Y
-  attribute \src "ls180.v:6075.103-6075.148"
-  wire $eq$ls180.v:6075$1650_Y
-  attribute \src "ls180.v:6076.106-6076.151"
-  wire $eq$ls180.v:6076$1654_Y
-  attribute \src "ls180.v:6078.103-6078.148"
-  wire $eq$ls180.v:6078$1657_Y
-  attribute \src "ls180.v:6079.106-6079.151"
-  wire $eq$ls180.v:6079$1661_Y
-  attribute \src "ls180.v:6081.103-6081.148"
-  wire $eq$ls180.v:6081$1664_Y
-  attribute \src "ls180.v:6082.106-6082.151"
-  wire $eq$ls180.v:6082$1668_Y
-  attribute \src "ls180.v:6118.32-6118.78"
-  wire $eq$ls180.v:6118$1670_Y
-  attribute \src "ls180.v:6120.100-6120.144"
-  wire $eq$ls180.v:6120$1672_Y
-  attribute \src "ls180.v:6121.103-6121.147"
-  wire $eq$ls180.v:6121$1676_Y
-  attribute \src "ls180.v:6123.100-6123.144"
-  wire $eq$ls180.v:6123$1679_Y
-  attribute \src "ls180.v:6124.103-6124.147"
-  wire $eq$ls180.v:6124$1683_Y
-  attribute \src "ls180.v:6126.100-6126.144"
-  wire $eq$ls180.v:6126$1686_Y
-  attribute \src "ls180.v:6127.103-6127.147"
-  wire $eq$ls180.v:6127$1690_Y
-  attribute \src "ls180.v:6129.100-6129.144"
-  wire $eq$ls180.v:6129$1693_Y
-  attribute \src "ls180.v:6130.103-6130.147"
-  wire $eq$ls180.v:6130$1697_Y
-  attribute \src "ls180.v:6132.100-6132.144"
-  wire $eq$ls180.v:6132$1700_Y
-  attribute \src "ls180.v:6133.103-6133.147"
-  wire $eq$ls180.v:6133$1704_Y
-  attribute \src "ls180.v:6135.100-6135.144"
-  wire $eq$ls180.v:6135$1707_Y
-  attribute \src "ls180.v:6136.103-6136.147"
-  wire $eq$ls180.v:6136$1711_Y
-  attribute \src "ls180.v:6138.100-6138.144"
-  wire $eq$ls180.v:6138$1714_Y
-  attribute \src "ls180.v:6139.103-6139.147"
-  wire $eq$ls180.v:6139$1718_Y
-  attribute \src "ls180.v:6141.100-6141.144"
-  wire $eq$ls180.v:6141$1721_Y
-  attribute \src "ls180.v:6142.103-6142.147"
-  wire $eq$ls180.v:6142$1725_Y
-  attribute \src "ls180.v:6144.102-6144.146"
-  wire $eq$ls180.v:6144$1728_Y
-  attribute \src "ls180.v:6145.105-6145.149"
-  wire $eq$ls180.v:6145$1732_Y
-  attribute \src "ls180.v:6147.102-6147.146"
-  wire $eq$ls180.v:6147$1735_Y
-  attribute \src "ls180.v:6148.105-6148.149"
-  wire $eq$ls180.v:6148$1739_Y
-  attribute \src "ls180.v:6150.102-6150.147"
-  wire $eq$ls180.v:6150$1742_Y
-  attribute \src "ls180.v:6151.105-6151.150"
-  wire $eq$ls180.v:6151$1746_Y
-  attribute \src "ls180.v:6153.102-6153.147"
-  wire $eq$ls180.v:6153$1749_Y
-  attribute \src "ls180.v:6154.105-6154.150"
-  wire $eq$ls180.v:6154$1753_Y
-  attribute \src "ls180.v:6156.102-6156.147"
-  wire $eq$ls180.v:6156$1756_Y
-  attribute \src "ls180.v:6157.105-6157.150"
-  wire $eq$ls180.v:6157$1760_Y
-  attribute \src "ls180.v:6159.99-6159.144"
-  wire $eq$ls180.v:6159$1763_Y
-  attribute \src "ls180.v:6160.102-6160.147"
-  wire $eq$ls180.v:6160$1767_Y
+  wire $and$ls180.v:6163$1689_Y
+  attribute \src "ls180.v:6165.43-6165.96"
+  wire $and$ls180.v:6165$1690_Y
+  attribute \src "ls180.v:6165.42-6165.147"
+  wire $and$ls180.v:6165$1692_Y
+  attribute \src "ls180.v:6166.43-6166.99"
+  wire $and$ls180.v:6166$1694_Y
+  attribute \src "ls180.v:6166.42-6166.150"
+  wire $and$ls180.v:6166$1696_Y
+  attribute \src "ls180.v:6168.46-6168.99"
+  wire $and$ls180.v:6168$1697_Y
+  attribute \src "ls180.v:6168.45-6168.150"
+  wire $and$ls180.v:6168$1699_Y
+  attribute \src "ls180.v:6169.46-6169.102"
+  wire $and$ls180.v:6169$1701_Y
+  attribute \src "ls180.v:6169.45-6169.153"
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+  attribute \src "ls180.v:7292.39-7292.104"
+  wire $and$ls180.v:7292$2432_Y
+  attribute \src "ls180.v:7292.38-7292.150"
+  wire $and$ls180.v:7292$2433_Y
+  attribute \src "ls180.v:7295.39-7295.82"
+  wire $and$ls180.v:7295$2434_Y
+  attribute \src "ls180.v:7295.38-7295.117"
+  wire $and$ls180.v:7295$2435_Y
+  attribute \src "ls180.v:7514.17-7514.67"
+  wire $and$ls180.v:7514$2442_Y
+  attribute \src "ls180.v:7593.8-7593.67"
+  wire $and$ls180.v:7593$2473_Y
+  attribute \src "ls180.v:7593.7-7593.102"
+  wire $and$ls180.v:7593$2475_Y
+  attribute \src "ls180.v:7612.7-7612.75"
+  wire $and$ls180.v:7612$2479_Y
+  attribute \src "ls180.v:7616.8-7616.65"
+  wire $and$ls180.v:7616$2480_Y
+  attribute \src "ls180.v:7616.7-7616.99"
+  wire $and$ls180.v:7616$2482_Y
+  attribute \src "ls180.v:7620.8-7620.65"
+  wire $and$ls180.v:7620$2483_Y
+  attribute \src "ls180.v:7620.7-7620.99"
+  wire $and$ls180.v:7620$2485_Y
+  attribute \src "ls180.v:7624.8-7624.65"
+  wire $and$ls180.v:7624$2486_Y
+  attribute \src "ls180.v:7624.7-7624.99"
+  wire $and$ls180.v:7624$2488_Y
+  attribute \src "ls180.v:7632.7-7632.56"
+  wire $and$ls180.v:7632$2490_Y
+  attribute \src "ls180.v:7660.7-7660.75"
+  wire $and$ls180.v:7660$2497_Y
+  attribute \src "ls180.v:7702.8-7702.131"
+  wire $and$ls180.v:7702$2503_Y
+  attribute \src "ls180.v:7702.7-7702.190"
+  wire $and$ls180.v:7702$2505_Y
+  attribute \src "ls180.v:7708.8-7708.131"
+  wire $and$ls180.v:7708$2508_Y
+  attribute \src "ls180.v:7708.7-7708.190"
+  wire $and$ls180.v:7708$2510_Y
+  attribute \src "ls180.v:7748.8-7748.131"
+  wire $and$ls180.v:7748$2519_Y
+  attribute \src "ls180.v:7748.7-7748.190"
+  wire $and$ls180.v:7748$2521_Y
+  attribute \src "ls180.v:7754.8-7754.131"
+  wire $and$ls180.v:7754$2524_Y
+  attribute \src "ls180.v:7754.7-7754.190"
+  wire $and$ls180.v:7754$2526_Y
+  attribute \src "ls180.v:7794.8-7794.131"
+  wire $and$ls180.v:7794$2535_Y
+  attribute \src "ls180.v:7794.7-7794.190"
+  wire $and$ls180.v:7794$2537_Y
+  attribute \src "ls180.v:7800.8-7800.131"
+  wire $and$ls180.v:7800$2540_Y
+  attribute \src "ls180.v:7800.7-7800.190"
+  wire $and$ls180.v:7800$2542_Y
+  attribute \src "ls180.v:7840.8-7840.131"
+  wire $and$ls180.v:7840$2551_Y
+  attribute \src "ls180.v:7840.7-7840.190"
+  wire $and$ls180.v:7840$2553_Y
+  attribute \src "ls180.v:7846.8-7846.131"
+  wire $and$ls180.v:7846$2556_Y
+  attribute \src "ls180.v:7846.7-7846.190"
+  wire $and$ls180.v:7846$2558_Y
+  attribute \src "ls180.v:8043.48-8043.124"
+  wire $and$ls180.v:8043$2583_Y
+  attribute \src "ls180.v:8043.130-8043.206"
+  wire $and$ls180.v:8043$2586_Y
+  attribute \src "ls180.v:8043.212-8043.288"
+  wire $and$ls180.v:8043$2589_Y
+  attribute \src "ls180.v:8043.294-8043.370"
+  wire $and$ls180.v:8043$2592_Y
+  attribute \src "ls180.v:8044.49-8044.125"
+  wire $and$ls180.v:8044$2595_Y
+  attribute \src "ls180.v:8044.131-8044.207"
+  wire $and$ls180.v:8044$2598_Y
+  attribute \src "ls180.v:8044.213-8044.289"
+  wire $and$ls180.v:8044$2601_Y
+  attribute \src "ls180.v:8044.295-8044.371"
+  wire $and$ls180.v:8044$2604_Y
+  attribute \src "ls180.v:8063.8-8063.49"
+  wire $and$ls180.v:8063$2607_Y
+  attribute \src "ls180.v:8066.8-8066.53"
+  wire $and$ls180.v:8066$2608_Y
+  attribute \src "ls180.v:8071.8-8071.59"
+  wire $and$ls180.v:8071$2610_Y
+  attribute \src "ls180.v:8071.7-8071.90"
+  wire $and$ls180.v:8071$2612_Y
+  attribute \src "ls180.v:8077.8-8077.59"
+  wire $and$ls180.v:8077$2613_Y
+  attribute \src "ls180.v:8101.8-8101.48"
+  wire $and$ls180.v:8101$2620_Y
+  attribute \src "ls180.v:8134.7-8134.57"
+  wire $and$ls180.v:8134$2626_Y
+  attribute \src "ls180.v:8141.7-8141.57"
+  wire $and$ls180.v:8141$2628_Y
+  attribute \src "ls180.v:8151.8-8151.75"
+  wire $and$ls180.v:8151$2629_Y
+  attribute \src "ls180.v:8151.7-8151.107"
+  wire $and$ls180.v:8151$2631_Y
+  attribute \src "ls180.v:8157.8-8157.75"
+  wire $and$ls180.v:8157$2634_Y
+  attribute \src "ls180.v:8157.7-8157.107"
+  wire $and$ls180.v:8157$2636_Y
+  attribute \src "ls180.v:8173.8-8173.75"
+  wire $and$ls180.v:8173$2640_Y
+  attribute \src "ls180.v:8173.7-8173.107"
+  wire $and$ls180.v:8173$2642_Y
+  attribute \src "ls180.v:8179.8-8179.75"
+  wire $and$ls180.v:8179$2645_Y
+  attribute \src "ls180.v:8179.7-8179.107"
+  wire $and$ls180.v:8179$2647_Y
+  attribute \src "ls180.v:8327.7-8327.96"
+  wire $and$ls180.v:8327$2675_Y
+  attribute \src "ls180.v:8328.8-8328.93"
+  wire $and$ls180.v:8328$2676_Y
+  attribute \src "ls180.v:8336.8-8336.93"
+  wire $and$ls180.v:8336$2677_Y
+  attribute \src "ls180.v:8408.7-8408.98"
+  wire $and$ls180.v:8408$2687_Y
+  attribute \src "ls180.v:8409.8-8409.95"
+  wire $and$ls180.v:8409$2688_Y
+  attribute \src "ls180.v:8417.8-8417.95"
+  wire $and$ls180.v:8417$2689_Y
+  attribute \src "ls180.v:8487.7-8487.100"
+  wire $and$ls180.v:8487$2699_Y
+  attribute \src "ls180.v:8488.8-8488.97"
+  wire $and$ls180.v:8488$2700_Y
+  attribute \src "ls180.v:8496.8-8496.97"
+  wire $and$ls180.v:8496$2701_Y
+  attribute \src "ls180.v:8587.7-8587.82"
+  wire $and$ls180.v:8587$2707_Y
+  attribute \src "ls180.v:8590.7-8590.82"
+  wire $and$ls180.v:8590$2708_Y
+  attribute \src "ls180.v:8593.7-8593.82"
+  wire $and$ls180.v:8593$2709_Y
+  attribute \src "ls180.v:8596.7-8596.82"
+  wire $and$ls180.v:8596$2710_Y
+  attribute \src "ls180.v:8599.7-8599.82"
+  wire $and$ls180.v:8599$2711_Y
+  attribute \src "ls180.v:8604.7-8604.82"
+  wire $and$ls180.v:8604$2712_Y
+  attribute \src "ls180.v:8609.7-8609.82"
+  wire $and$ls180.v:8609$2713_Y
+  attribute \src "ls180.v:8614.7-8614.82"
+  wire $and$ls180.v:8614$2714_Y
+  attribute \src "ls180.v:8619.7-8619.82"
+  wire $and$ls180.v:8619$2715_Y
+  attribute \src "ls180.v:8684.8-8684.83"
+  wire $and$ls180.v:8684$2718_Y
+  attribute \src "ls180.v:8684.7-8684.119"
+  wire $and$ls180.v:8684$2720_Y
+  attribute \src "ls180.v:8690.8-8690.83"
+  wire $and$ls180.v:8690$2723_Y
+  attribute \src "ls180.v:8690.7-8690.119"
+  wire $and$ls180.v:8690$2725_Y
+  attribute \src "ls180.v:8710.7-8710.88"
+  wire $and$ls180.v:8710$2732_Y
+  attribute \src "ls180.v:8711.8-8711.85"
+  wire $and$ls180.v:8711$2733_Y
+  attribute \src "ls180.v:8719.8-8719.85"
+  wire $and$ls180.v:8719$2734_Y
+  attribute \src "ls180.v:8763.7-8763.88"
+  wire $and$ls180.v:8763$2738_Y
+  attribute \src "ls180.v:8770.8-8770.83"
+  wire $and$ls180.v:8770$2740_Y
+  attribute \src "ls180.v:8770.7-8770.119"
+  wire $and$ls180.v:8770$2742_Y
+  attribute \src "ls180.v:8776.8-8776.83"
+  wire $and$ls180.v:8776$2745_Y
+  attribute \src "ls180.v:8776.7-8776.119"
+  wire $and$ls180.v:8776$2747_Y
+  attribute \src "ls180.v:2855.42-2855.101"
+  wire $eq$ls180.v:2855$30_Y
+  attribute \src "ls180.v:2862.11-2862.54"
+  wire $eq$ls180.v:2862$35_Y
+  attribute \src "ls180.v:2915.42-2915.101"
+  wire $eq$ls180.v:2915$41_Y
+  attribute \src "ls180.v:2922.11-2922.54"
+  wire $eq$ls180.v:2922$46_Y
+  attribute \src "ls180.v:2975.42-2975.101"
+  wire $eq$ls180.v:2975$52_Y
+  attribute \src "ls180.v:2982.11-2982.54"
+  wire $eq$ls180.v:2982$57_Y
+  attribute \src "ls180.v:3198.34-3198.65"
+  wire $eq$ls180.v:3198$124_Y
+  attribute \src "ls180.v:3202.68-3202.102"
+  wire $eq$ls180.v:3202$127_Y
+  attribute \src "ls180.v:3246.43-3246.134"
+  wire $eq$ls180.v:3246$132_Y
+  attribute \src "ls180.v:3263.47-3263.88"
+  wire $eq$ls180.v:3263$145_Y
+  attribute \src "ls180.v:3403.43-3403.134"
+  wire $eq$ls180.v:3403$162_Y
+  attribute \src "ls180.v:3420.47-3420.88"
+  wire $eq$ls180.v:3420$175_Y
+  attribute \src "ls180.v:3560.43-3560.134"
+  wire $eq$ls180.v:3560$192_Y
+  attribute \src "ls180.v:3577.47-3577.88"
+  wire $eq$ls180.v:3577$205_Y
+  attribute \src "ls180.v:3717.43-3717.134"
+  wire $eq$ls180.v:3717$222_Y
+  attribute \src "ls180.v:3734.47-3734.88"
+  wire $eq$ls180.v:3734$235_Y
+  attribute \src "ls180.v:3871.32-3871.56"
+  wire $eq$ls180.v:3871$282_Y
+  attribute \src "ls180.v:3872.32-3872.56"
+  wire $eq$ls180.v:3872$283_Y
+  attribute \src "ls180.v:3883.339-3883.418"
+  wire $eq$ls180.v:3883$297_Y
+  attribute \src "ls180.v:3883.423-3883.504"
+  wire $eq$ls180.v:3883$298_Y
+  attribute \src "ls180.v:3884.339-3884.418"
+  wire $eq$ls180.v:3884$310_Y
+  attribute \src "ls180.v:3884.423-3884.504"
+  wire $eq$ls180.v:3884$311_Y
+  attribute \src "ls180.v:3885.339-3885.418"
+  wire $eq$ls180.v:3885$323_Y
+  attribute \src "ls180.v:3885.423-3885.504"
+  wire $eq$ls180.v:3885$324_Y
+  attribute \src "ls180.v:3886.339-3886.418"
+  wire $eq$ls180.v:3886$336_Y
+  attribute \src "ls180.v:3886.423-3886.504"
+  wire $eq$ls180.v:3886$337_Y
+  attribute \src "ls180.v:3916.339-3916.418"
+  wire $eq$ls180.v:3916$355_Y
+  attribute \src "ls180.v:3916.423-3916.504"
+  wire $eq$ls180.v:3916$356_Y
+  attribute \src "ls180.v:3917.339-3917.418"
+  wire $eq$ls180.v:3917$368_Y
+  attribute \src "ls180.v:3917.423-3917.504"
+  wire $eq$ls180.v:3917$369_Y
+  attribute \src "ls180.v:3918.339-3918.418"
+  wire $eq$ls180.v:3918$381_Y
+  attribute \src "ls180.v:3918.423-3918.504"
+  wire $eq$ls180.v:3918$382_Y
+  attribute \src "ls180.v:3919.339-3919.418"
+  wire $eq$ls180.v:3919$394_Y
+  attribute \src "ls180.v:3919.423-3919.504"
+  wire $eq$ls180.v:3919$395_Y
+  attribute \src "ls180.v:3948.78-3948.113"
+  wire $eq$ls180.v:3948$404_Y
+  attribute \src "ls180.v:3951.78-3951.113"
+  wire $eq$ls180.v:3951$407_Y
+  attribute \src "ls180.v:3957.78-3957.113"
+  wire $eq$ls180.v:3957$411_Y
+  attribute \src "ls180.v:3960.78-3960.113"
+  wire $eq$ls180.v:3960$414_Y
+  attribute \src "ls180.v:3966.78-3966.113"
+  wire $eq$ls180.v:3966$418_Y
+  attribute \src "ls180.v:3969.78-3969.113"
+  wire $eq$ls180.v:3969$421_Y
+  attribute \src "ls180.v:3975.78-3975.113"
+  wire $eq$ls180.v:3975$425_Y
+  attribute \src "ls180.v:3978.78-3978.113"
+  wire $eq$ls180.v:3978$428_Y
+  attribute \src "ls180.v:4059.42-4059.82"
+  wire $eq$ls180.v:4059$451_Y
+  attribute \src "ls180.v:4059.145-4059.178"
+  wire $eq$ls180.v:4059$452_Y
+  attribute \src "ls180.v:4059.220-4059.253"
+  wire $eq$ls180.v:4059$455_Y
+  attribute \src "ls180.v:4059.295-4059.328"
+  wire $eq$ls180.v:4059$458_Y
+  attribute \src "ls180.v:4064.42-4064.82"
+  wire $eq$ls180.v:4064$467_Y
+  attribute \src "ls180.v:4064.145-4064.178"
+  wire $eq$ls180.v:4064$468_Y
+  attribute \src "ls180.v:4064.220-4064.253"
+  wire $eq$ls180.v:4064$471_Y
+  attribute \src "ls180.v:4064.295-4064.328"
+  wire $eq$ls180.v:4064$474_Y
+  attribute \src "ls180.v:4069.42-4069.82"
+  wire $eq$ls180.v:4069$483_Y
+  attribute \src "ls180.v:4069.145-4069.178"
+  wire $eq$ls180.v:4069$484_Y
+  attribute \src "ls180.v:4069.220-4069.253"
+  wire $eq$ls180.v:4069$487_Y
+  attribute \src "ls180.v:4069.295-4069.328"
+  wire $eq$ls180.v:4069$490_Y
+  attribute \src "ls180.v:4074.42-4074.82"
+  wire $eq$ls180.v:4074$499_Y
+  attribute \src "ls180.v:4074.145-4074.178"
+  wire $eq$ls180.v:4074$500_Y
+  attribute \src "ls180.v:4074.220-4074.253"
+  wire $eq$ls180.v:4074$503_Y
+  attribute \src "ls180.v:4074.295-4074.328"
+  wire $eq$ls180.v:4074$506_Y
+  attribute \src "ls180.v:4079.44-4079.77"
+  wire $eq$ls180.v:4079$515_Y
+  attribute \src "ls180.v:4079.83-4079.123"
+  wire $eq$ls180.v:4079$516_Y
+  attribute \src "ls180.v:4079.186-4079.219"
+  wire $eq$ls180.v:4079$517_Y
+  attribute \src "ls180.v:4079.261-4079.294"
+  wire $eq$ls180.v:4079$520_Y
+  attribute \src "ls180.v:4079.336-4079.369"
+  wire $eq$ls180.v:4079$523_Y
+  attribute \src "ls180.v:4079.418-4079.451"
+  wire $eq$ls180.v:4079$531_Y
+  attribute \src "ls180.v:4079.457-4079.497"
+  wire $eq$ls180.v:4079$532_Y
+  attribute \src "ls180.v:4079.560-4079.593"
+  wire $eq$ls180.v:4079$533_Y
+  attribute \src "ls180.v:4079.635-4079.668"
+  wire $eq$ls180.v:4079$536_Y
+  attribute \src "ls180.v:4079.710-4079.743"
+  wire $eq$ls180.v:4079$539_Y
+  attribute \src "ls180.v:4079.792-4079.825"
+  wire $eq$ls180.v:4079$547_Y
+  attribute \src "ls180.v:4079.831-4079.871"
+  wire $eq$ls180.v:4079$548_Y
+  attribute \src "ls180.v:4079.934-4079.967"
+  wire $eq$ls180.v:4079$549_Y
+  attribute \src "ls180.v:4079.1009-4079.1042"
+  wire $eq$ls180.v:4079$552_Y
+  attribute \src "ls180.v:4079.1084-4079.1117"
+  wire $eq$ls180.v:4079$555_Y
+  attribute \src "ls180.v:4079.1166-4079.1199"
+  wire $eq$ls180.v:4079$563_Y
+  attribute \src "ls180.v:4079.1205-4079.1245"
+  wire $eq$ls180.v:4079$564_Y
+  attribute \src "ls180.v:4079.1308-4079.1341"
+  wire $eq$ls180.v:4079$565_Y
+  attribute \src "ls180.v:4079.1383-4079.1416"
+  wire $eq$ls180.v:4079$568_Y
+  attribute \src "ls180.v:4079.1458-4079.1491"
+  wire $eq$ls180.v:4079$571_Y
+  attribute \src "ls180.v:4138.29-4138.57"
+  wire $eq$ls180.v:4138$584_Y
+  attribute \src "ls180.v:4145.11-4145.41"
+  wire $eq$ls180.v:4145$589_Y
+  attribute \src "ls180.v:4302.37-4302.111"
+  wire $eq$ls180.v:4302$654_Y
+  attribute \src "ls180.v:4303.37-4303.105"
+  wire $eq$ls180.v:4303$656_Y
+  attribute \src "ls180.v:4330.10-4330.67"
+  wire $eq$ls180.v:4330$660_Y
+  attribute \src "ls180.v:4360.35-4360.108"
+  wire $eq$ls180.v:4360$662_Y
+  attribute \src "ls180.v:4361.35-4361.102"
+  wire $eq$ls180.v:4361$664_Y
+  attribute \src "ls180.v:4389.10-4389.65"
+  wire $eq$ls180.v:4389$668_Y
+  attribute \src "ls180.v:4493.10-4493.40"
+  wire $eq$ls180.v:4493$695_Y
+  attribute \src "ls180.v:4550.10-4550.39"
+  wire $eq$ls180.v:4550$698_Y
+  attribute \src "ls180.v:4567.10-4567.39"
+  wire $eq$ls180.v:4567$700_Y
+  attribute \src "ls180.v:4595.38-4595.88"
+  wire $eq$ls180.v:4595$702_Y
+  attribute \src "ls180.v:4645.9-4645.40"
+  wire $eq$ls180.v:4645$712_Y
+  attribute \src "ls180.v:4654.36-4654.105"
+  wire $eq$ls180.v:4654$714_Y
+  attribute \src "ls180.v:4673.9-4673.40"
+  wire $eq$ls180.v:4673$718_Y
+  attribute \src "ls180.v:4685.10-4685.39"
+  wire $eq$ls180.v:4685$720_Y
+  attribute \src "ls180.v:4722.39-4722.94"
+  wire $eq$ls180.v:4722$724_Y
+  attribute \src "ls180.v:4759.32-4759.89"
+  wire $eq$ls180.v:4759$733_Y
+  attribute \src "ls180.v:4807.10-4807.40"
+  wire $eq$ls180.v:4807$737_Y
+  attribute \src "ls180.v:4856.40-4856.98"
+  wire $eq$ls180.v:4856$739_Y
+  attribute \src "ls180.v:4907.9-4907.41"
+  wire $eq$ls180.v:4907$749_Y
+  attribute \src "ls180.v:4916.37-4916.123"
+  wire $eq$ls180.v:4916$752_Y
+  attribute \src "ls180.v:4939.9-4939.41"
+  wire $eq$ls180.v:4939$755_Y
+  attribute \src "ls180.v:4949.10-4949.41"
+  wire $eq$ls180.v:4949$757_Y
+  attribute \src "ls180.v:5118.9-5118.47"
+  wire $eq$ls180.v:5118$939_Y
+  attribute \src "ls180.v:5148.10-5148.48"
+  wire $eq$ls180.v:5148$940_Y
+  attribute \src "ls180.v:5179.10-5179.78"
+  wire $eq$ls180.v:5179$945_Y
+  attribute \src "ls180.v:5179.83-5179.151"
+  wire $eq$ls180.v:5179$946_Y
+  attribute \src "ls180.v:5179.157-5179.225"
+  wire $eq$ls180.v:5179$948_Y
+  attribute \src "ls180.v:5179.231-5179.299"
+  wire $eq$ls180.v:5179$950_Y
+  attribute \src "ls180.v:5187.7-5187.44"
+  wire $eq$ls180.v:5187$954_Y
+  attribute \src "ls180.v:5197.7-5197.44"
+  wire $eq$ls180.v:5197$957_Y
+  attribute \src "ls180.v:5207.7-5207.44"
+  wire $eq$ls180.v:5207$960_Y
+  attribute \src "ls180.v:5217.7-5217.44"
+  wire $eq$ls180.v:5217$963_Y
+  attribute \src "ls180.v:5341.36-5341.64"
+  wire $eq$ls180.v:5341$1014_Y
+  attribute \src "ls180.v:5347.10-5347.39"
+  wire $eq$ls180.v:5347$1017_Y
+  attribute \src "ls180.v:5348.11-5348.39"
+  wire $eq$ls180.v:5348$1018_Y
+  attribute \src "ls180.v:5360.34-5360.63"
+  wire $eq$ls180.v:5360$1019_Y
+  attribute \src "ls180.v:5361.9-5361.37"
+  wire $eq$ls180.v:5361$1020_Y
+  attribute \src "ls180.v:5368.10-5368.55"
+  wire $eq$ls180.v:5368$1021_Y
+  attribute \src "ls180.v:5374.12-5374.41"
+  wire $eq$ls180.v:5374$1022_Y
+  attribute \src "ls180.v:5377.13-5377.42"
+  wire $eq$ls180.v:5377$1023_Y
+  attribute \src "ls180.v:5399.10-5399.76"
+  wire $eq$ls180.v:5399$1028_Y
+  attribute \src "ls180.v:5414.35-5414.101"
+  wire $eq$ls180.v:5414$1031_Y
+  attribute \src "ls180.v:5416.10-5416.56"
+  wire $eq$ls180.v:5416$1032_Y
+  attribute \src "ls180.v:5425.12-5425.78"
+  wire $eq$ls180.v:5425$1036_Y
+  attribute \src "ls180.v:5432.11-5432.57"
+  wire $eq$ls180.v:5432$1037_Y
+  attribute \src "ls180.v:5549.10-5549.105"
+  wire $eq$ls180.v:5549$1054_Y
+  attribute \src "ls180.v:5639.39-5639.106"
+  wire $eq$ls180.v:5639$1060_Y
+  attribute \src "ls180.v:5669.44-5669.82"
+  wire $eq$ls180.v:5669$1063_Y
+  attribute \src "ls180.v:5670.43-5670.81"
+  wire $eq$ls180.v:5670$1064_Y
+  attribute \src "ls180.v:5770.85-5770.106"
+  wire $eq$ls180.v:5770$1080_Y
+  attribute \src "ls180.v:5771.85-5771.106"
+  wire $eq$ls180.v:5771$1082_Y
+  attribute \src "ls180.v:5772.85-5772.106"
+  wire $eq$ls180.v:5772$1084_Y
+  attribute \src "ls180.v:5773.57-5773.78"
+  wire $eq$ls180.v:5773$1086_Y
+  attribute \src "ls180.v:5774.57-5774.78"
+  wire $eq$ls180.v:5774$1088_Y
+  attribute \src "ls180.v:5775.85-5775.106"
+  wire $eq$ls180.v:5775$1090_Y
+  attribute \src "ls180.v:5776.85-5776.106"
+  wire $eq$ls180.v:5776$1092_Y
+  attribute \src "ls180.v:5777.85-5777.106"
+  wire $eq$ls180.v:5777$1094_Y
+  attribute \src "ls180.v:5778.57-5778.78"
+  wire $eq$ls180.v:5778$1096_Y
+  attribute \src "ls180.v:5779.57-5779.78"
+  wire $eq$ls180.v:5779$1098_Y
+  attribute \src "ls180.v:5783.27-5783.59"
+  wire $eq$ls180.v:5783$1101_Y
+  attribute \src "ls180.v:5784.27-5784.59"
+  wire $eq$ls180.v:5784$1102_Y
+  attribute \src "ls180.v:5785.27-5785.60"
+  wire $eq$ls180.v:5785$1103_Y
+  attribute \src "ls180.v:5786.27-5786.60"
+  wire $eq$ls180.v:5786$1104_Y
+  attribute \src "ls180.v:5787.27-5787.68"
+  wire $eq$ls180.v:5787$1105_Y
+  attribute \src "ls180.v:5788.27-5788.66"
+  wire $eq$ls180.v:5788$1106_Y
+  attribute \src "ls180.v:5789.27-5789.61"
+  wire $eq$ls180.v:5789$1107_Y
+  attribute \src "ls180.v:5790.27-5790.65"
+  wire $eq$ls180.v:5790$1108_Y
+  attribute \src "ls180.v:5870.24-5870.45"
+  wire $eq$ls180.v:5870$1150_Y
+  attribute \src "ls180.v:5871.32-5871.77"
+  wire $eq$ls180.v:5871$1151_Y
+  attribute \src "ls180.v:5873.97-5873.141"
+  wire $eq$ls180.v:5873$1153_Y
+  attribute \src "ls180.v:5874.100-5874.144"
+  wire $eq$ls180.v:5874$1157_Y
+  attribute \src "ls180.v:5876.99-5876.143"
+  wire $eq$ls180.v:5876$1160_Y
+  attribute \src "ls180.v:5877.102-5877.146"
+  wire $eq$ls180.v:5877$1164_Y
+  attribute \src "ls180.v:5879.99-5879.143"
+  wire $eq$ls180.v:5879$1167_Y
+  attribute \src "ls180.v:5880.102-5880.146"
+  wire $eq$ls180.v:5880$1171_Y
+  attribute \src "ls180.v:5882.99-5882.143"
+  wire $eq$ls180.v:5882$1174_Y
+  attribute \src "ls180.v:5883.102-5883.146"
+  wire $eq$ls180.v:5883$1178_Y
+  attribute \src "ls180.v:5885.99-5885.143"
+  wire $eq$ls180.v:5885$1181_Y
+  attribute \src "ls180.v:5886.102-5886.146"
+  wire $eq$ls180.v:5886$1185_Y
+  attribute \src "ls180.v:5888.102-5888.146"
+  wire $eq$ls180.v:5888$1188_Y
+  attribute \src "ls180.v:5889.105-5889.149"
+  wire $eq$ls180.v:5889$1192_Y
+  attribute \src "ls180.v:5891.102-5891.146"
+  wire $eq$ls180.v:5891$1195_Y
+  attribute \src "ls180.v:5892.105-5892.149"
+  wire $eq$ls180.v:5892$1199_Y
+  attribute \src "ls180.v:5894.102-5894.146"
+  wire $eq$ls180.v:5894$1202_Y
+  attribute \src "ls180.v:5895.105-5895.149"
+  wire $eq$ls180.v:5895$1206_Y
+  attribute \src "ls180.v:5897.102-5897.146"
+  wire $eq$ls180.v:5897$1209_Y
+  attribute \src "ls180.v:5898.105-5898.149"
+  wire $eq$ls180.v:5898$1213_Y
+  attribute \src "ls180.v:5909.32-5909.77"
+  wire $eq$ls180.v:5909$1215_Y
+  attribute \src "ls180.v:5911.94-5911.138"
+  wire $eq$ls180.v:5911$1217_Y
+  attribute \src "ls180.v:5912.97-5912.141"
+  wire $eq$ls180.v:5912$1221_Y
+  attribute \src "ls180.v:5914.94-5914.138"
+  wire $eq$ls180.v:5914$1224_Y
+  attribute \src "ls180.v:5915.97-5915.141"
+  wire $eq$ls180.v:5915$1228_Y
+  attribute \src "ls180.v:5917.94-5917.138"
+  wire $eq$ls180.v:5917$1231_Y
+  attribute \src "ls180.v:5918.97-5918.141"
+  wire $eq$ls180.v:5918$1235_Y
+  attribute \src "ls180.v:5920.94-5920.138"
+  wire $eq$ls180.v:5920$1238_Y
+  attribute \src "ls180.v:5921.97-5921.141"
+  wire $eq$ls180.v:5921$1242_Y
+  attribute \src "ls180.v:5923.95-5923.139"
+  wire $eq$ls180.v:5923$1245_Y
+  attribute \src "ls180.v:5924.98-5924.142"
+  wire $eq$ls180.v:5924$1249_Y
+  attribute \src "ls180.v:5926.95-5926.139"
+  wire $eq$ls180.v:5926$1252_Y
+  attribute \src "ls180.v:5927.98-5927.142"
+  wire $eq$ls180.v:5927$1256_Y
+  attribute \src "ls180.v:5935.32-5935.78"
+  wire $eq$ls180.v:5935$1258_Y
+  attribute \src "ls180.v:5937.93-5937.135"
+  wire $eq$ls180.v:5937$1260_Y
+  attribute \src "ls180.v:5938.96-5938.138"
+  wire $eq$ls180.v:5938$1264_Y
+  attribute \src "ls180.v:5940.92-5940.134"
+  wire $eq$ls180.v:5940$1267_Y
+  attribute \src "ls180.v:5941.95-5941.137"
+  wire $eq$ls180.v:5941$1271_Y
+  attribute \src "ls180.v:5949.32-5949.77"
+  wire $eq$ls180.v:5949$1273_Y
+  attribute \src "ls180.v:5951.98-5951.142"
+  wire $eq$ls180.v:5951$1275_Y
+  attribute \src "ls180.v:5952.101-5952.145"
+  wire $eq$ls180.v:5952$1279_Y
+  attribute \src "ls180.v:5954.97-5954.141"
+  wire $eq$ls180.v:5954$1282_Y
+  attribute \src "ls180.v:5955.100-5955.144"
+  wire $eq$ls180.v:5955$1286_Y
+  attribute \src "ls180.v:5957.97-5957.141"
+  wire $eq$ls180.v:5957$1289_Y
+  attribute \src "ls180.v:5958.100-5958.144"
+  wire $eq$ls180.v:5958$1293_Y
+  attribute \src "ls180.v:5960.97-5960.141"
+  wire $eq$ls180.v:5960$1296_Y
+  attribute \src "ls180.v:5961.100-5961.144"
+  wire $eq$ls180.v:5961$1300_Y
+  attribute \src "ls180.v:5963.97-5963.141"
+  wire $eq$ls180.v:5963$1303_Y
+  attribute \src "ls180.v:5964.100-5964.144"
+  wire $eq$ls180.v:5964$1307_Y
+  attribute \src "ls180.v:5966.98-5966.142"
+  wire $eq$ls180.v:5966$1310_Y
+  attribute \src "ls180.v:5967.101-5967.145"
+  wire $eq$ls180.v:5967$1314_Y
+  attribute \src "ls180.v:5969.98-5969.142"
+  wire $eq$ls180.v:5969$1317_Y
+  attribute \src "ls180.v:5970.101-5970.145"
+  wire $eq$ls180.v:5970$1321_Y
+  attribute \src "ls180.v:5972.98-5972.142"
+  wire $eq$ls180.v:5972$1324_Y
+  attribute \src "ls180.v:5973.101-5973.145"
+  wire $eq$ls180.v:5973$1328_Y
+  attribute \src "ls180.v:5975.98-5975.142"
+  wire $eq$ls180.v:5975$1331_Y
+  attribute \src "ls180.v:5976.101-5976.145"
+  wire $eq$ls180.v:5976$1335_Y
+  attribute \src "ls180.v:5986.32-5986.78"
+  wire $eq$ls180.v:5986$1337_Y
+  attribute \src "ls180.v:5988.98-5988.142"
+  wire $eq$ls180.v:5988$1339_Y
+  attribute \src "ls180.v:5989.101-5989.145"
+  wire $eq$ls180.v:5989$1343_Y
+  attribute \src "ls180.v:5991.97-5991.141"
+  wire $eq$ls180.v:5991$1346_Y
+  attribute \src "ls180.v:5992.100-5992.144"
+  wire $eq$ls180.v:5992$1350_Y
+  attribute \src "ls180.v:5994.97-5994.141"
+  wire $eq$ls180.v:5994$1353_Y
+  attribute \src "ls180.v:5995.100-5995.144"
+  wire $eq$ls180.v:5995$1357_Y
+  attribute \src "ls180.v:5997.97-5997.141"
+  wire $eq$ls180.v:5997$1360_Y
+  attribute \src "ls180.v:5998.100-5998.144"
+  wire $eq$ls180.v:5998$1364_Y
+  attribute \src "ls180.v:6000.97-6000.141"
+  wire $eq$ls180.v:6000$1367_Y
+  attribute \src "ls180.v:6001.100-6001.144"
+  wire $eq$ls180.v:6001$1371_Y
+  attribute \src "ls180.v:6003.98-6003.142"
+  wire $eq$ls180.v:6003$1374_Y
+  attribute \src "ls180.v:6004.101-6004.145"
+  wire $eq$ls180.v:6004$1378_Y
+  attribute \src "ls180.v:6006.98-6006.142"
+  wire $eq$ls180.v:6006$1381_Y
+  attribute \src "ls180.v:6007.101-6007.145"
+  wire $eq$ls180.v:6007$1385_Y
+  attribute \src "ls180.v:6009.98-6009.142"
+  wire $eq$ls180.v:6009$1388_Y
+  attribute \src "ls180.v:6010.101-6010.145"
+  wire $eq$ls180.v:6010$1392_Y
+  attribute \src "ls180.v:6012.98-6012.142"
+  wire $eq$ls180.v:6012$1395_Y
+  attribute \src "ls180.v:6013.101-6013.145"
+  wire $eq$ls180.v:6013$1399_Y
+  attribute \src "ls180.v:6023.32-6023.78"
+  wire $eq$ls180.v:6023$1401_Y
+  attribute \src "ls180.v:6025.100-6025.144"
+  wire $eq$ls180.v:6025$1403_Y
+  attribute \src "ls180.v:6026.103-6026.147"
+  wire $eq$ls180.v:6026$1407_Y
+  attribute \src "ls180.v:6028.100-6028.144"
+  wire $eq$ls180.v:6028$1410_Y
+  attribute \src "ls180.v:6029.103-6029.147"
+  wire $eq$ls180.v:6029$1414_Y
+  attribute \src "ls180.v:6031.100-6031.144"
+  wire $eq$ls180.v:6031$1417_Y
+  attribute \src "ls180.v:6032.103-6032.147"
+  wire $eq$ls180.v:6032$1421_Y
+  attribute \src "ls180.v:6034.100-6034.144"
+  wire $eq$ls180.v:6034$1424_Y
+  attribute \src "ls180.v:6035.103-6035.147"
+  wire $eq$ls180.v:6035$1428_Y
+  attribute \src "ls180.v:6037.100-6037.144"
+  wire $eq$ls180.v:6037$1431_Y
+  attribute \src "ls180.v:6038.103-6038.147"
+  wire $eq$ls180.v:6038$1435_Y
+  attribute \src "ls180.v:6040.100-6040.144"
+  wire $eq$ls180.v:6040$1438_Y
+  attribute \src "ls180.v:6041.103-6041.147"
+  wire $eq$ls180.v:6041$1442_Y
+  attribute \src "ls180.v:6043.100-6043.144"
+  wire $eq$ls180.v:6043$1445_Y
+  attribute \src "ls180.v:6044.103-6044.147"
+  wire $eq$ls180.v:6044$1449_Y
+  attribute \src "ls180.v:6046.100-6046.144"
+  wire $eq$ls180.v:6046$1452_Y
+  attribute \src "ls180.v:6047.103-6047.147"
+  wire $eq$ls180.v:6047$1456_Y
+  attribute \src "ls180.v:6049.102-6049.146"
+  wire $eq$ls180.v:6049$1459_Y
+  attribute \src "ls180.v:6050.105-6050.149"
+  wire $eq$ls180.v:6050$1463_Y
+  attribute \src "ls180.v:6052.102-6052.146"
+  wire $eq$ls180.v:6052$1466_Y
+  attribute \src "ls180.v:6053.105-6053.149"
+  wire $eq$ls180.v:6053$1470_Y
+  attribute \src "ls180.v:6055.102-6055.147"
+  wire $eq$ls180.v:6055$1473_Y
+  attribute \src "ls180.v:6056.105-6056.150"
+  wire $eq$ls180.v:6056$1477_Y
+  attribute \src "ls180.v:6058.102-6058.147"
+  wire $eq$ls180.v:6058$1480_Y
+  attribute \src "ls180.v:6059.105-6059.150"
+  wire $eq$ls180.v:6059$1484_Y
+  attribute \src "ls180.v:6061.102-6061.147"
+  wire $eq$ls180.v:6061$1487_Y
+  attribute \src "ls180.v:6062.105-6062.150"
+  wire $eq$ls180.v:6062$1491_Y
+  attribute \src "ls180.v:6064.99-6064.144"
+  wire $eq$ls180.v:6064$1494_Y
+  attribute \src "ls180.v:6065.102-6065.147"
+  wire $eq$ls180.v:6065$1498_Y
+  attribute \src "ls180.v:6067.100-6067.145"
+  wire $eq$ls180.v:6067$1501_Y
+  attribute \src "ls180.v:6068.103-6068.148"
+  wire $eq$ls180.v:6068$1505_Y
+  attribute \src "ls180.v:6085.32-6085.78"
+  wire $eq$ls180.v:6085$1507_Y
+  attribute \src "ls180.v:6087.104-6087.148"
+  wire $eq$ls180.v:6087$1509_Y
+  attribute \src "ls180.v:6088.107-6088.151"
+  wire $eq$ls180.v:6088$1513_Y
+  attribute \src "ls180.v:6090.104-6090.148"
+  wire $eq$ls180.v:6090$1516_Y
+  attribute \src "ls180.v:6091.107-6091.151"
+  wire $eq$ls180.v:6091$1520_Y
+  attribute \src "ls180.v:6093.104-6093.148"
+  wire $eq$ls180.v:6093$1523_Y
+  attribute \src "ls180.v:6094.107-6094.151"
+  wire $eq$ls180.v:6094$1527_Y
+  attribute \src "ls180.v:6096.104-6096.148"
+  wire $eq$ls180.v:6096$1530_Y
+  attribute \src "ls180.v:6097.107-6097.151"
+  wire $eq$ls180.v:6097$1534_Y
+  attribute \src "ls180.v:6099.103-6099.147"
+  wire $eq$ls180.v:6099$1537_Y
+  attribute \src "ls180.v:6100.106-6100.150"
+  wire $eq$ls180.v:6100$1541_Y
+  attribute \src "ls180.v:6102.103-6102.147"
+  wire $eq$ls180.v:6102$1544_Y
+  attribute \src "ls180.v:6103.106-6103.150"
+  wire $eq$ls180.v:6103$1548_Y
+  attribute \src "ls180.v:6105.103-6105.147"
+  wire $eq$ls180.v:6105$1551_Y
+  attribute \src "ls180.v:6106.106-6106.150"
+  wire $eq$ls180.v:6106$1555_Y
+  attribute \src "ls180.v:6108.103-6108.147"
+  wire $eq$ls180.v:6108$1558_Y
+  attribute \src "ls180.v:6109.106-6109.150"
+  wire $eq$ls180.v:6109$1562_Y
+  attribute \src "ls180.v:6111.94-6111.138"
+  wire $eq$ls180.v:6111$1565_Y
+  attribute \src "ls180.v:6112.97-6112.141"
+  wire $eq$ls180.v:6112$1569_Y
+  attribute \src "ls180.v:6114.105-6114.149"
+  wire $eq$ls180.v:6114$1572_Y
+  attribute \src "ls180.v:6115.108-6115.152"
+  wire $eq$ls180.v:6115$1576_Y
+  attribute \src "ls180.v:6117.105-6117.150"
+  wire $eq$ls180.v:6117$1579_Y
+  attribute \src "ls180.v:6118.108-6118.153"
+  wire $eq$ls180.v:6118$1583_Y
+  attribute \src "ls180.v:6120.105-6120.150"
+  wire $eq$ls180.v:6120$1586_Y
+  attribute \src "ls180.v:6121.108-6121.153"
+  wire $eq$ls180.v:6121$1590_Y
+  attribute \src "ls180.v:6123.105-6123.150"
+  wire $eq$ls180.v:6123$1593_Y
+  attribute \src "ls180.v:6124.108-6124.153"
+  wire $eq$ls180.v:6124$1597_Y
+  attribute \src "ls180.v:6126.105-6126.150"
+  wire $eq$ls180.v:6126$1600_Y
+  attribute \src "ls180.v:6127.108-6127.153"
+  wire $eq$ls180.v:6127$1604_Y
+  attribute \src "ls180.v:6129.105-6129.150"
+  wire $eq$ls180.v:6129$1607_Y
+  attribute \src "ls180.v:6130.108-6130.153"
+  wire $eq$ls180.v:6130$1611_Y
+  attribute \src "ls180.v:6132.104-6132.149"
+  wire $eq$ls180.v:6132$1614_Y
+  attribute \src "ls180.v:6133.107-6133.152"
+  wire $eq$ls180.v:6133$1618_Y
+  attribute \src "ls180.v:6135.104-6135.149"
+  wire $eq$ls180.v:6135$1621_Y
+  attribute \src "ls180.v:6136.107-6136.152"
+  wire $eq$ls180.v:6136$1625_Y
+  attribute \src "ls180.v:6138.104-6138.149"
+  wire $eq$ls180.v:6138$1628_Y
+  attribute \src "ls180.v:6139.107-6139.152"
+  wire $eq$ls180.v:6139$1632_Y
+  attribute \src "ls180.v:6141.104-6141.149"
+  wire $eq$ls180.v:6141$1635_Y
+  attribute \src "ls180.v:6142.107-6142.152"
+  wire $eq$ls180.v:6142$1639_Y
+  attribute \src "ls180.v:6144.104-6144.149"
+  wire $eq$ls180.v:6144$1642_Y
+  attribute \src "ls180.v:6145.107-6145.152"
+  wire $eq$ls180.v:6145$1646_Y
+  attribute \src "ls180.v:6147.104-6147.149"
+  wire $eq$ls180.v:6147$1649_Y
+  attribute \src "ls180.v:6148.107-6148.152"
+  wire $eq$ls180.v:6148$1653_Y
+  attribute \src "ls180.v:6150.104-6150.149"
+  wire $eq$ls180.v:6150$1656_Y
+  attribute \src "ls180.v:6151.107-6151.152"
+  wire $eq$ls180.v:6151$1660_Y
+  attribute \src "ls180.v:6153.104-6153.149"
+  wire $eq$ls180.v:6153$1663_Y
+  attribute \src "ls180.v:6154.107-6154.152"
+  wire $eq$ls180.v:6154$1667_Y
+  attribute \src "ls180.v:6156.104-6156.149"
+  wire $eq$ls180.v:6156$1670_Y
+  attribute \src "ls180.v:6157.107-6157.152"
+  wire $eq$ls180.v:6157$1674_Y
+  attribute \src "ls180.v:6159.104-6159.149"
+  wire $eq$ls180.v:6159$1677_Y
+  attribute \src "ls180.v:6160.107-6160.152"
+  wire $eq$ls180.v:6160$1681_Y
   attribute \src "ls180.v:6162.100-6162.145"
-  wire $eq$ls180.v:6162$1770_Y
+  wire $eq$ls180.v:6162$1684_Y
   attribute \src "ls180.v:6163.103-6163.148"
-  wire $eq$ls180.v:6163$1774_Y
-  attribute \src "ls180.v:6165.102-6165.147"
-  wire $eq$ls180.v:6165$1777_Y
-  attribute \src "ls180.v:6166.105-6166.150"
-  wire $eq$ls180.v:6166$1781_Y
-  attribute \src "ls180.v:6168.102-6168.147"
-  wire $eq$ls180.v:6168$1784_Y
-  attribute \src "ls180.v:6169.105-6169.150"
-  wire $eq$ls180.v:6169$1788_Y
-  attribute \src "ls180.v:6171.102-6171.147"
-  wire $eq$ls180.v:6171$1791_Y
-  attribute \src "ls180.v:6172.105-6172.150"
-  wire $eq$ls180.v:6172$1795_Y
-  attribute \src "ls180.v:6174.102-6174.147"
-  wire $eq$ls180.v:6174$1798_Y
-  attribute \src "ls180.v:6175.105-6175.150"
-  wire $eq$ls180.v:6175$1802_Y
-  attribute \src "ls180.v:6197.32-6197.78"
-  wire $eq$ls180.v:6197$1804_Y
-  attribute \src "ls180.v:6199.102-6199.146"
-  wire $eq$ls180.v:6199$1806_Y
-  attribute \src "ls180.v:6200.105-6200.149"
-  wire $eq$ls180.v:6200$1810_Y
-  attribute \src "ls180.v:6202.107-6202.151"
-  wire $eq$ls180.v:6202$1813_Y
-  attribute \src "ls180.v:6203.110-6203.154"
-  wire $eq$ls180.v:6203$1817_Y
-  attribute \src "ls180.v:6205.107-6205.151"
-  wire $eq$ls180.v:6205$1820_Y
-  attribute \src "ls180.v:6206.110-6206.154"
-  wire $eq$ls180.v:6206$1824_Y
-  attribute \src "ls180.v:6208.100-6208.144"
-  wire $eq$ls180.v:6208$1827_Y
-  attribute \src "ls180.v:6209.103-6209.147"
-  wire $eq$ls180.v:6209$1831_Y
-  attribute \src "ls180.v:6214.32-6214.77"
-  wire $eq$ls180.v:6214$1833_Y
-  attribute \src "ls180.v:6216.104-6216.148"
-  wire $eq$ls180.v:6216$1835_Y
-  attribute \src "ls180.v:6217.107-6217.151"
-  wire $eq$ls180.v:6217$1839_Y
-  attribute \src "ls180.v:6219.108-6219.152"
-  wire $eq$ls180.v:6219$1842_Y
-  attribute \src "ls180.v:6220.111-6220.155"
-  wire $eq$ls180.v:6220$1846_Y
-  attribute \src "ls180.v:6222.98-6222.142"
-  wire $eq$ls180.v:6222$1849_Y
-  attribute \src "ls180.v:6223.101-6223.145"
-  wire $eq$ls180.v:6223$1853_Y
-  attribute \src "ls180.v:6225.108-6225.152"
-  wire $eq$ls180.v:6225$1856_Y
-  attribute \src "ls180.v:6226.111-6226.155"
-  wire $eq$ls180.v:6226$1860_Y
-  attribute \src "ls180.v:6228.108-6228.152"
-  wire $eq$ls180.v:6228$1863_Y
-  attribute \src "ls180.v:6229.111-6229.155"
-  wire $eq$ls180.v:6229$1867_Y
-  attribute \src "ls180.v:6231.109-6231.153"
-  wire $eq$ls180.v:6231$1870_Y
-  attribute \src "ls180.v:6232.112-6232.156"
-  wire $eq$ls180.v:6232$1874_Y
-  attribute \src "ls180.v:6234.107-6234.151"
-  wire $eq$ls180.v:6234$1877_Y
-  attribute \src "ls180.v:6235.110-6235.154"
-  wire $eq$ls180.v:6235$1881_Y
-  attribute \src "ls180.v:6237.107-6237.151"
-  wire $eq$ls180.v:6237$1884_Y
-  attribute \src "ls180.v:6238.110-6238.154"
-  wire $eq$ls180.v:6238$1888_Y
-  attribute \src "ls180.v:6240.107-6240.151"
-  wire $eq$ls180.v:6240$1891_Y
-  attribute \src "ls180.v:6241.110-6241.154"
-  wire $eq$ls180.v:6241$1895_Y
-  attribute \src "ls180.v:6243.107-6243.151"
-  wire $eq$ls180.v:6243$1898_Y
-  attribute \src "ls180.v:6244.110-6244.154"
-  wire $eq$ls180.v:6244$1902_Y
-  attribute \src "ls180.v:6259.33-6259.79"
-  wire $eq$ls180.v:6259$1904_Y
-  attribute \src "ls180.v:6261.102-6261.147"
-  wire $eq$ls180.v:6261$1906_Y
-  attribute \src "ls180.v:6262.105-6262.150"
-  wire $eq$ls180.v:6262$1910_Y
-  attribute \src "ls180.v:6264.102-6264.147"
-  wire $eq$ls180.v:6264$1913_Y
-  attribute \src "ls180.v:6265.105-6265.150"
-  wire $eq$ls180.v:6265$1917_Y
-  attribute \src "ls180.v:6267.100-6267.145"
-  wire $eq$ls180.v:6267$1920_Y
-  attribute \src "ls180.v:6268.103-6268.148"
-  wire $eq$ls180.v:6268$1924_Y
-  attribute \src "ls180.v:6270.99-6270.144"
-  wire $eq$ls180.v:6270$1927_Y
-  attribute \src "ls180.v:6271.102-6271.147"
-  wire $eq$ls180.v:6271$1931_Y
-  attribute \src "ls180.v:6273.98-6273.143"
-  wire $eq$ls180.v:6273$1934_Y
-  attribute \src "ls180.v:6274.101-6274.146"
-  wire $eq$ls180.v:6274$1938_Y
-  attribute \src "ls180.v:6276.97-6276.142"
-  wire $eq$ls180.v:6276$1941_Y
-  attribute \src "ls180.v:6277.100-6277.145"
-  wire $eq$ls180.v:6277$1945_Y
-  attribute \src "ls180.v:6279.103-6279.148"
-  wire $eq$ls180.v:6279$1948_Y
-  attribute \src "ls180.v:6280.106-6280.151"
-  wire $eq$ls180.v:6280$1952_Y
-  attribute \src "ls180.v:6299.33-6299.79"
-  wire $eq$ls180.v:6299$1955_Y
-  attribute \src "ls180.v:6301.102-6301.147"
-  wire $eq$ls180.v:6301$1957_Y
-  attribute \src "ls180.v:6302.105-6302.150"
-  wire $eq$ls180.v:6302$1961_Y
-  attribute \src "ls180.v:6304.102-6304.147"
-  wire $eq$ls180.v:6304$1964_Y
-  attribute \src "ls180.v:6305.105-6305.150"
-  wire $eq$ls180.v:6305$1968_Y
-  attribute \src "ls180.v:6307.100-6307.145"
-  wire $eq$ls180.v:6307$1971_Y
-  attribute \src "ls180.v:6308.103-6308.148"
-  wire $eq$ls180.v:6308$1975_Y
-  attribute \src "ls180.v:6310.99-6310.144"
-  wire $eq$ls180.v:6310$1978_Y
-  attribute \src "ls180.v:6311.102-6311.147"
-  wire $eq$ls180.v:6311$1982_Y
-  attribute \src "ls180.v:6313.98-6313.143"
-  wire $eq$ls180.v:6313$1985_Y
-  attribute \src "ls180.v:6314.101-6314.146"
-  wire $eq$ls180.v:6314$1989_Y
-  attribute \src "ls180.v:6316.97-6316.142"
-  wire $eq$ls180.v:6316$1992_Y
-  attribute \src "ls180.v:6317.100-6317.145"
-  wire $eq$ls180.v:6317$1996_Y
-  attribute \src "ls180.v:6319.103-6319.148"
-  wire $eq$ls180.v:6319$1999_Y
-  attribute \src "ls180.v:6320.106-6320.151"
-  wire $eq$ls180.v:6320$2003_Y
-  attribute \src "ls180.v:6322.106-6322.151"
-  wire $eq$ls180.v:6322$2006_Y
-  attribute \src "ls180.v:6323.109-6323.154"
-  wire $eq$ls180.v:6323$2010_Y
-  attribute \src "ls180.v:6325.106-6325.151"
-  wire $eq$ls180.v:6325$2013_Y
-  attribute \src "ls180.v:6326.109-6326.154"
-  wire $eq$ls180.v:6326$2017_Y
-  attribute \src "ls180.v:6347.33-6347.79"
-  wire $eq$ls180.v:6347$2020_Y
-  attribute \src "ls180.v:6349.99-6349.144"
-  wire $eq$ls180.v:6349$2022_Y
-  attribute \src "ls180.v:6350.102-6350.147"
-  wire $eq$ls180.v:6350$2026_Y
-  attribute \src "ls180.v:6352.99-6352.144"
-  wire $eq$ls180.v:6352$2029_Y
-  attribute \src "ls180.v:6353.102-6353.147"
-  wire $eq$ls180.v:6353$2033_Y
-  attribute \src "ls180.v:6355.99-6355.144"
-  wire $eq$ls180.v:6355$2036_Y
-  attribute \src "ls180.v:6356.102-6356.147"
-  wire $eq$ls180.v:6356$2040_Y
-  attribute \src "ls180.v:6358.99-6358.144"
-  wire $eq$ls180.v:6358$2043_Y
-  attribute \src "ls180.v:6359.102-6359.147"
-  wire $eq$ls180.v:6359$2047_Y
-  attribute \src "ls180.v:6361.101-6361.146"
-  wire $eq$ls180.v:6361$2050_Y
-  attribute \src "ls180.v:6362.104-6362.149"
-  wire $eq$ls180.v:6362$2054_Y
-  attribute \src "ls180.v:6364.101-6364.146"
-  wire $eq$ls180.v:6364$2057_Y
-  attribute \src "ls180.v:6365.104-6365.149"
-  wire $eq$ls180.v:6365$2061_Y
-  attribute \src "ls180.v:6367.101-6367.146"
-  wire $eq$ls180.v:6367$2064_Y
-  attribute \src "ls180.v:6368.104-6368.149"
-  wire $eq$ls180.v:6368$2068_Y
-  attribute \src "ls180.v:6370.101-6370.146"
-  wire $eq$ls180.v:6370$2071_Y
-  attribute \src "ls180.v:6371.104-6371.149"
-  wire $eq$ls180.v:6371$2075_Y
-  attribute \src "ls180.v:6373.97-6373.142"
-  wire $eq$ls180.v:6373$2078_Y
-  attribute \src "ls180.v:6374.100-6374.145"
-  wire $eq$ls180.v:6374$2082_Y
-  attribute \src "ls180.v:6376.107-6376.152"
-  wire $eq$ls180.v:6376$2085_Y
-  attribute \src "ls180.v:6377.110-6377.155"
-  wire $eq$ls180.v:6377$2089_Y
-  attribute \src "ls180.v:6379.100-6379.146"
-  wire $eq$ls180.v:6379$2092_Y
-  attribute \src "ls180.v:6380.103-6380.149"
-  wire $eq$ls180.v:6380$2096_Y
-  attribute \src "ls180.v:6382.100-6382.146"
-  wire $eq$ls180.v:6382$2099_Y
-  attribute \src "ls180.v:6383.103-6383.149"
-  wire $eq$ls180.v:6383$2103_Y
-  attribute \src "ls180.v:6385.100-6385.146"
-  wire $eq$ls180.v:6385$2106_Y
-  attribute \src "ls180.v:6386.103-6386.149"
-  wire $eq$ls180.v:6386$2110_Y
-  attribute \src "ls180.v:6388.100-6388.146"
-  wire $eq$ls180.v:6388$2113_Y
-  attribute \src "ls180.v:6389.103-6389.149"
-  wire $eq$ls180.v:6389$2117_Y
-  attribute \src "ls180.v:6391.112-6391.158"
-  wire $eq$ls180.v:6391$2120_Y
-  attribute \src "ls180.v:6392.115-6392.161"
-  wire $eq$ls180.v:6392$2124_Y
-  attribute \src "ls180.v:6394.113-6394.159"
-  wire $eq$ls180.v:6394$2127_Y
-  attribute \src "ls180.v:6395.116-6395.162"
-  wire $eq$ls180.v:6395$2131_Y
-  attribute \src "ls180.v:6397.104-6397.150"
-  wire $eq$ls180.v:6397$2134_Y
-  attribute \src "ls180.v:6398.107-6398.153"
-  wire $eq$ls180.v:6398$2138_Y
-  attribute \src "ls180.v:6415.33-6415.79"
-  wire $eq$ls180.v:6415$2140_Y
-  attribute \src "ls180.v:6417.90-6417.135"
-  wire $eq$ls180.v:6417$2142_Y
-  attribute \src "ls180.v:6418.93-6418.138"
-  wire $eq$ls180.v:6418$2146_Y
-  attribute \src "ls180.v:6420.100-6420.145"
-  wire $eq$ls180.v:6420$2149_Y
+  wire $eq$ls180.v:6163$1688_Y
+  attribute \src "ls180.v:6165.101-6165.146"
+  wire $eq$ls180.v:6165$1691_Y
+  attribute \src "ls180.v:6166.104-6166.149"
+  wire $eq$ls180.v:6166$1695_Y
+  attribute \src "ls180.v:6168.104-6168.149"
+  wire $eq$ls180.v:6168$1698_Y
+  attribute \src "ls180.v:6169.107-6169.152"
+  wire $eq$ls180.v:6169$1702_Y
+  attribute \src "ls180.v:6171.104-6171.149"
+  wire $eq$ls180.v:6171$1705_Y
+  attribute \src "ls180.v:6172.107-6172.152"
+  wire $eq$ls180.v:6172$1709_Y
+  attribute \src "ls180.v:6174.103-6174.148"
+  wire $eq$ls180.v:6174$1712_Y
+  attribute \src "ls180.v:6175.106-6175.151"
+  wire $eq$ls180.v:6175$1716_Y
+  attribute \src "ls180.v:6177.103-6177.148"
+  wire $eq$ls180.v:6177$1719_Y
+  attribute \src "ls180.v:6178.106-6178.151"
+  wire $eq$ls180.v:6178$1723_Y
+  attribute \src "ls180.v:6180.103-6180.148"
+  wire $eq$ls180.v:6180$1726_Y
+  attribute \src "ls180.v:6181.106-6181.151"
+  wire $eq$ls180.v:6181$1730_Y
+  attribute \src "ls180.v:6183.103-6183.148"
+  wire $eq$ls180.v:6183$1733_Y
+  attribute \src "ls180.v:6184.106-6184.151"
+  wire $eq$ls180.v:6184$1737_Y
+  attribute \src "ls180.v:6220.32-6220.78"
+  wire $eq$ls180.v:6220$1739_Y
+  attribute \src "ls180.v:6222.100-6222.144"
+  wire $eq$ls180.v:6222$1741_Y
+  attribute \src "ls180.v:6223.103-6223.147"
+  wire $eq$ls180.v:6223$1745_Y
+  attribute \src "ls180.v:6225.100-6225.144"
+  wire $eq$ls180.v:6225$1748_Y
+  attribute \src "ls180.v:6226.103-6226.147"
+  wire $eq$ls180.v:6226$1752_Y
+  attribute \src "ls180.v:6228.100-6228.144"
+  wire $eq$ls180.v:6228$1755_Y
+  attribute \src "ls180.v:6229.103-6229.147"
+  wire $eq$ls180.v:6229$1759_Y
+  attribute \src "ls180.v:6231.100-6231.144"
+  wire $eq$ls180.v:6231$1762_Y
+  attribute \src "ls180.v:6232.103-6232.147"
+  wire $eq$ls180.v:6232$1766_Y
+  attribute \src "ls180.v:6234.100-6234.144"
+  wire $eq$ls180.v:6234$1769_Y
+  attribute \src "ls180.v:6235.103-6235.147"
+  wire $eq$ls180.v:6235$1773_Y
+  attribute \src "ls180.v:6237.100-6237.144"
+  wire $eq$ls180.v:6237$1776_Y
+  attribute \src "ls180.v:6238.103-6238.147"
+  wire $eq$ls180.v:6238$1780_Y
+  attribute \src "ls180.v:6240.100-6240.144"
+  wire $eq$ls180.v:6240$1783_Y
+  attribute \src "ls180.v:6241.103-6241.147"
+  wire $eq$ls180.v:6241$1787_Y
+  attribute \src "ls180.v:6243.100-6243.144"
+  wire $eq$ls180.v:6243$1790_Y
+  attribute \src "ls180.v:6244.103-6244.147"
+  wire $eq$ls180.v:6244$1794_Y
+  attribute \src "ls180.v:6246.102-6246.146"
+  wire $eq$ls180.v:6246$1797_Y
+  attribute \src "ls180.v:6247.105-6247.149"
+  wire $eq$ls180.v:6247$1801_Y
+  attribute \src "ls180.v:6249.102-6249.146"
+  wire $eq$ls180.v:6249$1804_Y
+  attribute \src "ls180.v:6250.105-6250.149"
+  wire $eq$ls180.v:6250$1808_Y
+  attribute \src "ls180.v:6252.102-6252.147"
+  wire $eq$ls180.v:6252$1811_Y
+  attribute \src "ls180.v:6253.105-6253.150"
+  wire $eq$ls180.v:6253$1815_Y
+  attribute \src "ls180.v:6255.102-6255.147"
+  wire $eq$ls180.v:6255$1818_Y
+  attribute \src "ls180.v:6256.105-6256.150"
+  wire $eq$ls180.v:6256$1822_Y
+  attribute \src "ls180.v:6258.102-6258.147"
+  wire $eq$ls180.v:6258$1825_Y
+  attribute \src "ls180.v:6259.105-6259.150"
+  wire $eq$ls180.v:6259$1829_Y
+  attribute \src "ls180.v:6261.99-6261.144"
+  wire $eq$ls180.v:6261$1832_Y
+  attribute \src "ls180.v:6262.102-6262.147"
+  wire $eq$ls180.v:6262$1836_Y
+  attribute \src "ls180.v:6264.100-6264.145"
+  wire $eq$ls180.v:6264$1839_Y
+  attribute \src "ls180.v:6265.103-6265.148"
+  wire $eq$ls180.v:6265$1843_Y
+  attribute \src "ls180.v:6267.102-6267.147"
+  wire $eq$ls180.v:6267$1846_Y
+  attribute \src "ls180.v:6268.105-6268.150"
+  wire $eq$ls180.v:6268$1850_Y
+  attribute \src "ls180.v:6270.102-6270.147"
+  wire $eq$ls180.v:6270$1853_Y
+  attribute \src "ls180.v:6271.105-6271.150"
+  wire $eq$ls180.v:6271$1857_Y
+  attribute \src "ls180.v:6273.102-6273.147"
+  wire $eq$ls180.v:6273$1860_Y
+  attribute \src "ls180.v:6274.105-6274.150"
+  wire $eq$ls180.v:6274$1864_Y
+  attribute \src "ls180.v:6276.102-6276.147"
+  wire $eq$ls180.v:6276$1867_Y
+  attribute \src "ls180.v:6277.105-6277.150"
+  wire $eq$ls180.v:6277$1871_Y
+  attribute \src "ls180.v:6299.32-6299.78"
+  wire $eq$ls180.v:6299$1873_Y
+  attribute \src "ls180.v:6301.102-6301.146"
+  wire $eq$ls180.v:6301$1875_Y
+  attribute \src "ls180.v:6302.105-6302.149"
+  wire $eq$ls180.v:6302$1879_Y
+  attribute \src "ls180.v:6304.107-6304.151"
+  wire $eq$ls180.v:6304$1882_Y
+  attribute \src "ls180.v:6305.110-6305.154"
+  wire $eq$ls180.v:6305$1886_Y
+  attribute \src "ls180.v:6307.107-6307.151"
+  wire $eq$ls180.v:6307$1889_Y
+  attribute \src "ls180.v:6308.110-6308.154"
+  wire $eq$ls180.v:6308$1893_Y
+  attribute \src "ls180.v:6310.100-6310.144"
+  wire $eq$ls180.v:6310$1896_Y
+  attribute \src "ls180.v:6311.103-6311.147"
+  wire $eq$ls180.v:6311$1900_Y
+  attribute \src "ls180.v:6316.32-6316.77"
+  wire $eq$ls180.v:6316$1902_Y
+  attribute \src "ls180.v:6318.104-6318.148"
+  wire $eq$ls180.v:6318$1904_Y
+  attribute \src "ls180.v:6319.107-6319.151"
+  wire $eq$ls180.v:6319$1908_Y
+  attribute \src "ls180.v:6321.108-6321.152"
+  wire $eq$ls180.v:6321$1911_Y
+  attribute \src "ls180.v:6322.111-6322.155"
+  wire $eq$ls180.v:6322$1915_Y
+  attribute \src "ls180.v:6324.98-6324.142"
+  wire $eq$ls180.v:6324$1918_Y
+  attribute \src "ls180.v:6325.101-6325.145"
+  wire $eq$ls180.v:6325$1922_Y
+  attribute \src "ls180.v:6327.108-6327.152"
+  wire $eq$ls180.v:6327$1925_Y
+  attribute \src "ls180.v:6328.111-6328.155"
+  wire $eq$ls180.v:6328$1929_Y
+  attribute \src "ls180.v:6330.108-6330.152"
+  wire $eq$ls180.v:6330$1932_Y
+  attribute \src "ls180.v:6331.111-6331.155"
+  wire $eq$ls180.v:6331$1936_Y
+  attribute \src "ls180.v:6333.109-6333.153"
+  wire $eq$ls180.v:6333$1939_Y
+  attribute \src "ls180.v:6334.112-6334.156"
+  wire $eq$ls180.v:6334$1943_Y
+  attribute \src "ls180.v:6336.107-6336.151"
+  wire $eq$ls180.v:6336$1946_Y
+  attribute \src "ls180.v:6337.110-6337.154"
+  wire $eq$ls180.v:6337$1950_Y
+  attribute \src "ls180.v:6339.107-6339.151"
+  wire $eq$ls180.v:6339$1953_Y
+  attribute \src "ls180.v:6340.110-6340.154"
+  wire $eq$ls180.v:6340$1957_Y
+  attribute \src "ls180.v:6342.107-6342.151"
+  wire $eq$ls180.v:6342$1960_Y
+  attribute \src "ls180.v:6343.110-6343.154"
+  wire $eq$ls180.v:6343$1964_Y
+  attribute \src "ls180.v:6345.107-6345.151"
+  wire $eq$ls180.v:6345$1967_Y
+  attribute \src "ls180.v:6346.110-6346.154"
+  wire $eq$ls180.v:6346$1971_Y
+  attribute \src "ls180.v:6361.33-6361.79"
+  wire $eq$ls180.v:6361$1973_Y
+  attribute \src "ls180.v:6363.102-6363.147"
+  wire $eq$ls180.v:6363$1975_Y
+  attribute \src "ls180.v:6364.105-6364.150"
+  wire $eq$ls180.v:6364$1979_Y
+  attribute \src "ls180.v:6366.102-6366.147"
+  wire $eq$ls180.v:6366$1982_Y
+  attribute \src "ls180.v:6367.105-6367.150"
+  wire $eq$ls180.v:6367$1986_Y
+  attribute \src "ls180.v:6369.100-6369.145"
+  wire $eq$ls180.v:6369$1989_Y
+  attribute \src "ls180.v:6370.103-6370.148"
+  wire $eq$ls180.v:6370$1993_Y
+  attribute \src "ls180.v:6372.99-6372.144"
+  wire $eq$ls180.v:6372$1996_Y
+  attribute \src "ls180.v:6373.102-6373.147"
+  wire $eq$ls180.v:6373$2000_Y
+  attribute \src "ls180.v:6375.98-6375.143"
+  wire $eq$ls180.v:6375$2003_Y
+  attribute \src "ls180.v:6376.101-6376.146"
+  wire $eq$ls180.v:6376$2007_Y
+  attribute \src "ls180.v:6378.97-6378.142"
+  wire $eq$ls180.v:6378$2010_Y
+  attribute \src "ls180.v:6379.100-6379.145"
+  wire $eq$ls180.v:6379$2014_Y
+  attribute \src "ls180.v:6381.103-6381.148"
+  wire $eq$ls180.v:6381$2017_Y
+  attribute \src "ls180.v:6382.106-6382.151"
+  wire $eq$ls180.v:6382$2021_Y
+  attribute \src "ls180.v:6401.33-6401.79"
+  wire $eq$ls180.v:6401$2024_Y
+  attribute \src "ls180.v:6403.102-6403.147"
+  wire $eq$ls180.v:6403$2026_Y
+  attribute \src "ls180.v:6404.105-6404.150"
+  wire $eq$ls180.v:6404$2030_Y
+  attribute \src "ls180.v:6406.102-6406.147"
+  wire $eq$ls180.v:6406$2033_Y
+  attribute \src "ls180.v:6407.105-6407.150"
+  wire $eq$ls180.v:6407$2037_Y
+  attribute \src "ls180.v:6409.100-6409.145"
+  wire $eq$ls180.v:6409$2040_Y
+  attribute \src "ls180.v:6410.103-6410.148"
+  wire $eq$ls180.v:6410$2044_Y
+  attribute \src "ls180.v:6412.99-6412.144"
+  wire $eq$ls180.v:6412$2047_Y
+  attribute \src "ls180.v:6413.102-6413.147"
+  wire $eq$ls180.v:6413$2051_Y
+  attribute \src "ls180.v:6415.98-6415.143"
+  wire $eq$ls180.v:6415$2054_Y
+  attribute \src "ls180.v:6416.101-6416.146"
+  wire $eq$ls180.v:6416$2058_Y
+  attribute \src "ls180.v:6418.97-6418.142"
+  wire $eq$ls180.v:6418$2061_Y
+  attribute \src "ls180.v:6419.100-6419.145"
+  wire $eq$ls180.v:6419$2065_Y
   attribute \src "ls180.v:6421.103-6421.148"
-  wire $eq$ls180.v:6421$2153_Y
-  attribute \src "ls180.v:6423.101-6423.146"
-  wire $eq$ls180.v:6423$2156_Y
-  attribute \src "ls180.v:6424.104-6424.149"
-  wire $eq$ls180.v:6424$2160_Y
-  attribute \src "ls180.v:6426.105-6426.150"
-  wire $eq$ls180.v:6426$2163_Y
-  attribute \src "ls180.v:6427.108-6427.153"
-  wire $eq$ls180.v:6427$2167_Y
-  attribute \src "ls180.v:6429.106-6429.151"
-  wire $eq$ls180.v:6429$2170_Y
-  attribute \src "ls180.v:6430.109-6430.154"
-  wire $eq$ls180.v:6430$2174_Y
-  attribute \src "ls180.v:6432.104-6432.149"
-  wire $eq$ls180.v:6432$2177_Y
-  attribute \src "ls180.v:6433.107-6433.152"
-  wire $eq$ls180.v:6433$2181_Y
-  attribute \src "ls180.v:6435.101-6435.146"
-  wire $eq$ls180.v:6435$2184_Y
-  attribute \src "ls180.v:6436.104-6436.149"
-  wire $eq$ls180.v:6436$2188_Y
-  attribute \src "ls180.v:6438.100-6438.145"
-  wire $eq$ls180.v:6438$2191_Y
-  attribute \src "ls180.v:6439.103-6439.148"
-  wire $eq$ls180.v:6439$2195_Y
+  wire $eq$ls180.v:6421$2068_Y
+  attribute \src "ls180.v:6422.106-6422.151"
+  wire $eq$ls180.v:6422$2072_Y
+  attribute \src "ls180.v:6424.106-6424.151"
+  wire $eq$ls180.v:6424$2075_Y
+  attribute \src "ls180.v:6425.109-6425.154"
+  wire $eq$ls180.v:6425$2079_Y
+  attribute \src "ls180.v:6427.106-6427.151"
+  wire $eq$ls180.v:6427$2082_Y
+  attribute \src "ls180.v:6428.109-6428.154"
+  wire $eq$ls180.v:6428$2086_Y
   attribute \src "ls180.v:6449.33-6449.79"
-  wire $eq$ls180.v:6449$2197_Y
-  attribute \src "ls180.v:6451.106-6451.151"
-  wire $eq$ls180.v:6451$2199_Y
-  attribute \src "ls180.v:6452.109-6452.154"
-  wire $eq$ls180.v:6452$2203_Y
-  attribute \src "ls180.v:6454.106-6454.151"
-  wire $eq$ls180.v:6454$2206_Y
-  attribute \src "ls180.v:6455.109-6455.154"
-  wire $eq$ls180.v:6455$2210_Y
-  attribute \src "ls180.v:6457.106-6457.151"
-  wire $eq$ls180.v:6457$2213_Y
-  attribute \src "ls180.v:6458.109-6458.154"
-  wire $eq$ls180.v:6458$2217_Y
-  attribute \src "ls180.v:6460.106-6460.151"
-  wire $eq$ls180.v:6460$2220_Y
-  attribute \src "ls180.v:6461.109-6461.154"
-  wire $eq$ls180.v:6461$2224_Y
-  attribute \src "ls180.v:6842.41-6842.81"
-  wire $eq$ls180.v:6842$2261_Y
-  attribute \src "ls180.v:6842.144-6842.177"
-  wire $eq$ls180.v:6842$2262_Y
-  attribute \src "ls180.v:6842.219-6842.252"
-  wire $eq$ls180.v:6842$2265_Y
-  attribute \src "ls180.v:6842.294-6842.327"
-  wire $eq$ls180.v:6842$2268_Y
-  attribute \src "ls180.v:6866.41-6866.81"
-  wire $eq$ls180.v:6866$2277_Y
-  attribute \src "ls180.v:6866.144-6866.177"
-  wire $eq$ls180.v:6866$2278_Y
-  attribute \src "ls180.v:6866.219-6866.252"
-  wire $eq$ls180.v:6866$2281_Y
-  attribute \src "ls180.v:6866.294-6866.327"
-  wire $eq$ls180.v:6866$2284_Y
-  attribute \src "ls180.v:6890.41-6890.81"
-  wire $eq$ls180.v:6890$2293_Y
-  attribute \src "ls180.v:6890.144-6890.177"
-  wire $eq$ls180.v:6890$2294_Y
-  attribute \src "ls180.v:6890.219-6890.252"
-  wire $eq$ls180.v:6890$2297_Y
-  attribute \src "ls180.v:6890.294-6890.327"
-  wire $eq$ls180.v:6890$2300_Y
-  attribute \src "ls180.v:6914.41-6914.81"
-  wire $eq$ls180.v:6914$2309_Y
-  attribute \src "ls180.v:6914.144-6914.177"
-  wire $eq$ls180.v:6914$2310_Y
-  attribute \src "ls180.v:6914.219-6914.252"
-  wire $eq$ls180.v:6914$2313_Y
-  attribute \src "ls180.v:6914.294-6914.327"
-  wire $eq$ls180.v:6914$2316_Y
-  attribute \src "ls180.v:7495.8-7495.38"
-  wire $eq$ls180.v:7495$2407_Y
-  attribute \src "ls180.v:7526.8-7526.42"
-  wire $eq$ls180.v:7526$2415_Y
-  attribute \src "ls180.v:7546.38-7546.74"
-  wire $eq$ls180.v:7546$2418_Y
-  attribute \src "ls180.v:7553.7-7553.43"
-  wire $eq$ls180.v:7553$2420_Y
-  attribute \src "ls180.v:7560.7-7560.43"
-  wire $eq$ls180.v:7560$2421_Y
-  attribute \src "ls180.v:7568.7-7568.43"
-  wire $eq$ls180.v:7568$2422_Y
-  attribute \src "ls180.v:7620.9-7620.54"
-  wire $eq$ls180.v:7620$2440_Y
-  attribute \src "ls180.v:7666.9-7666.54"
-  wire $eq$ls180.v:7666$2456_Y
-  attribute \src "ls180.v:7712.9-7712.54"
-  wire $eq$ls180.v:7712$2472_Y
-  attribute \src "ls180.v:7758.9-7758.54"
-  wire $eq$ls180.v:7758$2488_Y
-  attribute \src "ls180.v:7908.9-7908.41"
-  wire $eq$ls180.v:7908$2500_Y
-  attribute \src "ls180.v:7923.9-7923.41"
-  wire $eq$ls180.v:7923$2503_Y
-  attribute \src "ls180.v:7929.49-7929.82"
-  wire $eq$ls180.v:7929$2504_Y
-  attribute \src "ls180.v:7929.131-7929.164"
-  wire $eq$ls180.v:7929$2507_Y
-  attribute \src "ls180.v:7929.213-7929.246"
-  wire $eq$ls180.v:7929$2510_Y
-  attribute \src "ls180.v:7929.295-7929.328"
-  wire $eq$ls180.v:7929$2513_Y
-  attribute \src "ls180.v:7930.50-7930.83"
-  wire $eq$ls180.v:7930$2516_Y
-  attribute \src "ls180.v:7930.132-7930.165"
-  wire $eq$ls180.v:7930$2519_Y
-  attribute \src "ls180.v:7930.214-7930.247"
-  wire $eq$ls180.v:7930$2522_Y
-  attribute \src "ls180.v:7930.296-7930.329"
-  wire $eq$ls180.v:7930$2525_Y
-  attribute \src "ls180.v:7965.9-7965.42"
-  wire $eq$ls180.v:7965$2537_Y
-  attribute \src "ls180.v:7968.10-7968.43"
-  wire $eq$ls180.v:7968$2538_Y
-  attribute \src "ls180.v:7994.9-7994.42"
-  wire $eq$ls180.v:7994$2544_Y
-  attribute \src "ls180.v:7999.10-7999.43"
-  wire $eq$ls180.v:7999$2545_Y
-  attribute \src "ls180.v:8206.9-8206.53"
-  wire $eq$ls180.v:8206$2594_Y
-  attribute \src "ls180.v:8287.9-8287.54"
-  wire $eq$ls180.v:8287$2606_Y
-  attribute \src "ls180.v:8366.9-8366.55"
-  wire $eq$ls180.v:8366$2618_Y
-  attribute \src "ls180.v:8589.9-8589.49"
-  wire $eq$ls180.v:8589$2651_Y
-  attribute \src "ls180.v:8165.8-8165.54"
-  wire $ge$ls180.v:8165$2586_Y
-  attribute \src "ls180.v:8179.8-8179.54"
-  wire $ge$ls180.v:8179$2590_Y
-  attribute \src "ls180.v:5151.47-5151.83"
-  wire $gt$ls180.v:5151$914_Y
-  attribute \src "ls180.v:5157.7-5157.43"
-  wire $lt$ls180.v:5157$917_Y
-  attribute \src "ls180.v:8160.8-8160.43"
-  wire $lt$ls180.v:8160$2584_Y
-  attribute \src "ls180.v:8174.8-8174.43"
-  wire $lt$ls180.v:8174$2588_Y
-  attribute \src "ls180.v:10055.33-10055.36"
-  wire width 32 $memrd$\mem$ls180.v:10055$2693_DATA
-  attribute \src "ls180.v:10066.12-10066.19"
-  wire width 25 $memrd$\storage$ls180.v:10066$2698_DATA
-  attribute \src "ls180.v:10073.68-10073.75"
-  wire width 25 $memrd$\storage$ls180.v:10073$2700_DATA
-  attribute \src "ls180.v:10080.14-10080.23"
-  wire width 25 $memrd$\storage_1$ls180.v:10080$2705_DATA
-  attribute \src "ls180.v:10087.68-10087.77"
-  wire width 25 $memrd$\storage_1$ls180.v:10087$2707_DATA
-  attribute \src "ls180.v:10094.14-10094.23"
-  wire width 25 $memrd$\storage_2$ls180.v:10094$2712_DATA
-  attribute \src "ls180.v:10101.68-10101.77"
-  wire width 25 $memrd$\storage_2$ls180.v:10101$2714_DATA
-  attribute \src "ls180.v:10108.14-10108.23"
-  wire width 25 $memrd$\storage_3$ls180.v:10108$2719_DATA
-  attribute \src "ls180.v:10115.68-10115.77"
-  wire width 25 $memrd$\storage_3$ls180.v:10115$2721_DATA
-  attribute \src "ls180.v:10123.14-10123.23"
-  wire width 10 $memrd$\storage_4$ls180.v:10123$2726_DATA
-  attribute \src "ls180.v:10128.15-10128.24"
-  wire width 10 $memrd$\storage_4$ls180.v:10128$2728_DATA
-  attribute \src "ls180.v:10140.14-10140.23"
-  wire width 10 $memrd$\storage_5$ls180.v:10140$2733_DATA
-  attribute \src "ls180.v:10145.15-10145.24"
-  wire width 10 $memrd$\storage_5$ls180.v:10145$2735_DATA
-  attribute \src "ls180.v:10156.14-10156.23"
-  wire width 10 $memrd$\storage_6$ls180.v:10156$2740_DATA
-  attribute \src "ls180.v:10163.45-10163.54"
-  wire width 10 $memrd$\storage_6$ls180.v:10163$2742_DATA
-  attribute \src "ls180.v:10170.14-10170.23"
-  wire width 10 $memrd$\storage_7$ls180.v:10170$2747_DATA
-  attribute \src "ls180.v:10177.45-10177.54"
-  wire width 10 $memrd$\storage_7$ls180.v:10177$2749_DATA
+  wire $eq$ls180.v:6449$2089_Y
+  attribute \src "ls180.v:6451.99-6451.144"
+  wire $eq$ls180.v:6451$2091_Y
+  attribute \src "ls180.v:6452.102-6452.147"
+  wire $eq$ls180.v:6452$2095_Y
+  attribute \src "ls180.v:6454.99-6454.144"
+  wire $eq$ls180.v:6454$2098_Y
+  attribute \src "ls180.v:6455.102-6455.147"
+  wire $eq$ls180.v:6455$2102_Y
+  attribute \src "ls180.v:6457.99-6457.144"
+  wire $eq$ls180.v:6457$2105_Y
+  attribute \src "ls180.v:6458.102-6458.147"
+  wire $eq$ls180.v:6458$2109_Y
+  attribute \src "ls180.v:6460.99-6460.144"
+  wire $eq$ls180.v:6460$2112_Y
+  attribute \src "ls180.v:6461.102-6461.147"
+  wire $eq$ls180.v:6461$2116_Y
+  attribute \src "ls180.v:6463.101-6463.146"
+  wire $eq$ls180.v:6463$2119_Y
+  attribute \src "ls180.v:6464.104-6464.149"
+  wire $eq$ls180.v:6464$2123_Y
+  attribute \src "ls180.v:6466.101-6466.146"
+  wire $eq$ls180.v:6466$2126_Y
+  attribute \src "ls180.v:6467.104-6467.149"
+  wire $eq$ls180.v:6467$2130_Y
+  attribute \src "ls180.v:6469.101-6469.146"
+  wire $eq$ls180.v:6469$2133_Y
+  attribute \src "ls180.v:6470.104-6470.149"
+  wire $eq$ls180.v:6470$2137_Y
+  attribute \src "ls180.v:6472.101-6472.146"
+  wire $eq$ls180.v:6472$2140_Y
+  attribute \src "ls180.v:6473.104-6473.149"
+  wire $eq$ls180.v:6473$2144_Y
+  attribute \src "ls180.v:6475.97-6475.142"
+  wire $eq$ls180.v:6475$2147_Y
+  attribute \src "ls180.v:6476.100-6476.145"
+  wire $eq$ls180.v:6476$2151_Y
+  attribute \src "ls180.v:6478.107-6478.152"
+  wire $eq$ls180.v:6478$2154_Y
+  attribute \src "ls180.v:6479.110-6479.155"
+  wire $eq$ls180.v:6479$2158_Y
+  attribute \src "ls180.v:6481.100-6481.146"
+  wire $eq$ls180.v:6481$2161_Y
+  attribute \src "ls180.v:6482.103-6482.149"
+  wire $eq$ls180.v:6482$2165_Y
+  attribute \src "ls180.v:6484.100-6484.146"
+  wire $eq$ls180.v:6484$2168_Y
+  attribute \src "ls180.v:6485.103-6485.149"
+  wire $eq$ls180.v:6485$2172_Y
+  attribute \src "ls180.v:6487.100-6487.146"
+  wire $eq$ls180.v:6487$2175_Y
+  attribute \src "ls180.v:6488.103-6488.149"
+  wire $eq$ls180.v:6488$2179_Y
+  attribute \src "ls180.v:6490.100-6490.146"
+  wire $eq$ls180.v:6490$2182_Y
+  attribute \src "ls180.v:6491.103-6491.149"
+  wire $eq$ls180.v:6491$2186_Y
+  attribute \src "ls180.v:6493.112-6493.158"
+  wire $eq$ls180.v:6493$2189_Y
+  attribute \src "ls180.v:6494.115-6494.161"
+  wire $eq$ls180.v:6494$2193_Y
+  attribute \src "ls180.v:6496.113-6496.159"
+  wire $eq$ls180.v:6496$2196_Y
+  attribute \src "ls180.v:6497.116-6497.162"
+  wire $eq$ls180.v:6497$2200_Y
+  attribute \src "ls180.v:6499.104-6499.150"
+  wire $eq$ls180.v:6499$2203_Y
+  attribute \src "ls180.v:6500.107-6500.153"
+  wire $eq$ls180.v:6500$2207_Y
+  attribute \src "ls180.v:6517.33-6517.79"
+  wire $eq$ls180.v:6517$2209_Y
+  attribute \src "ls180.v:6519.90-6519.135"
+  wire $eq$ls180.v:6519$2211_Y
+  attribute \src "ls180.v:6520.93-6520.138"
+  wire $eq$ls180.v:6520$2215_Y
+  attribute \src "ls180.v:6522.100-6522.145"
+  wire $eq$ls180.v:6522$2218_Y
+  attribute \src "ls180.v:6523.103-6523.148"
+  wire $eq$ls180.v:6523$2222_Y
+  attribute \src "ls180.v:6525.101-6525.146"
+  wire $eq$ls180.v:6525$2225_Y
+  attribute \src "ls180.v:6526.104-6526.149"
+  wire $eq$ls180.v:6526$2229_Y
+  attribute \src "ls180.v:6528.105-6528.150"
+  wire $eq$ls180.v:6528$2232_Y
+  attribute \src "ls180.v:6529.108-6529.153"
+  wire $eq$ls180.v:6529$2236_Y
+  attribute \src "ls180.v:6531.106-6531.151"
+  wire $eq$ls180.v:6531$2239_Y
+  attribute \src "ls180.v:6532.109-6532.154"
+  wire $eq$ls180.v:6532$2243_Y
+  attribute \src "ls180.v:6534.104-6534.149"
+  wire $eq$ls180.v:6534$2246_Y
+  attribute \src "ls180.v:6535.107-6535.152"
+  wire $eq$ls180.v:6535$2250_Y
+  attribute \src "ls180.v:6537.101-6537.146"
+  wire $eq$ls180.v:6537$2253_Y
+  attribute \src "ls180.v:6538.104-6538.149"
+  wire $eq$ls180.v:6538$2257_Y
+  attribute \src "ls180.v:6540.100-6540.145"
+  wire $eq$ls180.v:6540$2260_Y
+  attribute \src "ls180.v:6541.103-6541.148"
+  wire $eq$ls180.v:6541$2264_Y
+  attribute \src "ls180.v:6551.33-6551.79"
+  wire $eq$ls180.v:6551$2266_Y
+  attribute \src "ls180.v:6553.106-6553.151"
+  wire $eq$ls180.v:6553$2268_Y
+  attribute \src "ls180.v:6554.109-6554.154"
+  wire $eq$ls180.v:6554$2272_Y
+  attribute \src "ls180.v:6556.106-6556.151"
+  wire $eq$ls180.v:6556$2275_Y
+  attribute \src "ls180.v:6557.109-6557.154"
+  wire $eq$ls180.v:6557$2279_Y
+  attribute \src "ls180.v:6559.106-6559.151"
+  wire $eq$ls180.v:6559$2282_Y
+  attribute \src "ls180.v:6560.109-6560.154"
+  wire $eq$ls180.v:6560$2286_Y
+  attribute \src "ls180.v:6562.106-6562.151"
+  wire $eq$ls180.v:6562$2289_Y
+  attribute \src "ls180.v:6563.109-6563.154"
+  wire $eq$ls180.v:6563$2293_Y
+  attribute \src "ls180.v:6944.41-6944.81"
+  wire $eq$ls180.v:6944$2330_Y
+  attribute \src "ls180.v:6944.144-6944.177"
+  wire $eq$ls180.v:6944$2331_Y
+  attribute \src "ls180.v:6944.219-6944.252"
+  wire $eq$ls180.v:6944$2334_Y
+  attribute \src "ls180.v:6944.294-6944.327"
+  wire $eq$ls180.v:6944$2337_Y
+  attribute \src "ls180.v:6968.41-6968.81"
+  wire $eq$ls180.v:6968$2346_Y
+  attribute \src "ls180.v:6968.144-6968.177"
+  wire $eq$ls180.v:6968$2347_Y
+  attribute \src "ls180.v:6968.219-6968.252"
+  wire $eq$ls180.v:6968$2350_Y
+  attribute \src "ls180.v:6968.294-6968.327"
+  wire $eq$ls180.v:6968$2353_Y
+  attribute \src "ls180.v:6992.41-6992.81"
+  wire $eq$ls180.v:6992$2362_Y
+  attribute \src "ls180.v:6992.144-6992.177"
+  wire $eq$ls180.v:6992$2363_Y
+  attribute \src "ls180.v:6992.219-6992.252"
+  wire $eq$ls180.v:6992$2366_Y
+  attribute \src "ls180.v:6992.294-6992.327"
+  wire $eq$ls180.v:6992$2369_Y
+  attribute \src "ls180.v:7016.41-7016.81"
+  wire $eq$ls180.v:7016$2378_Y
+  attribute \src "ls180.v:7016.144-7016.177"
+  wire $eq$ls180.v:7016$2379_Y
+  attribute \src "ls180.v:7016.219-7016.252"
+  wire $eq$ls180.v:7016$2382_Y
+  attribute \src "ls180.v:7016.294-7016.327"
+  wire $eq$ls180.v:7016$2385_Y
+  attribute \src "ls180.v:7597.8-7597.38"
+  wire $eq$ls180.v:7597$2476_Y
+  attribute \src "ls180.v:7640.8-7640.42"
+  wire $eq$ls180.v:7640$2493_Y
+  attribute \src "ls180.v:7660.38-7660.74"
+  wire $eq$ls180.v:7660$2496_Y
+  attribute \src "ls180.v:7667.7-7667.43"
+  wire $eq$ls180.v:7667$2498_Y
+  attribute \src "ls180.v:7674.7-7674.43"
+  wire $eq$ls180.v:7674$2499_Y
+  attribute \src "ls180.v:7682.7-7682.43"
+  wire $eq$ls180.v:7682$2500_Y
+  attribute \src "ls180.v:7734.9-7734.54"
+  wire $eq$ls180.v:7734$2518_Y
+  attribute \src "ls180.v:7780.9-7780.54"
+  wire $eq$ls180.v:7780$2534_Y
+  attribute \src "ls180.v:7826.9-7826.54"
+  wire $eq$ls180.v:7826$2550_Y
+  attribute \src "ls180.v:7872.9-7872.54"
+  wire $eq$ls180.v:7872$2566_Y
+  attribute \src "ls180.v:8022.9-8022.41"
+  wire $eq$ls180.v:8022$2578_Y
+  attribute \src "ls180.v:8037.9-8037.41"
+  wire $eq$ls180.v:8037$2581_Y
+  attribute \src "ls180.v:8043.49-8043.82"
+  wire $eq$ls180.v:8043$2582_Y
+  attribute \src "ls180.v:8043.131-8043.164"
+  wire $eq$ls180.v:8043$2585_Y
+  attribute \src "ls180.v:8043.213-8043.246"
+  wire $eq$ls180.v:8043$2588_Y
+  attribute \src "ls180.v:8043.295-8043.328"
+  wire $eq$ls180.v:8043$2591_Y
+  attribute \src "ls180.v:8044.50-8044.83"
+  wire $eq$ls180.v:8044$2594_Y
+  attribute \src "ls180.v:8044.132-8044.165"
+  wire $eq$ls180.v:8044$2597_Y
+  attribute \src "ls180.v:8044.214-8044.247"
+  wire $eq$ls180.v:8044$2600_Y
+  attribute \src "ls180.v:8044.296-8044.329"
+  wire $eq$ls180.v:8044$2603_Y
+  attribute \src "ls180.v:8079.9-8079.42"
+  wire $eq$ls180.v:8079$2615_Y
+  attribute \src "ls180.v:8082.10-8082.43"
+  wire $eq$ls180.v:8082$2616_Y
+  attribute \src "ls180.v:8108.9-8108.42"
+  wire $eq$ls180.v:8108$2622_Y
+  attribute \src "ls180.v:8113.10-8113.43"
+  wire $eq$ls180.v:8113$2623_Y
+  attribute \src "ls180.v:8320.9-8320.53"
+  wire $eq$ls180.v:8320$2672_Y
+  attribute \src "ls180.v:8401.9-8401.54"
+  wire $eq$ls180.v:8401$2684_Y
+  attribute \src "ls180.v:8480.9-8480.55"
+  wire $eq$ls180.v:8480$2696_Y
+  attribute \src "ls180.v:8703.9-8703.49"
+  wire $eq$ls180.v:8703$2729_Y
+  attribute \src "ls180.v:8279.8-8279.54"
+  wire $ge$ls180.v:8279$2664_Y
+  attribute \src "ls180.v:8293.8-8293.54"
+  wire $ge$ls180.v:8293$2668_Y
+  attribute \src "ls180.v:5226.47-5226.83"
+  wire $gt$ls180.v:5226$965_Y
+  attribute \src "ls180.v:5232.7-5232.43"
+  wire $lt$ls180.v:5232$968_Y
+  attribute \src "ls180.v:8274.8-8274.43"
+  wire $lt$ls180.v:8274$2662_Y
+  attribute \src "ls180.v:8288.8-8288.43"
+  wire $lt$ls180.v:8288$2666_Y
+  attribute \src "ls180.v:10172.33-10172.36"
+  wire width 32 $memrd$\mem$ls180.v:10172$2771_DATA
+  attribute \src "ls180.v:10192.27-10192.32"
+  wire width 32 $memrd$\mem_1$ls180.v:10192$2785_DATA
+  attribute \src "ls180.v:10212.27-10212.32"
+  wire width 32 $memrd$\mem_2$ls180.v:10212$2799_DATA
+  attribute \src "ls180.v:10232.27-10232.32"
+  wire width 32 $memrd$\mem_3$ls180.v:10232$2813_DATA
+  attribute \src "ls180.v:10243.12-10243.19"
+  wire width 25 $memrd$\storage$ls180.v:10243$2818_DATA
+  attribute \src "ls180.v:10250.68-10250.75"
+  wire width 25 $memrd$\storage$ls180.v:10250$2820_DATA
+  attribute \src "ls180.v:10257.14-10257.23"
+  wire width 25 $memrd$\storage_1$ls180.v:10257$2825_DATA
+  attribute \src "ls180.v:10264.68-10264.77"
+  wire width 25 $memrd$\storage_1$ls180.v:10264$2827_DATA
+  attribute \src "ls180.v:10271.14-10271.23"
+  wire width 25 $memrd$\storage_2$ls180.v:10271$2832_DATA
+  attribute \src "ls180.v:10278.68-10278.77"
+  wire width 25 $memrd$\storage_2$ls180.v:10278$2834_DATA
+  attribute \src "ls180.v:10285.14-10285.23"
+  wire width 25 $memrd$\storage_3$ls180.v:10285$2839_DATA
+  attribute \src "ls180.v:10292.68-10292.77"
+  wire width 25 $memrd$\storage_3$ls180.v:10292$2841_DATA
+  attribute \src "ls180.v:10300.14-10300.23"
+  wire width 10 $memrd$\storage_4$ls180.v:10300$2846_DATA
+  attribute \src "ls180.v:10305.15-10305.24"
+  wire width 10 $memrd$\storage_4$ls180.v:10305$2848_DATA
+  attribute \src "ls180.v:10317.14-10317.23"
+  wire width 10 $memrd$\storage_5$ls180.v:10317$2853_DATA
+  attribute \src "ls180.v:10322.15-10322.24"
+  wire width 10 $memrd$\storage_5$ls180.v:10322$2855_DATA
+  attribute \src "ls180.v:10333.14-10333.23"
+  wire width 10 $memrd$\storage_6$ls180.v:10333$2860_DATA
+  attribute \src "ls180.v:10340.45-10340.54"
+  wire width 10 $memrd$\storage_6$ls180.v:10340$2862_DATA
+  attribute \src "ls180.v:10347.14-10347.23"
+  wire width 10 $memrd$\storage_7$ls180.v:10347$2867_DATA
+  attribute \src "ls180.v:10354.45-10354.54"
+  wire width 10 $memrd$\storage_7$ls180.v:10354$2869_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem$ls180.v:10162$1_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10162$1_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10162$1_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem$ls180.v:10164$2_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10164$2_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10164$2_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem$ls180.v:10166$3_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10166$3_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10166$3_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem$ls180.v:10168$4_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10168$4_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem$ls180.v:10168$4_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_1$ls180.v:10182$5_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10182$5_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10182$5_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_1$ls180.v:10184$6_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10184$6_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10184$6_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_1$ls180.v:10186$7_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10186$7_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10186$7_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_1$ls180.v:10188$8_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10188$8_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_1$ls180.v:10188$8_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_2$ls180.v:10202$9_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_2$ls180.v:10202$9_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_2$ls180.v:10202$9_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 7 $memwr$\mem_2$ls180.v:10204$10_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 32 $memwr$\mem_2$ls180.v:10204$10_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10045$1_ADDR
+  wire width 32 $memwr$\mem_2$ls180.v:10204$10_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10045$1_DATA
+  wire width 7 $memwr$\mem_2$ls180.v:10206$11_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10045$1_EN
+  wire width 32 $memwr$\mem_2$ls180.v:10206$11_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10047$2_ADDR
+  wire width 32 $memwr$\mem_2$ls180.v:10206$11_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10047$2_DATA
+  wire width 7 $memwr$\mem_2$ls180.v:10208$12_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10047$2_EN
+  wire width 32 $memwr$\mem_2$ls180.v:10208$12_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10049$3_ADDR
+  wire width 32 $memwr$\mem_2$ls180.v:10208$12_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10049$3_DATA
+  wire width 7 $memwr$\mem_3$ls180.v:10222$13_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10049$3_EN
+  wire width 32 $memwr$\mem_3$ls180.v:10222$13_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10051$4_ADDR
+  wire width 32 $memwr$\mem_3$ls180.v:10222$13_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10051$4_DATA
+  wire width 7 $memwr$\mem_3$ls180.v:10224$14_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10051$4_EN
+  wire width 32 $memwr$\mem_3$ls180.v:10224$14_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage$ls180.v:10065$5_ADDR
+  wire width 32 $memwr$\mem_3$ls180.v:10224$14_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:10065$5_DATA
+  wire width 7 $memwr$\mem_3$ls180.v:10226$15_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:10065$5_EN
+  wire width 32 $memwr$\mem_3$ls180.v:10226$15_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_1$ls180.v:10079$6_ADDR
+  wire width 32 $memwr$\mem_3$ls180.v:10226$15_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:10079$6_DATA
+  wire width 7 $memwr$\mem_3$ls180.v:10228$16_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:10079$6_EN
+  wire width 32 $memwr$\mem_3$ls180.v:10228$16_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_2$ls180.v:10093$7_ADDR
+  wire width 32 $memwr$\mem_3$ls180.v:10228$16_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:10093$7_DATA
+  wire width 3 $memwr$\storage$ls180.v:10242$17_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:10093$7_EN
+  wire width 25 $memwr$\storage$ls180.v:10242$17_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_3$ls180.v:10107$8_ADDR
+  wire width 25 $memwr$\storage$ls180.v:10242$17_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:10107$8_DATA
+  wire width 3 $memwr$\storage_1$ls180.v:10256$18_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:10107$8_EN
+  wire width 25 $memwr$\storage_1$ls180.v:10256$18_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_4$ls180.v:10122$9_ADDR
+  wire width 25 $memwr$\storage_1$ls180.v:10256$18_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:10122$9_DATA
+  wire width 3 $memwr$\storage_2$ls180.v:10270$19_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:10122$9_EN
+  wire width 25 $memwr$\storage_2$ls180.v:10270$19_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_5$ls180.v:10139$10_ADDR
+  wire width 25 $memwr$\storage_2$ls180.v:10270$19_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:10139$10_DATA
+  wire width 3 $memwr$\storage_3$ls180.v:10284$20_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:10139$10_EN
+  wire width 25 $memwr$\storage_3$ls180.v:10284$20_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 5 $memwr$\storage_6$ls180.v:10155$11_ADDR
+  wire width 25 $memwr$\storage_3$ls180.v:10284$20_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_6$ls180.v:10155$11_DATA
+  wire width 4 $memwr$\storage_4$ls180.v:10299$21_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_6$ls180.v:10155$11_EN
+  wire width 10 $memwr$\storage_4$ls180.v:10299$21_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 5 $memwr$\storage_7$ls180.v:10169$12_ADDR
+  wire width 10 $memwr$\storage_4$ls180.v:10299$21_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_7$ls180.v:10169$12_DATA
+  wire width 4 $memwr$\storage_5$ls180.v:10316$22_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_7$ls180.v:10169$12_EN
-  attribute \src "ls180.v:2965.41-2965.71"
-  wire $ne$ls180.v:2965$60_Y
-  attribute \src "ls180.v:3126.70-3126.104"
-  wire $ne$ls180.v:3126$74_Y
-  attribute \src "ls180.v:3187.8-3187.142"
-  wire $ne$ls180.v:3187$93_Y
-  attribute \src "ls180.v:3219.75-3219.133"
-  wire $ne$ls180.v:3219$100_Y
-  attribute \src "ls180.v:3220.75-3220.133"
-  wire $ne$ls180.v:3220$101_Y
-  attribute \src "ls180.v:3344.8-3344.142"
-  wire $ne$ls180.v:3344$123_Y
-  attribute \src "ls180.v:3376.75-3376.133"
-  wire $ne$ls180.v:3376$130_Y
-  attribute \src "ls180.v:3377.75-3377.133"
-  wire $ne$ls180.v:3377$131_Y
-  attribute \src "ls180.v:3501.8-3501.142"
-  wire $ne$ls180.v:3501$153_Y
-  attribute \src "ls180.v:3533.75-3533.133"
-  wire $ne$ls180.v:3533$160_Y
-  attribute \src "ls180.v:3534.75-3534.133"
-  wire $ne$ls180.v:3534$161_Y
-  attribute \src "ls180.v:3658.8-3658.142"
-  wire $ne$ls180.v:3658$183_Y
-  attribute \src "ls180.v:3690.75-3690.133"
-  wire $ne$ls180.v:3690$190_Y
-  attribute \src "ls180.v:3691.75-3691.133"
-  wire $ne$ls180.v:3691$191_Y
-  attribute \src "ls180.v:4183.47-4183.80"
-  wire $ne$ls180.v:4183$589_Y
-  attribute \src "ls180.v:4184.47-4184.79"
-  wire $ne$ls180.v:4184$590_Y
-  attribute \src "ls180.v:4213.47-4213.80"
-  wire $ne$ls180.v:4213$600_Y
-  attribute \src "ls180.v:4214.47-4214.79"
-  wire $ne$ls180.v:4214$601_Y
-  attribute \src "ls180.v:4683.32-4683.89"
-  wire $ne$ls180.v:4683$681_Y
-  attribute \src "ls180.v:5330.10-5330.56"
-  wire $ne$ls180.v:5330$978_Y
-  attribute \src "ls180.v:5435.51-5435.87"
-  wire $ne$ls180.v:5435$992_Y
-  attribute \src "ls180.v:5436.51-5436.86"
-  wire $ne$ls180.v:5436$993_Y
-  attribute \src "ls180.v:5643.51-5643.87"
-  wire $ne$ls180.v:5643$1023_Y
-  attribute \src "ls180.v:5644.51-5644.86"
-  wire $ne$ls180.v:5644$1024_Y
-  attribute \src "ls180.v:5675.79-5675.119"
-  wire $ne$ls180.v:5675$1027_Y
-  attribute \src "ls180.v:7485.7-7485.52"
-  wire $ne$ls180.v:7485$2402_Y
-  attribute \src "ls180.v:7535.9-7535.43"
-  wire $ne$ls180.v:7535$2416_Y
-  attribute \src "ls180.v:7571.8-7571.44"
-  wire $ne$ls180.v:7571$2423_Y
-  attribute \src "ls180.v:8509.9-8509.47"
-  wire $ne$ls180.v:8509$2638_Y
-  attribute \src "ls180.v:2773.45-2773.80"
-  wire $not$ls180.v:2773$14_Y
-  attribute \src "ls180.v:2812.61-2812.94"
-  wire $not$ls180.v:2812$19_Y
-  attribute \src "ls180.v:2813.61-2813.94"
-  wire $not$ls180.v:2813$20_Y
-  attribute \src "ls180.v:2833.45-2833.80"
-  wire $not$ls180.v:2833$25_Y
-  attribute \src "ls180.v:2872.61-2872.94"
-  wire $not$ls180.v:2872$30_Y
-  attribute \src "ls180.v:2873.61-2873.94"
-  wire $not$ls180.v:2873$31_Y
-  attribute \src "ls180.v:2893.45-2893.83"
-  wire $not$ls180.v:2893$36_Y
-  attribute \src "ls180.v:2932.61-2932.94"
-  wire $not$ls180.v:2932$41_Y
-  attribute \src "ls180.v:2933.61-2933.94"
-  wire $not$ls180.v:2933$42_Y
-  attribute \src "ls180.v:3075.34-3075.64"
-  wire $not$ls180.v:3075$66_Y
-  attribute \src "ls180.v:3076.31-3076.61"
-  wire $not$ls180.v:3076$67_Y
-  attribute \src "ls180.v:3077.32-3077.62"
-  wire $not$ls180.v:3077$68_Y
-  attribute \src "ls180.v:3078.32-3078.62"
-  wire $not$ls180.v:3078$69_Y
-  attribute \src "ls180.v:3120.33-3120.56"
-  wire $not$ls180.v:3120$72_Y
-  attribute \src "ls180.v:3221.58-3221.106"
-  wire $not$ls180.v:3221$102_Y
-  attribute \src "ls180.v:3275.9-3275.45"
-  wire $not$ls180.v:3275$107_Y
-  attribute \src "ls180.v:3378.58-3378.106"
-  wire $not$ls180.v:3378$132_Y
-  attribute \src "ls180.v:3432.9-3432.45"
-  wire $not$ls180.v:3432$137_Y
-  attribute \src "ls180.v:3535.58-3535.106"
-  wire $not$ls180.v:3535$162_Y
-  attribute \src "ls180.v:3589.9-3589.45"
-  wire $not$ls180.v:3589$167_Y
-  attribute \src "ls180.v:3692.58-3692.106"
-  wire $not$ls180.v:3692$192_Y
-  attribute \src "ls180.v:3746.9-3746.45"
-  wire $not$ls180.v:3746$197_Y
-  attribute \src "ls180.v:3788.149-3788.187"
-  wire $not$ls180.v:3788$200_Y
-  attribute \src "ls180.v:3788.193-3788.230"
-  wire $not$ls180.v:3788$202_Y
-  attribute \src "ls180.v:3789.149-3789.187"
-  wire $not$ls180.v:3789$206_Y
-  attribute \src "ls180.v:3789.193-3789.230"
-  wire $not$ls180.v:3789$208_Y
-  attribute \src "ls180.v:3805.43-3805.73"
-  wire width 2 $not$ls180.v:3805$236_Y
-  attribute \src "ls180.v:3808.205-3808.245"
-  wire $not$ls180.v:3808$239_Y
-  attribute \src "ls180.v:3808.251-3808.290"
-  wire $not$ls180.v:3808$241_Y
-  attribute \src "ls180.v:3808.159-3808.292"
-  wire $not$ls180.v:3808$243_Y
-  attribute \src "ls180.v:3809.205-3809.245"
-  wire $not$ls180.v:3809$252_Y
-  attribute \src "ls180.v:3809.251-3809.290"
-  wire $not$ls180.v:3809$254_Y
-  attribute \src "ls180.v:3809.159-3809.292"
-  wire $not$ls180.v:3809$256_Y
-  attribute \src "ls180.v:3810.205-3810.245"
-  wire $not$ls180.v:3810$265_Y
-  attribute \src "ls180.v:3810.251-3810.290"
-  wire $not$ls180.v:3810$267_Y
-  attribute \src "ls180.v:3810.159-3810.292"
-  wire $not$ls180.v:3810$269_Y
-  attribute \src "ls180.v:3811.205-3811.245"
-  wire $not$ls180.v:3811$278_Y
-  attribute \src "ls180.v:3811.251-3811.290"
-  wire $not$ls180.v:3811$280_Y
-  attribute \src "ls180.v:3811.159-3811.292"
-  wire $not$ls180.v:3811$282_Y
-  attribute \src "ls180.v:3838.71-3838.103"
-  wire $not$ls180.v:3838$293_Y
-  attribute \src "ls180.v:3841.205-3841.245"
-  wire $not$ls180.v:3841$297_Y
-  attribute \src "ls180.v:3841.251-3841.290"
-  wire $not$ls180.v:3841$299_Y
-  attribute \src "ls180.v:3841.159-3841.292"
-  wire $not$ls180.v:3841$301_Y
-  attribute \src "ls180.v:3842.205-3842.245"
-  wire $not$ls180.v:3842$310_Y
-  attribute \src "ls180.v:3842.251-3842.290"
-  wire $not$ls180.v:3842$312_Y
-  attribute \src "ls180.v:3842.159-3842.292"
-  wire $not$ls180.v:3842$314_Y
-  attribute \src "ls180.v:3843.205-3843.245"
-  wire $not$ls180.v:3843$323_Y
-  attribute \src "ls180.v:3843.251-3843.290"
-  wire $not$ls180.v:3843$325_Y
-  attribute \src "ls180.v:3843.159-3843.292"
-  wire $not$ls180.v:3843$327_Y
-  attribute \src "ls180.v:3844.205-3844.245"
-  wire $not$ls180.v:3844$336_Y
-  attribute \src "ls180.v:3844.251-3844.290"
-  wire $not$ls180.v:3844$338_Y
-  attribute \src "ls180.v:3844.159-3844.292"
-  wire $not$ls180.v:3844$340_Y
-  attribute \src "ls180.v:3907.71-3907.103"
-  wire $not$ls180.v:3907$379_Y
-  attribute \src "ls180.v:3928.112-3928.150"
-  wire $not$ls180.v:3928$382_Y
-  attribute \src "ls180.v:3928.156-3928.193"
-  wire $not$ls180.v:3928$384_Y
-  attribute \src "ls180.v:3928.68-3928.195"
-  wire $not$ls180.v:3928$386_Y
-  attribute \src "ls180.v:3936.11-3936.38"
-  wire $not$ls180.v:3936$389_Y
-  attribute \src "ls180.v:3966.112-3966.150"
-  wire $not$ls180.v:3966$391_Y
-  attribute \src "ls180.v:3966.156-3966.193"
-  wire $not$ls180.v:3966$393_Y
-  attribute \src "ls180.v:3966.68-3966.195"
-  wire $not$ls180.v:3966$395_Y
-  attribute \src "ls180.v:3974.11-3974.37"
-  wire $not$ls180.v:3974$398_Y
-  attribute \src "ls180.v:3984.87-3984.331"
-  wire $not$ls180.v:3984$410_Y
-  attribute \src "ls180.v:3985.35-3985.68"
-  wire $not$ls180.v:3985$413_Y
-  attribute \src "ls180.v:3985.73-3985.105"
-  wire $not$ls180.v:3985$414_Y
-  attribute \src "ls180.v:3989.87-3989.331"
-  wire $not$ls180.v:3989$426_Y
-  attribute \src "ls180.v:3990.35-3990.68"
-  wire $not$ls180.v:3990$429_Y
-  attribute \src "ls180.v:3990.73-3990.105"
-  wire $not$ls180.v:3990$430_Y
-  attribute \src "ls180.v:3994.87-3994.331"
-  wire $not$ls180.v:3994$442_Y
-  attribute \src "ls180.v:3995.35-3995.68"
-  wire $not$ls180.v:3995$445_Y
-  attribute \src "ls180.v:3995.73-3995.105"
-  wire $not$ls180.v:3995$446_Y
-  attribute \src "ls180.v:3999.87-3999.331"
-  wire $not$ls180.v:3999$458_Y
-  attribute \src "ls180.v:4000.35-4000.68"
-  wire $not$ls180.v:4000$461_Y
-  attribute \src "ls180.v:4000.73-4000.105"
-  wire $not$ls180.v:4000$462_Y
-  attribute \src "ls180.v:4004.128-4004.372"
-  wire $not$ls180.v:4004$475_Y
-  attribute \src "ls180.v:4004.502-4004.746"
-  wire $not$ls180.v:4004$491_Y
-  attribute \src "ls180.v:4004.876-4004.1120"
-  wire $not$ls180.v:4004$507_Y
-  attribute \src "ls180.v:4004.1250-4004.1494"
-  wire $not$ls180.v:4004$523_Y
-  attribute \src "ls180.v:4026.32-4026.50"
-  wire $not$ls180.v:4026$529_Y
-  attribute \src "ls180.v:4065.30-4065.50"
-  wire $not$ls180.v:4065$534_Y
-  attribute \src "ls180.v:4066.30-4066.50"
-  wire $not$ls180.v:4066$535_Y
-  attribute \src "ls180.v:4091.27-4091.48"
-  wire $not$ls180.v:4091$541_Y
-  attribute \src "ls180.v:4092.30-4092.50"
-  wire $not$ls180.v:4092$542_Y
-  attribute \src "ls180.v:4093.80-4093.98"
-  wire $not$ls180.v:4093$544_Y
-  attribute \src "ls180.v:4094.107-4094.127"
-  wire $not$ls180.v:4094$548_Y
-  attribute \src "ls180.v:4095.78-4095.103"
-  wire $not$ls180.v:4095$551_Y
-  attribute \src "ls180.v:4096.91-4096.111"
-  wire $not$ls180.v:4096$554_Y
-  attribute \src "ls180.v:4112.35-4112.64"
-  wire $not$ls180.v:4112$563_Y
-  attribute \src "ls180.v:4113.36-4113.67"
-  wire $not$ls180.v:4113$564_Y
-  attribute \src "ls180.v:4119.32-4119.61"
-  wire $not$ls180.v:4119$565_Y
-  attribute \src "ls180.v:4125.36-4125.67"
-  wire $not$ls180.v:4125$566_Y
-  attribute \src "ls180.v:4126.35-4126.64"
-  wire $not$ls180.v:4126$567_Y
-  attribute \src "ls180.v:4129.32-4129.63"
-  wire $not$ls180.v:4129$570_Y
-  attribute \src "ls180.v:4167.81-4167.108"
-  wire $not$ls180.v:4167$580_Y
-  attribute \src "ls180.v:4197.81-4197.108"
-  wire $not$ls180.v:4197$591_Y
-  attribute \src "ls180.v:4397.60-4397.85"
-  wire $not$ls180.v:4397$640_Y
-  attribute \src "ls180.v:4538.54-4538.96"
-  wire $not$ls180.v:4538$654_Y
-  attribute \src "ls180.v:4541.48-4541.86"
-  wire $not$ls180.v:4541$657_Y
-  attribute \src "ls180.v:4665.55-4665.98"
-  wire $not$ls180.v:4665$675_Y
-  attribute \src "ls180.v:4668.49-4668.88"
-  wire $not$ls180.v:4668$678_Y
-  attribute \src "ls180.v:4718.30-4718.58"
-  wire $not$ls180.v:4718$684_Y
-  attribute \src "ls180.v:4799.56-4799.100"
-  wire $not$ls180.v:4799$690_Y
-  attribute \src "ls180.v:4802.50-4802.90"
-  wire $not$ls180.v:4802$693_Y
-  attribute \src "ls180.v:4918.42-4918.74"
-  wire $not$ls180.v:4918$709_Y
-  attribute \src "ls180.v:5442.50-5442.88"
-  wire $not$ls180.v:5442$994_Y
-  attribute \src "ls180.v:5454.52-5454.102"
-  wire $not$ls180.v:5454$997_Y
-  attribute \src "ls180.v:5513.38-5513.74"
-  wire $not$ls180.v:5513$1004_Y
-  attribute \src "ls180.v:5755.69-5755.88"
-  wire $not$ls180.v:5755$1065_Y
-  attribute \src "ls180.v:5772.63-5772.94"
-  wire $not$ls180.v:5772$1086_Y
-  attribute \src "ls180.v:5775.65-5775.96"
-  wire $not$ls180.v:5775$1093_Y
-  attribute \src "ls180.v:5778.65-5778.96"
-  wire $not$ls180.v:5778$1100_Y
-  attribute \src "ls180.v:5781.65-5781.96"
-  wire $not$ls180.v:5781$1107_Y
-  attribute \src "ls180.v:5784.65-5784.96"
-  wire $not$ls180.v:5784$1114_Y
-  attribute \src "ls180.v:5787.68-5787.99"
-  wire $not$ls180.v:5787$1121_Y
-  attribute \src "ls180.v:5790.68-5790.99"
-  wire $not$ls180.v:5790$1128_Y
-  attribute \src "ls180.v:5793.68-5793.99"
-  wire $not$ls180.v:5793$1135_Y
-  attribute \src "ls180.v:5796.68-5796.99"
-  wire $not$ls180.v:5796$1142_Y
-  attribute \src "ls180.v:5810.60-5810.91"
-  wire $not$ls180.v:5810$1150_Y
-  attribute \src "ls180.v:5813.60-5813.91"
-  wire $not$ls180.v:5813$1157_Y
-  attribute \src "ls180.v:5816.60-5816.91"
-  wire $not$ls180.v:5816$1164_Y
-  attribute \src "ls180.v:5819.60-5819.91"
-  wire $not$ls180.v:5819$1171_Y
-  attribute \src "ls180.v:5822.61-5822.92"
-  wire $not$ls180.v:5822$1178_Y
-  attribute \src "ls180.v:5825.61-5825.92"
-  wire $not$ls180.v:5825$1185_Y
-  attribute \src "ls180.v:5836.59-5836.90"
-  wire $not$ls180.v:5836$1193_Y
-  attribute \src "ls180.v:5839.58-5839.89"
-  wire $not$ls180.v:5839$1200_Y
-  attribute \src "ls180.v:5850.64-5850.95"
-  wire $not$ls180.v:5850$1208_Y
-  attribute \src "ls180.v:5853.63-5853.94"
-  wire $not$ls180.v:5853$1215_Y
-  attribute \src "ls180.v:5856.63-5856.94"
-  wire $not$ls180.v:5856$1222_Y
-  attribute \src "ls180.v:5859.63-5859.94"
-  wire $not$ls180.v:5859$1229_Y
-  attribute \src "ls180.v:5862.63-5862.94"
-  wire $not$ls180.v:5862$1236_Y
-  attribute \src "ls180.v:5865.64-5865.95"
-  wire $not$ls180.v:5865$1243_Y
-  attribute \src "ls180.v:5868.64-5868.95"
-  wire $not$ls180.v:5868$1250_Y
-  attribute \src "ls180.v:5871.64-5871.95"
-  wire $not$ls180.v:5871$1257_Y
-  attribute \src "ls180.v:5874.64-5874.95"
-  wire $not$ls180.v:5874$1264_Y
-  attribute \src "ls180.v:5887.64-5887.95"
-  wire $not$ls180.v:5887$1272_Y
-  attribute \src "ls180.v:5890.63-5890.94"
-  wire $not$ls180.v:5890$1279_Y
-  attribute \src "ls180.v:5893.63-5893.94"
-  wire $not$ls180.v:5893$1286_Y
-  attribute \src "ls180.v:5896.63-5896.94"
-  wire $not$ls180.v:5896$1293_Y
-  attribute \src "ls180.v:5899.63-5899.94"
-  wire $not$ls180.v:5899$1300_Y
-  attribute \src "ls180.v:5902.64-5902.95"
-  wire $not$ls180.v:5902$1307_Y
-  attribute \src "ls180.v:5905.64-5905.95"
-  wire $not$ls180.v:5905$1314_Y
-  attribute \src "ls180.v:5908.64-5908.95"
-  wire $not$ls180.v:5908$1321_Y
-  attribute \src "ls180.v:5911.64-5911.95"
-  wire $not$ls180.v:5911$1328_Y
-  attribute \src "ls180.v:5924.66-5924.97"
-  wire $not$ls180.v:5924$1336_Y
-  attribute \src "ls180.v:5927.66-5927.97"
-  wire $not$ls180.v:5927$1343_Y
-  attribute \src "ls180.v:5930.66-5930.97"
-  wire $not$ls180.v:5930$1350_Y
-  attribute \src "ls180.v:5933.66-5933.97"
-  wire $not$ls180.v:5933$1357_Y
-  attribute \src "ls180.v:5936.66-5936.97"
-  wire $not$ls180.v:5936$1364_Y
-  attribute \src "ls180.v:5939.66-5939.97"
-  wire $not$ls180.v:5939$1371_Y
-  attribute \src "ls180.v:5942.66-5942.97"
-  wire $not$ls180.v:5942$1378_Y
-  attribute \src "ls180.v:5945.66-5945.97"
-  wire $not$ls180.v:5945$1385_Y
-  attribute \src "ls180.v:5948.68-5948.99"
-  wire $not$ls180.v:5948$1392_Y
-  attribute \src "ls180.v:5951.68-5951.99"
-  wire $not$ls180.v:5951$1399_Y
-  attribute \src "ls180.v:5954.68-5954.99"
-  wire $not$ls180.v:5954$1406_Y
-  attribute \src "ls180.v:5957.68-5957.99"
-  wire $not$ls180.v:5957$1413_Y
-  attribute \src "ls180.v:5960.68-5960.99"
-  wire $not$ls180.v:5960$1420_Y
-  attribute \src "ls180.v:5963.65-5963.96"
-  wire $not$ls180.v:5963$1427_Y
-  attribute \src "ls180.v:5966.66-5966.97"
-  wire $not$ls180.v:5966$1434_Y
-  attribute \src "ls180.v:5986.70-5986.101"
-  wire $not$ls180.v:5986$1442_Y
-  attribute \src "ls180.v:5989.70-5989.101"
-  wire $not$ls180.v:5989$1449_Y
-  attribute \src "ls180.v:5992.70-5992.101"
-  wire $not$ls180.v:5992$1456_Y
-  attribute \src "ls180.v:5995.70-5995.101"
-  wire $not$ls180.v:5995$1463_Y
-  attribute \src "ls180.v:5998.69-5998.100"
-  wire $not$ls180.v:5998$1470_Y
-  attribute \src "ls180.v:6001.69-6001.100"
-  wire $not$ls180.v:6001$1477_Y
-  attribute \src "ls180.v:6004.69-6004.100"
-  wire $not$ls180.v:6004$1484_Y
-  attribute \src "ls180.v:6007.69-6007.100"
-  wire $not$ls180.v:6007$1491_Y
-  attribute \src "ls180.v:6010.60-6010.91"
-  wire $not$ls180.v:6010$1498_Y
-  attribute \src "ls180.v:6013.71-6013.102"
-  wire $not$ls180.v:6013$1505_Y
-  attribute \src "ls180.v:6016.71-6016.102"
-  wire $not$ls180.v:6016$1512_Y
-  attribute \src "ls180.v:6019.71-6019.102"
-  wire $not$ls180.v:6019$1519_Y
-  attribute \src "ls180.v:6022.71-6022.102"
-  wire $not$ls180.v:6022$1526_Y
-  attribute \src "ls180.v:6025.71-6025.102"
-  wire $not$ls180.v:6025$1533_Y
-  attribute \src "ls180.v:6028.71-6028.102"
-  wire $not$ls180.v:6028$1540_Y
-  attribute \src "ls180.v:6031.70-6031.101"
-  wire $not$ls180.v:6031$1547_Y
-  attribute \src "ls180.v:6034.70-6034.101"
-  wire $not$ls180.v:6034$1554_Y
-  attribute \src "ls180.v:6037.70-6037.101"
-  wire $not$ls180.v:6037$1561_Y
-  attribute \src "ls180.v:6040.70-6040.101"
-  wire $not$ls180.v:6040$1568_Y
-  attribute \src "ls180.v:6043.70-6043.101"
-  wire $not$ls180.v:6043$1575_Y
-  attribute \src "ls180.v:6046.70-6046.101"
-  wire $not$ls180.v:6046$1582_Y
-  attribute \src "ls180.v:6049.70-6049.101"
-  wire $not$ls180.v:6049$1589_Y
-  attribute \src "ls180.v:6052.70-6052.101"
-  wire $not$ls180.v:6052$1596_Y
-  attribute \src "ls180.v:6055.70-6055.101"
-  wire $not$ls180.v:6055$1603_Y
-  attribute \src "ls180.v:6058.70-6058.101"
-  wire $not$ls180.v:6058$1610_Y
-  attribute \src "ls180.v:6061.66-6061.97"
-  wire $not$ls180.v:6061$1617_Y
-  attribute \src "ls180.v:6064.67-6064.98"
-  wire $not$ls180.v:6064$1624_Y
-  attribute \src "ls180.v:6067.70-6067.101"
-  wire $not$ls180.v:6067$1631_Y
-  attribute \src "ls180.v:6070.70-6070.101"
-  wire $not$ls180.v:6070$1638_Y
-  attribute \src "ls180.v:6073.69-6073.100"
-  wire $not$ls180.v:6073$1645_Y
-  attribute \src "ls180.v:6076.69-6076.100"
-  wire $not$ls180.v:6076$1652_Y
-  attribute \src "ls180.v:6079.69-6079.100"
-  wire $not$ls180.v:6079$1659_Y
-  attribute \src "ls180.v:6082.69-6082.100"
-  wire $not$ls180.v:6082$1666_Y
-  attribute \src "ls180.v:6121.66-6121.97"
-  wire $not$ls180.v:6121$1674_Y
-  attribute \src "ls180.v:6124.66-6124.97"
-  wire $not$ls180.v:6124$1681_Y
-  attribute \src "ls180.v:6127.66-6127.97"
-  wire $not$ls180.v:6127$1688_Y
-  attribute \src "ls180.v:6130.66-6130.97"
-  wire $not$ls180.v:6130$1695_Y
-  attribute \src "ls180.v:6133.66-6133.97"
-  wire $not$ls180.v:6133$1702_Y
-  attribute \src "ls180.v:6136.66-6136.97"
-  wire $not$ls180.v:6136$1709_Y
-  attribute \src "ls180.v:6139.66-6139.97"
-  wire $not$ls180.v:6139$1716_Y
-  attribute \src "ls180.v:6142.66-6142.97"
-  wire $not$ls180.v:6142$1723_Y
-  attribute \src "ls180.v:6145.68-6145.99"
-  wire $not$ls180.v:6145$1730_Y
-  attribute \src "ls180.v:6148.68-6148.99"
-  wire $not$ls180.v:6148$1737_Y
-  attribute \src "ls180.v:6151.68-6151.99"
-  wire $not$ls180.v:6151$1744_Y
-  attribute \src "ls180.v:6154.68-6154.99"
-  wire $not$ls180.v:6154$1751_Y
-  attribute \src "ls180.v:6157.68-6157.99"
-  wire $not$ls180.v:6157$1758_Y
-  attribute \src "ls180.v:6160.65-6160.96"
-  wire $not$ls180.v:6160$1765_Y
+  wire width 10 $memwr$\storage_5$ls180.v:10316$22_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 10 $memwr$\storage_5$ls180.v:10316$22_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 5 $memwr$\storage_6$ls180.v:10332$23_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 10 $memwr$\storage_6$ls180.v:10332$23_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 10 $memwr$\storage_6$ls180.v:10332$23_EN
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 5 $memwr$\storage_7$ls180.v:10346$24_ADDR
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 10 $memwr$\storage_7$ls180.v:10346$24_DATA
+  attribute \src "ls180.v:0.0-0.0"
+  wire width 10 $memwr$\storage_7$ls180.v:10346$24_EN
+  attribute \src "ls180.v:3010.41-3010.71"
+  wire $ne$ls180.v:3010$72_Y
+  attribute \src "ls180.v:3201.70-3201.104"
+  wire $ne$ls180.v:3201$125_Y
+  attribute \src "ls180.v:3262.8-3262.142"
+  wire $ne$ls180.v:3262$144_Y
+  attribute \src "ls180.v:3294.75-3294.133"
+  wire $ne$ls180.v:3294$151_Y
+  attribute \src "ls180.v:3295.75-3295.133"
+  wire $ne$ls180.v:3295$152_Y
+  attribute \src "ls180.v:3419.8-3419.142"
+  wire $ne$ls180.v:3419$174_Y
+  attribute \src "ls180.v:3451.75-3451.133"
+  wire $ne$ls180.v:3451$181_Y
+  attribute \src "ls180.v:3452.75-3452.133"
+  wire $ne$ls180.v:3452$182_Y
+  attribute \src "ls180.v:3576.8-3576.142"
+  wire $ne$ls180.v:3576$204_Y
+  attribute \src "ls180.v:3608.75-3608.133"
+  wire $ne$ls180.v:3608$211_Y
+  attribute \src "ls180.v:3609.75-3609.133"
+  wire $ne$ls180.v:3609$212_Y
+  attribute \src "ls180.v:3733.8-3733.142"
+  wire $ne$ls180.v:3733$234_Y
+  attribute \src "ls180.v:3765.75-3765.133"
+  wire $ne$ls180.v:3765$241_Y
+  attribute \src "ls180.v:3766.75-3766.133"
+  wire $ne$ls180.v:3766$242_Y
+  attribute \src "ls180.v:4258.47-4258.80"
+  wire $ne$ls180.v:4258$640_Y
+  attribute \src "ls180.v:4259.47-4259.79"
+  wire $ne$ls180.v:4259$641_Y
+  attribute \src "ls180.v:4288.47-4288.80"
+  wire $ne$ls180.v:4288$651_Y
+  attribute \src "ls180.v:4289.47-4289.79"
+  wire $ne$ls180.v:4289$652_Y
+  attribute \src "ls180.v:4758.32-4758.89"
+  wire $ne$ls180.v:4758$732_Y
+  attribute \src "ls180.v:5405.10-5405.56"
+  wire $ne$ls180.v:5405$1029_Y
+  attribute \src "ls180.v:5510.51-5510.87"
+  wire $ne$ls180.v:5510$1043_Y
+  attribute \src "ls180.v:5511.51-5511.86"
+  wire $ne$ls180.v:5511$1044_Y
+  attribute \src "ls180.v:5718.51-5718.87"
+  wire $ne$ls180.v:5718$1074_Y
+  attribute \src "ls180.v:5719.51-5719.86"
+  wire $ne$ls180.v:5719$1075_Y
+  attribute \src "ls180.v:5750.79-5750.119"
+  wire $ne$ls180.v:5750$1078_Y
+  attribute \src "ls180.v:7587.7-7587.52"
+  wire $ne$ls180.v:7587$2471_Y
+  attribute \src "ls180.v:7649.9-7649.43"
+  wire $ne$ls180.v:7649$2494_Y
+  attribute \src "ls180.v:7685.8-7685.44"
+  wire $ne$ls180.v:7685$2501_Y
+  attribute \src "ls180.v:8623.9-8623.47"
+  wire $ne$ls180.v:8623$2716_Y
+  attribute \src "ls180.v:2818.45-2818.80"
+  wire $not$ls180.v:2818$26_Y
+  attribute \src "ls180.v:2857.61-2857.94"
+  wire $not$ls180.v:2857$31_Y
+  attribute \src "ls180.v:2858.61-2858.94"
+  wire $not$ls180.v:2858$32_Y
+  attribute \src "ls180.v:2878.45-2878.80"
+  wire $not$ls180.v:2878$37_Y
+  attribute \src "ls180.v:2917.61-2917.94"
+  wire $not$ls180.v:2917$42_Y
+  attribute \src "ls180.v:2918.61-2918.94"
+  wire $not$ls180.v:2918$43_Y
+  attribute \src "ls180.v:2938.45-2938.83"
+  wire $not$ls180.v:2938$48_Y
+  attribute \src "ls180.v:2977.61-2977.94"
+  wire $not$ls180.v:2977$53_Y
+  attribute \src "ls180.v:2978.61-2978.94"
+  wire $not$ls180.v:2978$54_Y
+  attribute \src "ls180.v:3150.34-3150.64"
+  wire $not$ls180.v:3150$117_Y
+  attribute \src "ls180.v:3151.31-3151.61"
+  wire $not$ls180.v:3151$118_Y
+  attribute \src "ls180.v:3152.32-3152.62"
+  wire $not$ls180.v:3152$119_Y
+  attribute \src "ls180.v:3153.32-3153.62"
+  wire $not$ls180.v:3153$120_Y
+  attribute \src "ls180.v:3195.33-3195.56"
+  wire $not$ls180.v:3195$123_Y
+  attribute \src "ls180.v:3296.58-3296.106"
+  wire $not$ls180.v:3296$153_Y
+  attribute \src "ls180.v:3350.9-3350.45"
+  wire $not$ls180.v:3350$158_Y
+  attribute \src "ls180.v:3453.58-3453.106"
+  wire $not$ls180.v:3453$183_Y
+  attribute \src "ls180.v:3507.9-3507.45"
+  wire $not$ls180.v:3507$188_Y
+  attribute \src "ls180.v:3610.58-3610.106"
+  wire $not$ls180.v:3610$213_Y
+  attribute \src "ls180.v:3664.9-3664.45"
+  wire $not$ls180.v:3664$218_Y
+  attribute \src "ls180.v:3767.58-3767.106"
+  wire $not$ls180.v:3767$243_Y
+  attribute \src "ls180.v:3821.9-3821.45"
+  wire $not$ls180.v:3821$248_Y
+  attribute \src "ls180.v:3863.149-3863.187"
+  wire $not$ls180.v:3863$251_Y
+  attribute \src "ls180.v:3863.193-3863.230"
+  wire $not$ls180.v:3863$253_Y
+  attribute \src "ls180.v:3864.149-3864.187"
+  wire $not$ls180.v:3864$257_Y
+  attribute \src "ls180.v:3864.193-3864.230"
+  wire $not$ls180.v:3864$259_Y
+  attribute \src "ls180.v:3880.43-3880.73"
+  wire width 2 $not$ls180.v:3880$287_Y
+  attribute \src "ls180.v:3883.205-3883.245"
+  wire $not$ls180.v:3883$290_Y
+  attribute \src "ls180.v:3883.251-3883.290"
+  wire $not$ls180.v:3883$292_Y
+  attribute \src "ls180.v:3883.159-3883.292"
+  wire $not$ls180.v:3883$294_Y
+  attribute \src "ls180.v:3884.205-3884.245"
+  wire $not$ls180.v:3884$303_Y
+  attribute \src "ls180.v:3884.251-3884.290"
+  wire $not$ls180.v:3884$305_Y
+  attribute \src "ls180.v:3884.159-3884.292"
+  wire $not$ls180.v:3884$307_Y
+  attribute \src "ls180.v:3885.205-3885.245"
+  wire $not$ls180.v:3885$316_Y
+  attribute \src "ls180.v:3885.251-3885.290"
+  wire $not$ls180.v:3885$318_Y
+  attribute \src "ls180.v:3885.159-3885.292"
+  wire $not$ls180.v:3885$320_Y
+  attribute \src "ls180.v:3886.205-3886.245"
+  wire $not$ls180.v:3886$329_Y
+  attribute \src "ls180.v:3886.251-3886.290"
+  wire $not$ls180.v:3886$331_Y
+  attribute \src "ls180.v:3886.159-3886.292"
+  wire $not$ls180.v:3886$333_Y
+  attribute \src "ls180.v:3913.71-3913.103"
+  wire $not$ls180.v:3913$344_Y
+  attribute \src "ls180.v:3916.205-3916.245"
+  wire $not$ls180.v:3916$348_Y
+  attribute \src "ls180.v:3916.251-3916.290"
+  wire $not$ls180.v:3916$350_Y
+  attribute \src "ls180.v:3916.159-3916.292"
+  wire $not$ls180.v:3916$352_Y
+  attribute \src "ls180.v:3917.205-3917.245"
+  wire $not$ls180.v:3917$361_Y
+  attribute \src "ls180.v:3917.251-3917.290"
+  wire $not$ls180.v:3917$363_Y
+  attribute \src "ls180.v:3917.159-3917.292"
+  wire $not$ls180.v:3917$365_Y
+  attribute \src "ls180.v:3918.205-3918.245"
+  wire $not$ls180.v:3918$374_Y
+  attribute \src "ls180.v:3918.251-3918.290"
+  wire $not$ls180.v:3918$376_Y
+  attribute \src "ls180.v:3918.159-3918.292"
+  wire $not$ls180.v:3918$378_Y
+  attribute \src "ls180.v:3919.205-3919.245"
+  wire $not$ls180.v:3919$387_Y
+  attribute \src "ls180.v:3919.251-3919.290"
+  wire $not$ls180.v:3919$389_Y
+  attribute \src "ls180.v:3919.159-3919.292"
+  wire $not$ls180.v:3919$391_Y
+  attribute \src "ls180.v:3982.71-3982.103"
+  wire $not$ls180.v:3982$430_Y
+  attribute \src "ls180.v:4003.112-4003.150"
+  wire $not$ls180.v:4003$433_Y
+  attribute \src "ls180.v:4003.156-4003.193"
+  wire $not$ls180.v:4003$435_Y
+  attribute \src "ls180.v:4003.68-4003.195"
+  wire $not$ls180.v:4003$437_Y
+  attribute \src "ls180.v:4011.11-4011.38"
+  wire $not$ls180.v:4011$440_Y
+  attribute \src "ls180.v:4041.112-4041.150"
+  wire $not$ls180.v:4041$442_Y
+  attribute \src "ls180.v:4041.156-4041.193"
+  wire $not$ls180.v:4041$444_Y
+  attribute \src "ls180.v:4041.68-4041.195"
+  wire $not$ls180.v:4041$446_Y
+  attribute \src "ls180.v:4049.11-4049.37"
+  wire $not$ls180.v:4049$449_Y
+  attribute \src "ls180.v:4059.87-4059.331"
+  wire $not$ls180.v:4059$461_Y
+  attribute \src "ls180.v:4060.35-4060.68"
+  wire $not$ls180.v:4060$464_Y
+  attribute \src "ls180.v:4060.73-4060.105"
+  wire $not$ls180.v:4060$465_Y
+  attribute \src "ls180.v:4064.87-4064.331"
+  wire $not$ls180.v:4064$477_Y
+  attribute \src "ls180.v:4065.35-4065.68"
+  wire $not$ls180.v:4065$480_Y
+  attribute \src "ls180.v:4065.73-4065.105"
+  wire $not$ls180.v:4065$481_Y
+  attribute \src "ls180.v:4069.87-4069.331"
+  wire $not$ls180.v:4069$493_Y
+  attribute \src "ls180.v:4070.35-4070.68"
+  wire $not$ls180.v:4070$496_Y
+  attribute \src "ls180.v:4070.73-4070.105"
+  wire $not$ls180.v:4070$497_Y
+  attribute \src "ls180.v:4074.87-4074.331"
+  wire $not$ls180.v:4074$509_Y
+  attribute \src "ls180.v:4075.35-4075.68"
+  wire $not$ls180.v:4075$512_Y
+  attribute \src "ls180.v:4075.73-4075.105"
+  wire $not$ls180.v:4075$513_Y
+  attribute \src "ls180.v:4079.128-4079.372"
+  wire $not$ls180.v:4079$526_Y
+  attribute \src "ls180.v:4079.502-4079.746"
+  wire $not$ls180.v:4079$542_Y
+  attribute \src "ls180.v:4079.876-4079.1120"
+  wire $not$ls180.v:4079$558_Y
+  attribute \src "ls180.v:4079.1250-4079.1494"
+  wire $not$ls180.v:4079$574_Y
+  attribute \src "ls180.v:4101.32-4101.50"
+  wire $not$ls180.v:4101$580_Y
+  attribute \src "ls180.v:4140.30-4140.50"
+  wire $not$ls180.v:4140$585_Y
+  attribute \src "ls180.v:4141.30-4141.50"
+  wire $not$ls180.v:4141$586_Y
+  attribute \src "ls180.v:4166.27-4166.48"
+  wire $not$ls180.v:4166$592_Y
+  attribute \src "ls180.v:4167.30-4167.50"
+  wire $not$ls180.v:4167$593_Y
+  attribute \src "ls180.v:4168.80-4168.98"
+  wire $not$ls180.v:4168$595_Y
+  attribute \src "ls180.v:4169.107-4169.127"
+  wire $not$ls180.v:4169$599_Y
+  attribute \src "ls180.v:4170.78-4170.103"
+  wire $not$ls180.v:4170$602_Y
+  attribute \src "ls180.v:4171.91-4171.111"
+  wire $not$ls180.v:4171$605_Y
+  attribute \src "ls180.v:4187.35-4187.64"
+  wire $not$ls180.v:4187$614_Y
+  attribute \src "ls180.v:4188.36-4188.67"
+  wire $not$ls180.v:4188$615_Y
+  attribute \src "ls180.v:4194.32-4194.61"
+  wire $not$ls180.v:4194$616_Y
+  attribute \src "ls180.v:4200.36-4200.67"
+  wire $not$ls180.v:4200$617_Y
+  attribute \src "ls180.v:4201.35-4201.64"
+  wire $not$ls180.v:4201$618_Y
+  attribute \src "ls180.v:4204.32-4204.63"
+  wire $not$ls180.v:4204$621_Y
+  attribute \src "ls180.v:4242.81-4242.108"
+  wire $not$ls180.v:4242$631_Y
+  attribute \src "ls180.v:4272.81-4272.108"
+  wire $not$ls180.v:4272$642_Y
+  attribute \src "ls180.v:4472.60-4472.85"
+  wire $not$ls180.v:4472$691_Y
+  attribute \src "ls180.v:4613.54-4613.96"
+  wire $not$ls180.v:4613$705_Y
+  attribute \src "ls180.v:4616.48-4616.86"
+  wire $not$ls180.v:4616$708_Y
+  attribute \src "ls180.v:4740.55-4740.98"
+  wire $not$ls180.v:4740$726_Y
+  attribute \src "ls180.v:4743.49-4743.88"
+  wire $not$ls180.v:4743$729_Y
+  attribute \src "ls180.v:4793.30-4793.58"
+  wire $not$ls180.v:4793$735_Y
+  attribute \src "ls180.v:4874.56-4874.100"
+  wire $not$ls180.v:4874$741_Y
+  attribute \src "ls180.v:4877.50-4877.90"
+  wire $not$ls180.v:4877$744_Y
+  attribute \src "ls180.v:4993.42-4993.74"
+  wire $not$ls180.v:4993$760_Y
+  attribute \src "ls180.v:5517.50-5517.88"
+  wire $not$ls180.v:5517$1045_Y
+  attribute \src "ls180.v:5529.52-5529.102"
+  wire $not$ls180.v:5529$1048_Y
+  attribute \src "ls180.v:5588.38-5588.74"
+  wire $not$ls180.v:5588$1055_Y
+  attribute \src "ls180.v:5857.69-5857.88"
+  wire $not$ls180.v:5857$1125_Y
+  attribute \src "ls180.v:5874.63-5874.94"
+  wire $not$ls180.v:5874$1155_Y
+  attribute \src "ls180.v:5877.65-5877.96"
+  wire $not$ls180.v:5877$1162_Y
+  attribute \src "ls180.v:5880.65-5880.96"
+  wire $not$ls180.v:5880$1169_Y
+  attribute \src "ls180.v:5883.65-5883.96"
+  wire $not$ls180.v:5883$1176_Y
+  attribute \src "ls180.v:5886.65-5886.96"
+  wire $not$ls180.v:5886$1183_Y
+  attribute \src "ls180.v:5889.68-5889.99"
+  wire $not$ls180.v:5889$1190_Y
+  attribute \src "ls180.v:5892.68-5892.99"
+  wire $not$ls180.v:5892$1197_Y
+  attribute \src "ls180.v:5895.68-5895.99"
+  wire $not$ls180.v:5895$1204_Y
+  attribute \src "ls180.v:5898.68-5898.99"
+  wire $not$ls180.v:5898$1211_Y
+  attribute \src "ls180.v:5912.60-5912.91"
+  wire $not$ls180.v:5912$1219_Y
+  attribute \src "ls180.v:5915.60-5915.91"
+  wire $not$ls180.v:5915$1226_Y
+  attribute \src "ls180.v:5918.60-5918.91"
+  wire $not$ls180.v:5918$1233_Y
+  attribute \src "ls180.v:5921.60-5921.91"
+  wire $not$ls180.v:5921$1240_Y
+  attribute \src "ls180.v:5924.61-5924.92"
+  wire $not$ls180.v:5924$1247_Y
+  attribute \src "ls180.v:5927.61-5927.92"
+  wire $not$ls180.v:5927$1254_Y
+  attribute \src "ls180.v:5938.59-5938.90"
+  wire $not$ls180.v:5938$1262_Y
+  attribute \src "ls180.v:5941.58-5941.89"
+  wire $not$ls180.v:5941$1269_Y
+  attribute \src "ls180.v:5952.64-5952.95"
+  wire $not$ls180.v:5952$1277_Y
+  attribute \src "ls180.v:5955.63-5955.94"
+  wire $not$ls180.v:5955$1284_Y
+  attribute \src "ls180.v:5958.63-5958.94"
+  wire $not$ls180.v:5958$1291_Y
+  attribute \src "ls180.v:5961.63-5961.94"
+  wire $not$ls180.v:5961$1298_Y
+  attribute \src "ls180.v:5964.63-5964.94"
+  wire $not$ls180.v:5964$1305_Y
+  attribute \src "ls180.v:5967.64-5967.95"
+  wire $not$ls180.v:5967$1312_Y
+  attribute \src "ls180.v:5970.64-5970.95"
+  wire $not$ls180.v:5970$1319_Y
+  attribute \src "ls180.v:5973.64-5973.95"
+  wire $not$ls180.v:5973$1326_Y
+  attribute \src "ls180.v:5976.64-5976.95"
+  wire $not$ls180.v:5976$1333_Y
+  attribute \src "ls180.v:5989.64-5989.95"
+  wire $not$ls180.v:5989$1341_Y
+  attribute \src "ls180.v:5992.63-5992.94"
+  wire $not$ls180.v:5992$1348_Y
+  attribute \src "ls180.v:5995.63-5995.94"
+  wire $not$ls180.v:5995$1355_Y
+  attribute \src "ls180.v:5998.63-5998.94"
+  wire $not$ls180.v:5998$1362_Y
+  attribute \src "ls180.v:6001.63-6001.94"
+  wire $not$ls180.v:6001$1369_Y
+  attribute \src "ls180.v:6004.64-6004.95"
+  wire $not$ls180.v:6004$1376_Y
+  attribute \src "ls180.v:6007.64-6007.95"
+  wire $not$ls180.v:6007$1383_Y
+  attribute \src "ls180.v:6010.64-6010.95"
+  wire $not$ls180.v:6010$1390_Y
+  attribute \src "ls180.v:6013.64-6013.95"
+  wire $not$ls180.v:6013$1397_Y
+  attribute \src "ls180.v:6026.66-6026.97"
+  wire $not$ls180.v:6026$1405_Y
+  attribute \src "ls180.v:6029.66-6029.97"
+  wire $not$ls180.v:6029$1412_Y
+  attribute \src "ls180.v:6032.66-6032.97"
+  wire $not$ls180.v:6032$1419_Y
+  attribute \src "ls180.v:6035.66-6035.97"
+  wire $not$ls180.v:6035$1426_Y
+  attribute \src "ls180.v:6038.66-6038.97"
+  wire $not$ls180.v:6038$1433_Y
+  attribute \src "ls180.v:6041.66-6041.97"
+  wire $not$ls180.v:6041$1440_Y
+  attribute \src "ls180.v:6044.66-6044.97"
+  wire $not$ls180.v:6044$1447_Y
+  attribute \src "ls180.v:6047.66-6047.97"
+  wire $not$ls180.v:6047$1454_Y
+  attribute \src "ls180.v:6050.68-6050.99"
+  wire $not$ls180.v:6050$1461_Y
+  attribute \src "ls180.v:6053.68-6053.99"
+  wire $not$ls180.v:6053$1468_Y
+  attribute \src "ls180.v:6056.68-6056.99"
+  wire $not$ls180.v:6056$1475_Y
+  attribute \src "ls180.v:6059.68-6059.99"
+  wire $not$ls180.v:6059$1482_Y
+  attribute \src "ls180.v:6062.68-6062.99"
+  wire $not$ls180.v:6062$1489_Y
+  attribute \src "ls180.v:6065.65-6065.96"
+  wire $not$ls180.v:6065$1496_Y
+  attribute \src "ls180.v:6068.66-6068.97"
+  wire $not$ls180.v:6068$1503_Y
+  attribute \src "ls180.v:6088.70-6088.101"
+  wire $not$ls180.v:6088$1511_Y
+  attribute \src "ls180.v:6091.70-6091.101"
+  wire $not$ls180.v:6091$1518_Y
+  attribute \src "ls180.v:6094.70-6094.101"
+  wire $not$ls180.v:6094$1525_Y
+  attribute \src "ls180.v:6097.70-6097.101"
+  wire $not$ls180.v:6097$1532_Y
+  attribute \src "ls180.v:6100.69-6100.100"
+  wire $not$ls180.v:6100$1539_Y
+  attribute \src "ls180.v:6103.69-6103.100"
+  wire $not$ls180.v:6103$1546_Y
+  attribute \src "ls180.v:6106.69-6106.100"
+  wire $not$ls180.v:6106$1553_Y
+  attribute \src "ls180.v:6109.69-6109.100"
+  wire $not$ls180.v:6109$1560_Y
+  attribute \src "ls180.v:6112.60-6112.91"
+  wire $not$ls180.v:6112$1567_Y
+  attribute \src "ls180.v:6115.71-6115.102"
+  wire $not$ls180.v:6115$1574_Y
+  attribute \src "ls180.v:6118.71-6118.102"
+  wire $not$ls180.v:6118$1581_Y
+  attribute \src "ls180.v:6121.71-6121.102"
+  wire $not$ls180.v:6121$1588_Y
+  attribute \src "ls180.v:6124.71-6124.102"
+  wire $not$ls180.v:6124$1595_Y
+  attribute \src "ls180.v:6127.71-6127.102"
+  wire $not$ls180.v:6127$1602_Y
+  attribute \src "ls180.v:6130.71-6130.102"
+  wire $not$ls180.v:6130$1609_Y
+  attribute \src "ls180.v:6133.70-6133.101"
+  wire $not$ls180.v:6133$1616_Y
+  attribute \src "ls180.v:6136.70-6136.101"
+  wire $not$ls180.v:6136$1623_Y
+  attribute \src "ls180.v:6139.70-6139.101"
+  wire $not$ls180.v:6139$1630_Y
+  attribute \src "ls180.v:6142.70-6142.101"
+  wire $not$ls180.v:6142$1637_Y
+  attribute \src "ls180.v:6145.70-6145.101"
+  wire $not$ls180.v:6145$1644_Y
+  attribute \src "ls180.v:6148.70-6148.101"
+  wire $not$ls180.v:6148$1651_Y
+  attribute \src "ls180.v:6151.70-6151.101"
+  wire $not$ls180.v:6151$1658_Y
+  attribute \src "ls180.v:6154.70-6154.101"
+  wire $not$ls180.v:6154$1665_Y
+  attribute \src "ls180.v:6157.70-6157.101"
+  wire $not$ls180.v:6157$1672_Y
+  attribute \src "ls180.v:6160.70-6160.101"
+  wire $not$ls180.v:6160$1679_Y
   attribute \src "ls180.v:6163.66-6163.97"
-  wire $not$ls180.v:6163$1772_Y
-  attribute \src "ls180.v:6166.68-6166.99"
-  wire $not$ls180.v:6166$1779_Y
-  attribute \src "ls180.v:6169.68-6169.99"
-  wire $not$ls180.v:6169$1786_Y
-  attribute \src "ls180.v:6172.68-6172.99"
-  wire $not$ls180.v:6172$1793_Y
-  attribute \src "ls180.v:6175.68-6175.99"
-  wire $not$ls180.v:6175$1800_Y
-  attribute \src "ls180.v:6200.68-6200.99"
-  wire $not$ls180.v:6200$1808_Y
-  attribute \src "ls180.v:6203.73-6203.104"
-  wire $not$ls180.v:6203$1815_Y
-  attribute \src "ls180.v:6206.73-6206.104"
-  wire $not$ls180.v:6206$1822_Y
-  attribute \src "ls180.v:6209.66-6209.97"
-  wire $not$ls180.v:6209$1829_Y
-  attribute \src "ls180.v:6217.70-6217.101"
-  wire $not$ls180.v:6217$1837_Y
-  attribute \src "ls180.v:6220.74-6220.105"
-  wire $not$ls180.v:6220$1844_Y
-  attribute \src "ls180.v:6223.64-6223.95"
-  wire $not$ls180.v:6223$1851_Y
-  attribute \src "ls180.v:6226.74-6226.105"
-  wire $not$ls180.v:6226$1858_Y
-  attribute \src "ls180.v:6229.74-6229.105"
-  wire $not$ls180.v:6229$1865_Y
-  attribute \src "ls180.v:6232.75-6232.106"
-  wire $not$ls180.v:6232$1872_Y
-  attribute \src "ls180.v:6235.73-6235.104"
-  wire $not$ls180.v:6235$1879_Y
-  attribute \src "ls180.v:6238.73-6238.104"
-  wire $not$ls180.v:6238$1886_Y
-  attribute \src "ls180.v:6241.73-6241.104"
-  wire $not$ls180.v:6241$1893_Y
-  attribute \src "ls180.v:6244.73-6244.104"
-  wire $not$ls180.v:6244$1900_Y
-  attribute \src "ls180.v:6262.67-6262.99"
-  wire $not$ls180.v:6262$1908_Y
-  attribute \src "ls180.v:6265.67-6265.99"
-  wire $not$ls180.v:6265$1915_Y
-  attribute \src "ls180.v:6268.65-6268.97"
-  wire $not$ls180.v:6268$1922_Y
-  attribute \src "ls180.v:6271.64-6271.96"
-  wire $not$ls180.v:6271$1929_Y
-  attribute \src "ls180.v:6274.63-6274.95"
-  wire $not$ls180.v:6274$1936_Y
-  attribute \src "ls180.v:6277.62-6277.94"
-  wire $not$ls180.v:6277$1943_Y
-  attribute \src "ls180.v:6280.68-6280.100"
-  wire $not$ls180.v:6280$1950_Y
-  attribute \src "ls180.v:6302.67-6302.99"
-  wire $not$ls180.v:6302$1959_Y
-  attribute \src "ls180.v:6305.67-6305.99"
-  wire $not$ls180.v:6305$1966_Y
-  attribute \src "ls180.v:6308.65-6308.97"
-  wire $not$ls180.v:6308$1973_Y
-  attribute \src "ls180.v:6311.64-6311.96"
-  wire $not$ls180.v:6311$1980_Y
-  attribute \src "ls180.v:6314.63-6314.95"
-  wire $not$ls180.v:6314$1987_Y
-  attribute \src "ls180.v:6317.62-6317.94"
-  wire $not$ls180.v:6317$1994_Y
-  attribute \src "ls180.v:6320.68-6320.100"
-  wire $not$ls180.v:6320$2001_Y
-  attribute \src "ls180.v:6323.71-6323.103"
-  wire $not$ls180.v:6323$2008_Y
-  attribute \src "ls180.v:6326.71-6326.103"
-  wire $not$ls180.v:6326$2015_Y
-  attribute \src "ls180.v:6350.64-6350.96"
-  wire $not$ls180.v:6350$2024_Y
-  attribute \src "ls180.v:6353.64-6353.96"
-  wire $not$ls180.v:6353$2031_Y
-  attribute \src "ls180.v:6356.64-6356.96"
-  wire $not$ls180.v:6356$2038_Y
-  attribute \src "ls180.v:6359.64-6359.96"
-  wire $not$ls180.v:6359$2045_Y
-  attribute \src "ls180.v:6362.66-6362.98"
-  wire $not$ls180.v:6362$2052_Y
-  attribute \src "ls180.v:6365.66-6365.98"
-  wire $not$ls180.v:6365$2059_Y
-  attribute \src "ls180.v:6368.66-6368.98"
-  wire $not$ls180.v:6368$2066_Y
-  attribute \src "ls180.v:6371.66-6371.98"
-  wire $not$ls180.v:6371$2073_Y
-  attribute \src "ls180.v:6374.62-6374.94"
-  wire $not$ls180.v:6374$2080_Y
-  attribute \src "ls180.v:6377.72-6377.104"
-  wire $not$ls180.v:6377$2087_Y
-  attribute \src "ls180.v:6380.65-6380.97"
-  wire $not$ls180.v:6380$2094_Y
-  attribute \src "ls180.v:6383.65-6383.97"
-  wire $not$ls180.v:6383$2101_Y
-  attribute \src "ls180.v:6386.65-6386.97"
-  wire $not$ls180.v:6386$2108_Y
-  attribute \src "ls180.v:6389.65-6389.97"
-  wire $not$ls180.v:6389$2115_Y
-  attribute \src "ls180.v:6392.77-6392.109"
-  wire $not$ls180.v:6392$2122_Y
-  attribute \src "ls180.v:6395.78-6395.110"
-  wire $not$ls180.v:6395$2129_Y
-  attribute \src "ls180.v:6398.69-6398.101"
-  wire $not$ls180.v:6398$2136_Y
-  attribute \src "ls180.v:6418.55-6418.87"
-  wire $not$ls180.v:6418$2144_Y
-  attribute \src "ls180.v:6421.65-6421.97"
-  wire $not$ls180.v:6421$2151_Y
-  attribute \src "ls180.v:6424.66-6424.98"
-  wire $not$ls180.v:6424$2158_Y
-  attribute \src "ls180.v:6427.70-6427.102"
-  wire $not$ls180.v:6427$2165_Y
-  attribute \src "ls180.v:6430.71-6430.103"
-  wire $not$ls180.v:6430$2172_Y
-  attribute \src "ls180.v:6433.69-6433.101"
-  wire $not$ls180.v:6433$2179_Y
-  attribute \src "ls180.v:6436.66-6436.98"
-  wire $not$ls180.v:6436$2186_Y
-  attribute \src "ls180.v:6439.65-6439.97"
-  wire $not$ls180.v:6439$2193_Y
-  attribute \src "ls180.v:6452.71-6452.103"
-  wire $not$ls180.v:6452$2201_Y
-  attribute \src "ls180.v:6455.71-6455.103"
-  wire $not$ls180.v:6455$2208_Y
-  attribute \src "ls180.v:6458.71-6458.103"
-  wire $not$ls180.v:6458$2215_Y
-  attribute \src "ls180.v:6461.71-6461.103"
-  wire $not$ls180.v:6461$2222_Y
-  attribute \src "ls180.v:6842.86-6842.330"
-  wire $not$ls180.v:6842$2271_Y
-  attribute \src "ls180.v:6866.86-6866.330"
-  wire $not$ls180.v:6866$2287_Y
-  attribute \src "ls180.v:6890.86-6890.330"
-  wire $not$ls180.v:6890$2303_Y
-  attribute \src "ls180.v:6914.86-6914.330"
-  wire $not$ls180.v:6914$2319_Y
-  attribute \src "ls180.v:7412.18-7412.42"
-  wire $not$ls180.v:7412$2372_Y
-  attribute \src "ls180.v:7491.72-7491.101"
-  wire $not$ls180.v:7491$2405_Y
-  attribute \src "ls180.v:7510.8-7510.38"
-  wire $not$ls180.v:7510$2409_Y
-  attribute \src "ls180.v:7518.32-7518.55"
-  wire $not$ls180.v:7518$2411_Y
-  attribute \src "ls180.v:7588.136-7588.189"
-  wire $not$ls180.v:7588$2426_Y
-  attribute \src "ls180.v:7594.136-7594.189"
-  wire $not$ls180.v:7594$2431_Y
-  attribute \src "ls180.v:7595.8-7595.61"
-  wire $not$ls180.v:7595$2433_Y
-  attribute \src "ls180.v:7603.8-7603.56"
-  wire $not$ls180.v:7603$2436_Y
-  attribute \src "ls180.v:7618.8-7618.46"
-  wire $not$ls180.v:7618$2438_Y
-  attribute \src "ls180.v:7634.136-7634.189"
-  wire $not$ls180.v:7634$2442_Y
-  attribute \src "ls180.v:7640.136-7640.189"
-  wire $not$ls180.v:7640$2447_Y
-  attribute \src "ls180.v:7641.8-7641.61"
-  wire $not$ls180.v:7641$2449_Y
-  attribute \src "ls180.v:7649.8-7649.56"
-  wire $not$ls180.v:7649$2452_Y
-  attribute \src "ls180.v:7664.8-7664.46"
-  wire $not$ls180.v:7664$2454_Y
-  attribute \src "ls180.v:7680.136-7680.189"
-  wire $not$ls180.v:7680$2458_Y
-  attribute \src "ls180.v:7686.136-7686.189"
-  wire $not$ls180.v:7686$2463_Y
-  attribute \src "ls180.v:7687.8-7687.61"
-  wire $not$ls180.v:7687$2465_Y
-  attribute \src "ls180.v:7695.8-7695.56"
-  wire $not$ls180.v:7695$2468_Y
-  attribute \src "ls180.v:7710.8-7710.46"
-  wire $not$ls180.v:7710$2470_Y
-  attribute \src "ls180.v:7726.136-7726.189"
-  wire $not$ls180.v:7726$2474_Y
-  attribute \src "ls180.v:7732.136-7732.189"
-  wire $not$ls180.v:7732$2479_Y
-  attribute \src "ls180.v:7733.8-7733.61"
-  wire $not$ls180.v:7733$2481_Y
-  attribute \src "ls180.v:7741.8-7741.56"
-  wire $not$ls180.v:7741$2484_Y
-  attribute \src "ls180.v:7756.8-7756.46"
-  wire $not$ls180.v:7756$2486_Y
-  attribute \src "ls180.v:7764.7-7764.22"
-  wire $not$ls180.v:7764$2489_Y
-  attribute \src "ls180.v:7767.8-7767.29"
-  wire $not$ls180.v:7767$2490_Y
-  attribute \src "ls180.v:7771.7-7771.22"
-  wire $not$ls180.v:7771$2492_Y
-  attribute \src "ls180.v:7774.8-7774.29"
-  wire $not$ls180.v:7774$2493_Y
-  attribute \src "ls180.v:7893.30-7893.60"
-  wire $not$ls180.v:7893$2495_Y
-  attribute \src "ls180.v:7894.30-7894.60"
-  wire $not$ls180.v:7894$2496_Y
-  attribute \src "ls180.v:7895.29-7895.59"
-  wire $not$ls180.v:7895$2497_Y
-  attribute \src "ls180.v:7906.8-7906.33"
-  wire $not$ls180.v:7906$2498_Y
-  attribute \src "ls180.v:7921.8-7921.33"
-  wire $not$ls180.v:7921$2501_Y
-  attribute \src "ls180.v:7957.36-7957.58"
-  wire $not$ls180.v:7957$2531_Y
-  attribute \src "ls180.v:7957.64-7957.89"
-  wire $not$ls180.v:7957$2533_Y
-  attribute \src "ls180.v:7986.7-7986.29"
-  wire $not$ls180.v:7986$2540_Y
-  attribute \src "ls180.v:7987.9-7987.26"
-  wire $not$ls180.v:7987$2541_Y
-  attribute \src "ls180.v:8020.8-8020.29"
-  wire $not$ls180.v:8020$2547_Y
-  attribute \src "ls180.v:8027.8-8027.29"
-  wire $not$ls180.v:8027$2549_Y
-  attribute \src "ls180.v:8037.80-8037.106"
-  wire $not$ls180.v:8037$2552_Y
-  attribute \src "ls180.v:8043.80-8043.106"
-  wire $not$ls180.v:8043$2557_Y
-  attribute \src "ls180.v:8044.8-8044.34"
-  wire $not$ls180.v:8044$2559_Y
-  attribute \src "ls180.v:8059.80-8059.106"
-  wire $not$ls180.v:8059$2563_Y
-  attribute \src "ls180.v:8065.80-8065.106"
-  wire $not$ls180.v:8065$2568_Y
-  attribute \src "ls180.v:8066.8-8066.34"
-  wire $not$ls180.v:8066$2570_Y
-  attribute \src "ls180.v:8097.22-8097.41"
-  wire $not$ls180.v:8097$2574_Y
-  attribute \src "ls180.v:8097.46-8097.73"
-  wire $not$ls180.v:8097$2575_Y
-  attribute \src "ls180.v:8132.22-8132.40"
-  wire $not$ls180.v:8132$2579_Y
-  attribute \src "ls180.v:8132.45-8132.70"
-  wire $not$ls180.v:8132$2580_Y
-  attribute \src "ls180.v:8186.7-8186.31"
-  wire $not$ls180.v:8186$2591_Y
-  attribute \src "ls180.v:8258.8-8258.46"
-  wire $not$ls180.v:8258$2603_Y
-  attribute \src "ls180.v:8339.8-8339.47"
-  wire $not$ls180.v:8339$2615_Y
-  attribute \src "ls180.v:8400.8-8400.48"
-  wire $not$ls180.v:8400$2627_Y
-  attribute \src "ls180.v:8570.88-8570.118"
-  wire $not$ls180.v:8570$2641_Y
-  attribute \src "ls180.v:8576.88-8576.118"
-  wire $not$ls180.v:8576$2646_Y
-  attribute \src "ls180.v:8577.8-8577.38"
-  wire $not$ls180.v:8577$2648_Y
-  attribute \src "ls180.v:8656.88-8656.118"
-  wire $not$ls180.v:8656$2663_Y
-  attribute \src "ls180.v:8662.88-8662.118"
-  wire $not$ls180.v:8662$2668_Y
-  attribute \src "ls180.v:8663.8-8663.38"
-  wire $not$ls180.v:8663$2670_Y
-  attribute \src "ls180.v:8683.9-8683.28"
-  wire $not$ls180.v:8683$2673_Y
-  attribute \src "ls180.v:8702.9-8702.28"
-  wire $not$ls180.v:8702$2674_Y
-  attribute \src "ls180.v:8721.9-8721.28"
-  wire $not$ls180.v:8721$2675_Y
-  attribute \src "ls180.v:8740.9-8740.28"
-  wire $not$ls180.v:8740$2676_Y
-  attribute \src "ls180.v:8759.9-8759.28"
-  wire $not$ls180.v:8759$2677_Y
-  attribute \src "ls180.v:8780.8-8780.21"
-  wire $not$ls180.v:8780$2678_Y
-  attribute \src "ls180.v:10279.8-10279.51"
-  wire $or$ls180.v:10279$2750_Y
-  attribute \src "ls180.v:2814.10-2814.96"
-  wire $or$ls180.v:2814$21_Y
-  attribute \src "ls180.v:2874.10-2874.96"
-  wire $or$ls180.v:2874$32_Y
-  attribute \src "ls180.v:2934.10-2934.96"
-  wire $or$ls180.v:2934$43_Y
-  attribute \src "ls180.v:3126.39-3126.105"
-  wire $or$ls180.v:3126$75_Y
-  attribute \src "ls180.v:3169.59-3169.140"
-  wire $or$ls180.v:3169$79_Y
-  attribute \src "ls180.v:3170.44-3170.151"
-  wire $or$ls180.v:3170$80_Y
-  attribute \src "ls180.v:3178.45-3178.170"
-  wire width 13 $or$ls180.v:3178$84_Y
-  attribute \src "ls180.v:3215.127-3215.245"
-  wire $or$ls180.v:3215$97_Y
-  attribute \src "ls180.v:3221.57-3221.157"
-  wire $or$ls180.v:3221$103_Y
-  attribute \src "ls180.v:3326.59-3326.140"
-  wire $or$ls180.v:3326$109_Y
-  attribute \src "ls180.v:3327.44-3327.151"
-  wire $or$ls180.v:3327$110_Y
-  attribute \src "ls180.v:3335.45-3335.170"
-  wire width 13 $or$ls180.v:3335$114_Y
-  attribute \src "ls180.v:3372.127-3372.245"
-  wire $or$ls180.v:3372$127_Y
-  attribute \src "ls180.v:3378.57-3378.157"
-  wire $or$ls180.v:3378$133_Y
-  attribute \src "ls180.v:3483.59-3483.140"
-  wire $or$ls180.v:3483$139_Y
-  attribute \src "ls180.v:3484.44-3484.151"
-  wire $or$ls180.v:3484$140_Y
-  attribute \src "ls180.v:3492.45-3492.170"
-  wire width 13 $or$ls180.v:3492$144_Y
-  attribute \src "ls180.v:3529.127-3529.245"
-  wire $or$ls180.v:3529$157_Y
-  attribute \src "ls180.v:3535.57-3535.157"
-  wire $or$ls180.v:3535$163_Y
-  attribute \src "ls180.v:3640.59-3640.140"
-  wire $or$ls180.v:3640$169_Y
-  attribute \src "ls180.v:3641.44-3641.151"
-  wire $or$ls180.v:3641$170_Y
-  attribute \src "ls180.v:3649.45-3649.170"
-  wire width 13 $or$ls180.v:3649$174_Y
-  attribute \src "ls180.v:3686.127-3686.245"
-  wire $or$ls180.v:3686$187_Y
-  attribute \src "ls180.v:3692.57-3692.157"
-  wire $or$ls180.v:3692$193_Y
-  attribute \src "ls180.v:3791.107-3791.193"
-  wire $or$ls180.v:3791$213_Y
-  attribute \src "ls180.v:3794.39-3794.204"
-  wire $or$ls180.v:3794$219_Y
-  attribute \src "ls180.v:3794.38-3794.289"
-  wire $or$ls180.v:3794$221_Y
-  attribute \src "ls180.v:3794.37-3794.374"
-  wire $or$ls180.v:3794$223_Y
-  attribute \src "ls180.v:3795.40-3795.207"
-  wire $or$ls180.v:3795$226_Y
-  attribute \src "ls180.v:3795.39-3795.293"
-  wire $or$ls180.v:3795$228_Y
-  attribute \src "ls180.v:3795.38-3795.379"
-  wire $or$ls180.v:3795$230_Y
-  attribute \src "ls180.v:3808.158-3808.332"
-  wire $or$ls180.v:3808$244_Y
-  attribute \src "ls180.v:3808.75-3808.506"
-  wire $or$ls180.v:3808$249_Y
-  attribute \src "ls180.v:3809.158-3809.332"
-  wire $or$ls180.v:3809$257_Y
-  attribute \src "ls180.v:3809.75-3809.506"
-  wire $or$ls180.v:3809$262_Y
-  attribute \src "ls180.v:3810.158-3810.332"
-  wire $or$ls180.v:3810$270_Y
-  attribute \src "ls180.v:3810.75-3810.506"
-  wire $or$ls180.v:3810$275_Y
-  attribute \src "ls180.v:3811.158-3811.332"
-  wire $or$ls180.v:3811$283_Y
-  attribute \src "ls180.v:3811.75-3811.506"
-  wire $or$ls180.v:3811$288_Y
-  attribute \src "ls180.v:3838.36-3838.104"
-  wire $or$ls180.v:3838$294_Y
-  attribute \src "ls180.v:3841.158-3841.332"
-  wire $or$ls180.v:3841$302_Y
-  attribute \src "ls180.v:3841.75-3841.506"
-  wire $or$ls180.v:3841$307_Y
-  attribute \src "ls180.v:3842.158-3842.332"
-  wire $or$ls180.v:3842$315_Y
-  attribute \src "ls180.v:3842.75-3842.506"
-  wire $or$ls180.v:3842$320_Y
-  attribute \src "ls180.v:3843.158-3843.332"
-  wire $or$ls180.v:3843$328_Y
-  attribute \src "ls180.v:3843.75-3843.506"
-  wire $or$ls180.v:3843$333_Y
-  attribute \src "ls180.v:3844.158-3844.332"
-  wire $or$ls180.v:3844$341_Y
-  attribute \src "ls180.v:3844.75-3844.506"
-  wire $or$ls180.v:3844$346_Y
-  attribute \src "ls180.v:3907.36-3907.104"
-  wire $or$ls180.v:3907$380_Y
-  attribute \src "ls180.v:3928.67-3928.221"
-  wire $or$ls180.v:3928$387_Y
-  attribute \src "ls180.v:3936.10-3936.62"
-  wire $or$ls180.v:3936$390_Y
-  attribute \src "ls180.v:3966.67-3966.221"
-  wire $or$ls180.v:3966$396_Y
-  attribute \src "ls180.v:3974.10-3974.61"
-  wire $or$ls180.v:3974$399_Y
-  attribute \src "ls180.v:3984.91-3984.180"
-  wire $or$ls180.v:3984$403_Y
-  attribute \src "ls180.v:3984.90-3984.255"
-  wire $or$ls180.v:3984$406_Y
-  attribute \src "ls180.v:3984.89-3984.330"
-  wire $or$ls180.v:3984$409_Y
-  attribute \src "ls180.v:3989.91-3989.180"
-  wire $or$ls180.v:3989$419_Y
-  attribute \src "ls180.v:3989.90-3989.255"
-  wire $or$ls180.v:3989$422_Y
-  attribute \src "ls180.v:3989.89-3989.330"
-  wire $or$ls180.v:3989$425_Y
-  attribute \src "ls180.v:3994.91-3994.180"
-  wire $or$ls180.v:3994$435_Y
-  attribute \src "ls180.v:3994.90-3994.255"
-  wire $or$ls180.v:3994$438_Y
-  attribute \src "ls180.v:3994.89-3994.330"
-  wire $or$ls180.v:3994$441_Y
-  attribute \src "ls180.v:3999.91-3999.180"
-  wire $or$ls180.v:3999$451_Y
-  attribute \src "ls180.v:3999.90-3999.255"
-  wire $or$ls180.v:3999$454_Y
-  attribute \src "ls180.v:3999.89-3999.330"
-  wire $or$ls180.v:3999$457_Y
-  attribute \src "ls180.v:4004.132-4004.221"
-  wire $or$ls180.v:4004$468_Y
-  attribute \src "ls180.v:4004.131-4004.296"
-  wire $or$ls180.v:4004$471_Y
-  attribute \src "ls180.v:4004.130-4004.371"
-  wire $or$ls180.v:4004$474_Y
-  attribute \src "ls180.v:4004.34-4004.411"
-  wire $or$ls180.v:4004$479_Y
-  attribute \src "ls180.v:4004.506-4004.595"
-  wire $or$ls180.v:4004$484_Y
-  attribute \src "ls180.v:4004.505-4004.670"
-  wire $or$ls180.v:4004$487_Y
-  attribute \src "ls180.v:4004.504-4004.745"
-  wire $or$ls180.v:4004$490_Y
-  attribute \src "ls180.v:4004.33-4004.785"
-  wire $or$ls180.v:4004$495_Y
-  attribute \src "ls180.v:4004.880-4004.969"
-  wire $or$ls180.v:4004$500_Y
-  attribute \src "ls180.v:4004.879-4004.1044"
-  wire $or$ls180.v:4004$503_Y
-  attribute \src "ls180.v:4004.878-4004.1119"
-  wire $or$ls180.v:4004$506_Y
-  attribute \src "ls180.v:4004.32-4004.1159"
-  wire $or$ls180.v:4004$511_Y
-  attribute \src "ls180.v:4004.1254-4004.1343"
-  wire $or$ls180.v:4004$516_Y
-  attribute \src "ls180.v:4004.1253-4004.1418"
-  wire $or$ls180.v:4004$519_Y
-  attribute \src "ls180.v:4004.1252-4004.1493"
-  wire $or$ls180.v:4004$522_Y
-  attribute \src "ls180.v:4004.31-4004.1533"
-  wire $or$ls180.v:4004$527_Y
-  attribute \src "ls180.v:4067.10-4067.52"
-  wire $or$ls180.v:4067$536_Y
-  attribute \src "ls180.v:4094.35-4094.74"
-  wire $or$ls180.v:4094$546_Y
-  attribute \src "ls180.v:4095.34-4095.73"
-  wire $or$ls180.v:4095$550_Y
-  attribute \src "ls180.v:4096.48-4096.130"
-  wire $or$ls180.v:4096$556_Y
-  attribute \src "ls180.v:4097.24-4097.87"
-  wire $or$ls180.v:4097$559_Y
-  attribute \src "ls180.v:4098.26-4098.95"
-  wire $or$ls180.v:4098$561_Y
-  attribute \src "ls180.v:4128.42-4128.89"
-  wire $or$ls180.v:4128$569_Y
-  attribute \src "ls180.v:4152.25-4152.174"
-  wire $or$ls180.v:4152$579_Y
-  attribute \src "ls180.v:4167.80-4167.132"
-  wire $or$ls180.v:4167$581_Y
-  attribute \src "ls180.v:4178.72-4178.135"
-  wire $or$ls180.v:4178$586_Y
-  attribute \src "ls180.v:4197.80-4197.132"
-  wire $or$ls180.v:4197$592_Y
-  attribute \src "ls180.v:4208.72-4208.135"
-  wire $or$ls180.v:4208$597_Y
-  attribute \src "ls180.v:4342.36-4342.111"
-  wire $or$ls180.v:4342$618_Y
-  attribute \src "ls180.v:4342.35-4342.151"
-  wire $or$ls180.v:4342$619_Y
-  attribute \src "ls180.v:4342.34-4342.192"
-  wire $or$ls180.v:4342$620_Y
-  attribute \src "ls180.v:4342.33-4342.233"
-  wire $or$ls180.v:4342$621_Y
-  attribute \src "ls180.v:4343.39-4343.120"
-  wire $or$ls180.v:4343$622_Y
-  attribute \src "ls180.v:4343.38-4343.163"
-  wire $or$ls180.v:4343$623_Y
-  attribute \src "ls180.v:4343.37-4343.207"
-  wire $or$ls180.v:4343$624_Y
-  attribute \src "ls180.v:4343.36-4343.251"
-  wire $or$ls180.v:4343$625_Y
-  attribute \src "ls180.v:4344.38-4344.117"
-  wire $or$ls180.v:4344$626_Y
-  attribute \src "ls180.v:4344.37-4344.159"
-  wire $or$ls180.v:4344$627_Y
-  attribute \src "ls180.v:4344.36-4344.202"
-  wire $or$ls180.v:4344$628_Y
-  attribute \src "ls180.v:4344.35-4344.245"
-  wire $or$ls180.v:4344$629_Y
-  attribute \src "ls180.v:4345.40-4345.123"
-  wire $or$ls180.v:4345$630_Y
-  attribute \src "ls180.v:4345.39-4345.167"
-  wire $or$ls180.v:4345$631_Y
-  attribute \src "ls180.v:4345.38-4345.212"
-  wire $or$ls180.v:4345$632_Y
-  attribute \src "ls180.v:4345.37-4345.257"
-  wire $or$ls180.v:4345$633_Y
-  attribute \src "ls180.v:4346.39-4346.120"
-  wire width 4 $or$ls180.v:4346$634_Y
-  attribute \src "ls180.v:4346.38-4346.163"
-  wire width 4 $or$ls180.v:4346$635_Y
-  attribute \src "ls180.v:4346.37-4346.207"
-  wire width 4 $or$ls180.v:4346$636_Y
-  attribute \src "ls180.v:4346.36-4346.251"
-  wire width 4 $or$ls180.v:4346$637_Y
-  attribute \src "ls180.v:4367.35-4367.80"
-  wire $or$ls180.v:4367$638_Y
-  attribute \src "ls180.v:4521.91-4521.144"
-  wire $or$ls180.v:4521$652_Y
-  attribute \src "ls180.v:4538.53-4538.143"
-  wire $or$ls180.v:4538$655_Y
-  attribute \src "ls180.v:4541.47-4541.127"
-  wire $or$ls180.v:4541$658_Y
-  attribute \src "ls180.v:4665.54-4665.146"
-  wire $or$ls180.v:4665$676_Y
-  attribute \src "ls180.v:4668.48-4668.130"
-  wire $or$ls180.v:4668$679_Y
-  attribute \src "ls180.v:4799.55-4799.149"
-  wire $or$ls180.v:4799$691_Y
-  attribute \src "ls180.v:4802.49-4802.133"
-  wire $or$ls180.v:4802$694_Y
-  attribute \src "ls180.v:5431.80-5431.151"
-  wire $or$ls180.v:5431$989_Y
-  attribute \src "ls180.v:5442.49-5442.131"
-  wire $or$ls180.v:5442$995_Y
-  attribute \src "ls180.v:5639.80-5639.151"
-  wire $or$ls180.v:5639$1020_Y
-  attribute \src "ls180.v:5754.33-5754.102"
-  wire $or$ls180.v:5754$1060_Y
-  attribute \src "ls180.v:5754.32-5754.144"
-  wire $or$ls180.v:5754$1061_Y
-  attribute \src "ls180.v:5754.31-5754.165"
-  wire $or$ls180.v:5754$1062_Y
-  attribute \src "ls180.v:5754.30-5754.201"
-  wire $or$ls180.v:5754$1063_Y
-  attribute \src "ls180.v:5760.28-5760.97"
-  wire $or$ls180.v:5760$1068_Y
-  attribute \src "ls180.v:5760.27-5760.139"
-  wire $or$ls180.v:5760$1069_Y
-  attribute \src "ls180.v:5760.26-5760.160"
-  wire $or$ls180.v:5760$1070_Y
-  attribute \src "ls180.v:5760.25-5760.196"
-  wire $or$ls180.v:5760$1071_Y
-  attribute \src "ls180.v:5761.30-5761.169"
-  wire width 32 $or$ls180.v:5761$1074_Y
-  attribute \src "ls180.v:5761.29-5761.246"
-  wire width 32 $or$ls180.v:5761$1076_Y
-  attribute \src "ls180.v:5761.28-5761.302"
-  wire width 32 $or$ls180.v:5761$1078_Y
-  attribute \src "ls180.v:5761.27-5761.373"
-  wire width 32 $or$ls180.v:5761$1080_Y
-  attribute \src "ls180.v:6515.55-6515.124"
-  wire width 8 $or$ls180.v:6515$2226_Y
-  attribute \src "ls180.v:6515.54-6515.161"
-  wire width 8 $or$ls180.v:6515$2227_Y
-  attribute \src "ls180.v:6515.53-6515.198"
-  wire width 8 $or$ls180.v:6515$2228_Y
-  attribute \src "ls180.v:6515.52-6515.235"
-  wire width 8 $or$ls180.v:6515$2229_Y
-  attribute \src "ls180.v:6515.51-6515.272"
-  wire width 8 $or$ls180.v:6515$2230_Y
-  attribute \src "ls180.v:6515.50-6515.309"
-  wire width 8 $or$ls180.v:6515$2231_Y
-  attribute \src "ls180.v:6515.49-6515.346"
-  wire width 8 $or$ls180.v:6515$2232_Y
-  attribute \src "ls180.v:6515.48-6515.383"
-  wire width 8 $or$ls180.v:6515$2233_Y
-  attribute \src "ls180.v:6515.47-6515.420"
-  wire width 8 $or$ls180.v:6515$2234_Y
-  attribute \src "ls180.v:6515.46-6515.458"
-  wire width 8 $or$ls180.v:6515$2235_Y
-  attribute \src "ls180.v:6515.45-6515.496"
-  wire width 8 $or$ls180.v:6515$2236_Y
-  attribute \src "ls180.v:6515.44-6515.534"
-  wire width 8 $or$ls180.v:6515$2237_Y
-  attribute \src "ls180.v:6515.43-6515.572"
-  wire width 8 $or$ls180.v:6515$2238_Y
-  attribute \src "ls180.v:6515.42-6515.610"
-  wire width 8 $or$ls180.v:6515$2239_Y
-  attribute \src "ls180.v:6842.90-6842.179"
-  wire $or$ls180.v:6842$2264_Y
-  attribute \src "ls180.v:6842.89-6842.254"
-  wire $or$ls180.v:6842$2267_Y
-  attribute \src "ls180.v:6842.88-6842.329"
-  wire $or$ls180.v:6842$2270_Y
-  attribute \src "ls180.v:6866.90-6866.179"
-  wire $or$ls180.v:6866$2280_Y
-  attribute \src "ls180.v:6866.89-6866.254"
-  wire $or$ls180.v:6866$2283_Y
-  attribute \src "ls180.v:6866.88-6866.329"
-  wire $or$ls180.v:6866$2286_Y
-  attribute \src "ls180.v:6890.90-6890.179"
-  wire $or$ls180.v:6890$2296_Y
-  attribute \src "ls180.v:6890.89-6890.254"
-  wire $or$ls180.v:6890$2299_Y
-  attribute \src "ls180.v:6890.88-6890.329"
-  wire $or$ls180.v:6890$2302_Y
-  attribute \src "ls180.v:6914.90-6914.179"
-  wire $or$ls180.v:6914$2312_Y
-  attribute \src "ls180.v:6914.89-6914.254"
-  wire $or$ls180.v:6914$2315_Y
-  attribute \src "ls180.v:6914.88-6914.329"
-  wire $or$ls180.v:6914$2318_Y
-  attribute \src "ls180.v:7428.20-7428.71"
-  wire $or$ls180.v:7428$2375_Y
-  attribute \src "ls180.v:7429.20-7429.71"
-  wire $or$ls180.v:7429$2376_Y
-  attribute \src "ls180.v:7430.20-7430.71"
-  wire $or$ls180.v:7430$2377_Y
-  attribute \src "ls180.v:7431.20-7431.71"
-  wire $or$ls180.v:7431$2378_Y
-  attribute \src "ls180.v:7432.20-7432.71"
-  wire $or$ls180.v:7432$2379_Y
-  attribute \src "ls180.v:7433.20-7433.71"
-  wire $or$ls180.v:7433$2380_Y
-  attribute \src "ls180.v:7434.20-7434.71"
-  wire $or$ls180.v:7434$2381_Y
-  attribute \src "ls180.v:7435.20-7435.71"
-  wire $or$ls180.v:7435$2382_Y
-  attribute \src "ls180.v:7436.20-7436.71"
-  wire $or$ls180.v:7436$2383_Y
-  attribute \src "ls180.v:7437.20-7437.71"
-  wire $or$ls180.v:7437$2384_Y
-  attribute \src "ls180.v:7438.21-7438.73"
-  wire $or$ls180.v:7438$2385_Y
-  attribute \src "ls180.v:7439.21-7439.73"
-  wire $or$ls180.v:7439$2386_Y
-  attribute \src "ls180.v:7440.21-7440.73"
-  wire $or$ls180.v:7440$2387_Y
-  attribute \src "ls180.v:7441.21-7441.73"
-  wire $or$ls180.v:7441$2388_Y
-  attribute \src "ls180.v:7442.21-7442.73"
-  wire $or$ls180.v:7442$2389_Y
-  attribute \src "ls180.v:7443.21-7443.73"
-  wire $or$ls180.v:7443$2390_Y
-  attribute \src "ls180.v:7444.21-7444.73"
-  wire $or$ls180.v:7444$2391_Y
-  attribute \src "ls180.v:7445.21-7445.73"
-  wire $or$ls180.v:7445$2392_Y
-  attribute \src "ls180.v:7446.21-7446.73"
-  wire $or$ls180.v:7446$2393_Y
-  attribute \src "ls180.v:7447.21-7447.73"
-  wire $or$ls180.v:7447$2394_Y
-  attribute \src "ls180.v:7448.21-7448.73"
-  wire $or$ls180.v:7448$2395_Y
-  attribute \src "ls180.v:7449.21-7449.73"
-  wire $or$ls180.v:7449$2396_Y
-  attribute \src "ls180.v:7450.21-7450.73"
-  wire $or$ls180.v:7450$2397_Y
-  attribute \src "ls180.v:7451.21-7451.73"
-  wire $or$ls180.v:7451$2398_Y
-  attribute \src "ls180.v:7452.7-7452.93"
-  wire $or$ls180.v:7452$2399_Y
-  attribute \src "ls180.v:7463.7-7463.93"
-  wire $or$ls180.v:7463$2400_Y
-  attribute \src "ls180.v:7474.7-7474.93"
-  wire $or$ls180.v:7474$2401_Y
-  attribute \src "ls180.v:7603.7-7603.107"
-  wire $or$ls180.v:7603$2437_Y
-  attribute \src "ls180.v:7649.7-7649.107"
-  wire $or$ls180.v:7649$2453_Y
-  attribute \src "ls180.v:7695.7-7695.107"
-  wire $or$ls180.v:7695$2469_Y
-  attribute \src "ls180.v:7741.7-7741.107"
-  wire $or$ls180.v:7741$2485_Y
-  attribute \src "ls180.v:7929.40-7929.125"
-  wire $or$ls180.v:7929$2506_Y
-  attribute \src "ls180.v:7929.39-7929.207"
-  wire $or$ls180.v:7929$2509_Y
-  attribute \src "ls180.v:7929.38-7929.289"
-  wire $or$ls180.v:7929$2512_Y
-  attribute \src "ls180.v:7929.37-7929.371"
-  wire $or$ls180.v:7929$2515_Y
-  attribute \src "ls180.v:7930.41-7930.126"
-  wire $or$ls180.v:7930$2518_Y
-  attribute \src "ls180.v:7930.40-7930.208"
-  wire $or$ls180.v:7930$2521_Y
-  attribute \src "ls180.v:7930.39-7930.290"
-  wire $or$ls180.v:7930$2524_Y
-  attribute \src "ls180.v:7930.38-7930.372"
-  wire $or$ls180.v:7930$2527_Y
-  attribute \src "ls180.v:7934.7-7934.49"
-  wire $or$ls180.v:7934$2528_Y
-  attribute \src "ls180.v:8097.21-8097.74"
-  wire $or$ls180.v:8097$2576_Y
-  attribute \src "ls180.v:8132.21-8132.71"
-  wire $or$ls180.v:8132$2581_Y
-  attribute \src "ls180.v:8200.32-8200.85"
-  wire $or$ls180.v:8200$2593_Y
-  attribute \src "ls180.v:8206.8-8206.97"
-  wire $or$ls180.v:8206$2595_Y
-  attribute \src "ls180.v:8223.52-8223.139"
-  wire $or$ls180.v:8223$2600_Y
-  attribute \src "ls180.v:8224.51-8224.136"
-  wire $or$ls180.v:8224$2601_Y
-  attribute \src "ls180.v:8258.7-8258.87"
-  wire $or$ls180.v:8258$2604_Y
-  attribute \src "ls180.v:8281.33-8281.88"
-  wire $or$ls180.v:8281$2605_Y
-  attribute \src "ls180.v:8287.8-8287.99"
-  wire $or$ls180.v:8287$2607_Y
-  attribute \src "ls180.v:8304.53-8304.142"
-  wire $or$ls180.v:8304$2612_Y
-  attribute \src "ls180.v:8305.52-8305.139"
-  wire $or$ls180.v:8305$2613_Y
-  attribute \src "ls180.v:8339.7-8339.89"
-  wire $or$ls180.v:8339$2616_Y
-  attribute \src "ls180.v:8360.34-8360.91"
-  wire $or$ls180.v:8360$2617_Y
-  attribute \src "ls180.v:8366.8-8366.101"
-  wire $or$ls180.v:8366$2619_Y
-  attribute \src "ls180.v:8383.54-8383.145"
-  wire $or$ls180.v:8383$2624_Y
-  attribute \src "ls180.v:8384.53-8384.142"
-  wire $or$ls180.v:8384$2625_Y
-  attribute \src "ls180.v:8400.7-8400.91"
-  wire $or$ls180.v:8400$2628_Y
-  attribute \src "ls180.v:8589.8-8589.89"
-  wire $or$ls180.v:8589$2652_Y
-  attribute \src "ls180.v:8606.48-8606.127"
-  wire $or$ls180.v:8606$2657_Y
-  attribute \src "ls180.v:8607.47-8607.124"
-  wire $or$ls180.v:8607$2658_Y
-  attribute \src "ls180.v:3178.46-3178.94"
-  wire width 13 $sshl$ls180.v:3178$83_Y
-  attribute \src "ls180.v:3335.46-3335.94"
-  wire width 13 $sshl$ls180.v:3335$113_Y
-  attribute \src "ls180.v:3492.46-3492.94"
-  wire width 13 $sshl$ls180.v:3492$143_Y
-  attribute \src "ls180.v:3649.46-3649.94"
-  wire width 13 $sshl$ls180.v:3649$173_Y
-  attribute \src "ls180.v:3209.63-3209.122"
-  wire width 3 $sub$ls180.v:3209$96_Y
-  attribute \src "ls180.v:3366.63-3366.122"
-  wire width 3 $sub$ls180.v:3366$126_Y
-  attribute \src "ls180.v:3523.63-3523.122"
-  wire width 3 $sub$ls180.v:3523$156_Y
-  attribute \src "ls180.v:3680.63-3680.122"
-  wire width 3 $sub$ls180.v:3680$186_Y
-  attribute \src "ls180.v:4086.38-4086.75"
-  wire width 31 $sub$ls180.v:4086$540_Y
-  attribute \src "ls180.v:4172.36-4172.68"
-  wire width 4 $sub$ls180.v:4172$585_Y
-  attribute \src "ls180.v:4202.36-4202.68"
-  wire width 4 $sub$ls180.v:4202$596_Y
-  attribute \src "ls180.v:4227.70-4227.110"
-  wire width 16 $sub$ls180.v:4227$602_Y
-  attribute \src "ls180.v:4228.70-4228.104"
-  wire width 16 $sub$ls180.v:4228$604_Y
-  attribute \src "ls180.v:4255.37-4255.66"
-  wire width 8 $sub$ls180.v:4255$608_Y
-  attribute \src "ls180.v:4285.67-4285.107"
-  wire width 16 $sub$ls180.v:4285$610_Y
-  attribute \src "ls180.v:4286.67-4286.101"
-  wire width 16 $sub$ls180.v:4286$612_Y
-  attribute \src "ls180.v:4314.35-4314.64"
-  wire width 8 $sub$ls180.v:4314$616_Y
-  attribute \src "ls180.v:4568.60-4568.90"
-  wire width 32 $sub$ls180.v:4568$660_Y
-  attribute \src "ls180.v:4579.62-4579.104"
-  wire width 8 $sub$ls180.v:4579$662_Y
-  attribute \src "ls180.v:4596.60-4596.90"
-  wire width 32 $sub$ls180.v:4596$666_Y
-  attribute \src "ls180.v:4825.62-4825.93"
-  wire width 32 $sub$ls180.v:4825$696_Y
-  attribute \src "ls180.v:4830.62-4830.93"
-  wire width 32 $sub$ls180.v:4830$697_Y
-  attribute \src "ls180.v:4841.64-4841.122"
-  wire width 10 $sub$ls180.v:4841$700_Y
-  attribute \src "ls180.v:4862.62-4862.93"
-  wire width 32 $sub$ls180.v:4862$703_Y
-  attribute \src "ls180.v:5324.37-5324.75"
-  wire width 32 $sub$ls180.v:5324$976_Y
-  attribute \src "ls180.v:5339.62-5339.100"
-  wire width 32 $sub$ls180.v:5339$979_Y
-  attribute \src "ls180.v:5350.39-5350.77"
-  wire width 32 $sub$ls180.v:5350$984_Y
-  attribute \src "ls180.v:5425.40-5425.76"
-  wire width 5 $sub$ls180.v:5425$988_Y
-  attribute \src "ls180.v:5474.56-5474.104"
-  wire width 32 $sub$ls180.v:5474$1002_Y
-  attribute \src "ls180.v:5564.71-5564.105"
-  wire width 32 $sub$ls180.v:5564$1008_Y
-  attribute \src "ls180.v:5633.40-5633.76"
-  wire width 5 $sub$ls180.v:5633$1019_Y
-  attribute \src "ls180.v:7498.31-7498.60"
-  wire width 32 $sub$ls180.v:7498$2408_Y
-  attribute \src "ls180.v:7519.31-7519.61"
-  wire width 10 $sub$ls180.v:7519$2413_Y
-  attribute \src "ls180.v:7525.34-7525.67"
-  wire $sub$ls180.v:7525$2414_Y
-  attribute \src "ls180.v:7536.36-7536.69"
-  wire $sub$ls180.v:7536$2417_Y
-  attribute \src "ls180.v:7600.59-7600.116"
-  wire width 4 $sub$ls180.v:7600$2435_Y
-  attribute \src "ls180.v:7619.46-7619.90"
-  wire width 3 $sub$ls180.v:7619$2439_Y
-  attribute \src "ls180.v:7646.59-7646.116"
-  wire width 4 $sub$ls180.v:7646$2451_Y
-  attribute \src "ls180.v:7665.46-7665.90"
-  wire width 3 $sub$ls180.v:7665$2455_Y
-  attribute \src "ls180.v:7692.59-7692.116"
-  wire width 4 $sub$ls180.v:7692$2467_Y
-  attribute \src "ls180.v:7711.46-7711.90"
-  wire width 3 $sub$ls180.v:7711$2471_Y
-  attribute \src "ls180.v:7738.59-7738.116"
-  wire width 4 $sub$ls180.v:7738$2483_Y
-  attribute \src "ls180.v:7757.46-7757.90"
-  wire width 3 $sub$ls180.v:7757$2487_Y
-  attribute \src "ls180.v:7768.25-7768.48"
-  wire width 5 $sub$ls180.v:7768$2491_Y
-  attribute \src "ls180.v:7775.25-7775.48"
-  wire width 4 $sub$ls180.v:7775$2494_Y
-  attribute \src "ls180.v:7907.33-7907.64"
-  wire $sub$ls180.v:7907$2499_Y
-  attribute \src "ls180.v:7922.33-7922.64"
-  wire width 3 $sub$ls180.v:7922$2502_Y
-  attribute \src "ls180.v:8049.33-8049.64"
-  wire width 5 $sub$ls180.v:8049$2561_Y
-  attribute \src "ls180.v:8071.33-8071.64"
-  wire width 5 $sub$ls180.v:8071$2572_Y
-  attribute \src "ls180.v:8106.34-8106.66"
-  wire width 3 $sub$ls180.v:8106$2577_Y
-  attribute \src "ls180.v:8141.32-8141.62"
-  wire width 3 $sub$ls180.v:8141$2582_Y
-  attribute \src "ls180.v:8165.30-8165.53"
-  wire width 32 $sub$ls180.v:8165$2585_Y
-  attribute \src "ls180.v:8179.30-8179.53"
-  wire width 32 $sub$ls180.v:8179$2589_Y
-  attribute \src "ls180.v:8582.36-8582.70"
-  wire width 6 $sub$ls180.v:8582$2650_Y
-  attribute \src "ls180.v:8668.36-8668.70"
-  wire width 6 $sub$ls180.v:8668$2672_Y
-  attribute \src "ls180.v:8781.22-8781.42"
-  wire width 20 $sub$ls180.v:8781$2679_Y
-  attribute \src "ls180.v:4922.353-4922.425"
-  wire $xor$ls180.v:4922$710_Y
-  attribute \src "ls180.v:4922.200-4922.272"
-  wire $xor$ls180.v:4922$711_Y
-  attribute \src "ls180.v:4922.160-4922.273"
-  wire $xor$ls180.v:4922$712_Y
-  attribute \src "ls180.v:4923.353-4923.425"
-  wire $xor$ls180.v:4923$713_Y
-  attribute \src "ls180.v:4923.200-4923.272"
-  wire $xor$ls180.v:4923$714_Y
-  attribute \src "ls180.v:4923.160-4923.273"
-  wire $xor$ls180.v:4923$715_Y
-  attribute \src "ls180.v:4924.353-4924.425"
-  wire $xor$ls180.v:4924$716_Y
-  attribute \src "ls180.v:4924.200-4924.272"
-  wire $xor$ls180.v:4924$717_Y
-  attribute \src "ls180.v:4924.160-4924.273"
-  wire $xor$ls180.v:4924$718_Y
-  attribute \src "ls180.v:4925.353-4925.425"
-  wire $xor$ls180.v:4925$719_Y
-  attribute \src "ls180.v:4925.200-4925.272"
-  wire $xor$ls180.v:4925$720_Y
-  attribute \src "ls180.v:4925.160-4925.273"
-  wire $xor$ls180.v:4925$721_Y
-  attribute \src "ls180.v:4926.353-4926.425"
-  wire $xor$ls180.v:4926$722_Y
-  attribute \src "ls180.v:4926.200-4926.272"
-  wire $xor$ls180.v:4926$723_Y
-  attribute \src "ls180.v:4926.160-4926.273"
-  wire $xor$ls180.v:4926$724_Y
-  attribute \src "ls180.v:4927.353-4927.425"
-  wire $xor$ls180.v:4927$725_Y
-  attribute \src "ls180.v:4927.200-4927.272"
-  wire $xor$ls180.v:4927$726_Y
-  attribute \src "ls180.v:4927.160-4927.273"
-  wire $xor$ls180.v:4927$727_Y
-  attribute \src "ls180.v:4928.353-4928.425"
-  wire $xor$ls180.v:4928$728_Y
-  attribute \src "ls180.v:4928.200-4928.272"
-  wire $xor$ls180.v:4928$729_Y
-  attribute \src "ls180.v:4928.160-4928.273"
-  wire $xor$ls180.v:4928$730_Y
-  attribute \src "ls180.v:4929.353-4929.425"
-  wire $xor$ls180.v:4929$731_Y
-  attribute \src "ls180.v:4929.200-4929.272"
-  wire $xor$ls180.v:4929$732_Y
-  attribute \src "ls180.v:4929.160-4929.273"
-  wire $xor$ls180.v:4929$733_Y
-  attribute \src "ls180.v:4930.353-4930.425"
-  wire $xor$ls180.v:4930$734_Y
-  attribute \src "ls180.v:4930.200-4930.272"
-  wire $xor$ls180.v:4930$735_Y
-  attribute \src "ls180.v:4930.160-4930.273"
-  wire $xor$ls180.v:4930$736_Y
-  attribute \src "ls180.v:4931.354-4931.426"
-  wire $xor$ls180.v:4931$737_Y
-  attribute \src "ls180.v:4931.201-4931.273"
-  wire $xor$ls180.v:4931$738_Y
-  attribute \src "ls180.v:4931.161-4931.274"
-  wire $xor$ls180.v:4931$739_Y
-  attribute \src "ls180.v:4932.361-4932.434"
-  wire $xor$ls180.v:4932$740_Y
-  attribute \src "ls180.v:4932.205-4932.278"
-  wire $xor$ls180.v:4932$741_Y
-  attribute \src "ls180.v:4932.164-4932.279"
-  wire $xor$ls180.v:4932$742_Y
-  attribute \src "ls180.v:4933.361-4933.434"
-  wire $xor$ls180.v:4933$743_Y
-  attribute \src "ls180.v:4933.205-4933.278"
-  wire $xor$ls180.v:4933$744_Y
-  attribute \src "ls180.v:4933.164-4933.279"
-  wire $xor$ls180.v:4933$745_Y
-  attribute \src "ls180.v:4934.361-4934.434"
-  wire $xor$ls180.v:4934$746_Y
-  attribute \src "ls180.v:4934.205-4934.278"
-  wire $xor$ls180.v:4934$747_Y
-  attribute \src "ls180.v:4934.164-4934.279"
-  wire $xor$ls180.v:4934$748_Y
-  attribute \src "ls180.v:4935.361-4935.434"
-  wire $xor$ls180.v:4935$749_Y
-  attribute \src "ls180.v:4935.205-4935.278"
-  wire $xor$ls180.v:4935$750_Y
-  attribute \src "ls180.v:4935.164-4935.279"
-  wire $xor$ls180.v:4935$751_Y
-  attribute \src "ls180.v:4936.361-4936.434"
-  wire $xor$ls180.v:4936$752_Y
-  attribute \src "ls180.v:4936.205-4936.278"
-  wire $xor$ls180.v:4936$753_Y
-  attribute \src "ls180.v:4936.164-4936.279"
-  wire $xor$ls180.v:4936$754_Y
-  attribute \src "ls180.v:4937.361-4937.434"
-  wire $xor$ls180.v:4937$755_Y
-  attribute \src "ls180.v:4937.205-4937.278"
-  wire $xor$ls180.v:4937$756_Y
-  attribute \src "ls180.v:4937.164-4937.279"
-  wire $xor$ls180.v:4937$757_Y
-  attribute \src "ls180.v:4938.361-4938.434"
-  wire $xor$ls180.v:4938$758_Y
-  attribute \src "ls180.v:4938.205-4938.278"
-  wire $xor$ls180.v:4938$759_Y
-  attribute \src "ls180.v:4938.164-4938.279"
-  wire $xor$ls180.v:4938$760_Y
-  attribute \src "ls180.v:4939.361-4939.434"
-  wire $xor$ls180.v:4939$761_Y
-  attribute \src "ls180.v:4939.205-4939.278"
-  wire $xor$ls180.v:4939$762_Y
-  attribute \src "ls180.v:4939.164-4939.279"
-  wire $xor$ls180.v:4939$763_Y
-  attribute \src "ls180.v:4940.361-4940.434"
-  wire $xor$ls180.v:4940$764_Y
-  attribute \src "ls180.v:4940.205-4940.278"
-  wire $xor$ls180.v:4940$765_Y
-  attribute \src "ls180.v:4940.164-4940.279"
-  wire $xor$ls180.v:4940$766_Y
-  attribute \src "ls180.v:4941.361-4941.434"
-  wire $xor$ls180.v:4941$767_Y
-  attribute \src "ls180.v:4941.205-4941.278"
-  wire $xor$ls180.v:4941$768_Y
-  attribute \src "ls180.v:4941.164-4941.279"
-  wire $xor$ls180.v:4941$769_Y
-  attribute \src "ls180.v:4942.361-4942.434"
-  wire $xor$ls180.v:4942$770_Y
-  attribute \src "ls180.v:4942.205-4942.278"
-  wire $xor$ls180.v:4942$771_Y
-  attribute \src "ls180.v:4942.164-4942.279"
-  wire $xor$ls180.v:4942$772_Y
-  attribute \src "ls180.v:4943.361-4943.434"
-  wire $xor$ls180.v:4943$773_Y
-  attribute \src "ls180.v:4943.205-4943.278"
-  wire $xor$ls180.v:4943$774_Y
-  attribute \src "ls180.v:4943.164-4943.279"
-  wire $xor$ls180.v:4943$775_Y
-  attribute \src "ls180.v:4944.361-4944.434"
-  wire $xor$ls180.v:4944$776_Y
-  attribute \src "ls180.v:4944.205-4944.278"
-  wire $xor$ls180.v:4944$777_Y
-  attribute \src "ls180.v:4944.164-4944.279"
-  wire $xor$ls180.v:4944$778_Y
-  attribute \src "ls180.v:4945.361-4945.434"
-  wire $xor$ls180.v:4945$779_Y
-  attribute \src "ls180.v:4945.205-4945.278"
-  wire $xor$ls180.v:4945$780_Y
-  attribute \src "ls180.v:4945.164-4945.279"
-  wire $xor$ls180.v:4945$781_Y
-  attribute \src "ls180.v:4946.361-4946.434"
-  wire $xor$ls180.v:4946$782_Y
-  attribute \src "ls180.v:4946.205-4946.278"
-  wire $xor$ls180.v:4946$783_Y
-  attribute \src "ls180.v:4946.164-4946.279"
-  wire $xor$ls180.v:4946$784_Y
-  attribute \src "ls180.v:4947.361-4947.434"
-  wire $xor$ls180.v:4947$785_Y
-  attribute \src "ls180.v:4947.205-4947.278"
-  wire $xor$ls180.v:4947$786_Y
-  attribute \src "ls180.v:4947.164-4947.279"
-  wire $xor$ls180.v:4947$787_Y
-  attribute \src "ls180.v:4948.361-4948.434"
-  wire $xor$ls180.v:4948$788_Y
-  attribute \src "ls180.v:4948.205-4948.278"
-  wire $xor$ls180.v:4948$789_Y
-  attribute \src "ls180.v:4948.164-4948.279"
-  wire $xor$ls180.v:4948$790_Y
-  attribute \src "ls180.v:4949.361-4949.434"
-  wire $xor$ls180.v:4949$791_Y
-  attribute \src "ls180.v:4949.205-4949.278"
-  wire $xor$ls180.v:4949$792_Y
-  attribute \src "ls180.v:4949.164-4949.279"
-  wire $xor$ls180.v:4949$793_Y
-  attribute \src "ls180.v:4950.361-4950.434"
-  wire $xor$ls180.v:4950$794_Y
-  attribute \src "ls180.v:4950.205-4950.278"
-  wire $xor$ls180.v:4950$795_Y
-  attribute \src "ls180.v:4950.164-4950.279"
-  wire $xor$ls180.v:4950$796_Y
-  attribute \src "ls180.v:4951.361-4951.434"
-  wire $xor$ls180.v:4951$797_Y
-  attribute \src "ls180.v:4951.205-4951.278"
-  wire $xor$ls180.v:4951$798_Y
-  attribute \src "ls180.v:4951.164-4951.279"
-  wire $xor$ls180.v:4951$799_Y
-  attribute \src "ls180.v:4952.360-4952.432"
-  wire $xor$ls180.v:4952$800_Y
-  attribute \src "ls180.v:4952.205-4952.277"
-  wire $xor$ls180.v:4952$801_Y
-  attribute \src "ls180.v:4952.164-4952.278"
-  wire $xor$ls180.v:4952$802_Y
-  attribute \src "ls180.v:4953.360-4953.432"
-  wire $xor$ls180.v:4953$803_Y
-  attribute \src "ls180.v:4953.205-4953.277"
-  wire $xor$ls180.v:4953$804_Y
-  attribute \src "ls180.v:4953.164-4953.278"
-  wire $xor$ls180.v:4953$805_Y
-  attribute \src "ls180.v:4954.360-4954.432"
-  wire $xor$ls180.v:4954$806_Y
-  attribute \src "ls180.v:4954.205-4954.277"
-  wire $xor$ls180.v:4954$807_Y
-  attribute \src "ls180.v:4954.164-4954.278"
-  wire $xor$ls180.v:4954$808_Y
-  attribute \src "ls180.v:4955.360-4955.432"
-  wire $xor$ls180.v:4955$809_Y
-  attribute \src "ls180.v:4955.205-4955.277"
-  wire $xor$ls180.v:4955$810_Y
-  attribute \src "ls180.v:4955.164-4955.278"
-  wire $xor$ls180.v:4955$811_Y
-  attribute \src "ls180.v:4956.360-4956.432"
-  wire $xor$ls180.v:4956$812_Y
-  attribute \src "ls180.v:4956.205-4956.277"
-  wire $xor$ls180.v:4956$813_Y
-  attribute \src "ls180.v:4956.164-4956.278"
-  wire $xor$ls180.v:4956$814_Y
-  attribute \src "ls180.v:4957.360-4957.432"
-  wire $xor$ls180.v:4957$815_Y
-  attribute \src "ls180.v:4957.205-4957.277"
-  wire $xor$ls180.v:4957$816_Y
-  attribute \src "ls180.v:4957.164-4957.278"
-  wire $xor$ls180.v:4957$817_Y
-  attribute \src "ls180.v:4958.360-4958.432"
-  wire $xor$ls180.v:4958$818_Y
-  attribute \src "ls180.v:4958.205-4958.277"
-  wire $xor$ls180.v:4958$819_Y
-  attribute \src "ls180.v:4958.164-4958.278"
-  wire $xor$ls180.v:4958$820_Y
-  attribute \src "ls180.v:4959.360-4959.432"
-  wire $xor$ls180.v:4959$821_Y
-  attribute \src "ls180.v:4959.205-4959.277"
-  wire $xor$ls180.v:4959$822_Y
-  attribute \src "ls180.v:4959.164-4959.278"
-  wire $xor$ls180.v:4959$823_Y
-  attribute \src "ls180.v:4960.360-4960.432"
-  wire $xor$ls180.v:4960$824_Y
-  attribute \src "ls180.v:4960.205-4960.277"
-  wire $xor$ls180.v:4960$825_Y
-  attribute \src "ls180.v:4960.164-4960.278"
-  wire $xor$ls180.v:4960$826_Y
-  attribute \src "ls180.v:4961.360-4961.432"
-  wire $xor$ls180.v:4961$827_Y
-  attribute \src "ls180.v:4961.205-4961.277"
-  wire $xor$ls180.v:4961$828_Y
-  attribute \src "ls180.v:4961.164-4961.278"
-  wire $xor$ls180.v:4961$829_Y
-  attribute \src "ls180.v:4982.899-4982.983"
-  wire $xor$ls180.v:4982$843_Y
-  attribute \src "ls180.v:4982.634-4982.718"
-  wire $xor$ls180.v:4982$844_Y
-  attribute \src "ls180.v:4982.588-4982.719"
-  wire $xor$ls180.v:4982$845_Y
-  attribute \src "ls180.v:4982.234-4982.318"
-  wire $xor$ls180.v:4982$846_Y
-  attribute \src "ls180.v:4982.187-4982.319"
-  wire $xor$ls180.v:4982$847_Y
-  attribute \src "ls180.v:4983.899-4983.983"
-  wire $xor$ls180.v:4983$848_Y
-  attribute \src "ls180.v:4983.634-4983.718"
-  wire $xor$ls180.v:4983$849_Y
-  attribute \src "ls180.v:4983.588-4983.719"
-  wire $xor$ls180.v:4983$850_Y
-  attribute \src "ls180.v:4983.234-4983.318"
-  wire $xor$ls180.v:4983$851_Y
-  attribute \src "ls180.v:4983.187-4983.319"
-  wire $xor$ls180.v:4983$852_Y
-  attribute \src "ls180.v:4992.899-4992.983"
-  wire $xor$ls180.v:4992$854_Y
-  attribute \src "ls180.v:4992.634-4992.718"
-  wire $xor$ls180.v:4992$855_Y
-  attribute \src "ls180.v:4992.588-4992.719"
-  wire $xor$ls180.v:4992$856_Y
-  attribute \src "ls180.v:4992.234-4992.318"
-  wire $xor$ls180.v:4992$857_Y
-  attribute \src "ls180.v:4992.187-4992.319"
-  wire $xor$ls180.v:4992$858_Y
-  attribute \src "ls180.v:4993.899-4993.983"
-  wire $xor$ls180.v:4993$859_Y
-  attribute \src "ls180.v:4993.634-4993.718"
-  wire $xor$ls180.v:4993$860_Y
-  attribute \src "ls180.v:4993.588-4993.719"
-  wire $xor$ls180.v:4993$861_Y
-  attribute \src "ls180.v:4993.234-4993.318"
-  wire $xor$ls180.v:4993$862_Y
-  attribute \src "ls180.v:4993.187-4993.319"
-  wire $xor$ls180.v:4993$863_Y
-  attribute \src "ls180.v:5002.899-5002.983"
-  wire $xor$ls180.v:5002$865_Y
-  attribute \src "ls180.v:5002.634-5002.718"
-  wire $xor$ls180.v:5002$866_Y
-  attribute \src "ls180.v:5002.588-5002.719"
-  wire $xor$ls180.v:5002$867_Y
-  attribute \src "ls180.v:5002.234-5002.318"
-  wire $xor$ls180.v:5002$868_Y
-  attribute \src "ls180.v:5002.187-5002.319"
-  wire $xor$ls180.v:5002$869_Y
-  attribute \src "ls180.v:5003.899-5003.983"
-  wire $xor$ls180.v:5003$870_Y
-  attribute \src "ls180.v:5003.634-5003.718"
-  wire $xor$ls180.v:5003$871_Y
-  attribute \src "ls180.v:5003.588-5003.719"
-  wire $xor$ls180.v:5003$872_Y
-  attribute \src "ls180.v:5003.234-5003.318"
-  wire $xor$ls180.v:5003$873_Y
-  attribute \src "ls180.v:5003.187-5003.319"
-  wire $xor$ls180.v:5003$874_Y
-  attribute \src "ls180.v:5012.899-5012.983"
-  wire $xor$ls180.v:5012$876_Y
-  attribute \src "ls180.v:5012.634-5012.718"
-  wire $xor$ls180.v:5012$877_Y
-  attribute \src "ls180.v:5012.588-5012.719"
-  wire $xor$ls180.v:5012$878_Y
-  attribute \src "ls180.v:5012.234-5012.318"
-  wire $xor$ls180.v:5012$879_Y
-  attribute \src "ls180.v:5012.187-5012.319"
-  wire $xor$ls180.v:5012$880_Y
-  attribute \src "ls180.v:5013.899-5013.983"
-  wire $xor$ls180.v:5013$881_Y
-  attribute \src "ls180.v:5013.634-5013.718"
-  wire $xor$ls180.v:5013$882_Y
-  attribute \src "ls180.v:5013.588-5013.719"
-  wire $xor$ls180.v:5013$883_Y
-  attribute \src "ls180.v:5013.234-5013.318"
-  wire $xor$ls180.v:5013$884_Y
-  attribute \src "ls180.v:5013.187-5013.319"
-  wire $xor$ls180.v:5013$885_Y
-  attribute \src "ls180.v:5164.879-5164.961"
-  wire $xor$ls180.v:5164$918_Y
-  attribute \src "ls180.v:5164.620-5164.702"
-  wire $xor$ls180.v:5164$919_Y
-  attribute \src "ls180.v:5164.575-5164.703"
-  wire $xor$ls180.v:5164$920_Y
-  attribute \src "ls180.v:5164.229-5164.311"
-  wire $xor$ls180.v:5164$921_Y
-  attribute \src "ls180.v:5164.183-5164.312"
-  wire $xor$ls180.v:5164$922_Y
-  attribute \src "ls180.v:5165.879-5165.961"
-  wire $xor$ls180.v:5165$923_Y
-  attribute \src "ls180.v:5165.620-5165.702"
-  wire $xor$ls180.v:5165$924_Y
-  attribute \src "ls180.v:5165.575-5165.703"
-  wire $xor$ls180.v:5165$925_Y
-  attribute \src "ls180.v:5165.229-5165.311"
-  wire $xor$ls180.v:5165$926_Y
-  attribute \src "ls180.v:5165.183-5165.312"
-  wire $xor$ls180.v:5165$927_Y
-  attribute \src "ls180.v:5174.879-5174.961"
-  wire $xor$ls180.v:5174$929_Y
-  attribute \src "ls180.v:5174.620-5174.702"
-  wire $xor$ls180.v:5174$930_Y
-  attribute \src "ls180.v:5174.575-5174.703"
-  wire $xor$ls180.v:5174$931_Y
-  attribute \src "ls180.v:5174.229-5174.311"
-  wire $xor$ls180.v:5174$932_Y
-  attribute \src "ls180.v:5174.183-5174.312"
-  wire $xor$ls180.v:5174$933_Y
-  attribute \src "ls180.v:5175.879-5175.961"
-  wire $xor$ls180.v:5175$934_Y
-  attribute \src "ls180.v:5175.620-5175.702"
-  wire $xor$ls180.v:5175$935_Y
-  attribute \src "ls180.v:5175.575-5175.703"
-  wire $xor$ls180.v:5175$936_Y
-  attribute \src "ls180.v:5175.229-5175.311"
-  wire $xor$ls180.v:5175$937_Y
-  attribute \src "ls180.v:5175.183-5175.312"
-  wire $xor$ls180.v:5175$938_Y
-  attribute \src "ls180.v:5184.879-5184.961"
-  wire $xor$ls180.v:5184$940_Y
-  attribute \src "ls180.v:5184.620-5184.702"
-  wire $xor$ls180.v:5184$941_Y
-  attribute \src "ls180.v:5184.575-5184.703"
-  wire $xor$ls180.v:5184$942_Y
-  attribute \src "ls180.v:5184.229-5184.311"
-  wire $xor$ls180.v:5184$943_Y
-  attribute \src "ls180.v:5184.183-5184.312"
-  wire $xor$ls180.v:5184$944_Y
-  attribute \src "ls180.v:5185.879-5185.961"
-  wire $xor$ls180.v:5185$945_Y
-  attribute \src "ls180.v:5185.620-5185.702"
-  wire $xor$ls180.v:5185$946_Y
-  attribute \src "ls180.v:5185.575-5185.703"
-  wire $xor$ls180.v:5185$947_Y
-  attribute \src "ls180.v:5185.229-5185.311"
-  wire $xor$ls180.v:5185$948_Y
-  attribute \src "ls180.v:5185.183-5185.312"
-  wire $xor$ls180.v:5185$949_Y
-  attribute \src "ls180.v:5194.879-5194.961"
-  wire $xor$ls180.v:5194$951_Y
-  attribute \src "ls180.v:5194.620-5194.702"
-  wire $xor$ls180.v:5194$952_Y
-  attribute \src "ls180.v:5194.575-5194.703"
-  wire $xor$ls180.v:5194$953_Y
-  attribute \src "ls180.v:5194.229-5194.311"
-  wire $xor$ls180.v:5194$954_Y
-  attribute \src "ls180.v:5194.183-5194.312"
-  wire $xor$ls180.v:5194$955_Y
-  attribute \src "ls180.v:5195.879-5195.961"
-  wire $xor$ls180.v:5195$956_Y
-  attribute \src "ls180.v:5195.620-5195.702"
-  wire $xor$ls180.v:5195$957_Y
-  attribute \src "ls180.v:5195.575-5195.703"
-  wire $xor$ls180.v:5195$958_Y
-  attribute \src "ls180.v:5195.229-5195.311"
-  wire $xor$ls180.v:5195$959_Y
-  attribute \src "ls180.v:5195.183-5195.312"
-  wire $xor$ls180.v:5195$960_Y
-  attribute \src "ls180.v:1745.11-1745.42"
+  wire $not$ls180.v:6163$1686_Y
+  attribute \src "ls180.v:6166.67-6166.98"
+  wire $not$ls180.v:6166$1693_Y
+  attribute \src "ls180.v:6169.70-6169.101"
+  wire $not$ls180.v:6169$1700_Y
+  attribute \src "ls180.v:6172.70-6172.101"
+  wire $not$ls180.v:6172$1707_Y
+  attribute \src "ls180.v:6175.69-6175.100"
+  wire $not$ls180.v:6175$1714_Y
+  attribute \src "ls180.v:6178.69-6178.100"
+  wire $not$ls180.v:6178$1721_Y
+  attribute \src "ls180.v:6181.69-6181.100"
+  wire $not$ls180.v:6181$1728_Y
+  attribute \src "ls180.v:6184.69-6184.100"
+  wire $not$ls180.v:6184$1735_Y
+  attribute \src "ls180.v:6223.66-6223.97"
+  wire $not$ls180.v:6223$1743_Y
+  attribute \src "ls180.v:6226.66-6226.97"
+  wire $not$ls180.v:6226$1750_Y
+  attribute \src "ls180.v:6229.66-6229.97"
+  wire $not$ls180.v:6229$1757_Y
+  attribute \src "ls180.v:6232.66-6232.97"
+  wire $not$ls180.v:6232$1764_Y
+  attribute \src "ls180.v:6235.66-6235.97"
+  wire $not$ls180.v:6235$1771_Y
+  attribute \src "ls180.v:6238.66-6238.97"
+  wire $not$ls180.v:6238$1778_Y
+  attribute \src "ls180.v:6241.66-6241.97"
+  wire $not$ls180.v:6241$1785_Y
+  attribute \src "ls180.v:6244.66-6244.97"
+  wire $not$ls180.v:6244$1792_Y
+  attribute \src "ls180.v:6247.68-6247.99"
+  wire $not$ls180.v:6247$1799_Y
+  attribute \src "ls180.v:6250.68-6250.99"
+  wire $not$ls180.v:6250$1806_Y
+  attribute \src "ls180.v:6253.68-6253.99"
+  wire $not$ls180.v:6253$1813_Y
+  attribute \src "ls180.v:6256.68-6256.99"
+  wire $not$ls180.v:6256$1820_Y
+  attribute \src "ls180.v:6259.68-6259.99"
+  wire $not$ls180.v:6259$1827_Y
+  attribute \src "ls180.v:6262.65-6262.96"
+  wire $not$ls180.v:6262$1834_Y
+  attribute \src "ls180.v:6265.66-6265.97"
+  wire $not$ls180.v:6265$1841_Y
+  attribute \src "ls180.v:6268.68-6268.99"
+  wire $not$ls180.v:6268$1848_Y
+  attribute \src "ls180.v:6271.68-6271.99"
+  wire $not$ls180.v:6271$1855_Y
+  attribute \src "ls180.v:6274.68-6274.99"
+  wire $not$ls180.v:6274$1862_Y
+  attribute \src "ls180.v:6277.68-6277.99"
+  wire $not$ls180.v:6277$1869_Y
+  attribute \src "ls180.v:6302.68-6302.99"
+  wire $not$ls180.v:6302$1877_Y
+  attribute \src "ls180.v:6305.73-6305.104"
+  wire $not$ls180.v:6305$1884_Y
+  attribute \src "ls180.v:6308.73-6308.104"
+  wire $not$ls180.v:6308$1891_Y
+  attribute \src "ls180.v:6311.66-6311.97"
+  wire $not$ls180.v:6311$1898_Y
+  attribute \src "ls180.v:6319.70-6319.101"
+  wire $not$ls180.v:6319$1906_Y
+  attribute \src "ls180.v:6322.74-6322.105"
+  wire $not$ls180.v:6322$1913_Y
+  attribute \src "ls180.v:6325.64-6325.95"
+  wire $not$ls180.v:6325$1920_Y
+  attribute \src "ls180.v:6328.74-6328.105"
+  wire $not$ls180.v:6328$1927_Y
+  attribute \src "ls180.v:6331.74-6331.105"
+  wire $not$ls180.v:6331$1934_Y
+  attribute \src "ls180.v:6334.75-6334.106"
+  wire $not$ls180.v:6334$1941_Y
+  attribute \src "ls180.v:6337.73-6337.104"
+  wire $not$ls180.v:6337$1948_Y
+  attribute \src "ls180.v:6340.73-6340.104"
+  wire $not$ls180.v:6340$1955_Y
+  attribute \src "ls180.v:6343.73-6343.104"
+  wire $not$ls180.v:6343$1962_Y
+  attribute \src "ls180.v:6346.73-6346.104"
+  wire $not$ls180.v:6346$1969_Y
+  attribute \src "ls180.v:6364.67-6364.99"
+  wire $not$ls180.v:6364$1977_Y
+  attribute \src "ls180.v:6367.67-6367.99"
+  wire $not$ls180.v:6367$1984_Y
+  attribute \src "ls180.v:6370.65-6370.97"
+  wire $not$ls180.v:6370$1991_Y
+  attribute \src "ls180.v:6373.64-6373.96"
+  wire $not$ls180.v:6373$1998_Y
+  attribute \src "ls180.v:6376.63-6376.95"
+  wire $not$ls180.v:6376$2005_Y
+  attribute \src "ls180.v:6379.62-6379.94"
+  wire $not$ls180.v:6379$2012_Y
+  attribute \src "ls180.v:6382.68-6382.100"
+  wire $not$ls180.v:6382$2019_Y
+  attribute \src "ls180.v:6404.67-6404.99"
+  wire $not$ls180.v:6404$2028_Y
+  attribute \src "ls180.v:6407.67-6407.99"
+  wire $not$ls180.v:6407$2035_Y
+  attribute \src "ls180.v:6410.65-6410.97"
+  wire $not$ls180.v:6410$2042_Y
+  attribute \src "ls180.v:6413.64-6413.96"
+  wire $not$ls180.v:6413$2049_Y
+  attribute \src "ls180.v:6416.63-6416.95"
+  wire $not$ls180.v:6416$2056_Y
+  attribute \src "ls180.v:6419.62-6419.94"
+  wire $not$ls180.v:6419$2063_Y
+  attribute \src "ls180.v:6422.68-6422.100"
+  wire $not$ls180.v:6422$2070_Y
+  attribute \src "ls180.v:6425.71-6425.103"
+  wire $not$ls180.v:6425$2077_Y
+  attribute \src "ls180.v:6428.71-6428.103"
+  wire $not$ls180.v:6428$2084_Y
+  attribute \src "ls180.v:6452.64-6452.96"
+  wire $not$ls180.v:6452$2093_Y
+  attribute \src "ls180.v:6455.64-6455.96"
+  wire $not$ls180.v:6455$2100_Y
+  attribute \src "ls180.v:6458.64-6458.96"
+  wire $not$ls180.v:6458$2107_Y
+  attribute \src "ls180.v:6461.64-6461.96"
+  wire $not$ls180.v:6461$2114_Y
+  attribute \src "ls180.v:6464.66-6464.98"
+  wire $not$ls180.v:6464$2121_Y
+  attribute \src "ls180.v:6467.66-6467.98"
+  wire $not$ls180.v:6467$2128_Y
+  attribute \src "ls180.v:6470.66-6470.98"
+  wire $not$ls180.v:6470$2135_Y
+  attribute \src "ls180.v:6473.66-6473.98"
+  wire $not$ls180.v:6473$2142_Y
+  attribute \src "ls180.v:6476.62-6476.94"
+  wire $not$ls180.v:6476$2149_Y
+  attribute \src "ls180.v:6479.72-6479.104"
+  wire $not$ls180.v:6479$2156_Y
+  attribute \src "ls180.v:6482.65-6482.97"
+  wire $not$ls180.v:6482$2163_Y
+  attribute \src "ls180.v:6485.65-6485.97"
+  wire $not$ls180.v:6485$2170_Y
+  attribute \src "ls180.v:6488.65-6488.97"
+  wire $not$ls180.v:6488$2177_Y
+  attribute \src "ls180.v:6491.65-6491.97"
+  wire $not$ls180.v:6491$2184_Y
+  attribute \src "ls180.v:6494.77-6494.109"
+  wire $not$ls180.v:6494$2191_Y
+  attribute \src "ls180.v:6497.78-6497.110"
+  wire $not$ls180.v:6497$2198_Y
+  attribute \src "ls180.v:6500.69-6500.101"
+  wire $not$ls180.v:6500$2205_Y
+  attribute \src "ls180.v:6520.55-6520.87"
+  wire $not$ls180.v:6520$2213_Y
+  attribute \src "ls180.v:6523.65-6523.97"
+  wire $not$ls180.v:6523$2220_Y
+  attribute \src "ls180.v:6526.66-6526.98"
+  wire $not$ls180.v:6526$2227_Y
+  attribute \src "ls180.v:6529.70-6529.102"
+  wire $not$ls180.v:6529$2234_Y
+  attribute \src "ls180.v:6532.71-6532.103"
+  wire $not$ls180.v:6532$2241_Y
+  attribute \src "ls180.v:6535.69-6535.101"
+  wire $not$ls180.v:6535$2248_Y
+  attribute \src "ls180.v:6538.66-6538.98"
+  wire $not$ls180.v:6538$2255_Y
+  attribute \src "ls180.v:6541.65-6541.97"
+  wire $not$ls180.v:6541$2262_Y
+  attribute \src "ls180.v:6554.71-6554.103"
+  wire $not$ls180.v:6554$2270_Y
+  attribute \src "ls180.v:6557.71-6557.103"
+  wire $not$ls180.v:6557$2277_Y
+  attribute \src "ls180.v:6560.71-6560.103"
+  wire $not$ls180.v:6560$2284_Y
+  attribute \src "ls180.v:6563.71-6563.103"
+  wire $not$ls180.v:6563$2291_Y
+  attribute \src "ls180.v:6944.86-6944.330"
+  wire $not$ls180.v:6944$2340_Y
+  attribute \src "ls180.v:6968.86-6968.330"
+  wire $not$ls180.v:6968$2356_Y
+  attribute \src "ls180.v:6992.86-6992.330"
+  wire $not$ls180.v:6992$2372_Y
+  attribute \src "ls180.v:7016.86-7016.330"
+  wire $not$ls180.v:7016$2388_Y
+  attribute \src "ls180.v:7514.18-7514.42"
+  wire $not$ls180.v:7514$2441_Y
+  attribute \src "ls180.v:7593.72-7593.101"
+  wire $not$ls180.v:7593$2474_Y
+  attribute \src "ls180.v:7612.8-7612.38"
+  wire $not$ls180.v:7612$2478_Y
+  attribute \src "ls180.v:7616.70-7616.98"
+  wire $not$ls180.v:7616$2481_Y
+  attribute \src "ls180.v:7620.70-7620.98"
+  wire $not$ls180.v:7620$2484_Y
+  attribute \src "ls180.v:7624.70-7624.98"
+  wire $not$ls180.v:7624$2487_Y
+  attribute \src "ls180.v:7632.32-7632.55"
+  wire $not$ls180.v:7632$2489_Y
+  attribute \src "ls180.v:7702.136-7702.189"
+  wire $not$ls180.v:7702$2504_Y
+  attribute \src "ls180.v:7708.136-7708.189"
+  wire $not$ls180.v:7708$2509_Y
+  attribute \src "ls180.v:7709.8-7709.61"
+  wire $not$ls180.v:7709$2511_Y
+  attribute \src "ls180.v:7717.8-7717.56"
+  wire $not$ls180.v:7717$2514_Y
+  attribute \src "ls180.v:7732.8-7732.46"
+  wire $not$ls180.v:7732$2516_Y
+  attribute \src "ls180.v:7748.136-7748.189"
+  wire $not$ls180.v:7748$2520_Y
+  attribute \src "ls180.v:7754.136-7754.189"
+  wire $not$ls180.v:7754$2525_Y
+  attribute \src "ls180.v:7755.8-7755.61"
+  wire $not$ls180.v:7755$2527_Y
+  attribute \src "ls180.v:7763.8-7763.56"
+  wire $not$ls180.v:7763$2530_Y
+  attribute \src "ls180.v:7778.8-7778.46"
+  wire $not$ls180.v:7778$2532_Y
+  attribute \src "ls180.v:7794.136-7794.189"
+  wire $not$ls180.v:7794$2536_Y
+  attribute \src "ls180.v:7800.136-7800.189"
+  wire $not$ls180.v:7800$2541_Y
+  attribute \src "ls180.v:7801.8-7801.61"
+  wire $not$ls180.v:7801$2543_Y
+  attribute \src "ls180.v:7809.8-7809.56"
+  wire $not$ls180.v:7809$2546_Y
+  attribute \src "ls180.v:7824.8-7824.46"
+  wire $not$ls180.v:7824$2548_Y
+  attribute \src "ls180.v:7840.136-7840.189"
+  wire $not$ls180.v:7840$2552_Y
+  attribute \src "ls180.v:7846.136-7846.189"
+  wire $not$ls180.v:7846$2557_Y
+  attribute \src "ls180.v:7847.8-7847.61"
+  wire $not$ls180.v:7847$2559_Y
+  attribute \src "ls180.v:7855.8-7855.56"
+  wire $not$ls180.v:7855$2562_Y
+  attribute \src "ls180.v:7870.8-7870.46"
+  wire $not$ls180.v:7870$2564_Y
+  attribute \src "ls180.v:7878.7-7878.22"
+  wire $not$ls180.v:7878$2567_Y
+  attribute \src "ls180.v:7881.8-7881.29"
+  wire $not$ls180.v:7881$2568_Y
+  attribute \src "ls180.v:7885.7-7885.22"
+  wire $not$ls180.v:7885$2570_Y
+  attribute \src "ls180.v:7888.8-7888.29"
+  wire $not$ls180.v:7888$2571_Y
+  attribute \src "ls180.v:8007.30-8007.60"
+  wire $not$ls180.v:8007$2573_Y
+  attribute \src "ls180.v:8008.30-8008.60"
+  wire $not$ls180.v:8008$2574_Y
+  attribute \src "ls180.v:8009.29-8009.59"
+  wire $not$ls180.v:8009$2575_Y
+  attribute \src "ls180.v:8020.8-8020.33"
+  wire $not$ls180.v:8020$2576_Y
+  attribute \src "ls180.v:8035.8-8035.33"
+  wire $not$ls180.v:8035$2579_Y
+  attribute \src "ls180.v:8071.36-8071.58"
+  wire $not$ls180.v:8071$2609_Y
+  attribute \src "ls180.v:8071.64-8071.89"
+  wire $not$ls180.v:8071$2611_Y
+  attribute \src "ls180.v:8100.7-8100.29"
+  wire $not$ls180.v:8100$2618_Y
+  attribute \src "ls180.v:8101.9-8101.26"
+  wire $not$ls180.v:8101$2619_Y
+  attribute \src "ls180.v:8134.8-8134.29"
+  wire $not$ls180.v:8134$2625_Y
+  attribute \src "ls180.v:8141.8-8141.29"
+  wire $not$ls180.v:8141$2627_Y
+  attribute \src "ls180.v:8151.80-8151.106"
+  wire $not$ls180.v:8151$2630_Y
+  attribute \src "ls180.v:8157.80-8157.106"
+  wire $not$ls180.v:8157$2635_Y
+  attribute \src "ls180.v:8158.8-8158.34"
+  wire $not$ls180.v:8158$2637_Y
+  attribute \src "ls180.v:8173.80-8173.106"
+  wire $not$ls180.v:8173$2641_Y
+  attribute \src "ls180.v:8179.80-8179.106"
+  wire $not$ls180.v:8179$2646_Y
+  attribute \src "ls180.v:8180.8-8180.34"
+  wire $not$ls180.v:8180$2648_Y
+  attribute \src "ls180.v:8211.22-8211.41"
+  wire $not$ls180.v:8211$2652_Y
+  attribute \src "ls180.v:8211.46-8211.73"
+  wire $not$ls180.v:8211$2653_Y
+  attribute \src "ls180.v:8246.22-8246.40"
+  wire $not$ls180.v:8246$2657_Y
+  attribute \src "ls180.v:8246.45-8246.70"
+  wire $not$ls180.v:8246$2658_Y
+  attribute \src "ls180.v:8300.7-8300.31"
+  wire $not$ls180.v:8300$2669_Y
+  attribute \src "ls180.v:8372.8-8372.46"
+  wire $not$ls180.v:8372$2681_Y
+  attribute \src "ls180.v:8453.8-8453.47"
+  wire $not$ls180.v:8453$2693_Y
+  attribute \src "ls180.v:8514.8-8514.48"
+  wire $not$ls180.v:8514$2705_Y
+  attribute \src "ls180.v:8684.88-8684.118"
+  wire $not$ls180.v:8684$2719_Y
+  attribute \src "ls180.v:8690.88-8690.118"
+  wire $not$ls180.v:8690$2724_Y
+  attribute \src "ls180.v:8691.8-8691.38"
+  wire $not$ls180.v:8691$2726_Y
+  attribute \src "ls180.v:8770.88-8770.118"
+  wire $not$ls180.v:8770$2741_Y
+  attribute \src "ls180.v:8776.88-8776.118"
+  wire $not$ls180.v:8776$2746_Y
+  attribute \src "ls180.v:8777.8-8777.38"
+  wire $not$ls180.v:8777$2748_Y
+  attribute \src "ls180.v:8797.9-8797.28"
+  wire $not$ls180.v:8797$2751_Y
+  attribute \src "ls180.v:8816.9-8816.28"
+  wire $not$ls180.v:8816$2752_Y
+  attribute \src "ls180.v:8835.9-8835.28"
+  wire $not$ls180.v:8835$2753_Y
+  attribute \src "ls180.v:8854.9-8854.28"
+  wire $not$ls180.v:8854$2754_Y
+  attribute \src "ls180.v:8873.9-8873.28"
+  wire $not$ls180.v:8873$2755_Y
+  attribute \src "ls180.v:8894.8-8894.21"
+  wire $not$ls180.v:8894$2756_Y
+  attribute \src "ls180.v:10456.8-10456.51"
+  wire $or$ls180.v:10456$2870_Y
+  attribute \src "ls180.v:2859.10-2859.96"
+  wire $or$ls180.v:2859$33_Y
+  attribute \src "ls180.v:2919.10-2919.96"
+  wire $or$ls180.v:2919$44_Y
+  attribute \src "ls180.v:2979.10-2979.96"
+  wire $or$ls180.v:2979$55_Y
+  attribute \src "ls180.v:3201.39-3201.105"
+  wire $or$ls180.v:3201$126_Y
+  attribute \src "ls180.v:3244.59-3244.140"
+  wire $or$ls180.v:3244$130_Y
+  attribute \src "ls180.v:3245.44-3245.151"
+  wire $or$ls180.v:3245$131_Y
+  attribute \src "ls180.v:3253.45-3253.170"
+  wire width 13 $or$ls180.v:3253$135_Y
+  attribute \src "ls180.v:3290.127-3290.245"
+  wire $or$ls180.v:3290$148_Y
+  attribute \src "ls180.v:3296.57-3296.157"
+  wire $or$ls180.v:3296$154_Y
+  attribute \src "ls180.v:3401.59-3401.140"
+  wire $or$ls180.v:3401$160_Y
+  attribute \src "ls180.v:3402.44-3402.151"
+  wire $or$ls180.v:3402$161_Y
+  attribute \src "ls180.v:3410.45-3410.170"
+  wire width 13 $or$ls180.v:3410$165_Y
+  attribute \src "ls180.v:3447.127-3447.245"
+  wire $or$ls180.v:3447$178_Y
+  attribute \src "ls180.v:3453.57-3453.157"
+  wire $or$ls180.v:3453$184_Y
+  attribute \src "ls180.v:3558.59-3558.140"
+  wire $or$ls180.v:3558$190_Y
+  attribute \src "ls180.v:3559.44-3559.151"
+  wire $or$ls180.v:3559$191_Y
+  attribute \src "ls180.v:3567.45-3567.170"
+  wire width 13 $or$ls180.v:3567$195_Y
+  attribute \src "ls180.v:3604.127-3604.245"
+  wire $or$ls180.v:3604$208_Y
+  attribute \src "ls180.v:3610.57-3610.157"
+  wire $or$ls180.v:3610$214_Y
+  attribute \src "ls180.v:3715.59-3715.140"
+  wire $or$ls180.v:3715$220_Y
+  attribute \src "ls180.v:3716.44-3716.151"
+  wire $or$ls180.v:3716$221_Y
+  attribute \src "ls180.v:3724.45-3724.170"
+  wire width 13 $or$ls180.v:3724$225_Y
+  attribute \src "ls180.v:3761.127-3761.245"
+  wire $or$ls180.v:3761$238_Y
+  attribute \src "ls180.v:3767.57-3767.157"
+  wire $or$ls180.v:3767$244_Y
+  attribute \src "ls180.v:3866.107-3866.193"
+  wire $or$ls180.v:3866$264_Y
+  attribute \src "ls180.v:3869.39-3869.204"
+  wire $or$ls180.v:3869$270_Y
+  attribute \src "ls180.v:3869.38-3869.289"
+  wire $or$ls180.v:3869$272_Y
+  attribute \src "ls180.v:3869.37-3869.374"
+  wire $or$ls180.v:3869$274_Y
+  attribute \src "ls180.v:3870.40-3870.207"
+  wire $or$ls180.v:3870$277_Y
+  attribute \src "ls180.v:3870.39-3870.293"
+  wire $or$ls180.v:3870$279_Y
+  attribute \src "ls180.v:3870.38-3870.379"
+  wire $or$ls180.v:3870$281_Y
+  attribute \src "ls180.v:3883.158-3883.332"
+  wire $or$ls180.v:3883$295_Y
+  attribute \src "ls180.v:3883.75-3883.506"
+  wire $or$ls180.v:3883$300_Y
+  attribute \src "ls180.v:3884.158-3884.332"
+  wire $or$ls180.v:3884$308_Y
+  attribute \src "ls180.v:3884.75-3884.506"
+  wire $or$ls180.v:3884$313_Y
+  attribute \src "ls180.v:3885.158-3885.332"
+  wire $or$ls180.v:3885$321_Y
+  attribute \src "ls180.v:3885.75-3885.506"
+  wire $or$ls180.v:3885$326_Y
+  attribute \src "ls180.v:3886.158-3886.332"
+  wire $or$ls180.v:3886$334_Y
+  attribute \src "ls180.v:3886.75-3886.506"
+  wire $or$ls180.v:3886$339_Y
+  attribute \src "ls180.v:3913.36-3913.104"
+  wire $or$ls180.v:3913$345_Y
+  attribute \src "ls180.v:3916.158-3916.332"
+  wire $or$ls180.v:3916$353_Y
+  attribute \src "ls180.v:3916.75-3916.506"
+  wire $or$ls180.v:3916$358_Y
+  attribute \src "ls180.v:3917.158-3917.332"
+  wire $or$ls180.v:3917$366_Y
+  attribute \src "ls180.v:3917.75-3917.506"
+  wire $or$ls180.v:3917$371_Y
+  attribute \src "ls180.v:3918.158-3918.332"
+  wire $or$ls180.v:3918$379_Y
+  attribute \src "ls180.v:3918.75-3918.506"
+  wire $or$ls180.v:3918$384_Y
+  attribute \src "ls180.v:3919.158-3919.332"
+  wire $or$ls180.v:3919$392_Y
+  attribute \src "ls180.v:3919.75-3919.506"
+  wire $or$ls180.v:3919$397_Y
+  attribute \src "ls180.v:3982.36-3982.104"
+  wire $or$ls180.v:3982$431_Y
+  attribute \src "ls180.v:4003.67-4003.221"
+  wire $or$ls180.v:4003$438_Y
+  attribute \src "ls180.v:4011.10-4011.62"
+  wire $or$ls180.v:4011$441_Y
+  attribute \src "ls180.v:4041.67-4041.221"
+  wire $or$ls180.v:4041$447_Y
+  attribute \src "ls180.v:4049.10-4049.61"
+  wire $or$ls180.v:4049$450_Y
+  attribute \src "ls180.v:4059.91-4059.180"
+  wire $or$ls180.v:4059$454_Y
+  attribute \src "ls180.v:4059.90-4059.255"
+  wire $or$ls180.v:4059$457_Y
+  attribute \src "ls180.v:4059.89-4059.330"
+  wire $or$ls180.v:4059$460_Y
+  attribute \src "ls180.v:4064.91-4064.180"
+  wire $or$ls180.v:4064$470_Y
+  attribute \src "ls180.v:4064.90-4064.255"
+  wire $or$ls180.v:4064$473_Y
+  attribute \src "ls180.v:4064.89-4064.330"
+  wire $or$ls180.v:4064$476_Y
+  attribute \src "ls180.v:4069.91-4069.180"
+  wire $or$ls180.v:4069$486_Y
+  attribute \src "ls180.v:4069.90-4069.255"
+  wire $or$ls180.v:4069$489_Y
+  attribute \src "ls180.v:4069.89-4069.330"
+  wire $or$ls180.v:4069$492_Y
+  attribute \src "ls180.v:4074.91-4074.180"
+  wire $or$ls180.v:4074$502_Y
+  attribute \src "ls180.v:4074.90-4074.255"
+  wire $or$ls180.v:4074$505_Y
+  attribute \src "ls180.v:4074.89-4074.330"
+  wire $or$ls180.v:4074$508_Y
+  attribute \src "ls180.v:4079.132-4079.221"
+  wire $or$ls180.v:4079$519_Y
+  attribute \src "ls180.v:4079.131-4079.296"
+  wire $or$ls180.v:4079$522_Y
+  attribute \src "ls180.v:4079.130-4079.371"
+  wire $or$ls180.v:4079$525_Y
+  attribute \src "ls180.v:4079.34-4079.411"
+  wire $or$ls180.v:4079$530_Y
+  attribute \src "ls180.v:4079.506-4079.595"
+  wire $or$ls180.v:4079$535_Y
+  attribute \src "ls180.v:4079.505-4079.670"
+  wire $or$ls180.v:4079$538_Y
+  attribute \src "ls180.v:4079.504-4079.745"
+  wire $or$ls180.v:4079$541_Y
+  attribute \src "ls180.v:4079.33-4079.785"
+  wire $or$ls180.v:4079$546_Y
+  attribute \src "ls180.v:4079.880-4079.969"
+  wire $or$ls180.v:4079$551_Y
+  attribute \src "ls180.v:4079.879-4079.1044"
+  wire $or$ls180.v:4079$554_Y
+  attribute \src "ls180.v:4079.878-4079.1119"
+  wire $or$ls180.v:4079$557_Y
+  attribute \src "ls180.v:4079.32-4079.1159"
+  wire $or$ls180.v:4079$562_Y
+  attribute \src "ls180.v:4079.1254-4079.1343"
+  wire $or$ls180.v:4079$567_Y
+  attribute \src "ls180.v:4079.1253-4079.1418"
+  wire $or$ls180.v:4079$570_Y
+  attribute \src "ls180.v:4079.1252-4079.1493"
+  wire $or$ls180.v:4079$573_Y
+  attribute \src "ls180.v:4079.31-4079.1533"
+  wire $or$ls180.v:4079$578_Y
+  attribute \src "ls180.v:4142.10-4142.52"
+  wire $or$ls180.v:4142$587_Y
+  attribute \src "ls180.v:4169.35-4169.74"
+  wire $or$ls180.v:4169$597_Y
+  attribute \src "ls180.v:4170.34-4170.73"
+  wire $or$ls180.v:4170$601_Y
+  attribute \src "ls180.v:4171.48-4171.130"
+  wire $or$ls180.v:4171$607_Y
+  attribute \src "ls180.v:4172.24-4172.87"
+  wire $or$ls180.v:4172$610_Y
+  attribute \src "ls180.v:4173.26-4173.95"
+  wire $or$ls180.v:4173$612_Y
+  attribute \src "ls180.v:4203.42-4203.89"
+  wire $or$ls180.v:4203$620_Y
+  attribute \src "ls180.v:4227.25-4227.174"
+  wire $or$ls180.v:4227$630_Y
+  attribute \src "ls180.v:4242.80-4242.132"
+  wire $or$ls180.v:4242$632_Y
+  attribute \src "ls180.v:4253.72-4253.135"
+  wire $or$ls180.v:4253$637_Y
+  attribute \src "ls180.v:4272.80-4272.132"
+  wire $or$ls180.v:4272$643_Y
+  attribute \src "ls180.v:4283.72-4283.135"
+  wire $or$ls180.v:4283$648_Y
+  attribute \src "ls180.v:4417.36-4417.111"
+  wire $or$ls180.v:4417$669_Y
+  attribute \src "ls180.v:4417.35-4417.151"
+  wire $or$ls180.v:4417$670_Y
+  attribute \src "ls180.v:4417.34-4417.192"
+  wire $or$ls180.v:4417$671_Y
+  attribute \src "ls180.v:4417.33-4417.233"
+  wire $or$ls180.v:4417$672_Y
+  attribute \src "ls180.v:4418.39-4418.120"
+  wire $or$ls180.v:4418$673_Y
+  attribute \src "ls180.v:4418.38-4418.163"
+  wire $or$ls180.v:4418$674_Y
+  attribute \src "ls180.v:4418.37-4418.207"
+  wire $or$ls180.v:4418$675_Y
+  attribute \src "ls180.v:4418.36-4418.251"
+  wire $or$ls180.v:4418$676_Y
+  attribute \src "ls180.v:4419.38-4419.117"
+  wire $or$ls180.v:4419$677_Y
+  attribute \src "ls180.v:4419.37-4419.159"
+  wire $or$ls180.v:4419$678_Y
+  attribute \src "ls180.v:4419.36-4419.202"
+  wire $or$ls180.v:4419$679_Y
+  attribute \src "ls180.v:4419.35-4419.245"
+  wire $or$ls180.v:4419$680_Y
+  attribute \src "ls180.v:4420.40-4420.123"
+  wire $or$ls180.v:4420$681_Y
+  attribute \src "ls180.v:4420.39-4420.167"
+  wire $or$ls180.v:4420$682_Y
+  attribute \src "ls180.v:4420.38-4420.212"
+  wire $or$ls180.v:4420$683_Y
+  attribute \src "ls180.v:4420.37-4420.257"
+  wire $or$ls180.v:4420$684_Y
+  attribute \src "ls180.v:4421.39-4421.120"
+  wire width 4 $or$ls180.v:4421$685_Y
+  attribute \src "ls180.v:4421.38-4421.163"
+  wire width 4 $or$ls180.v:4421$686_Y
+  attribute \src "ls180.v:4421.37-4421.207"
+  wire width 4 $or$ls180.v:4421$687_Y
+  attribute \src "ls180.v:4421.36-4421.251"
+  wire width 4 $or$ls180.v:4421$688_Y
+  attribute \src "ls180.v:4442.35-4442.80"
+  wire $or$ls180.v:4442$689_Y
+  attribute \src "ls180.v:4596.91-4596.144"
+  wire $or$ls180.v:4596$703_Y
+  attribute \src "ls180.v:4613.53-4613.143"
+  wire $or$ls180.v:4613$706_Y
+  attribute \src "ls180.v:4616.47-4616.127"
+  wire $or$ls180.v:4616$709_Y
+  attribute \src "ls180.v:4740.54-4740.146"
+  wire $or$ls180.v:4740$727_Y
+  attribute \src "ls180.v:4743.48-4743.130"
+  wire $or$ls180.v:4743$730_Y
+  attribute \src "ls180.v:4874.55-4874.149"
+  wire $or$ls180.v:4874$742_Y
+  attribute \src "ls180.v:4877.49-4877.133"
+  wire $or$ls180.v:4877$745_Y
+  attribute \src "ls180.v:5506.80-5506.151"
+  wire $or$ls180.v:5506$1040_Y
+  attribute \src "ls180.v:5517.49-5517.131"
+  wire $or$ls180.v:5517$1046_Y
+  attribute \src "ls180.v:5714.80-5714.151"
+  wire $or$ls180.v:5714$1071_Y
+  attribute \src "ls180.v:5856.36-5856.94"
+  wire $or$ls180.v:5856$1117_Y
+  attribute \src "ls180.v:5856.35-5856.125"
+  wire $or$ls180.v:5856$1118_Y
+  attribute \src "ls180.v:5856.34-5856.156"
+  wire $or$ls180.v:5856$1119_Y
+  attribute \src "ls180.v:5856.33-5856.198"
+  wire $or$ls180.v:5856$1120_Y
+  attribute \src "ls180.v:5856.32-5856.240"
+  wire $or$ls180.v:5856$1121_Y
+  attribute \src "ls180.v:5856.31-5856.261"
+  wire $or$ls180.v:5856$1122_Y
+  attribute \src "ls180.v:5856.30-5856.297"
+  wire $or$ls180.v:5856$1123_Y
+  attribute \src "ls180.v:5862.31-5862.89"
+  wire $or$ls180.v:5862$1128_Y
+  attribute \src "ls180.v:5862.30-5862.120"
+  wire $or$ls180.v:5862$1129_Y
+  attribute \src "ls180.v:5862.29-5862.151"
+  wire $or$ls180.v:5862$1130_Y
+  attribute \src "ls180.v:5862.28-5862.193"
+  wire $or$ls180.v:5862$1131_Y
+  attribute \src "ls180.v:5862.27-5862.235"
+  wire $or$ls180.v:5862$1132_Y
+  attribute \src "ls180.v:5862.26-5862.256"
+  wire $or$ls180.v:5862$1133_Y
+  attribute \src "ls180.v:5862.25-5862.292"
+  wire $or$ls180.v:5862$1134_Y
+  attribute \src "ls180.v:5863.33-5863.161"
+  wire width 32 $or$ls180.v:5863$1137_Y
+  attribute \src "ls180.v:5863.32-5863.227"
+  wire width 32 $or$ls180.v:5863$1139_Y
+  attribute \src "ls180.v:5863.31-5863.293"
+  wire width 32 $or$ls180.v:5863$1141_Y
+  attribute \src "ls180.v:5863.30-5863.370"
+  wire width 32 $or$ls180.v:5863$1143_Y
+  attribute \src "ls180.v:5863.29-5863.447"
+  wire width 32 $or$ls180.v:5863$1145_Y
+  attribute \src "ls180.v:5863.28-5863.503"
+  wire width 32 $or$ls180.v:5863$1147_Y
+  attribute \src "ls180.v:5863.27-5863.574"
+  wire width 32 $or$ls180.v:5863$1149_Y
+  attribute \src "ls180.v:6617.55-6617.124"
+  wire width 8 $or$ls180.v:6617$2295_Y
+  attribute \src "ls180.v:6617.54-6617.161"
+  wire width 8 $or$ls180.v:6617$2296_Y
+  attribute \src "ls180.v:6617.53-6617.198"
+  wire width 8 $or$ls180.v:6617$2297_Y
+  attribute \src "ls180.v:6617.52-6617.235"
+  wire width 8 $or$ls180.v:6617$2298_Y
+  attribute \src "ls180.v:6617.51-6617.272"
+  wire width 8 $or$ls180.v:6617$2299_Y
+  attribute \src "ls180.v:6617.50-6617.309"
+  wire width 8 $or$ls180.v:6617$2300_Y
+  attribute \src "ls180.v:6617.49-6617.346"
+  wire width 8 $or$ls180.v:6617$2301_Y
+  attribute \src "ls180.v:6617.48-6617.383"
+  wire width 8 $or$ls180.v:6617$2302_Y
+  attribute \src "ls180.v:6617.47-6617.420"
+  wire width 8 $or$ls180.v:6617$2303_Y
+  attribute \src "ls180.v:6617.46-6617.458"
+  wire width 8 $or$ls180.v:6617$2304_Y
+  attribute \src "ls180.v:6617.45-6617.496"
+  wire width 8 $or$ls180.v:6617$2305_Y
+  attribute \src "ls180.v:6617.44-6617.534"
+  wire width 8 $or$ls180.v:6617$2306_Y
+  attribute \src "ls180.v:6617.43-6617.572"
+  wire width 8 $or$ls180.v:6617$2307_Y
+  attribute \src "ls180.v:6617.42-6617.610"
+  wire width 8 $or$ls180.v:6617$2308_Y
+  attribute \src "ls180.v:6944.90-6944.179"
+  wire $or$ls180.v:6944$2333_Y
+  attribute \src "ls180.v:6944.89-6944.254"
+  wire $or$ls180.v:6944$2336_Y
+  attribute \src "ls180.v:6944.88-6944.329"
+  wire $or$ls180.v:6944$2339_Y
+  attribute \src "ls180.v:6968.90-6968.179"
+  wire $or$ls180.v:6968$2349_Y
+  attribute \src "ls180.v:6968.89-6968.254"
+  wire $or$ls180.v:6968$2352_Y
+  attribute \src "ls180.v:6968.88-6968.329"
+  wire $or$ls180.v:6968$2355_Y
+  attribute \src "ls180.v:6992.90-6992.179"
+  wire $or$ls180.v:6992$2365_Y
+  attribute \src "ls180.v:6992.89-6992.254"
+  wire $or$ls180.v:6992$2368_Y
+  attribute \src "ls180.v:6992.88-6992.329"
+  wire $or$ls180.v:6992$2371_Y
+  attribute \src "ls180.v:7016.90-7016.179"
+  wire $or$ls180.v:7016$2381_Y
+  attribute \src "ls180.v:7016.89-7016.254"
+  wire $or$ls180.v:7016$2384_Y
+  attribute \src "ls180.v:7016.88-7016.329"
+  wire $or$ls180.v:7016$2387_Y
+  attribute \src "ls180.v:7530.20-7530.71"
+  wire $or$ls180.v:7530$2444_Y
+  attribute \src "ls180.v:7531.20-7531.71"
+  wire $or$ls180.v:7531$2445_Y
+  attribute \src "ls180.v:7532.20-7532.71"
+  wire $or$ls180.v:7532$2446_Y
+  attribute \src "ls180.v:7533.20-7533.71"
+  wire $or$ls180.v:7533$2447_Y
+  attribute \src "ls180.v:7534.20-7534.71"
+  wire $or$ls180.v:7534$2448_Y
+  attribute \src "ls180.v:7535.20-7535.71"
+  wire $or$ls180.v:7535$2449_Y
+  attribute \src "ls180.v:7536.20-7536.71"
+  wire $or$ls180.v:7536$2450_Y
+  attribute \src "ls180.v:7537.20-7537.71"
+  wire $or$ls180.v:7537$2451_Y
+  attribute \src "ls180.v:7538.20-7538.71"
+  wire $or$ls180.v:7538$2452_Y
+  attribute \src "ls180.v:7539.20-7539.71"
+  wire $or$ls180.v:7539$2453_Y
+  attribute \src "ls180.v:7540.21-7540.73"
+  wire $or$ls180.v:7540$2454_Y
+  attribute \src "ls180.v:7541.21-7541.73"
+  wire $or$ls180.v:7541$2455_Y
+  attribute \src "ls180.v:7542.21-7542.73"
+  wire $or$ls180.v:7542$2456_Y
+  attribute \src "ls180.v:7543.21-7543.73"
+  wire $or$ls180.v:7543$2457_Y
+  attribute \src "ls180.v:7544.21-7544.73"
+  wire $or$ls180.v:7544$2458_Y
+  attribute \src "ls180.v:7545.21-7545.73"
+  wire $or$ls180.v:7545$2459_Y
+  attribute \src "ls180.v:7546.21-7546.73"
+  wire $or$ls180.v:7546$2460_Y
+  attribute \src "ls180.v:7547.21-7547.73"
+  wire $or$ls180.v:7547$2461_Y
+  attribute \src "ls180.v:7548.21-7548.73"
+  wire $or$ls180.v:7548$2462_Y
+  attribute \src "ls180.v:7549.21-7549.73"
+  wire $or$ls180.v:7549$2463_Y
+  attribute \src "ls180.v:7550.21-7550.73"
+  wire $or$ls180.v:7550$2464_Y
+  attribute \src "ls180.v:7551.21-7551.73"
+  wire $or$ls180.v:7551$2465_Y
+  attribute \src "ls180.v:7552.21-7552.73"
+  wire $or$ls180.v:7552$2466_Y
+  attribute \src "ls180.v:7553.21-7553.73"
+  wire $or$ls180.v:7553$2467_Y
+  attribute \src "ls180.v:7554.7-7554.93"
+  wire $or$ls180.v:7554$2468_Y
+  attribute \src "ls180.v:7565.7-7565.93"
+  wire $or$ls180.v:7565$2469_Y
+  attribute \src "ls180.v:7576.7-7576.93"
+  wire $or$ls180.v:7576$2470_Y
+  attribute \src "ls180.v:7717.7-7717.107"
+  wire $or$ls180.v:7717$2515_Y
+  attribute \src "ls180.v:7763.7-7763.107"
+  wire $or$ls180.v:7763$2531_Y
+  attribute \src "ls180.v:7809.7-7809.107"
+  wire $or$ls180.v:7809$2547_Y
+  attribute \src "ls180.v:7855.7-7855.107"
+  wire $or$ls180.v:7855$2563_Y
+  attribute \src "ls180.v:8043.40-8043.125"
+  wire $or$ls180.v:8043$2584_Y
+  attribute \src "ls180.v:8043.39-8043.207"
+  wire $or$ls180.v:8043$2587_Y
+  attribute \src "ls180.v:8043.38-8043.289"
+  wire $or$ls180.v:8043$2590_Y
+  attribute \src "ls180.v:8043.37-8043.371"
+  wire $or$ls180.v:8043$2593_Y
+  attribute \src "ls180.v:8044.41-8044.126"
+  wire $or$ls180.v:8044$2596_Y
+  attribute \src "ls180.v:8044.40-8044.208"
+  wire $or$ls180.v:8044$2599_Y
+  attribute \src "ls180.v:8044.39-8044.290"
+  wire $or$ls180.v:8044$2602_Y
+  attribute \src "ls180.v:8044.38-8044.372"
+  wire $or$ls180.v:8044$2605_Y
+  attribute \src "ls180.v:8048.7-8048.49"
+  wire $or$ls180.v:8048$2606_Y
+  attribute \src "ls180.v:8211.21-8211.74"
+  wire $or$ls180.v:8211$2654_Y
+  attribute \src "ls180.v:8246.21-8246.71"
+  wire $or$ls180.v:8246$2659_Y
+  attribute \src "ls180.v:8314.32-8314.85"
+  wire $or$ls180.v:8314$2671_Y
+  attribute \src "ls180.v:8320.8-8320.97"
+  wire $or$ls180.v:8320$2673_Y
+  attribute \src "ls180.v:8337.52-8337.139"
+  wire $or$ls180.v:8337$2678_Y
+  attribute \src "ls180.v:8338.51-8338.136"
+  wire $or$ls180.v:8338$2679_Y
+  attribute \src "ls180.v:8372.7-8372.87"
+  wire $or$ls180.v:8372$2682_Y
+  attribute \src "ls180.v:8395.33-8395.88"
+  wire $or$ls180.v:8395$2683_Y
+  attribute \src "ls180.v:8401.8-8401.99"
+  wire $or$ls180.v:8401$2685_Y
+  attribute \src "ls180.v:8418.53-8418.142"
+  wire $or$ls180.v:8418$2690_Y
+  attribute \src "ls180.v:8419.52-8419.139"
+  wire $or$ls180.v:8419$2691_Y
+  attribute \src "ls180.v:8453.7-8453.89"
+  wire $or$ls180.v:8453$2694_Y
+  attribute \src "ls180.v:8474.34-8474.91"
+  wire $or$ls180.v:8474$2695_Y
+  attribute \src "ls180.v:8480.8-8480.101"
+  wire $or$ls180.v:8480$2697_Y
+  attribute \src "ls180.v:8497.54-8497.145"
+  wire $or$ls180.v:8497$2702_Y
+  attribute \src "ls180.v:8498.53-8498.142"
+  wire $or$ls180.v:8498$2703_Y
+  attribute \src "ls180.v:8514.7-8514.91"
+  wire $or$ls180.v:8514$2706_Y
+  attribute \src "ls180.v:8703.8-8703.89"
+  wire $or$ls180.v:8703$2730_Y
+  attribute \src "ls180.v:8720.48-8720.127"
+  wire $or$ls180.v:8720$2735_Y
+  attribute \src "ls180.v:8721.47-8721.124"
+  wire $or$ls180.v:8721$2736_Y
+  attribute \src "ls180.v:3253.46-3253.94"
+  wire width 13 $sshl$ls180.v:3253$134_Y
+  attribute \src "ls180.v:3410.46-3410.94"
+  wire width 13 $sshl$ls180.v:3410$164_Y
+  attribute \src "ls180.v:3567.46-3567.94"
+  wire width 13 $sshl$ls180.v:3567$194_Y
+  attribute \src "ls180.v:3724.46-3724.94"
+  wire width 13 $sshl$ls180.v:3724$224_Y
+  attribute \src "ls180.v:3284.63-3284.122"
+  wire width 3 $sub$ls180.v:3284$147_Y
+  attribute \src "ls180.v:3441.63-3441.122"
+  wire width 3 $sub$ls180.v:3441$177_Y
+  attribute \src "ls180.v:3598.63-3598.122"
+  wire width 3 $sub$ls180.v:3598$207_Y
+  attribute \src "ls180.v:3755.63-3755.122"
+  wire width 3 $sub$ls180.v:3755$237_Y
+  attribute \src "ls180.v:4161.38-4161.75"
+  wire width 31 $sub$ls180.v:4161$591_Y
+  attribute \src "ls180.v:4247.36-4247.68"
+  wire width 4 $sub$ls180.v:4247$636_Y
+  attribute \src "ls180.v:4277.36-4277.68"
+  wire width 4 $sub$ls180.v:4277$647_Y
+  attribute \src "ls180.v:4302.70-4302.110"
+  wire width 16 $sub$ls180.v:4302$653_Y
+  attribute \src "ls180.v:4303.70-4303.104"
+  wire width 16 $sub$ls180.v:4303$655_Y
+  attribute \src "ls180.v:4330.37-4330.66"
+  wire width 8 $sub$ls180.v:4330$659_Y
+  attribute \src "ls180.v:4360.67-4360.107"
+  wire width 16 $sub$ls180.v:4360$661_Y
+  attribute \src "ls180.v:4361.67-4361.101"
+  wire width 16 $sub$ls180.v:4361$663_Y
+  attribute \src "ls180.v:4389.35-4389.64"
+  wire width 8 $sub$ls180.v:4389$667_Y
+  attribute \src "ls180.v:4643.60-4643.90"
+  wire width 32 $sub$ls180.v:4643$711_Y
+  attribute \src "ls180.v:4654.62-4654.104"
+  wire width 8 $sub$ls180.v:4654$713_Y
+  attribute \src "ls180.v:4671.60-4671.90"
+  wire width 32 $sub$ls180.v:4671$717_Y
+  attribute \src "ls180.v:4900.62-4900.93"
+  wire width 32 $sub$ls180.v:4900$747_Y
+  attribute \src "ls180.v:4905.62-4905.93"
+  wire width 32 $sub$ls180.v:4905$748_Y
+  attribute \src "ls180.v:4916.64-4916.122"
+  wire width 10 $sub$ls180.v:4916$751_Y
+  attribute \src "ls180.v:4937.62-4937.93"
+  wire width 32 $sub$ls180.v:4937$754_Y
+  attribute \src "ls180.v:5399.37-5399.75"
+  wire width 32 $sub$ls180.v:5399$1027_Y
+  attribute \src "ls180.v:5414.62-5414.100"
+  wire width 32 $sub$ls180.v:5414$1030_Y
+  attribute \src "ls180.v:5425.39-5425.77"
+  wire width 32 $sub$ls180.v:5425$1035_Y
+  attribute \src "ls180.v:5500.40-5500.76"
+  wire width 5 $sub$ls180.v:5500$1039_Y
+  attribute \src "ls180.v:5549.56-5549.104"
+  wire width 32 $sub$ls180.v:5549$1053_Y
+  attribute \src "ls180.v:5639.71-5639.105"
+  wire width 32 $sub$ls180.v:5639$1059_Y
+  attribute \src "ls180.v:5708.40-5708.76"
+  wire width 5 $sub$ls180.v:5708$1070_Y
+  attribute \src "ls180.v:7600.31-7600.60"
+  wire width 32 $sub$ls180.v:7600$2477_Y
+  attribute \src "ls180.v:7633.31-7633.61"
+  wire width 10 $sub$ls180.v:7633$2491_Y
+  attribute \src "ls180.v:7639.34-7639.67"
+  wire $sub$ls180.v:7639$2492_Y
+  attribute \src "ls180.v:7650.36-7650.69"
+  wire $sub$ls180.v:7650$2495_Y
+  attribute \src "ls180.v:7714.59-7714.116"
+  wire width 4 $sub$ls180.v:7714$2513_Y
+  attribute \src "ls180.v:7733.46-7733.90"
+  wire width 3 $sub$ls180.v:7733$2517_Y
+  attribute \src "ls180.v:7760.59-7760.116"
+  wire width 4 $sub$ls180.v:7760$2529_Y
+  attribute \src "ls180.v:7779.46-7779.90"
+  wire width 3 $sub$ls180.v:7779$2533_Y
+  attribute \src "ls180.v:7806.59-7806.116"
+  wire width 4 $sub$ls180.v:7806$2545_Y
+  attribute \src "ls180.v:7825.46-7825.90"
+  wire width 3 $sub$ls180.v:7825$2549_Y
+  attribute \src "ls180.v:7852.59-7852.116"
+  wire width 4 $sub$ls180.v:7852$2561_Y
+  attribute \src "ls180.v:7871.46-7871.90"
+  wire width 3 $sub$ls180.v:7871$2565_Y
+  attribute \src "ls180.v:7882.25-7882.48"
+  wire width 5 $sub$ls180.v:7882$2569_Y
+  attribute \src "ls180.v:7889.25-7889.48"
+  wire width 4 $sub$ls180.v:7889$2572_Y
+  attribute \src "ls180.v:8021.33-8021.64"
+  wire $sub$ls180.v:8021$2577_Y
+  attribute \src "ls180.v:8036.33-8036.64"
+  wire width 3 $sub$ls180.v:8036$2580_Y
+  attribute \src "ls180.v:8163.33-8163.64"
+  wire width 5 $sub$ls180.v:8163$2639_Y
+  attribute \src "ls180.v:8185.33-8185.64"
+  wire width 5 $sub$ls180.v:8185$2650_Y
+  attribute \src "ls180.v:8220.34-8220.66"
+  wire width 3 $sub$ls180.v:8220$2655_Y
+  attribute \src "ls180.v:8255.32-8255.62"
+  wire width 3 $sub$ls180.v:8255$2660_Y
+  attribute \src "ls180.v:8279.30-8279.53"
+  wire width 32 $sub$ls180.v:8279$2663_Y
+  attribute \src "ls180.v:8293.30-8293.53"
+  wire width 32 $sub$ls180.v:8293$2667_Y
+  attribute \src "ls180.v:8696.36-8696.70"
+  wire width 6 $sub$ls180.v:8696$2728_Y
+  attribute \src "ls180.v:8782.36-8782.70"
+  wire width 6 $sub$ls180.v:8782$2750_Y
+  attribute \src "ls180.v:8895.22-8895.42"
+  wire width 20 $sub$ls180.v:8895$2757_Y
+  attribute \src "ls180.v:4997.353-4997.425"
+  wire $xor$ls180.v:4997$761_Y
+  attribute \src "ls180.v:4997.200-4997.272"
+  wire $xor$ls180.v:4997$762_Y
+  attribute \src "ls180.v:4997.160-4997.273"
+  wire $xor$ls180.v:4997$763_Y
+  attribute \src "ls180.v:4998.353-4998.425"
+  wire $xor$ls180.v:4998$764_Y
+  attribute \src "ls180.v:4998.200-4998.272"
+  wire $xor$ls180.v:4998$765_Y
+  attribute \src "ls180.v:4998.160-4998.273"
+  wire $xor$ls180.v:4998$766_Y
+  attribute \src "ls180.v:4999.353-4999.425"
+  wire $xor$ls180.v:4999$767_Y
+  attribute \src "ls180.v:4999.200-4999.272"
+  wire $xor$ls180.v:4999$768_Y
+  attribute \src "ls180.v:4999.160-4999.273"
+  wire $xor$ls180.v:4999$769_Y
+  attribute \src "ls180.v:5000.353-5000.425"
+  wire $xor$ls180.v:5000$770_Y
+  attribute \src "ls180.v:5000.200-5000.272"
+  wire $xor$ls180.v:5000$771_Y
+  attribute \src "ls180.v:5000.160-5000.273"
+  wire $xor$ls180.v:5000$772_Y
+  attribute \src "ls180.v:5001.353-5001.425"
+  wire $xor$ls180.v:5001$773_Y
+  attribute \src "ls180.v:5001.200-5001.272"
+  wire $xor$ls180.v:5001$774_Y
+  attribute \src "ls180.v:5001.160-5001.273"
+  wire $xor$ls180.v:5001$775_Y
+  attribute \src "ls180.v:5002.353-5002.425"
+  wire $xor$ls180.v:5002$776_Y
+  attribute \src "ls180.v:5002.200-5002.272"
+  wire $xor$ls180.v:5002$777_Y
+  attribute \src "ls180.v:5002.160-5002.273"
+  wire $xor$ls180.v:5002$778_Y
+  attribute \src "ls180.v:5003.353-5003.425"
+  wire $xor$ls180.v:5003$779_Y
+  attribute \src "ls180.v:5003.200-5003.272"
+  wire $xor$ls180.v:5003$780_Y
+  attribute \src "ls180.v:5003.160-5003.273"
+  wire $xor$ls180.v:5003$781_Y
+  attribute \src "ls180.v:5004.353-5004.425"
+  wire $xor$ls180.v:5004$782_Y
+  attribute \src "ls180.v:5004.200-5004.272"
+  wire $xor$ls180.v:5004$783_Y
+  attribute \src "ls180.v:5004.160-5004.273"
+  wire $xor$ls180.v:5004$784_Y
+  attribute \src "ls180.v:5005.353-5005.425"
+  wire $xor$ls180.v:5005$785_Y
+  attribute \src "ls180.v:5005.200-5005.272"
+  wire $xor$ls180.v:5005$786_Y
+  attribute \src "ls180.v:5005.160-5005.273"
+  wire $xor$ls180.v:5005$787_Y
+  attribute \src "ls180.v:5006.354-5006.426"
+  wire $xor$ls180.v:5006$788_Y
+  attribute \src "ls180.v:5006.201-5006.273"
+  wire $xor$ls180.v:5006$789_Y
+  attribute \src "ls180.v:5006.161-5006.274"
+  wire $xor$ls180.v:5006$790_Y
+  attribute \src "ls180.v:5007.361-5007.434"
+  wire $xor$ls180.v:5007$791_Y
+  attribute \src "ls180.v:5007.205-5007.278"
+  wire $xor$ls180.v:5007$792_Y
+  attribute \src "ls180.v:5007.164-5007.279"
+  wire $xor$ls180.v:5007$793_Y
+  attribute \src "ls180.v:5008.361-5008.434"
+  wire $xor$ls180.v:5008$794_Y
+  attribute \src "ls180.v:5008.205-5008.278"
+  wire $xor$ls180.v:5008$795_Y
+  attribute \src "ls180.v:5008.164-5008.279"
+  wire $xor$ls180.v:5008$796_Y
+  attribute \src "ls180.v:5009.361-5009.434"
+  wire $xor$ls180.v:5009$797_Y
+  attribute \src "ls180.v:5009.205-5009.278"
+  wire $xor$ls180.v:5009$798_Y
+  attribute \src "ls180.v:5009.164-5009.279"
+  wire $xor$ls180.v:5009$799_Y
+  attribute \src "ls180.v:5010.361-5010.434"
+  wire $xor$ls180.v:5010$800_Y
+  attribute \src "ls180.v:5010.205-5010.278"
+  wire $xor$ls180.v:5010$801_Y
+  attribute \src "ls180.v:5010.164-5010.279"
+  wire $xor$ls180.v:5010$802_Y
+  attribute \src "ls180.v:5011.361-5011.434"
+  wire $xor$ls180.v:5011$803_Y
+  attribute \src "ls180.v:5011.205-5011.278"
+  wire $xor$ls180.v:5011$804_Y
+  attribute \src "ls180.v:5011.164-5011.279"
+  wire $xor$ls180.v:5011$805_Y
+  attribute \src "ls180.v:5012.361-5012.434"
+  wire $xor$ls180.v:5012$806_Y
+  attribute \src "ls180.v:5012.205-5012.278"
+  wire $xor$ls180.v:5012$807_Y
+  attribute \src "ls180.v:5012.164-5012.279"
+  wire $xor$ls180.v:5012$808_Y
+  attribute \src "ls180.v:5013.361-5013.434"
+  wire $xor$ls180.v:5013$809_Y
+  attribute \src "ls180.v:5013.205-5013.278"
+  wire $xor$ls180.v:5013$810_Y
+  attribute \src "ls180.v:5013.164-5013.279"
+  wire $xor$ls180.v:5013$811_Y
+  attribute \src "ls180.v:5014.361-5014.434"
+  wire $xor$ls180.v:5014$812_Y
+  attribute \src "ls180.v:5014.205-5014.278"
+  wire $xor$ls180.v:5014$813_Y
+  attribute \src "ls180.v:5014.164-5014.279"
+  wire $xor$ls180.v:5014$814_Y
+  attribute \src "ls180.v:5015.361-5015.434"
+  wire $xor$ls180.v:5015$815_Y
+  attribute \src "ls180.v:5015.205-5015.278"
+  wire $xor$ls180.v:5015$816_Y
+  attribute \src "ls180.v:5015.164-5015.279"
+  wire $xor$ls180.v:5015$817_Y
+  attribute \src "ls180.v:5016.361-5016.434"
+  wire $xor$ls180.v:5016$818_Y
+  attribute \src "ls180.v:5016.205-5016.278"
+  wire $xor$ls180.v:5016$819_Y
+  attribute \src "ls180.v:5016.164-5016.279"
+  wire $xor$ls180.v:5016$820_Y
+  attribute \src "ls180.v:5017.361-5017.434"
+  wire $xor$ls180.v:5017$821_Y
+  attribute \src "ls180.v:5017.205-5017.278"
+  wire $xor$ls180.v:5017$822_Y
+  attribute \src "ls180.v:5017.164-5017.279"
+  wire $xor$ls180.v:5017$823_Y
+  attribute \src "ls180.v:5018.361-5018.434"
+  wire $xor$ls180.v:5018$824_Y
+  attribute \src "ls180.v:5018.205-5018.278"
+  wire $xor$ls180.v:5018$825_Y
+  attribute \src "ls180.v:5018.164-5018.279"
+  wire $xor$ls180.v:5018$826_Y
+  attribute \src "ls180.v:5019.361-5019.434"
+  wire $xor$ls180.v:5019$827_Y
+  attribute \src "ls180.v:5019.205-5019.278"
+  wire $xor$ls180.v:5019$828_Y
+  attribute \src "ls180.v:5019.164-5019.279"
+  wire $xor$ls180.v:5019$829_Y
+  attribute \src "ls180.v:5020.361-5020.434"
+  wire $xor$ls180.v:5020$830_Y
+  attribute \src "ls180.v:5020.205-5020.278"
+  wire $xor$ls180.v:5020$831_Y
+  attribute \src "ls180.v:5020.164-5020.279"
+  wire $xor$ls180.v:5020$832_Y
+  attribute \src "ls180.v:5021.361-5021.434"
+  wire $xor$ls180.v:5021$833_Y
+  attribute \src "ls180.v:5021.205-5021.278"
+  wire $xor$ls180.v:5021$834_Y
+  attribute \src "ls180.v:5021.164-5021.279"
+  wire $xor$ls180.v:5021$835_Y
+  attribute \src "ls180.v:5022.361-5022.434"
+  wire $xor$ls180.v:5022$836_Y
+  attribute \src "ls180.v:5022.205-5022.278"
+  wire $xor$ls180.v:5022$837_Y
+  attribute \src "ls180.v:5022.164-5022.279"
+  wire $xor$ls180.v:5022$838_Y
+  attribute \src "ls180.v:5023.361-5023.434"
+  wire $xor$ls180.v:5023$839_Y
+  attribute \src "ls180.v:5023.205-5023.278"
+  wire $xor$ls180.v:5023$840_Y
+  attribute \src "ls180.v:5023.164-5023.279"
+  wire $xor$ls180.v:5023$841_Y
+  attribute \src "ls180.v:5024.361-5024.434"
+  wire $xor$ls180.v:5024$842_Y
+  attribute \src "ls180.v:5024.205-5024.278"
+  wire $xor$ls180.v:5024$843_Y
+  attribute \src "ls180.v:5024.164-5024.279"
+  wire $xor$ls180.v:5024$844_Y
+  attribute \src "ls180.v:5025.361-5025.434"
+  wire $xor$ls180.v:5025$845_Y
+  attribute \src "ls180.v:5025.205-5025.278"
+  wire $xor$ls180.v:5025$846_Y
+  attribute \src "ls180.v:5025.164-5025.279"
+  wire $xor$ls180.v:5025$847_Y
+  attribute \src "ls180.v:5026.361-5026.434"
+  wire $xor$ls180.v:5026$848_Y
+  attribute \src "ls180.v:5026.205-5026.278"
+  wire $xor$ls180.v:5026$849_Y
+  attribute \src "ls180.v:5026.164-5026.279"
+  wire $xor$ls180.v:5026$850_Y
+  attribute \src "ls180.v:5027.360-5027.432"
+  wire $xor$ls180.v:5027$851_Y
+  attribute \src "ls180.v:5027.205-5027.277"
+  wire $xor$ls180.v:5027$852_Y
+  attribute \src "ls180.v:5027.164-5027.278"
+  wire $xor$ls180.v:5027$853_Y
+  attribute \src "ls180.v:5028.360-5028.432"
+  wire $xor$ls180.v:5028$854_Y
+  attribute \src "ls180.v:5028.205-5028.277"
+  wire $xor$ls180.v:5028$855_Y
+  attribute \src "ls180.v:5028.164-5028.278"
+  wire $xor$ls180.v:5028$856_Y
+  attribute \src "ls180.v:5029.360-5029.432"
+  wire $xor$ls180.v:5029$857_Y
+  attribute \src "ls180.v:5029.205-5029.277"
+  wire $xor$ls180.v:5029$858_Y
+  attribute \src "ls180.v:5029.164-5029.278"
+  wire $xor$ls180.v:5029$859_Y
+  attribute \src "ls180.v:5030.360-5030.432"
+  wire $xor$ls180.v:5030$860_Y
+  attribute \src "ls180.v:5030.205-5030.277"
+  wire $xor$ls180.v:5030$861_Y
+  attribute \src "ls180.v:5030.164-5030.278"
+  wire $xor$ls180.v:5030$862_Y
+  attribute \src "ls180.v:5031.360-5031.432"
+  wire $xor$ls180.v:5031$863_Y
+  attribute \src "ls180.v:5031.205-5031.277"
+  wire $xor$ls180.v:5031$864_Y
+  attribute \src "ls180.v:5031.164-5031.278"
+  wire $xor$ls180.v:5031$865_Y
+  attribute \src "ls180.v:5032.360-5032.432"
+  wire $xor$ls180.v:5032$866_Y
+  attribute \src "ls180.v:5032.205-5032.277"
+  wire $xor$ls180.v:5032$867_Y
+  attribute \src "ls180.v:5032.164-5032.278"
+  wire $xor$ls180.v:5032$868_Y
+  attribute \src "ls180.v:5033.360-5033.432"
+  wire $xor$ls180.v:5033$869_Y
+  attribute \src "ls180.v:5033.205-5033.277"
+  wire $xor$ls180.v:5033$870_Y
+  attribute \src "ls180.v:5033.164-5033.278"
+  wire $xor$ls180.v:5033$871_Y
+  attribute \src "ls180.v:5034.360-5034.432"
+  wire $xor$ls180.v:5034$872_Y
+  attribute \src "ls180.v:5034.205-5034.277"
+  wire $xor$ls180.v:5034$873_Y
+  attribute \src "ls180.v:5034.164-5034.278"
+  wire $xor$ls180.v:5034$874_Y
+  attribute \src "ls180.v:5035.360-5035.432"
+  wire $xor$ls180.v:5035$875_Y
+  attribute \src "ls180.v:5035.205-5035.277"
+  wire $xor$ls180.v:5035$876_Y
+  attribute \src "ls180.v:5035.164-5035.278"
+  wire $xor$ls180.v:5035$877_Y
+  attribute \src "ls180.v:5036.360-5036.432"
+  wire $xor$ls180.v:5036$878_Y
+  attribute \src "ls180.v:5036.205-5036.277"
+  wire $xor$ls180.v:5036$879_Y
+  attribute \src "ls180.v:5036.164-5036.278"
+  wire $xor$ls180.v:5036$880_Y
+  attribute \src "ls180.v:5057.899-5057.983"
+  wire $xor$ls180.v:5057$894_Y
+  attribute \src "ls180.v:5057.634-5057.718"
+  wire $xor$ls180.v:5057$895_Y
+  attribute \src "ls180.v:5057.588-5057.719"
+  wire $xor$ls180.v:5057$896_Y
+  attribute \src "ls180.v:5057.234-5057.318"
+  wire $xor$ls180.v:5057$897_Y
+  attribute \src "ls180.v:5057.187-5057.319"
+  wire $xor$ls180.v:5057$898_Y
+  attribute \src "ls180.v:5058.899-5058.983"
+  wire $xor$ls180.v:5058$899_Y
+  attribute \src "ls180.v:5058.634-5058.718"
+  wire $xor$ls180.v:5058$900_Y
+  attribute \src "ls180.v:5058.588-5058.719"
+  wire $xor$ls180.v:5058$901_Y
+  attribute \src "ls180.v:5058.234-5058.318"
+  wire $xor$ls180.v:5058$902_Y
+  attribute \src "ls180.v:5058.187-5058.319"
+  wire $xor$ls180.v:5058$903_Y
+  attribute \src "ls180.v:5067.899-5067.983"
+  wire $xor$ls180.v:5067$905_Y
+  attribute \src "ls180.v:5067.634-5067.718"
+  wire $xor$ls180.v:5067$906_Y
+  attribute \src "ls180.v:5067.588-5067.719"
+  wire $xor$ls180.v:5067$907_Y
+  attribute \src "ls180.v:5067.234-5067.318"
+  wire $xor$ls180.v:5067$908_Y
+  attribute \src "ls180.v:5067.187-5067.319"
+  wire $xor$ls180.v:5067$909_Y
+  attribute \src "ls180.v:5068.899-5068.983"
+  wire $xor$ls180.v:5068$910_Y
+  attribute \src "ls180.v:5068.634-5068.718"
+  wire $xor$ls180.v:5068$911_Y
+  attribute \src "ls180.v:5068.588-5068.719"
+  wire $xor$ls180.v:5068$912_Y
+  attribute \src "ls180.v:5068.234-5068.318"
+  wire $xor$ls180.v:5068$913_Y
+  attribute \src "ls180.v:5068.187-5068.319"
+  wire $xor$ls180.v:5068$914_Y
+  attribute \src "ls180.v:5077.899-5077.983"
+  wire $xor$ls180.v:5077$916_Y
+  attribute \src "ls180.v:5077.634-5077.718"
+  wire $xor$ls180.v:5077$917_Y
+  attribute \src "ls180.v:5077.588-5077.719"
+  wire $xor$ls180.v:5077$918_Y
+  attribute \src "ls180.v:5077.234-5077.318"
+  wire $xor$ls180.v:5077$919_Y
+  attribute \src "ls180.v:5077.187-5077.319"
+  wire $xor$ls180.v:5077$920_Y
+  attribute \src "ls180.v:5078.899-5078.983"
+  wire $xor$ls180.v:5078$921_Y
+  attribute \src "ls180.v:5078.634-5078.718"
+  wire $xor$ls180.v:5078$922_Y
+  attribute \src "ls180.v:5078.588-5078.719"
+  wire $xor$ls180.v:5078$923_Y
+  attribute \src "ls180.v:5078.234-5078.318"
+  wire $xor$ls180.v:5078$924_Y
+  attribute \src "ls180.v:5078.187-5078.319"
+  wire $xor$ls180.v:5078$925_Y
+  attribute \src "ls180.v:5087.899-5087.983"
+  wire $xor$ls180.v:5087$927_Y
+  attribute \src "ls180.v:5087.634-5087.718"
+  wire $xor$ls180.v:5087$928_Y
+  attribute \src "ls180.v:5087.588-5087.719"
+  wire $xor$ls180.v:5087$929_Y
+  attribute \src "ls180.v:5087.234-5087.318"
+  wire $xor$ls180.v:5087$930_Y
+  attribute \src "ls180.v:5087.187-5087.319"
+  wire $xor$ls180.v:5087$931_Y
+  attribute \src "ls180.v:5088.899-5088.983"
+  wire $xor$ls180.v:5088$932_Y
+  attribute \src "ls180.v:5088.634-5088.718"
+  wire $xor$ls180.v:5088$933_Y
+  attribute \src "ls180.v:5088.588-5088.719"
+  wire $xor$ls180.v:5088$934_Y
+  attribute \src "ls180.v:5088.234-5088.318"
+  wire $xor$ls180.v:5088$935_Y
+  attribute \src "ls180.v:5088.187-5088.319"
+  wire $xor$ls180.v:5088$936_Y
+  attribute \src "ls180.v:5239.879-5239.961"
+  wire $xor$ls180.v:5239$969_Y
+  attribute \src "ls180.v:5239.620-5239.702"
+  wire $xor$ls180.v:5239$970_Y
+  attribute \src "ls180.v:5239.575-5239.703"
+  wire $xor$ls180.v:5239$971_Y
+  attribute \src "ls180.v:5239.229-5239.311"
+  wire $xor$ls180.v:5239$972_Y
+  attribute \src "ls180.v:5239.183-5239.312"
+  wire $xor$ls180.v:5239$973_Y
+  attribute \src "ls180.v:5240.879-5240.961"
+  wire $xor$ls180.v:5240$974_Y
+  attribute \src "ls180.v:5240.620-5240.702"
+  wire $xor$ls180.v:5240$975_Y
+  attribute \src "ls180.v:5240.575-5240.703"
+  wire $xor$ls180.v:5240$976_Y
+  attribute \src "ls180.v:5240.229-5240.311"
+  wire $xor$ls180.v:5240$977_Y
+  attribute \src "ls180.v:5240.183-5240.312"
+  wire $xor$ls180.v:5240$978_Y
+  attribute \src "ls180.v:5249.879-5249.961"
+  wire $xor$ls180.v:5249$980_Y
+  attribute \src "ls180.v:5249.620-5249.702"
+  wire $xor$ls180.v:5249$981_Y
+  attribute \src "ls180.v:5249.575-5249.703"
+  wire $xor$ls180.v:5249$982_Y
+  attribute \src "ls180.v:5249.229-5249.311"
+  wire $xor$ls180.v:5249$983_Y
+  attribute \src "ls180.v:5249.183-5249.312"
+  wire $xor$ls180.v:5249$984_Y
+  attribute \src "ls180.v:5250.879-5250.961"
+  wire $xor$ls180.v:5250$985_Y
+  attribute \src "ls180.v:5250.620-5250.702"
+  wire $xor$ls180.v:5250$986_Y
+  attribute \src "ls180.v:5250.575-5250.703"
+  wire $xor$ls180.v:5250$987_Y
+  attribute \src "ls180.v:5250.229-5250.311"
+  wire $xor$ls180.v:5250$988_Y
+  attribute \src "ls180.v:5250.183-5250.312"
+  wire $xor$ls180.v:5250$989_Y
+  attribute \src "ls180.v:5259.879-5259.961"
+  wire $xor$ls180.v:5259$991_Y
+  attribute \src "ls180.v:5259.620-5259.702"
+  wire $xor$ls180.v:5259$992_Y
+  attribute \src "ls180.v:5259.575-5259.703"
+  wire $xor$ls180.v:5259$993_Y
+  attribute \src "ls180.v:5259.229-5259.311"
+  wire $xor$ls180.v:5259$994_Y
+  attribute \src "ls180.v:5259.183-5259.312"
+  wire $xor$ls180.v:5259$995_Y
+  attribute \src "ls180.v:5260.183-5260.312"
+  wire $xor$ls180.v:5260$1000_Y
+  attribute \src "ls180.v:5260.879-5260.961"
+  wire $xor$ls180.v:5260$996_Y
+  attribute \src "ls180.v:5260.620-5260.702"
+  wire $xor$ls180.v:5260$997_Y
+  attribute \src "ls180.v:5260.575-5260.703"
+  wire $xor$ls180.v:5260$998_Y
+  attribute \src "ls180.v:5260.229-5260.311"
+  wire $xor$ls180.v:5260$999_Y
+  attribute \src "ls180.v:5269.879-5269.961"
+  wire $xor$ls180.v:5269$1002_Y
+  attribute \src "ls180.v:5269.620-5269.702"
+  wire $xor$ls180.v:5269$1003_Y
+  attribute \src "ls180.v:5269.575-5269.703"
+  wire $xor$ls180.v:5269$1004_Y
+  attribute \src "ls180.v:5269.229-5269.311"
+  wire $xor$ls180.v:5269$1005_Y
+  attribute \src "ls180.v:5269.183-5269.312"
+  wire $xor$ls180.v:5269$1006_Y
+  attribute \src "ls180.v:5270.879-5270.961"
+  wire $xor$ls180.v:5270$1007_Y
+  attribute \src "ls180.v:5270.620-5270.702"
+  wire $xor$ls180.v:5270$1008_Y
+  attribute \src "ls180.v:5270.575-5270.703"
+  wire $xor$ls180.v:5270$1009_Y
+  attribute \src "ls180.v:5270.229-5270.311"
+  wire $xor$ls180.v:5270$1010_Y
+  attribute \src "ls180.v:5270.183-5270.312"
+  wire $xor$ls180.v:5270$1011_Y
+  attribute \src "ls180.v:1790.11-1790.42"
   wire width 3 \builder_bankmachine0_next_state
-  attribute \src "ls180.v:1744.11-1744.37"
+  attribute \src "ls180.v:1789.11-1789.37"
   wire width 3 \builder_bankmachine0_state
-  attribute \src "ls180.v:1747.11-1747.42"
+  attribute \src "ls180.v:1792.11-1792.42"
   wire width 3 \builder_bankmachine1_next_state
-  attribute \src "ls180.v:1746.11-1746.37"
+  attribute \src "ls180.v:1791.11-1791.37"
   wire width 3 \builder_bankmachine1_state
-  attribute \src "ls180.v:1749.11-1749.42"
+  attribute \src "ls180.v:1794.11-1794.42"
   wire width 3 \builder_bankmachine2_next_state
-  attribute \src "ls180.v:1748.11-1748.37"
+  attribute \src "ls180.v:1793.11-1793.37"
   wire width 3 \builder_bankmachine2_state
-  attribute \src "ls180.v:1751.11-1751.42"
+  attribute \src "ls180.v:1796.11-1796.42"
   wire width 3 \builder_bankmachine3_next_state
-  attribute \src "ls180.v:1750.11-1750.37"
+  attribute \src "ls180.v:1795.11-1795.37"
   wire width 3 \builder_bankmachine3_state
-  attribute \src "ls180.v:2596.5-2596.34"
+  attribute \src "ls180.v:2641.5-2641.34"
   wire \builder_comb_rhs_array_muxed0
-  attribute \src "ls180.v:2597.12-2597.41"
+  attribute \src "ls180.v:2642.12-2642.41"
   wire width 13 \builder_comb_rhs_array_muxed1
-  attribute \src "ls180.v:2609.5-2609.35"
+  attribute \src "ls180.v:2654.5-2654.35"
   wire \builder_comb_rhs_array_muxed10
-  attribute \src "ls180.v:2610.5-2610.35"
+  attribute \src "ls180.v:2655.5-2655.35"
   wire \builder_comb_rhs_array_muxed11
-  attribute \src "ls180.v:2614.12-2614.42"
+  attribute \src "ls180.v:2659.12-2659.42"
   wire width 22 \builder_comb_rhs_array_muxed12
-  attribute \src "ls180.v:2615.5-2615.35"
+  attribute \src "ls180.v:2660.5-2660.35"
   wire \builder_comb_rhs_array_muxed13
-  attribute \src "ls180.v:2616.5-2616.35"
+  attribute \src "ls180.v:2661.5-2661.35"
   wire \builder_comb_rhs_array_muxed14
-  attribute \src "ls180.v:2617.12-2617.42"
+  attribute \src "ls180.v:2662.12-2662.42"
   wire width 22 \builder_comb_rhs_array_muxed15
-  attribute \src "ls180.v:2618.5-2618.35"
+  attribute \src "ls180.v:2663.5-2663.35"
   wire \builder_comb_rhs_array_muxed16
-  attribute \src "ls180.v:2619.5-2619.35"
+  attribute \src "ls180.v:2664.5-2664.35"
   wire \builder_comb_rhs_array_muxed17
-  attribute \src "ls180.v:2620.12-2620.42"
+  attribute \src "ls180.v:2665.12-2665.42"
   wire width 22 \builder_comb_rhs_array_muxed18
-  attribute \src "ls180.v:2621.5-2621.35"
+  attribute \src "ls180.v:2666.5-2666.35"
   wire \builder_comb_rhs_array_muxed19
-  attribute \src "ls180.v:2598.11-2598.40"
+  attribute \src "ls180.v:2643.11-2643.40"
   wire width 2 \builder_comb_rhs_array_muxed2
-  attribute \src "ls180.v:2622.5-2622.35"
+  attribute \src "ls180.v:2667.5-2667.35"
   wire \builder_comb_rhs_array_muxed20
-  attribute \src "ls180.v:2623.12-2623.42"
+  attribute \src "ls180.v:2668.12-2668.42"
   wire width 22 \builder_comb_rhs_array_muxed21
-  attribute \src "ls180.v:2624.5-2624.35"
+  attribute \src "ls180.v:2669.5-2669.35"
   wire \builder_comb_rhs_array_muxed22
-  attribute \src "ls180.v:2625.5-2625.35"
+  attribute \src "ls180.v:2670.5-2670.35"
   wire \builder_comb_rhs_array_muxed23
-  attribute \src "ls180.v:2626.12-2626.42"
+  attribute \src "ls180.v:2671.12-2671.42"
   wire width 32 \builder_comb_rhs_array_muxed24
-  attribute \src "ls180.v:2627.12-2627.42"
+  attribute \src "ls180.v:2672.12-2672.42"
   wire width 32 \builder_comb_rhs_array_muxed25
-  attribute \src "ls180.v:2628.11-2628.41"
+  attribute \src "ls180.v:2673.11-2673.41"
   wire width 4 \builder_comb_rhs_array_muxed26
-  attribute \src "ls180.v:2629.5-2629.35"
+  attribute \src "ls180.v:2674.5-2674.35"
   wire \builder_comb_rhs_array_muxed27
-  attribute \src "ls180.v:2630.5-2630.35"
+  attribute \src "ls180.v:2675.5-2675.35"
   wire \builder_comb_rhs_array_muxed28
-  attribute \src "ls180.v:2631.5-2631.35"
+  attribute \src "ls180.v:2676.5-2676.35"
   wire \builder_comb_rhs_array_muxed29
-  attribute \src "ls180.v:2599.5-2599.34"
+  attribute \src "ls180.v:2644.5-2644.34"
   wire \builder_comb_rhs_array_muxed3
-  attribute \src "ls180.v:2632.11-2632.41"
+  attribute \src "ls180.v:2677.11-2677.41"
   wire width 3 \builder_comb_rhs_array_muxed30
-  attribute \src "ls180.v:2633.11-2633.41"
+  attribute \src "ls180.v:2678.11-2678.41"
   wire width 2 \builder_comb_rhs_array_muxed31
-  attribute \src "ls180.v:2600.5-2600.34"
+  attribute \src "ls180.v:2645.5-2645.34"
   wire \builder_comb_rhs_array_muxed4
-  attribute \src "ls180.v:2601.5-2601.34"
+  attribute \src "ls180.v:2646.5-2646.34"
   wire \builder_comb_rhs_array_muxed5
-  attribute \src "ls180.v:2605.5-2605.34"
+  attribute \src "ls180.v:2650.5-2650.34"
   wire \builder_comb_rhs_array_muxed6
-  attribute \src "ls180.v:2606.12-2606.41"
+  attribute \src "ls180.v:2651.12-2651.41"
   wire width 13 \builder_comb_rhs_array_muxed7
-  attribute \src "ls180.v:2607.11-2607.40"
+  attribute \src "ls180.v:2652.11-2652.40"
   wire width 2 \builder_comb_rhs_array_muxed8
-  attribute \src "ls180.v:2608.5-2608.34"
+  attribute \src "ls180.v:2653.5-2653.34"
   wire \builder_comb_rhs_array_muxed9
-  attribute \src "ls180.v:2602.5-2602.32"
+  attribute \src "ls180.v:2647.5-2647.32"
   wire \builder_comb_t_array_muxed0
-  attribute \src "ls180.v:2603.5-2603.32"
+  attribute \src "ls180.v:2648.5-2648.32"
   wire \builder_comb_t_array_muxed1
-  attribute \src "ls180.v:2604.5-2604.32"
+  attribute \src "ls180.v:2649.5-2649.32"
   wire \builder_comb_t_array_muxed2
-  attribute \src "ls180.v:2611.5-2611.32"
+  attribute \src "ls180.v:2656.5-2656.32"
   wire \builder_comb_t_array_muxed3
-  attribute \src "ls180.v:2612.5-2612.32"
+  attribute \src "ls180.v:2657.5-2657.32"
   wire \builder_comb_t_array_muxed4
-  attribute \src "ls180.v:2613.5-2613.32"
+  attribute \src "ls180.v:2658.5-2658.32"
   wire \builder_comb_t_array_muxed5
-  attribute \src "ls180.v:1731.5-1731.34"
+  attribute \src "ls180.v:1776.5-1776.34"
   wire \builder_converter0_next_state
-  attribute \src "ls180.v:1730.5-1730.29"
+  attribute \src "ls180.v:1775.5-1775.29"
   wire \builder_converter0_state
-  attribute \src "ls180.v:1735.5-1735.34"
+  attribute \src "ls180.v:1780.5-1780.34"
   wire \builder_converter1_next_state
-  attribute \src "ls180.v:1734.5-1734.29"
+  attribute \src "ls180.v:1779.5-1779.29"
   wire \builder_converter1_state
-  attribute \src "ls180.v:1739.5-1739.34"
+  attribute \src "ls180.v:1784.5-1784.34"
   wire \builder_converter2_next_state
-  attribute \src "ls180.v:1738.5-1738.29"
+  attribute \src "ls180.v:1783.5-1783.29"
   wire \builder_converter2_state
-  attribute \src "ls180.v:1776.5-1776.33"
+  attribute \src "ls180.v:1821.5-1821.33"
   wire \builder_converter_next_state
-  attribute \src "ls180.v:1775.5-1775.28"
+  attribute \src "ls180.v:1820.5-1820.28"
   wire \builder_converter_state
-  attribute \src "ls180.v:1896.12-1896.25"
+  attribute \src "ls180.v:1941.12-1941.25"
   wire width 20 \builder_count
-  attribute \src "ls180.v:2584.13-2584.41"
+  attribute \src "ls180.v:2629.13-2629.41"
   wire width 14 \builder_csr_interconnect_adr
-  attribute \src "ls180.v:2587.12-2587.42"
+  attribute \src "ls180.v:2632.12-2632.42"
   wire width 8 \builder_csr_interconnect_dat_r
-  attribute \src "ls180.v:2586.12-2586.42"
+  attribute \src "ls180.v:2631.12-2631.42"
   wire width 8 \builder_csr_interconnect_dat_w
-  attribute \src "ls180.v:2585.6-2585.33"
+  attribute \src "ls180.v:2630.6-2630.33"
   wire \builder_csr_interconnect_we
-  attribute \src "ls180.v:1934.12-1934.42"
+  attribute \src "ls180.v:1979.12-1979.42"
   wire width 8 \builder_csrbank0_bus_errors0_r
-  attribute \src "ls180.v:1933.6-1933.37"
+  attribute \src "ls180.v:1978.6-1978.37"
   wire \builder_csrbank0_bus_errors0_re
-  attribute \src "ls180.v:1936.12-1936.42"
+  attribute \src "ls180.v:1981.12-1981.42"
   wire width 8 \builder_csrbank0_bus_errors0_w
-  attribute \src "ls180.v:1935.6-1935.37"
+  attribute \src "ls180.v:1980.6-1980.37"
   wire \builder_csrbank0_bus_errors0_we
-  attribute \src "ls180.v:1930.12-1930.42"
+  attribute \src "ls180.v:1975.12-1975.42"
   wire width 8 \builder_csrbank0_bus_errors1_r
-  attribute \src "ls180.v:1929.6-1929.37"
+  attribute \src "ls180.v:1974.6-1974.37"
   wire \builder_csrbank0_bus_errors1_re
-  attribute \src "ls180.v:1932.12-1932.42"
+  attribute \src "ls180.v:1977.12-1977.42"
   wire width 8 \builder_csrbank0_bus_errors1_w
-  attribute \src "ls180.v:1931.6-1931.37"
+  attribute \src "ls180.v:1976.6-1976.37"
   wire \builder_csrbank0_bus_errors1_we
-  attribute \src "ls180.v:1926.12-1926.42"
+  attribute \src "ls180.v:1971.12-1971.42"
   wire width 8 \builder_csrbank0_bus_errors2_r
-  attribute \src "ls180.v:1925.6-1925.37"
+  attribute \src "ls180.v:1970.6-1970.37"
   wire \builder_csrbank0_bus_errors2_re
-  attribute \src "ls180.v:1928.12-1928.42"
+  attribute \src "ls180.v:1973.12-1973.42"
   wire width 8 \builder_csrbank0_bus_errors2_w
-  attribute \src "ls180.v:1927.6-1927.37"
+  attribute \src "ls180.v:1972.6-1972.37"
   wire \builder_csrbank0_bus_errors2_we
-  attribute \src "ls180.v:1922.12-1922.42"
+  attribute \src "ls180.v:1967.12-1967.42"
   wire width 8 \builder_csrbank0_bus_errors3_r
-  attribute \src "ls180.v:1921.6-1921.37"
+  attribute \src "ls180.v:1966.6-1966.37"
   wire \builder_csrbank0_bus_errors3_re
-  attribute \src "ls180.v:1924.12-1924.42"
+  attribute \src "ls180.v:1969.12-1969.42"
   wire width 8 \builder_csrbank0_bus_errors3_w
-  attribute \src "ls180.v:1923.6-1923.37"
+  attribute \src "ls180.v:1968.6-1968.37"
   wire \builder_csrbank0_bus_errors3_we
-  attribute \src "ls180.v:1902.6-1902.31"
+  attribute \src "ls180.v:1947.6-1947.31"
   wire \builder_csrbank0_reset0_r
-  attribute \src "ls180.v:1901.6-1901.32"
+  attribute \src "ls180.v:1946.6-1946.32"
   wire \builder_csrbank0_reset0_re
-  attribute \src "ls180.v:1904.6-1904.31"
+  attribute \src "ls180.v:1949.6-1949.31"
   wire \builder_csrbank0_reset0_w
-  attribute \src "ls180.v:1903.6-1903.32"
+  attribute \src "ls180.v:1948.6-1948.32"
   wire \builder_csrbank0_reset0_we
-  attribute \src "ls180.v:1918.12-1918.39"
+  attribute \src "ls180.v:1963.12-1963.39"
   wire width 8 \builder_csrbank0_scratch0_r
-  attribute \src "ls180.v:1917.6-1917.34"
+  attribute \src "ls180.v:1962.6-1962.34"
   wire \builder_csrbank0_scratch0_re
-  attribute \src "ls180.v:1920.12-1920.39"
+  attribute \src "ls180.v:1965.12-1965.39"
   wire width 8 \builder_csrbank0_scratch0_w
-  attribute \src "ls180.v:1919.6-1919.34"
+  attribute \src "ls180.v:1964.6-1964.34"
   wire \builder_csrbank0_scratch0_we
-  attribute \src "ls180.v:1914.12-1914.39"
+  attribute \src "ls180.v:1959.12-1959.39"
   wire width 8 \builder_csrbank0_scratch1_r
-  attribute \src "ls180.v:1913.6-1913.34"
+  attribute \src "ls180.v:1958.6-1958.34"
   wire \builder_csrbank0_scratch1_re
-  attribute \src "ls180.v:1916.12-1916.39"
+  attribute \src "ls180.v:1961.12-1961.39"
   wire width 8 \builder_csrbank0_scratch1_w
-  attribute \src "ls180.v:1915.6-1915.34"
+  attribute \src "ls180.v:1960.6-1960.34"
   wire \builder_csrbank0_scratch1_we
-  attribute \src "ls180.v:1910.12-1910.39"
+  attribute \src "ls180.v:1955.12-1955.39"
   wire width 8 \builder_csrbank0_scratch2_r
-  attribute \src "ls180.v:1909.6-1909.34"
+  attribute \src "ls180.v:1954.6-1954.34"
   wire \builder_csrbank0_scratch2_re
-  attribute \src "ls180.v:1912.12-1912.39"
+  attribute \src "ls180.v:1957.12-1957.39"
   wire width 8 \builder_csrbank0_scratch2_w
-  attribute \src "ls180.v:1911.6-1911.34"
+  attribute \src "ls180.v:1956.6-1956.34"
   wire \builder_csrbank0_scratch2_we
-  attribute \src "ls180.v:1906.12-1906.39"
+  attribute \src "ls180.v:1951.12-1951.39"
   wire width 8 \builder_csrbank0_scratch3_r
-  attribute \src "ls180.v:1905.6-1905.34"
+  attribute \src "ls180.v:1950.6-1950.34"
   wire \builder_csrbank0_scratch3_re
-  attribute \src "ls180.v:1908.12-1908.39"
+  attribute \src "ls180.v:1953.12-1953.39"
   wire width 8 \builder_csrbank0_scratch3_w
-  attribute \src "ls180.v:1907.6-1907.34"
+  attribute \src "ls180.v:1952.6-1952.34"
   wire \builder_csrbank0_scratch3_we
-  attribute \src "ls180.v:1937.6-1937.26"
+  attribute \src "ls180.v:1982.6-1982.26"
   wire \builder_csrbank0_sel
-  attribute \src "ls180.v:2408.12-2408.40"
+  attribute \src "ls180.v:2453.12-2453.40"
   wire width 8 \builder_csrbank10_control0_r
-  attribute \src "ls180.v:2407.6-2407.35"
+  attribute \src "ls180.v:2452.6-2452.35"
   wire \builder_csrbank10_control0_re
-  attribute \src "ls180.v:2410.12-2410.40"
+  attribute \src "ls180.v:2455.12-2455.40"
   wire width 8 \builder_csrbank10_control0_w
-  attribute \src "ls180.v:2409.6-2409.35"
+  attribute \src "ls180.v:2454.6-2454.35"
   wire \builder_csrbank10_control0_we
-  attribute \src "ls180.v:2404.12-2404.40"
+  attribute \src "ls180.v:2449.12-2449.40"
   wire width 8 \builder_csrbank10_control1_r
-  attribute \src "ls180.v:2403.6-2403.35"
+  attribute \src "ls180.v:2448.6-2448.35"
   wire \builder_csrbank10_control1_re
-  attribute \src "ls180.v:2406.12-2406.40"
+  attribute \src "ls180.v:2451.12-2451.40"
   wire width 8 \builder_csrbank10_control1_w
-  attribute \src "ls180.v:2405.6-2405.35"
+  attribute \src "ls180.v:2450.6-2450.35"
   wire \builder_csrbank10_control1_we
-  attribute \src "ls180.v:2424.6-2424.29"
+  attribute \src "ls180.v:2469.6-2469.29"
   wire \builder_csrbank10_cs0_r
-  attribute \src "ls180.v:2423.6-2423.30"
+  attribute \src "ls180.v:2468.6-2468.30"
   wire \builder_csrbank10_cs0_re
-  attribute \src "ls180.v:2426.6-2426.29"
+  attribute \src "ls180.v:2471.6-2471.29"
   wire \builder_csrbank10_cs0_w
-  attribute \src "ls180.v:2425.6-2425.30"
+  attribute \src "ls180.v:2470.6-2470.30"
   wire \builder_csrbank10_cs0_we
-  attribute \src "ls180.v:2428.6-2428.35"
+  attribute \src "ls180.v:2473.6-2473.35"
   wire \builder_csrbank10_loopback0_r
-  attribute \src "ls180.v:2427.6-2427.36"
+  attribute \src "ls180.v:2472.6-2472.36"
   wire \builder_csrbank10_loopback0_re
-  attribute \src "ls180.v:2430.6-2430.35"
+  attribute \src "ls180.v:2475.6-2475.35"
   wire \builder_csrbank10_loopback0_w
-  attribute \src "ls180.v:2429.6-2429.36"
+  attribute \src "ls180.v:2474.6-2474.36"
   wire \builder_csrbank10_loopback0_we
-  attribute \src "ls180.v:2420.12-2420.36"
+  attribute \src "ls180.v:2465.12-2465.36"
   wire width 8 \builder_csrbank10_miso_r
-  attribute \src "ls180.v:2419.6-2419.31"
+  attribute \src "ls180.v:2464.6-2464.31"
   wire \builder_csrbank10_miso_re
-  attribute \src "ls180.v:2422.12-2422.36"
+  attribute \src "ls180.v:2467.12-2467.36"
   wire width 8 \builder_csrbank10_miso_w
-  attribute \src "ls180.v:2421.6-2421.31"
+  attribute \src "ls180.v:2466.6-2466.31"
   wire \builder_csrbank10_miso_we
-  attribute \src "ls180.v:2416.12-2416.37"
+  attribute \src "ls180.v:2461.12-2461.37"
   wire width 8 \builder_csrbank10_mosi0_r
-  attribute \src "ls180.v:2415.6-2415.32"
+  attribute \src "ls180.v:2460.6-2460.32"
   wire \builder_csrbank10_mosi0_re
-  attribute \src "ls180.v:2418.12-2418.37"
+  attribute \src "ls180.v:2463.12-2463.37"
   wire width 8 \builder_csrbank10_mosi0_w
-  attribute \src "ls180.v:2417.6-2417.32"
+  attribute \src "ls180.v:2462.6-2462.32"
   wire \builder_csrbank10_mosi0_we
-  attribute \src "ls180.v:2431.6-2431.27"
+  attribute \src "ls180.v:2476.6-2476.27"
   wire \builder_csrbank10_sel
-  attribute \src "ls180.v:2412.6-2412.32"
+  attribute \src "ls180.v:2457.6-2457.32"
   wire \builder_csrbank10_status_r
-  attribute \src "ls180.v:2411.6-2411.33"
+  attribute \src "ls180.v:2456.6-2456.33"
   wire \builder_csrbank10_status_re
-  attribute \src "ls180.v:2414.6-2414.32"
+  attribute \src "ls180.v:2459.6-2459.32"
   wire \builder_csrbank10_status_w
-  attribute \src "ls180.v:2413.6-2413.33"
+  attribute \src "ls180.v:2458.6-2458.33"
   wire \builder_csrbank10_status_we
-  attribute \src "ls180.v:2469.12-2469.44"
+  attribute \src "ls180.v:2514.12-2514.44"
   wire width 8 \builder_csrbank11_clk_divider0_r
-  attribute \src "ls180.v:2468.6-2468.39"
+  attribute \src "ls180.v:2513.6-2513.39"
   wire \builder_csrbank11_clk_divider0_re
-  attribute \src "ls180.v:2471.12-2471.44"
+  attribute \src "ls180.v:2516.12-2516.44"
   wire width 8 \builder_csrbank11_clk_divider0_w
-  attribute \src "ls180.v:2470.6-2470.39"
+  attribute \src "ls180.v:2515.6-2515.39"
   wire \builder_csrbank11_clk_divider0_we
-  attribute \src "ls180.v:2465.12-2465.44"
+  attribute \src "ls180.v:2510.12-2510.44"
   wire width 8 \builder_csrbank11_clk_divider1_r
-  attribute \src "ls180.v:2464.6-2464.39"
+  attribute \src "ls180.v:2509.6-2509.39"
   wire \builder_csrbank11_clk_divider1_re
-  attribute \src "ls180.v:2467.12-2467.44"
+  attribute \src "ls180.v:2512.12-2512.44"
   wire width 8 \builder_csrbank11_clk_divider1_w
-  attribute \src "ls180.v:2466.6-2466.39"
+  attribute \src "ls180.v:2511.6-2511.39"
   wire \builder_csrbank11_clk_divider1_we
-  attribute \src "ls180.v:2441.12-2441.40"
+  attribute \src "ls180.v:2486.12-2486.40"
   wire width 8 \builder_csrbank11_control0_r
-  attribute \src "ls180.v:2440.6-2440.35"
+  attribute \src "ls180.v:2485.6-2485.35"
   wire \builder_csrbank11_control0_re
-  attribute \src "ls180.v:2443.12-2443.40"
+  attribute \src "ls180.v:2488.12-2488.40"
   wire width 8 \builder_csrbank11_control0_w
-  attribute \src "ls180.v:2442.6-2442.35"
+  attribute \src "ls180.v:2487.6-2487.35"
   wire \builder_csrbank11_control0_we
-  attribute \src "ls180.v:2437.12-2437.40"
+  attribute \src "ls180.v:2482.12-2482.40"
   wire width 8 \builder_csrbank11_control1_r
-  attribute \src "ls180.v:2436.6-2436.35"
+  attribute \src "ls180.v:2481.6-2481.35"
   wire \builder_csrbank11_control1_re
-  attribute \src "ls180.v:2439.12-2439.40"
+  attribute \src "ls180.v:2484.12-2484.40"
   wire width 8 \builder_csrbank11_control1_w
-  attribute \src "ls180.v:2438.6-2438.35"
+  attribute \src "ls180.v:2483.6-2483.35"
   wire \builder_csrbank11_control1_we
-  attribute \src "ls180.v:2457.6-2457.29"
+  attribute \src "ls180.v:2502.6-2502.29"
   wire \builder_csrbank11_cs0_r
-  attribute \src "ls180.v:2456.6-2456.30"
+  attribute \src "ls180.v:2501.6-2501.30"
   wire \builder_csrbank11_cs0_re
-  attribute \src "ls180.v:2459.6-2459.29"
+  attribute \src "ls180.v:2504.6-2504.29"
   wire \builder_csrbank11_cs0_w
-  attribute \src "ls180.v:2458.6-2458.30"
+  attribute \src "ls180.v:2503.6-2503.30"
   wire \builder_csrbank11_cs0_we
-  attribute \src "ls180.v:2461.6-2461.35"
+  attribute \src "ls180.v:2506.6-2506.35"
   wire \builder_csrbank11_loopback0_r
-  attribute \src "ls180.v:2460.6-2460.36"
+  attribute \src "ls180.v:2505.6-2505.36"
   wire \builder_csrbank11_loopback0_re
-  attribute \src "ls180.v:2463.6-2463.35"
+  attribute \src "ls180.v:2508.6-2508.35"
   wire \builder_csrbank11_loopback0_w
-  attribute \src "ls180.v:2462.6-2462.36"
+  attribute \src "ls180.v:2507.6-2507.36"
   wire \builder_csrbank11_loopback0_we
-  attribute \src "ls180.v:2453.12-2453.36"
+  attribute \src "ls180.v:2498.12-2498.36"
   wire width 8 \builder_csrbank11_miso_r
-  attribute \src "ls180.v:2452.6-2452.31"
+  attribute \src "ls180.v:2497.6-2497.31"
   wire \builder_csrbank11_miso_re
-  attribute \src "ls180.v:2455.12-2455.36"
+  attribute \src "ls180.v:2500.12-2500.36"
   wire width 8 \builder_csrbank11_miso_w
-  attribute \src "ls180.v:2454.6-2454.31"
+  attribute \src "ls180.v:2499.6-2499.31"
   wire \builder_csrbank11_miso_we
-  attribute \src "ls180.v:2449.12-2449.37"
+  attribute \src "ls180.v:2494.12-2494.37"
   wire width 8 \builder_csrbank11_mosi0_r
-  attribute \src "ls180.v:2448.6-2448.32"
+  attribute \src "ls180.v:2493.6-2493.32"
   wire \builder_csrbank11_mosi0_re
-  attribute \src "ls180.v:2451.12-2451.37"
+  attribute \src "ls180.v:2496.12-2496.37"
   wire width 8 \builder_csrbank11_mosi0_w
-  attribute \src "ls180.v:2450.6-2450.32"
+  attribute \src "ls180.v:2495.6-2495.32"
   wire \builder_csrbank11_mosi0_we
-  attribute \src "ls180.v:2472.6-2472.27"
+  attribute \src "ls180.v:2517.6-2517.27"
   wire \builder_csrbank11_sel
-  attribute \src "ls180.v:2445.6-2445.32"
+  attribute \src "ls180.v:2490.6-2490.32"
   wire \builder_csrbank11_status_r
-  attribute \src "ls180.v:2444.6-2444.33"
+  attribute \src "ls180.v:2489.6-2489.33"
   wire \builder_csrbank11_status_re
-  attribute \src "ls180.v:2447.6-2447.32"
+  attribute \src "ls180.v:2492.6-2492.32"
   wire \builder_csrbank11_status_w
-  attribute \src "ls180.v:2446.6-2446.33"
+  attribute \src "ls180.v:2491.6-2491.33"
   wire \builder_csrbank11_status_we
-  attribute \src "ls180.v:2510.6-2510.29"
+  attribute \src "ls180.v:2555.6-2555.29"
   wire \builder_csrbank12_en0_r
-  attribute \src "ls180.v:2509.6-2509.30"
+  attribute \src "ls180.v:2554.6-2554.30"
   wire \builder_csrbank12_en0_re
-  attribute \src "ls180.v:2512.6-2512.29"
+  attribute \src "ls180.v:2557.6-2557.29"
   wire \builder_csrbank12_en0_w
-  attribute \src "ls180.v:2511.6-2511.30"
+  attribute \src "ls180.v:2556.6-2556.30"
   wire \builder_csrbank12_en0_we
-  attribute \src "ls180.v:2534.6-2534.36"
+  attribute \src "ls180.v:2579.6-2579.36"
   wire \builder_csrbank12_ev_enable0_r
-  attribute \src "ls180.v:2533.6-2533.37"
+  attribute \src "ls180.v:2578.6-2578.37"
   wire \builder_csrbank12_ev_enable0_re
-  attribute \src "ls180.v:2536.6-2536.36"
+  attribute \src "ls180.v:2581.6-2581.36"
   wire \builder_csrbank12_ev_enable0_w
-  attribute \src "ls180.v:2535.6-2535.37"
+  attribute \src "ls180.v:2580.6-2580.37"
   wire \builder_csrbank12_ev_enable0_we
-  attribute \src "ls180.v:2490.12-2490.37"
+  attribute \src "ls180.v:2535.12-2535.37"
   wire width 8 \builder_csrbank12_load0_r
-  attribute \src "ls180.v:2489.6-2489.32"
+  attribute \src "ls180.v:2534.6-2534.32"
   wire \builder_csrbank12_load0_re
-  attribute \src "ls180.v:2492.12-2492.37"
+  attribute \src "ls180.v:2537.12-2537.37"
   wire width 8 \builder_csrbank12_load0_w
-  attribute \src "ls180.v:2491.6-2491.32"
+  attribute \src "ls180.v:2536.6-2536.32"
   wire \builder_csrbank12_load0_we
-  attribute \src "ls180.v:2486.12-2486.37"
+  attribute \src "ls180.v:2531.12-2531.37"
   wire width 8 \builder_csrbank12_load1_r
-  attribute \src "ls180.v:2485.6-2485.32"
+  attribute \src "ls180.v:2530.6-2530.32"
   wire \builder_csrbank12_load1_re
-  attribute \src "ls180.v:2488.12-2488.37"
+  attribute \src "ls180.v:2533.12-2533.37"
   wire width 8 \builder_csrbank12_load1_w
-  attribute \src "ls180.v:2487.6-2487.32"
+  attribute \src "ls180.v:2532.6-2532.32"
   wire \builder_csrbank12_load1_we
-  attribute \src "ls180.v:2482.12-2482.37"
+  attribute \src "ls180.v:2527.12-2527.37"
   wire width 8 \builder_csrbank12_load2_r
-  attribute \src "ls180.v:2481.6-2481.32"
+  attribute \src "ls180.v:2526.6-2526.32"
   wire \builder_csrbank12_load2_re
-  attribute \src "ls180.v:2484.12-2484.37"
+  attribute \src "ls180.v:2529.12-2529.37"
   wire width 8 \builder_csrbank12_load2_w
-  attribute \src "ls180.v:2483.6-2483.32"
+  attribute \src "ls180.v:2528.6-2528.32"
   wire \builder_csrbank12_load2_we
-  attribute \src "ls180.v:2478.12-2478.37"
+  attribute \src "ls180.v:2523.12-2523.37"
   wire width 8 \builder_csrbank12_load3_r
-  attribute \src "ls180.v:2477.6-2477.32"
+  attribute \src "ls180.v:2522.6-2522.32"
   wire \builder_csrbank12_load3_re
-  attribute \src "ls180.v:2480.12-2480.37"
+  attribute \src "ls180.v:2525.12-2525.37"
   wire width 8 \builder_csrbank12_load3_w
-  attribute \src "ls180.v:2479.6-2479.32"
+  attribute \src "ls180.v:2524.6-2524.32"
   wire \builder_csrbank12_load3_we
-  attribute \src "ls180.v:2506.12-2506.39"
+  attribute \src "ls180.v:2551.12-2551.39"
   wire width 8 \builder_csrbank12_reload0_r
-  attribute \src "ls180.v:2505.6-2505.34"
+  attribute \src "ls180.v:2550.6-2550.34"
   wire \builder_csrbank12_reload0_re
-  attribute \src "ls180.v:2508.12-2508.39"
+  attribute \src "ls180.v:2553.12-2553.39"
   wire width 8 \builder_csrbank12_reload0_w
-  attribute \src "ls180.v:2507.6-2507.34"
+  attribute \src "ls180.v:2552.6-2552.34"
   wire \builder_csrbank12_reload0_we
-  attribute \src "ls180.v:2502.12-2502.39"
+  attribute \src "ls180.v:2547.12-2547.39"
   wire width 8 \builder_csrbank12_reload1_r
-  attribute \src "ls180.v:2501.6-2501.34"
+  attribute \src "ls180.v:2546.6-2546.34"
   wire \builder_csrbank12_reload1_re
-  attribute \src "ls180.v:2504.12-2504.39"
+  attribute \src "ls180.v:2549.12-2549.39"
   wire width 8 \builder_csrbank12_reload1_w
-  attribute \src "ls180.v:2503.6-2503.34"
+  attribute \src "ls180.v:2548.6-2548.34"
   wire \builder_csrbank12_reload1_we
-  attribute \src "ls180.v:2498.12-2498.39"
+  attribute \src "ls180.v:2543.12-2543.39"
   wire width 8 \builder_csrbank12_reload2_r
-  attribute \src "ls180.v:2497.6-2497.34"
+  attribute \src "ls180.v:2542.6-2542.34"
   wire \builder_csrbank12_reload2_re
-  attribute \src "ls180.v:2500.12-2500.39"
+  attribute \src "ls180.v:2545.12-2545.39"
   wire width 8 \builder_csrbank12_reload2_w
-  attribute \src "ls180.v:2499.6-2499.34"
+  attribute \src "ls180.v:2544.6-2544.34"
   wire \builder_csrbank12_reload2_we
-  attribute \src "ls180.v:2494.12-2494.39"
+  attribute \src "ls180.v:2539.12-2539.39"
   wire width 8 \builder_csrbank12_reload3_r
-  attribute \src "ls180.v:2493.6-2493.34"
+  attribute \src "ls180.v:2538.6-2538.34"
   wire \builder_csrbank12_reload3_re
-  attribute \src "ls180.v:2496.12-2496.39"
+  attribute \src "ls180.v:2541.12-2541.39"
   wire width 8 \builder_csrbank12_reload3_w
-  attribute \src "ls180.v:2495.6-2495.34"
+  attribute \src "ls180.v:2540.6-2540.34"
   wire \builder_csrbank12_reload3_we
-  attribute \src "ls180.v:2537.6-2537.27"
+  attribute \src "ls180.v:2582.6-2582.27"
   wire \builder_csrbank12_sel
-  attribute \src "ls180.v:2514.6-2514.39"
+  attribute \src "ls180.v:2559.6-2559.39"
   wire \builder_csrbank12_update_value0_r
-  attribute \src "ls180.v:2513.6-2513.40"
+  attribute \src "ls180.v:2558.6-2558.40"
   wire \builder_csrbank12_update_value0_re
-  attribute \src "ls180.v:2516.6-2516.39"
+  attribute \src "ls180.v:2561.6-2561.39"
   wire \builder_csrbank12_update_value0_w
-  attribute \src "ls180.v:2515.6-2515.40"
+  attribute \src "ls180.v:2560.6-2560.40"
   wire \builder_csrbank12_update_value0_we
-  attribute \src "ls180.v:2530.12-2530.38"
+  attribute \src "ls180.v:2575.12-2575.38"
   wire width 8 \builder_csrbank12_value0_r
-  attribute \src "ls180.v:2529.6-2529.33"
+  attribute \src "ls180.v:2574.6-2574.33"
   wire \builder_csrbank12_value0_re
-  attribute \src "ls180.v:2532.12-2532.38"
+  attribute \src "ls180.v:2577.12-2577.38"
   wire width 8 \builder_csrbank12_value0_w
-  attribute \src "ls180.v:2531.6-2531.33"
+  attribute \src "ls180.v:2576.6-2576.33"
   wire \builder_csrbank12_value0_we
-  attribute \src "ls180.v:2526.12-2526.38"
+  attribute \src "ls180.v:2571.12-2571.38"
   wire width 8 \builder_csrbank12_value1_r
-  attribute \src "ls180.v:2525.6-2525.33"
+  attribute \src "ls180.v:2570.6-2570.33"
   wire \builder_csrbank12_value1_re
-  attribute \src "ls180.v:2528.12-2528.38"
+  attribute \src "ls180.v:2573.12-2573.38"
   wire width 8 \builder_csrbank12_value1_w
-  attribute \src "ls180.v:2527.6-2527.33"
+  attribute \src "ls180.v:2572.6-2572.33"
   wire \builder_csrbank12_value1_we
-  attribute \src "ls180.v:2522.12-2522.38"
+  attribute \src "ls180.v:2567.12-2567.38"
   wire width 8 \builder_csrbank12_value2_r
-  attribute \src "ls180.v:2521.6-2521.33"
+  attribute \src "ls180.v:2566.6-2566.33"
   wire \builder_csrbank12_value2_re
-  attribute \src "ls180.v:2524.12-2524.38"
+  attribute \src "ls180.v:2569.12-2569.38"
   wire width 8 \builder_csrbank12_value2_w
-  attribute \src "ls180.v:2523.6-2523.33"
+  attribute \src "ls180.v:2568.6-2568.33"
   wire \builder_csrbank12_value2_we
-  attribute \src "ls180.v:2518.12-2518.38"
+  attribute \src "ls180.v:2563.12-2563.38"
   wire width 8 \builder_csrbank12_value3_r
-  attribute \src "ls180.v:2517.6-2517.33"
+  attribute \src "ls180.v:2562.6-2562.33"
   wire \builder_csrbank12_value3_re
-  attribute \src "ls180.v:2520.12-2520.38"
+  attribute \src "ls180.v:2565.12-2565.38"
   wire width 8 \builder_csrbank12_value3_w
-  attribute \src "ls180.v:2519.6-2519.33"
+  attribute \src "ls180.v:2564.6-2564.33"
   wire \builder_csrbank12_value3_we
-  attribute \src "ls180.v:2551.12-2551.42"
+  attribute \src "ls180.v:2596.12-2596.42"
   wire width 2 \builder_csrbank13_ev_enable0_r
-  attribute \src "ls180.v:2550.6-2550.37"
+  attribute \src "ls180.v:2595.6-2595.37"
   wire \builder_csrbank13_ev_enable0_re
-  attribute \src "ls180.v:2553.12-2553.42"
+  attribute \src "ls180.v:2598.12-2598.42"
   wire width 2 \builder_csrbank13_ev_enable0_w
-  attribute \src "ls180.v:2552.6-2552.37"
+  attribute \src "ls180.v:2597.6-2597.37"
   wire \builder_csrbank13_ev_enable0_we
-  attribute \src "ls180.v:2547.6-2547.33"
+  attribute \src "ls180.v:2592.6-2592.33"
   wire \builder_csrbank13_rxempty_r
-  attribute \src "ls180.v:2546.6-2546.34"
+  attribute \src "ls180.v:2591.6-2591.34"
   wire \builder_csrbank13_rxempty_re
-  attribute \src "ls180.v:2549.6-2549.33"
+  attribute \src "ls180.v:2594.6-2594.33"
   wire \builder_csrbank13_rxempty_w
-  attribute \src "ls180.v:2548.6-2548.34"
+  attribute \src "ls180.v:2593.6-2593.34"
   wire \builder_csrbank13_rxempty_we
-  attribute \src "ls180.v:2559.6-2559.32"
+  attribute \src "ls180.v:2604.6-2604.32"
   wire \builder_csrbank13_rxfull_r
-  attribute \src "ls180.v:2558.6-2558.33"
+  attribute \src "ls180.v:2603.6-2603.33"
   wire \builder_csrbank13_rxfull_re
-  attribute \src "ls180.v:2561.6-2561.32"
+  attribute \src "ls180.v:2606.6-2606.32"
   wire \builder_csrbank13_rxfull_w
-  attribute \src "ls180.v:2560.6-2560.33"
+  attribute \src "ls180.v:2605.6-2605.33"
   wire \builder_csrbank13_rxfull_we
-  attribute \src "ls180.v:2562.6-2562.27"
+  attribute \src "ls180.v:2607.6-2607.27"
   wire \builder_csrbank13_sel
-  attribute \src "ls180.v:2555.6-2555.33"
+  attribute \src "ls180.v:2600.6-2600.33"
   wire \builder_csrbank13_txempty_r
-  attribute \src "ls180.v:2554.6-2554.34"
+  attribute \src "ls180.v:2599.6-2599.34"
   wire \builder_csrbank13_txempty_re
-  attribute \src "ls180.v:2557.6-2557.33"
+  attribute \src "ls180.v:2602.6-2602.33"
   wire \builder_csrbank13_txempty_w
-  attribute \src "ls180.v:2556.6-2556.34"
+  attribute \src "ls180.v:2601.6-2601.34"
   wire \builder_csrbank13_txempty_we
-  attribute \src "ls180.v:2543.6-2543.32"
+  attribute \src "ls180.v:2588.6-2588.32"
   wire \builder_csrbank13_txfull_r
-  attribute \src "ls180.v:2542.6-2542.33"
+  attribute \src "ls180.v:2587.6-2587.33"
   wire \builder_csrbank13_txfull_re
-  attribute \src "ls180.v:2545.6-2545.32"
+  attribute \src "ls180.v:2590.6-2590.32"
   wire \builder_csrbank13_txfull_w
-  attribute \src "ls180.v:2544.6-2544.33"
+  attribute \src "ls180.v:2589.6-2589.33"
   wire \builder_csrbank13_txfull_we
-  attribute \src "ls180.v:2583.6-2583.27"
+  attribute \src "ls180.v:2628.6-2628.27"
   wire \builder_csrbank14_sel
-  attribute \src "ls180.v:2580.12-2580.44"
+  attribute \src "ls180.v:2625.12-2625.44"
   wire width 8 \builder_csrbank14_tuning_word0_r
-  attribute \src "ls180.v:2579.6-2579.39"
+  attribute \src "ls180.v:2624.6-2624.39"
   wire \builder_csrbank14_tuning_word0_re
-  attribute \src "ls180.v:2582.12-2582.44"
+  attribute \src "ls180.v:2627.12-2627.44"
   wire width 8 \builder_csrbank14_tuning_word0_w
-  attribute \src "ls180.v:2581.6-2581.39"
+  attribute \src "ls180.v:2626.6-2626.39"
   wire \builder_csrbank14_tuning_word0_we
-  attribute \src "ls180.v:2576.12-2576.44"
+  attribute \src "ls180.v:2621.12-2621.44"
   wire width 8 \builder_csrbank14_tuning_word1_r
-  attribute \src "ls180.v:2575.6-2575.39"
+  attribute \src "ls180.v:2620.6-2620.39"
   wire \builder_csrbank14_tuning_word1_re
-  attribute \src "ls180.v:2578.12-2578.44"
+  attribute \src "ls180.v:2623.12-2623.44"
   wire width 8 \builder_csrbank14_tuning_word1_w
-  attribute \src "ls180.v:2577.6-2577.39"
+  attribute \src "ls180.v:2622.6-2622.39"
   wire \builder_csrbank14_tuning_word1_we
-  attribute \src "ls180.v:2572.12-2572.44"
+  attribute \src "ls180.v:2617.12-2617.44"
   wire width 8 \builder_csrbank14_tuning_word2_r
-  attribute \src "ls180.v:2571.6-2571.39"
+  attribute \src "ls180.v:2616.6-2616.39"
   wire \builder_csrbank14_tuning_word2_re
-  attribute \src "ls180.v:2574.12-2574.44"
+  attribute \src "ls180.v:2619.12-2619.44"
   wire width 8 \builder_csrbank14_tuning_word2_w
-  attribute \src "ls180.v:2573.6-2573.39"
+  attribute \src "ls180.v:2618.6-2618.39"
   wire \builder_csrbank14_tuning_word2_we
-  attribute \src "ls180.v:2568.12-2568.44"
+  attribute \src "ls180.v:2613.12-2613.44"
   wire width 8 \builder_csrbank14_tuning_word3_r
-  attribute \src "ls180.v:2567.6-2567.39"
+  attribute \src "ls180.v:2612.6-2612.39"
   wire \builder_csrbank14_tuning_word3_re
-  attribute \src "ls180.v:2570.12-2570.44"
+  attribute \src "ls180.v:2615.12-2615.44"
   wire width 8 \builder_csrbank14_tuning_word3_w
-  attribute \src "ls180.v:2569.6-2569.39"
+  attribute \src "ls180.v:2614.6-2614.39"
   wire \builder_csrbank14_tuning_word3_we
-  attribute \src "ls180.v:1955.12-1955.34"
+  attribute \src "ls180.v:2000.12-2000.34"
   wire width 8 \builder_csrbank1_in0_r
-  attribute \src "ls180.v:1954.6-1954.29"
+  attribute \src "ls180.v:1999.6-1999.29"
   wire \builder_csrbank1_in0_re
-  attribute \src "ls180.v:1957.12-1957.34"
+  attribute \src "ls180.v:2002.12-2002.34"
   wire width 8 \builder_csrbank1_in0_w
-  attribute \src "ls180.v:1956.6-1956.29"
+  attribute \src "ls180.v:2001.6-2001.29"
   wire \builder_csrbank1_in0_we
-  attribute \src "ls180.v:1951.12-1951.34"
+  attribute \src "ls180.v:1996.12-1996.34"
   wire width 8 \builder_csrbank1_in1_r
-  attribute \src "ls180.v:1950.6-1950.29"
+  attribute \src "ls180.v:1995.6-1995.29"
   wire \builder_csrbank1_in1_re
-  attribute \src "ls180.v:1953.12-1953.34"
+  attribute \src "ls180.v:1998.12-1998.34"
   wire width 8 \builder_csrbank1_in1_w
-  attribute \src "ls180.v:1952.6-1952.29"
+  attribute \src "ls180.v:1997.6-1997.29"
   wire \builder_csrbank1_in1_we
-  attribute \src "ls180.v:1947.12-1947.34"
+  attribute \src "ls180.v:1992.12-1992.34"
   wire width 8 \builder_csrbank1_oe0_r
-  attribute \src "ls180.v:1946.6-1946.29"
+  attribute \src "ls180.v:1991.6-1991.29"
   wire \builder_csrbank1_oe0_re
-  attribute \src "ls180.v:1949.12-1949.34"
+  attribute \src "ls180.v:1994.12-1994.34"
   wire width 8 \builder_csrbank1_oe0_w
-  attribute \src "ls180.v:1948.6-1948.29"
+  attribute \src "ls180.v:1993.6-1993.29"
   wire \builder_csrbank1_oe0_we
-  attribute \src "ls180.v:1943.12-1943.34"
+  attribute \src "ls180.v:1988.12-1988.34"
   wire width 8 \builder_csrbank1_oe1_r
-  attribute \src "ls180.v:1942.6-1942.29"
+  attribute \src "ls180.v:1987.6-1987.29"
   wire \builder_csrbank1_oe1_re
-  attribute \src "ls180.v:1945.12-1945.34"
+  attribute \src "ls180.v:1990.12-1990.34"
   wire width 8 \builder_csrbank1_oe1_w
-  attribute \src "ls180.v:1944.6-1944.29"
+  attribute \src "ls180.v:1989.6-1989.29"
   wire \builder_csrbank1_oe1_we
-  attribute \src "ls180.v:1963.12-1963.35"
+  attribute \src "ls180.v:2008.12-2008.35"
   wire width 8 \builder_csrbank1_out0_r
-  attribute \src "ls180.v:1962.6-1962.30"
+  attribute \src "ls180.v:2007.6-2007.30"
   wire \builder_csrbank1_out0_re
-  attribute \src "ls180.v:1965.12-1965.35"
+  attribute \src "ls180.v:2010.12-2010.35"
   wire width 8 \builder_csrbank1_out0_w
-  attribute \src "ls180.v:1964.6-1964.30"
+  attribute \src "ls180.v:2009.6-2009.30"
   wire \builder_csrbank1_out0_we
-  attribute \src "ls180.v:1959.12-1959.35"
+  attribute \src "ls180.v:2004.12-2004.35"
   wire width 8 \builder_csrbank1_out1_r
-  attribute \src "ls180.v:1958.6-1958.30"
+  attribute \src "ls180.v:2003.6-2003.30"
   wire \builder_csrbank1_out1_re
-  attribute \src "ls180.v:1961.12-1961.35"
+  attribute \src "ls180.v:2006.12-2006.35"
   wire width 8 \builder_csrbank1_out1_w
-  attribute \src "ls180.v:1960.6-1960.30"
+  attribute \src "ls180.v:2005.6-2005.30"
   wire \builder_csrbank1_out1_we
-  attribute \src "ls180.v:1966.6-1966.26"
+  attribute \src "ls180.v:2011.6-2011.26"
   wire \builder_csrbank1_sel
-  attribute \src "ls180.v:1976.6-1976.26"
+  attribute \src "ls180.v:2021.6-2021.26"
   wire \builder_csrbank2_r_r
-  attribute \src "ls180.v:1975.6-1975.27"
+  attribute \src "ls180.v:2020.6-2020.27"
   wire \builder_csrbank2_r_re
-  attribute \src "ls180.v:1978.6-1978.26"
+  attribute \src "ls180.v:2023.6-2023.26"
   wire \builder_csrbank2_r_w
-  attribute \src "ls180.v:1977.6-1977.27"
+  attribute \src "ls180.v:2022.6-2022.27"
   wire \builder_csrbank2_r_we
-  attribute \src "ls180.v:1979.6-1979.26"
+  attribute \src "ls180.v:2024.6-2024.26"
   wire \builder_csrbank2_sel
-  attribute \src "ls180.v:1972.12-1972.33"
+  attribute \src "ls180.v:2017.12-2017.33"
   wire width 3 \builder_csrbank2_w0_r
-  attribute \src "ls180.v:1971.6-1971.28"
+  attribute \src "ls180.v:2016.6-2016.28"
   wire \builder_csrbank2_w0_re
-  attribute \src "ls180.v:1974.12-1974.33"
+  attribute \src "ls180.v:2019.12-2019.33"
   wire width 3 \builder_csrbank2_w0_w
-  attribute \src "ls180.v:1973.6-1973.28"
+  attribute \src "ls180.v:2018.6-2018.28"
   wire \builder_csrbank2_w0_we
-  attribute \src "ls180.v:1985.6-1985.32"
+  attribute \src "ls180.v:2030.6-2030.32"
   wire \builder_csrbank3_enable0_r
-  attribute \src "ls180.v:1984.6-1984.33"
+  attribute \src "ls180.v:2029.6-2029.33"
   wire \builder_csrbank3_enable0_re
-  attribute \src "ls180.v:1987.6-1987.32"
+  attribute \src "ls180.v:2032.6-2032.32"
   wire \builder_csrbank3_enable0_w
-  attribute \src "ls180.v:1986.6-1986.33"
+  attribute \src "ls180.v:2031.6-2031.33"
   wire \builder_csrbank3_enable0_we
-  attribute \src "ls180.v:2017.12-2017.38"
+  attribute \src "ls180.v:2062.12-2062.38"
   wire width 8 \builder_csrbank3_period0_r
-  attribute \src "ls180.v:2016.6-2016.33"
+  attribute \src "ls180.v:2061.6-2061.33"
   wire \builder_csrbank3_period0_re
-  attribute \src "ls180.v:2019.12-2019.38"
+  attribute \src "ls180.v:2064.12-2064.38"
   wire width 8 \builder_csrbank3_period0_w
-  attribute \src "ls180.v:2018.6-2018.33"
+  attribute \src "ls180.v:2063.6-2063.33"
   wire \builder_csrbank3_period0_we
-  attribute \src "ls180.v:2013.12-2013.38"
+  attribute \src "ls180.v:2058.12-2058.38"
   wire width 8 \builder_csrbank3_period1_r
-  attribute \src "ls180.v:2012.6-2012.33"
+  attribute \src "ls180.v:2057.6-2057.33"
   wire \builder_csrbank3_period1_re
-  attribute \src "ls180.v:2015.12-2015.38"
+  attribute \src "ls180.v:2060.12-2060.38"
   wire width 8 \builder_csrbank3_period1_w
-  attribute \src "ls180.v:2014.6-2014.33"
+  attribute \src "ls180.v:2059.6-2059.33"
   wire \builder_csrbank3_period1_we
-  attribute \src "ls180.v:2009.12-2009.38"
+  attribute \src "ls180.v:2054.12-2054.38"
   wire width 8 \builder_csrbank3_period2_r
-  attribute \src "ls180.v:2008.6-2008.33"
+  attribute \src "ls180.v:2053.6-2053.33"
   wire \builder_csrbank3_period2_re
-  attribute \src "ls180.v:2011.12-2011.38"
+  attribute \src "ls180.v:2056.12-2056.38"
   wire width 8 \builder_csrbank3_period2_w
-  attribute \src "ls180.v:2010.6-2010.33"
+  attribute \src "ls180.v:2055.6-2055.33"
   wire \builder_csrbank3_period2_we
-  attribute \src "ls180.v:2005.12-2005.38"
+  attribute \src "ls180.v:2050.12-2050.38"
   wire width 8 \builder_csrbank3_period3_r
-  attribute \src "ls180.v:2004.6-2004.33"
+  attribute \src "ls180.v:2049.6-2049.33"
   wire \builder_csrbank3_period3_re
-  attribute \src "ls180.v:2007.12-2007.38"
+  attribute \src "ls180.v:2052.12-2052.38"
   wire width 8 \builder_csrbank3_period3_w
-  attribute \src "ls180.v:2006.6-2006.33"
+  attribute \src "ls180.v:2051.6-2051.33"
   wire \builder_csrbank3_period3_we
-  attribute \src "ls180.v:2020.6-2020.26"
+  attribute \src "ls180.v:2065.6-2065.26"
   wire \builder_csrbank3_sel
-  attribute \src "ls180.v:2001.12-2001.37"
+  attribute \src "ls180.v:2046.12-2046.37"
   wire width 8 \builder_csrbank3_width0_r
-  attribute \src "ls180.v:2000.6-2000.32"
+  attribute \src "ls180.v:2045.6-2045.32"
   wire \builder_csrbank3_width0_re
-  attribute \src "ls180.v:2003.12-2003.37"
+  attribute \src "ls180.v:2048.12-2048.37"
   wire width 8 \builder_csrbank3_width0_w
-  attribute \src "ls180.v:2002.6-2002.32"
+  attribute \src "ls180.v:2047.6-2047.32"
   wire \builder_csrbank3_width0_we
-  attribute \src "ls180.v:1997.12-1997.37"
+  attribute \src "ls180.v:2042.12-2042.37"
   wire width 8 \builder_csrbank3_width1_r
-  attribute \src "ls180.v:1996.6-1996.32"
+  attribute \src "ls180.v:2041.6-2041.32"
   wire \builder_csrbank3_width1_re
-  attribute \src "ls180.v:1999.12-1999.37"
+  attribute \src "ls180.v:2044.12-2044.37"
   wire width 8 \builder_csrbank3_width1_w
-  attribute \src "ls180.v:1998.6-1998.32"
+  attribute \src "ls180.v:2043.6-2043.32"
   wire \builder_csrbank3_width1_we
-  attribute \src "ls180.v:1993.12-1993.37"
+  attribute \src "ls180.v:2038.12-2038.37"
   wire width 8 \builder_csrbank3_width2_r
-  attribute \src "ls180.v:1992.6-1992.32"
+  attribute \src "ls180.v:2037.6-2037.32"
   wire \builder_csrbank3_width2_re
-  attribute \src "ls180.v:1995.12-1995.37"
+  attribute \src "ls180.v:2040.12-2040.37"
   wire width 8 \builder_csrbank3_width2_w
-  attribute \src "ls180.v:1994.6-1994.32"
+  attribute \src "ls180.v:2039.6-2039.32"
   wire \builder_csrbank3_width2_we
-  attribute \src "ls180.v:1989.12-1989.37"
+  attribute \src "ls180.v:2034.12-2034.37"
   wire width 8 \builder_csrbank3_width3_r
-  attribute \src "ls180.v:1988.6-1988.32"
+  attribute \src "ls180.v:2033.6-2033.32"
   wire \builder_csrbank3_width3_re
-  attribute \src "ls180.v:1991.12-1991.37"
+  attribute \src "ls180.v:2036.12-2036.37"
   wire width 8 \builder_csrbank3_width3_w
-  attribute \src "ls180.v:1990.6-1990.32"
+  attribute \src "ls180.v:2035.6-2035.32"
   wire \builder_csrbank3_width3_we
-  attribute \src "ls180.v:2026.6-2026.32"
+  attribute \src "ls180.v:2071.6-2071.32"
   wire \builder_csrbank4_enable0_r
-  attribute \src "ls180.v:2025.6-2025.33"
+  attribute \src "ls180.v:2070.6-2070.33"
   wire \builder_csrbank4_enable0_re
-  attribute \src "ls180.v:2028.6-2028.32"
+  attribute \src "ls180.v:2073.6-2073.32"
   wire \builder_csrbank4_enable0_w
-  attribute \src "ls180.v:2027.6-2027.33"
+  attribute \src "ls180.v:2072.6-2072.33"
   wire \builder_csrbank4_enable0_we
-  attribute \src "ls180.v:2058.12-2058.38"
+  attribute \src "ls180.v:2103.12-2103.38"
   wire width 8 \builder_csrbank4_period0_r
-  attribute \src "ls180.v:2057.6-2057.33"
+  attribute \src "ls180.v:2102.6-2102.33"
   wire \builder_csrbank4_period0_re
-  attribute \src "ls180.v:2060.12-2060.38"
+  attribute \src "ls180.v:2105.12-2105.38"
   wire width 8 \builder_csrbank4_period0_w
-  attribute \src "ls180.v:2059.6-2059.33"
+  attribute \src "ls180.v:2104.6-2104.33"
   wire \builder_csrbank4_period0_we
-  attribute \src "ls180.v:2054.12-2054.38"
+  attribute \src "ls180.v:2099.12-2099.38"
   wire width 8 \builder_csrbank4_period1_r
-  attribute \src "ls180.v:2053.6-2053.33"
+  attribute \src "ls180.v:2098.6-2098.33"
   wire \builder_csrbank4_period1_re
-  attribute \src "ls180.v:2056.12-2056.38"
+  attribute \src "ls180.v:2101.12-2101.38"
   wire width 8 \builder_csrbank4_period1_w
-  attribute \src "ls180.v:2055.6-2055.33"
+  attribute \src "ls180.v:2100.6-2100.33"
   wire \builder_csrbank4_period1_we
-  attribute \src "ls180.v:2050.12-2050.38"
+  attribute \src "ls180.v:2095.12-2095.38"
   wire width 8 \builder_csrbank4_period2_r
-  attribute \src "ls180.v:2049.6-2049.33"
+  attribute \src "ls180.v:2094.6-2094.33"
   wire \builder_csrbank4_period2_re
-  attribute \src "ls180.v:2052.12-2052.38"
+  attribute \src "ls180.v:2097.12-2097.38"
   wire width 8 \builder_csrbank4_period2_w
-  attribute \src "ls180.v:2051.6-2051.33"
+  attribute \src "ls180.v:2096.6-2096.33"
   wire \builder_csrbank4_period2_we
-  attribute \src "ls180.v:2046.12-2046.38"
+  attribute \src "ls180.v:2091.12-2091.38"
   wire width 8 \builder_csrbank4_period3_r
-  attribute \src "ls180.v:2045.6-2045.33"
+  attribute \src "ls180.v:2090.6-2090.33"
   wire \builder_csrbank4_period3_re
-  attribute \src "ls180.v:2048.12-2048.38"
+  attribute \src "ls180.v:2093.12-2093.38"
   wire width 8 \builder_csrbank4_period3_w
-  attribute \src "ls180.v:2047.6-2047.33"
+  attribute \src "ls180.v:2092.6-2092.33"
   wire \builder_csrbank4_period3_we
-  attribute \src "ls180.v:2061.6-2061.26"
+  attribute \src "ls180.v:2106.6-2106.26"
   wire \builder_csrbank4_sel
-  attribute \src "ls180.v:2042.12-2042.37"
+  attribute \src "ls180.v:2087.12-2087.37"
   wire width 8 \builder_csrbank4_width0_r
-  attribute \src "ls180.v:2041.6-2041.32"
+  attribute \src "ls180.v:2086.6-2086.32"
   wire \builder_csrbank4_width0_re
-  attribute \src "ls180.v:2044.12-2044.37"
+  attribute \src "ls180.v:2089.12-2089.37"
   wire width 8 \builder_csrbank4_width0_w
-  attribute \src "ls180.v:2043.6-2043.32"
+  attribute \src "ls180.v:2088.6-2088.32"
   wire \builder_csrbank4_width0_we
-  attribute \src "ls180.v:2038.12-2038.37"
+  attribute \src "ls180.v:2083.12-2083.37"
   wire width 8 \builder_csrbank4_width1_r
-  attribute \src "ls180.v:2037.6-2037.32"
+  attribute \src "ls180.v:2082.6-2082.32"
   wire \builder_csrbank4_width1_re
-  attribute \src "ls180.v:2040.12-2040.37"
+  attribute \src "ls180.v:2085.12-2085.37"
   wire width 8 \builder_csrbank4_width1_w
-  attribute \src "ls180.v:2039.6-2039.32"
+  attribute \src "ls180.v:2084.6-2084.32"
   wire \builder_csrbank4_width1_we
-  attribute \src "ls180.v:2034.12-2034.37"
+  attribute \src "ls180.v:2079.12-2079.37"
   wire width 8 \builder_csrbank4_width2_r
-  attribute \src "ls180.v:2033.6-2033.32"
+  attribute \src "ls180.v:2078.6-2078.32"
   wire \builder_csrbank4_width2_re
-  attribute \src "ls180.v:2036.12-2036.37"
+  attribute \src "ls180.v:2081.12-2081.37"
   wire width 8 \builder_csrbank4_width2_w
-  attribute \src "ls180.v:2035.6-2035.32"
+  attribute \src "ls180.v:2080.6-2080.32"
   wire \builder_csrbank4_width2_we
-  attribute \src "ls180.v:2030.12-2030.37"
+  attribute \src "ls180.v:2075.12-2075.37"
   wire width 8 \builder_csrbank4_width3_r
-  attribute \src "ls180.v:2029.6-2029.32"
+  attribute \src "ls180.v:2074.6-2074.32"
   wire \builder_csrbank4_width3_re
-  attribute \src "ls180.v:2032.12-2032.37"
+  attribute \src "ls180.v:2077.12-2077.37"
   wire width 8 \builder_csrbank4_width3_w
-  attribute \src "ls180.v:2031.6-2031.32"
+  attribute \src "ls180.v:2076.6-2076.32"
   wire \builder_csrbank4_width3_we
-  attribute \src "ls180.v:2095.12-2095.40"
+  attribute \src "ls180.v:2140.12-2140.40"
   wire width 8 \builder_csrbank5_dma_base0_r
-  attribute \src "ls180.v:2094.6-2094.35"
+  attribute \src "ls180.v:2139.6-2139.35"
   wire \builder_csrbank5_dma_base0_re
-  attribute \src "ls180.v:2097.12-2097.40"
+  attribute \src "ls180.v:2142.12-2142.40"
   wire width 8 \builder_csrbank5_dma_base0_w
-  attribute \src "ls180.v:2096.6-2096.35"
+  attribute \src "ls180.v:2141.6-2141.35"
   wire \builder_csrbank5_dma_base0_we
-  attribute \src "ls180.v:2091.12-2091.40"
+  attribute \src "ls180.v:2136.12-2136.40"
   wire width 8 \builder_csrbank5_dma_base1_r
-  attribute \src "ls180.v:2090.6-2090.35"
+  attribute \src "ls180.v:2135.6-2135.35"
   wire \builder_csrbank5_dma_base1_re
-  attribute \src "ls180.v:2093.12-2093.40"
+  attribute \src "ls180.v:2138.12-2138.40"
   wire width 8 \builder_csrbank5_dma_base1_w
-  attribute \src "ls180.v:2092.6-2092.35"
+  attribute \src "ls180.v:2137.6-2137.35"
   wire \builder_csrbank5_dma_base1_we
-  attribute \src "ls180.v:2087.12-2087.40"
+  attribute \src "ls180.v:2132.12-2132.40"
   wire width 8 \builder_csrbank5_dma_base2_r
-  attribute \src "ls180.v:2086.6-2086.35"
+  attribute \src "ls180.v:2131.6-2131.35"
   wire \builder_csrbank5_dma_base2_re
-  attribute \src "ls180.v:2089.12-2089.40"
+  attribute \src "ls180.v:2134.12-2134.40"
   wire width 8 \builder_csrbank5_dma_base2_w
-  attribute \src "ls180.v:2088.6-2088.35"
+  attribute \src "ls180.v:2133.6-2133.35"
   wire \builder_csrbank5_dma_base2_we
-  attribute \src "ls180.v:2083.12-2083.40"
+  attribute \src "ls180.v:2128.12-2128.40"
   wire width 8 \builder_csrbank5_dma_base3_r
-  attribute \src "ls180.v:2082.6-2082.35"
+  attribute \src "ls180.v:2127.6-2127.35"
   wire \builder_csrbank5_dma_base3_re
-  attribute \src "ls180.v:2085.12-2085.40"
+  attribute \src "ls180.v:2130.12-2130.40"
   wire width 8 \builder_csrbank5_dma_base3_w
-  attribute \src "ls180.v:2084.6-2084.35"
+  attribute \src "ls180.v:2129.6-2129.35"
   wire \builder_csrbank5_dma_base3_we
-  attribute \src "ls180.v:2079.12-2079.40"
+  attribute \src "ls180.v:2124.12-2124.40"
   wire width 8 \builder_csrbank5_dma_base4_r
-  attribute \src "ls180.v:2078.6-2078.35"
+  attribute \src "ls180.v:2123.6-2123.35"
   wire \builder_csrbank5_dma_base4_re
-  attribute \src "ls180.v:2081.12-2081.40"
+  attribute \src "ls180.v:2126.12-2126.40"
   wire width 8 \builder_csrbank5_dma_base4_w
-  attribute \src "ls180.v:2080.6-2080.35"
+  attribute \src "ls180.v:2125.6-2125.35"
   wire \builder_csrbank5_dma_base4_we
-  attribute \src "ls180.v:2075.12-2075.40"
+  attribute \src "ls180.v:2120.12-2120.40"
   wire width 8 \builder_csrbank5_dma_base5_r
-  attribute \src "ls180.v:2074.6-2074.35"
+  attribute \src "ls180.v:2119.6-2119.35"
   wire \builder_csrbank5_dma_base5_re
-  attribute \src "ls180.v:2077.12-2077.40"
+  attribute \src "ls180.v:2122.12-2122.40"
   wire width 8 \builder_csrbank5_dma_base5_w
-  attribute \src "ls180.v:2076.6-2076.35"
+  attribute \src "ls180.v:2121.6-2121.35"
   wire \builder_csrbank5_dma_base5_we
-  attribute \src "ls180.v:2071.12-2071.40"
+  attribute \src "ls180.v:2116.12-2116.40"
   wire width 8 \builder_csrbank5_dma_base6_r
-  attribute \src "ls180.v:2070.6-2070.35"
+  attribute \src "ls180.v:2115.6-2115.35"
   wire \builder_csrbank5_dma_base6_re
-  attribute \src "ls180.v:2073.12-2073.40"
+  attribute \src "ls180.v:2118.12-2118.40"
   wire width 8 \builder_csrbank5_dma_base6_w
-  attribute \src "ls180.v:2072.6-2072.35"
+  attribute \src "ls180.v:2117.6-2117.35"
   wire \builder_csrbank5_dma_base6_we
-  attribute \src "ls180.v:2067.12-2067.40"
+  attribute \src "ls180.v:2112.12-2112.40"
   wire width 8 \builder_csrbank5_dma_base7_r
-  attribute \src "ls180.v:2066.6-2066.35"
+  attribute \src "ls180.v:2111.6-2111.35"
   wire \builder_csrbank5_dma_base7_re
-  attribute \src "ls180.v:2069.12-2069.40"
+  attribute \src "ls180.v:2114.12-2114.40"
   wire width 8 \builder_csrbank5_dma_base7_w
-  attribute \src "ls180.v:2068.6-2068.35"
+  attribute \src "ls180.v:2113.6-2113.35"
   wire \builder_csrbank5_dma_base7_we
-  attribute \src "ls180.v:2119.6-2119.33"
+  attribute \src "ls180.v:2164.6-2164.33"
   wire \builder_csrbank5_dma_done_r
-  attribute \src "ls180.v:2118.6-2118.34"
+  attribute \src "ls180.v:2163.6-2163.34"
   wire \builder_csrbank5_dma_done_re
-  attribute \src "ls180.v:2121.6-2121.33"
+  attribute \src "ls180.v:2166.6-2166.33"
   wire \builder_csrbank5_dma_done_w
-  attribute \src "ls180.v:2120.6-2120.34"
+  attribute \src "ls180.v:2165.6-2165.34"
   wire \builder_csrbank5_dma_done_we
-  attribute \src "ls180.v:2115.6-2115.36"
+  attribute \src "ls180.v:2160.6-2160.36"
   wire \builder_csrbank5_dma_enable0_r
-  attribute \src "ls180.v:2114.6-2114.37"
+  attribute \src "ls180.v:2159.6-2159.37"
   wire \builder_csrbank5_dma_enable0_re
-  attribute \src "ls180.v:2117.6-2117.36"
+  attribute \src "ls180.v:2162.6-2162.36"
   wire \builder_csrbank5_dma_enable0_w
-  attribute \src "ls180.v:2116.6-2116.37"
+  attribute \src "ls180.v:2161.6-2161.37"
   wire \builder_csrbank5_dma_enable0_we
-  attribute \src "ls180.v:2111.12-2111.42"
+  attribute \src "ls180.v:2156.12-2156.42"
   wire width 8 \builder_csrbank5_dma_length0_r
-  attribute \src "ls180.v:2110.6-2110.37"
+  attribute \src "ls180.v:2155.6-2155.37"
   wire \builder_csrbank5_dma_length0_re
-  attribute \src "ls180.v:2113.12-2113.42"
+  attribute \src "ls180.v:2158.12-2158.42"
   wire width 8 \builder_csrbank5_dma_length0_w
-  attribute \src "ls180.v:2112.6-2112.37"
+  attribute \src "ls180.v:2157.6-2157.37"
   wire \builder_csrbank5_dma_length0_we
-  attribute \src "ls180.v:2107.12-2107.42"
+  attribute \src "ls180.v:2152.12-2152.42"
   wire width 8 \builder_csrbank5_dma_length1_r
-  attribute \src "ls180.v:2106.6-2106.37"
+  attribute \src "ls180.v:2151.6-2151.37"
   wire \builder_csrbank5_dma_length1_re
-  attribute \src "ls180.v:2109.12-2109.42"
+  attribute \src "ls180.v:2154.12-2154.42"
   wire width 8 \builder_csrbank5_dma_length1_w
-  attribute \src "ls180.v:2108.6-2108.37"
+  attribute \src "ls180.v:2153.6-2153.37"
   wire \builder_csrbank5_dma_length1_we
-  attribute \src "ls180.v:2103.12-2103.42"
+  attribute \src "ls180.v:2148.12-2148.42"
   wire width 8 \builder_csrbank5_dma_length2_r
-  attribute \src "ls180.v:2102.6-2102.37"
+  attribute \src "ls180.v:2147.6-2147.37"
   wire \builder_csrbank5_dma_length2_re
-  attribute \src "ls180.v:2105.12-2105.42"
+  attribute \src "ls180.v:2150.12-2150.42"
   wire width 8 \builder_csrbank5_dma_length2_w
-  attribute \src "ls180.v:2104.6-2104.37"
+  attribute \src "ls180.v:2149.6-2149.37"
   wire \builder_csrbank5_dma_length2_we
-  attribute \src "ls180.v:2099.12-2099.42"
+  attribute \src "ls180.v:2144.12-2144.42"
   wire width 8 \builder_csrbank5_dma_length3_r
-  attribute \src "ls180.v:2098.6-2098.37"
+  attribute \src "ls180.v:2143.6-2143.37"
   wire \builder_csrbank5_dma_length3_re
-  attribute \src "ls180.v:2101.12-2101.42"
+  attribute \src "ls180.v:2146.12-2146.42"
   wire width 8 \builder_csrbank5_dma_length3_w
-  attribute \src "ls180.v:2100.6-2100.37"
+  attribute \src "ls180.v:2145.6-2145.37"
   wire \builder_csrbank5_dma_length3_we
-  attribute \src "ls180.v:2123.6-2123.34"
+  attribute \src "ls180.v:2168.6-2168.34"
   wire \builder_csrbank5_dma_loop0_r
-  attribute \src "ls180.v:2122.6-2122.35"
+  attribute \src "ls180.v:2167.6-2167.35"
   wire \builder_csrbank5_dma_loop0_re
-  attribute \src "ls180.v:2125.6-2125.34"
+  attribute \src "ls180.v:2170.6-2170.34"
   wire \builder_csrbank5_dma_loop0_w
-  attribute \src "ls180.v:2124.6-2124.35"
+  attribute \src "ls180.v:2169.6-2169.35"
   wire \builder_csrbank5_dma_loop0_we
-  attribute \src "ls180.v:2126.6-2126.26"
+  attribute \src "ls180.v:2171.6-2171.26"
   wire \builder_csrbank5_sel
-  attribute \src "ls180.v:2256.12-2256.43"
+  attribute \src "ls180.v:2301.12-2301.43"
   wire width 8 \builder_csrbank6_block_count0_r
-  attribute \src "ls180.v:2255.6-2255.38"
+  attribute \src "ls180.v:2300.6-2300.38"
   wire \builder_csrbank6_block_count0_re
-  attribute \src "ls180.v:2258.12-2258.43"
+  attribute \src "ls180.v:2303.12-2303.43"
   wire width 8 \builder_csrbank6_block_count0_w
-  attribute \src "ls180.v:2257.6-2257.38"
+  attribute \src "ls180.v:2302.6-2302.38"
   wire \builder_csrbank6_block_count0_we
-  attribute \src "ls180.v:2252.12-2252.43"
+  attribute \src "ls180.v:2297.12-2297.43"
   wire width 8 \builder_csrbank6_block_count1_r
-  attribute \src "ls180.v:2251.6-2251.38"
+  attribute \src "ls180.v:2296.6-2296.38"
   wire \builder_csrbank6_block_count1_re
-  attribute \src "ls180.v:2254.12-2254.43"
+  attribute \src "ls180.v:2299.12-2299.43"
   wire width 8 \builder_csrbank6_block_count1_w
-  attribute \src "ls180.v:2253.6-2253.38"
+  attribute \src "ls180.v:2298.6-2298.38"
   wire \builder_csrbank6_block_count1_we
-  attribute \src "ls180.v:2248.12-2248.43"
+  attribute \src "ls180.v:2293.12-2293.43"
   wire width 8 \builder_csrbank6_block_count2_r
-  attribute \src "ls180.v:2247.6-2247.38"
+  attribute \src "ls180.v:2292.6-2292.38"
   wire \builder_csrbank6_block_count2_re
-  attribute \src "ls180.v:2250.12-2250.43"
+  attribute \src "ls180.v:2295.12-2295.43"
   wire width 8 \builder_csrbank6_block_count2_w
-  attribute \src "ls180.v:2249.6-2249.38"
+  attribute \src "ls180.v:2294.6-2294.38"
   wire \builder_csrbank6_block_count2_we
-  attribute \src "ls180.v:2244.12-2244.43"
+  attribute \src "ls180.v:2289.12-2289.43"
   wire width 8 \builder_csrbank6_block_count3_r
-  attribute \src "ls180.v:2243.6-2243.38"
+  attribute \src "ls180.v:2288.6-2288.38"
   wire \builder_csrbank6_block_count3_re
-  attribute \src "ls180.v:2246.12-2246.43"
+  attribute \src "ls180.v:2291.12-2291.43"
   wire width 8 \builder_csrbank6_block_count3_w
-  attribute \src "ls180.v:2245.6-2245.38"
+  attribute \src "ls180.v:2290.6-2290.38"
   wire \builder_csrbank6_block_count3_we
-  attribute \src "ls180.v:2240.12-2240.44"
+  attribute \src "ls180.v:2285.12-2285.44"
   wire width 8 \builder_csrbank6_block_length0_r
-  attribute \src "ls180.v:2239.6-2239.39"
+  attribute \src "ls180.v:2284.6-2284.39"
   wire \builder_csrbank6_block_length0_re
-  attribute \src "ls180.v:2242.12-2242.44"
+  attribute \src "ls180.v:2287.12-2287.44"
   wire width 8 \builder_csrbank6_block_length0_w
-  attribute \src "ls180.v:2241.6-2241.39"
+  attribute \src "ls180.v:2286.6-2286.39"
   wire \builder_csrbank6_block_length0_we
-  attribute \src "ls180.v:2236.12-2236.44"
+  attribute \src "ls180.v:2281.12-2281.44"
   wire width 2 \builder_csrbank6_block_length1_r
-  attribute \src "ls180.v:2235.6-2235.39"
+  attribute \src "ls180.v:2280.6-2280.39"
   wire \builder_csrbank6_block_length1_re
-  attribute \src "ls180.v:2238.12-2238.44"
+  attribute \src "ls180.v:2283.12-2283.44"
   wire width 2 \builder_csrbank6_block_length1_w
-  attribute \src "ls180.v:2237.6-2237.39"
+  attribute \src "ls180.v:2282.6-2282.39"
   wire \builder_csrbank6_block_length1_we
-  attribute \src "ls180.v:2144.12-2144.44"
+  attribute \src "ls180.v:2189.12-2189.44"
   wire width 8 \builder_csrbank6_cmd_argument0_r
-  attribute \src "ls180.v:2143.6-2143.39"
+  attribute \src "ls180.v:2188.6-2188.39"
   wire \builder_csrbank6_cmd_argument0_re
-  attribute \src "ls180.v:2146.12-2146.44"
+  attribute \src "ls180.v:2191.12-2191.44"
   wire width 8 \builder_csrbank6_cmd_argument0_w
-  attribute \src "ls180.v:2145.6-2145.39"
+  attribute \src "ls180.v:2190.6-2190.39"
   wire \builder_csrbank6_cmd_argument0_we
-  attribute \src "ls180.v:2140.12-2140.44"
+  attribute \src "ls180.v:2185.12-2185.44"
   wire width 8 \builder_csrbank6_cmd_argument1_r
-  attribute \src "ls180.v:2139.6-2139.39"
+  attribute \src "ls180.v:2184.6-2184.39"
   wire \builder_csrbank6_cmd_argument1_re
-  attribute \src "ls180.v:2142.12-2142.44"
+  attribute \src "ls180.v:2187.12-2187.44"
   wire width 8 \builder_csrbank6_cmd_argument1_w
-  attribute \src "ls180.v:2141.6-2141.39"
+  attribute \src "ls180.v:2186.6-2186.39"
   wire \builder_csrbank6_cmd_argument1_we
-  attribute \src "ls180.v:2136.12-2136.44"
+  attribute \src "ls180.v:2181.12-2181.44"
   wire width 8 \builder_csrbank6_cmd_argument2_r
-  attribute \src "ls180.v:2135.6-2135.39"
+  attribute \src "ls180.v:2180.6-2180.39"
   wire \builder_csrbank6_cmd_argument2_re
-  attribute \src "ls180.v:2138.12-2138.44"
+  attribute \src "ls180.v:2183.12-2183.44"
   wire width 8 \builder_csrbank6_cmd_argument2_w
-  attribute \src "ls180.v:2137.6-2137.39"
+  attribute \src "ls180.v:2182.6-2182.39"
   wire \builder_csrbank6_cmd_argument2_we
-  attribute \src "ls180.v:2132.12-2132.44"
+  attribute \src "ls180.v:2177.12-2177.44"
   wire width 8 \builder_csrbank6_cmd_argument3_r
-  attribute \src "ls180.v:2131.6-2131.39"
+  attribute \src "ls180.v:2176.6-2176.39"
   wire \builder_csrbank6_cmd_argument3_re
-  attribute \src "ls180.v:2134.12-2134.44"
+  attribute \src "ls180.v:2179.12-2179.44"
   wire width 8 \builder_csrbank6_cmd_argument3_w
-  attribute \src "ls180.v:2133.6-2133.39"
+  attribute \src "ls180.v:2178.6-2178.39"
   wire \builder_csrbank6_cmd_argument3_we
-  attribute \src "ls180.v:2160.12-2160.43"
+  attribute \src "ls180.v:2205.12-2205.43"
   wire width 8 \builder_csrbank6_cmd_command0_r
-  attribute \src "ls180.v:2159.6-2159.38"
+  attribute \src "ls180.v:2204.6-2204.38"
   wire \builder_csrbank6_cmd_command0_re
-  attribute \src "ls180.v:2162.12-2162.43"
+  attribute \src "ls180.v:2207.12-2207.43"
   wire width 8 \builder_csrbank6_cmd_command0_w
-  attribute \src "ls180.v:2161.6-2161.38"
+  attribute \src "ls180.v:2206.6-2206.38"
   wire \builder_csrbank6_cmd_command0_we
-  attribute \src "ls180.v:2156.12-2156.43"
+  attribute \src "ls180.v:2201.12-2201.43"
   wire width 8 \builder_csrbank6_cmd_command1_r
-  attribute \src "ls180.v:2155.6-2155.38"
+  attribute \src "ls180.v:2200.6-2200.38"
   wire \builder_csrbank6_cmd_command1_re
-  attribute \src "ls180.v:2158.12-2158.43"
+  attribute \src "ls180.v:2203.12-2203.43"
   wire width 8 \builder_csrbank6_cmd_command1_w
-  attribute \src "ls180.v:2157.6-2157.38"
+  attribute \src "ls180.v:2202.6-2202.38"
   wire \builder_csrbank6_cmd_command1_we
-  attribute \src "ls180.v:2152.12-2152.43"
+  attribute \src "ls180.v:2197.12-2197.43"
   wire width 8 \builder_csrbank6_cmd_command2_r
-  attribute \src "ls180.v:2151.6-2151.38"
+  attribute \src "ls180.v:2196.6-2196.38"
   wire \builder_csrbank6_cmd_command2_re
-  attribute \src "ls180.v:2154.12-2154.43"
+  attribute \src "ls180.v:2199.12-2199.43"
   wire width 8 \builder_csrbank6_cmd_command2_w
-  attribute \src "ls180.v:2153.6-2153.38"
+  attribute \src "ls180.v:2198.6-2198.38"
   wire \builder_csrbank6_cmd_command2_we
-  attribute \src "ls180.v:2148.12-2148.43"
+  attribute \src "ls180.v:2193.12-2193.43"
   wire width 8 \builder_csrbank6_cmd_command3_r
-  attribute \src "ls180.v:2147.6-2147.38"
+  attribute \src "ls180.v:2192.6-2192.38"
   wire \builder_csrbank6_cmd_command3_re
-  attribute \src "ls180.v:2150.12-2150.43"
+  attribute \src "ls180.v:2195.12-2195.43"
   wire width 8 \builder_csrbank6_cmd_command3_w
-  attribute \src "ls180.v:2149.6-2149.38"
+  attribute \src "ls180.v:2194.6-2194.38"
   wire \builder_csrbank6_cmd_command3_we
-  attribute \src "ls180.v:2228.12-2228.40"
+  attribute \src "ls180.v:2273.12-2273.40"
   wire width 4 \builder_csrbank6_cmd_event_r
-  attribute \src "ls180.v:2227.6-2227.35"
+  attribute \src "ls180.v:2272.6-2272.35"
   wire \builder_csrbank6_cmd_event_re
-  attribute \src "ls180.v:2230.12-2230.40"
+  attribute \src "ls180.v:2275.12-2275.40"
   wire width 4 \builder_csrbank6_cmd_event_w
-  attribute \src "ls180.v:2229.6-2229.35"
+  attribute \src "ls180.v:2274.6-2274.35"
   wire \builder_csrbank6_cmd_event_we
-  attribute \src "ls180.v:2224.12-2224.44"
+  attribute \src "ls180.v:2269.12-2269.44"
   wire width 8 \builder_csrbank6_cmd_response0_r
-  attribute \src "ls180.v:2223.6-2223.39"
+  attribute \src "ls180.v:2268.6-2268.39"
   wire \builder_csrbank6_cmd_response0_re
-  attribute \src "ls180.v:2226.12-2226.44"
+  attribute \src "ls180.v:2271.12-2271.44"
   wire width 8 \builder_csrbank6_cmd_response0_w
-  attribute \src "ls180.v:2225.6-2225.39"
+  attribute \src "ls180.v:2270.6-2270.39"
   wire \builder_csrbank6_cmd_response0_we
-  attribute \src "ls180.v:2184.12-2184.45"
+  attribute \src "ls180.v:2229.12-2229.45"
   wire width 8 \builder_csrbank6_cmd_response10_r
-  attribute \src "ls180.v:2183.6-2183.40"
+  attribute \src "ls180.v:2228.6-2228.40"
   wire \builder_csrbank6_cmd_response10_re
-  attribute \src "ls180.v:2186.12-2186.45"
+  attribute \src "ls180.v:2231.12-2231.45"
   wire width 8 \builder_csrbank6_cmd_response10_w
-  attribute \src "ls180.v:2185.6-2185.40"
+  attribute \src "ls180.v:2230.6-2230.40"
   wire \builder_csrbank6_cmd_response10_we
-  attribute \src "ls180.v:2180.12-2180.45"
+  attribute \src "ls180.v:2225.12-2225.45"
   wire width 8 \builder_csrbank6_cmd_response11_r
-  attribute \src "ls180.v:2179.6-2179.40"
+  attribute \src "ls180.v:2224.6-2224.40"
   wire \builder_csrbank6_cmd_response11_re
-  attribute \src "ls180.v:2182.12-2182.45"
+  attribute \src "ls180.v:2227.12-2227.45"
   wire width 8 \builder_csrbank6_cmd_response11_w
-  attribute \src "ls180.v:2181.6-2181.40"
+  attribute \src "ls180.v:2226.6-2226.40"
   wire \builder_csrbank6_cmd_response11_we
-  attribute \src "ls180.v:2176.12-2176.45"
+  attribute \src "ls180.v:2221.12-2221.45"
   wire width 8 \builder_csrbank6_cmd_response12_r
-  attribute \src "ls180.v:2175.6-2175.40"
+  attribute \src "ls180.v:2220.6-2220.40"
   wire \builder_csrbank6_cmd_response12_re
-  attribute \src "ls180.v:2178.12-2178.45"
+  attribute \src "ls180.v:2223.12-2223.45"
   wire width 8 \builder_csrbank6_cmd_response12_w
-  attribute \src "ls180.v:2177.6-2177.40"
+  attribute \src "ls180.v:2222.6-2222.40"
   wire \builder_csrbank6_cmd_response12_we
-  attribute \src "ls180.v:2172.12-2172.45"
+  attribute \src "ls180.v:2217.12-2217.45"
   wire width 8 \builder_csrbank6_cmd_response13_r
-  attribute \src "ls180.v:2171.6-2171.40"
+  attribute \src "ls180.v:2216.6-2216.40"
   wire \builder_csrbank6_cmd_response13_re
-  attribute \src "ls180.v:2174.12-2174.45"
+  attribute \src "ls180.v:2219.12-2219.45"
   wire width 8 \builder_csrbank6_cmd_response13_w
-  attribute \src "ls180.v:2173.6-2173.40"
+  attribute \src "ls180.v:2218.6-2218.40"
   wire \builder_csrbank6_cmd_response13_we
-  attribute \src "ls180.v:2168.12-2168.45"
+  attribute \src "ls180.v:2213.12-2213.45"
   wire width 8 \builder_csrbank6_cmd_response14_r
-  attribute \src "ls180.v:2167.6-2167.40"
+  attribute \src "ls180.v:2212.6-2212.40"
   wire \builder_csrbank6_cmd_response14_re
-  attribute \src "ls180.v:2170.12-2170.45"
+  attribute \src "ls180.v:2215.12-2215.45"
   wire width 8 \builder_csrbank6_cmd_response14_w
-  attribute \src "ls180.v:2169.6-2169.40"
+  attribute \src "ls180.v:2214.6-2214.40"
   wire \builder_csrbank6_cmd_response14_we
-  attribute \src "ls180.v:2164.12-2164.45"
+  attribute \src "ls180.v:2209.12-2209.45"
   wire width 8 \builder_csrbank6_cmd_response15_r
-  attribute \src "ls180.v:2163.6-2163.40"
+  attribute \src "ls180.v:2208.6-2208.40"
   wire \builder_csrbank6_cmd_response15_re
-  attribute \src "ls180.v:2166.12-2166.45"
+  attribute \src "ls180.v:2211.12-2211.45"
   wire width 8 \builder_csrbank6_cmd_response15_w
-  attribute \src "ls180.v:2165.6-2165.40"
+  attribute \src "ls180.v:2210.6-2210.40"
   wire \builder_csrbank6_cmd_response15_we
-  attribute \src "ls180.v:2220.12-2220.44"
+  attribute \src "ls180.v:2265.12-2265.44"
   wire width 8 \builder_csrbank6_cmd_response1_r
-  attribute \src "ls180.v:2219.6-2219.39"
+  attribute \src "ls180.v:2264.6-2264.39"
   wire \builder_csrbank6_cmd_response1_re
-  attribute \src "ls180.v:2222.12-2222.44"
+  attribute \src "ls180.v:2267.12-2267.44"
   wire width 8 \builder_csrbank6_cmd_response1_w
-  attribute \src "ls180.v:2221.6-2221.39"
+  attribute \src "ls180.v:2266.6-2266.39"
   wire \builder_csrbank6_cmd_response1_we
-  attribute \src "ls180.v:2216.12-2216.44"
+  attribute \src "ls180.v:2261.12-2261.44"
   wire width 8 \builder_csrbank6_cmd_response2_r
-  attribute \src "ls180.v:2215.6-2215.39"
+  attribute \src "ls180.v:2260.6-2260.39"
   wire \builder_csrbank6_cmd_response2_re
-  attribute \src "ls180.v:2218.12-2218.44"
+  attribute \src "ls180.v:2263.12-2263.44"
   wire width 8 \builder_csrbank6_cmd_response2_w
-  attribute \src "ls180.v:2217.6-2217.39"
+  attribute \src "ls180.v:2262.6-2262.39"
   wire \builder_csrbank6_cmd_response2_we
-  attribute \src "ls180.v:2212.12-2212.44"
+  attribute \src "ls180.v:2257.12-2257.44"
   wire width 8 \builder_csrbank6_cmd_response3_r
-  attribute \src "ls180.v:2211.6-2211.39"
+  attribute \src "ls180.v:2256.6-2256.39"
   wire \builder_csrbank6_cmd_response3_re
-  attribute \src "ls180.v:2214.12-2214.44"
+  attribute \src "ls180.v:2259.12-2259.44"
   wire width 8 \builder_csrbank6_cmd_response3_w
-  attribute \src "ls180.v:2213.6-2213.39"
+  attribute \src "ls180.v:2258.6-2258.39"
   wire \builder_csrbank6_cmd_response3_we
-  attribute \src "ls180.v:2208.12-2208.44"
+  attribute \src "ls180.v:2253.12-2253.44"
   wire width 8 \builder_csrbank6_cmd_response4_r
-  attribute \src "ls180.v:2207.6-2207.39"
+  attribute \src "ls180.v:2252.6-2252.39"
   wire \builder_csrbank6_cmd_response4_re
-  attribute \src "ls180.v:2210.12-2210.44"
+  attribute \src "ls180.v:2255.12-2255.44"
   wire width 8 \builder_csrbank6_cmd_response4_w
-  attribute \src "ls180.v:2209.6-2209.39"
+  attribute \src "ls180.v:2254.6-2254.39"
   wire \builder_csrbank6_cmd_response4_we
-  attribute \src "ls180.v:2204.12-2204.44"
+  attribute \src "ls180.v:2249.12-2249.44"
   wire width 8 \builder_csrbank6_cmd_response5_r
-  attribute \src "ls180.v:2203.6-2203.39"
+  attribute \src "ls180.v:2248.6-2248.39"
   wire \builder_csrbank6_cmd_response5_re
-  attribute \src "ls180.v:2206.12-2206.44"
+  attribute \src "ls180.v:2251.12-2251.44"
   wire width 8 \builder_csrbank6_cmd_response5_w
-  attribute \src "ls180.v:2205.6-2205.39"
+  attribute \src "ls180.v:2250.6-2250.39"
   wire \builder_csrbank6_cmd_response5_we
-  attribute \src "ls180.v:2200.12-2200.44"
+  attribute \src "ls180.v:2245.12-2245.44"
   wire width 8 \builder_csrbank6_cmd_response6_r
-  attribute \src "ls180.v:2199.6-2199.39"
+  attribute \src "ls180.v:2244.6-2244.39"
   wire \builder_csrbank6_cmd_response6_re
-  attribute \src "ls180.v:2202.12-2202.44"
+  attribute \src "ls180.v:2247.12-2247.44"
   wire width 8 \builder_csrbank6_cmd_response6_w
-  attribute \src "ls180.v:2201.6-2201.39"
+  attribute \src "ls180.v:2246.6-2246.39"
   wire \builder_csrbank6_cmd_response6_we
-  attribute \src "ls180.v:2196.12-2196.44"
+  attribute \src "ls180.v:2241.12-2241.44"
   wire width 8 \builder_csrbank6_cmd_response7_r
-  attribute \src "ls180.v:2195.6-2195.39"
+  attribute \src "ls180.v:2240.6-2240.39"
   wire \builder_csrbank6_cmd_response7_re
-  attribute \src "ls180.v:2198.12-2198.44"
+  attribute \src "ls180.v:2243.12-2243.44"
   wire width 8 \builder_csrbank6_cmd_response7_w
-  attribute \src "ls180.v:2197.6-2197.39"
+  attribute \src "ls180.v:2242.6-2242.39"
   wire \builder_csrbank6_cmd_response7_we
-  attribute \src "ls180.v:2192.12-2192.44"
+  attribute \src "ls180.v:2237.12-2237.44"
   wire width 8 \builder_csrbank6_cmd_response8_r
-  attribute \src "ls180.v:2191.6-2191.39"
+  attribute \src "ls180.v:2236.6-2236.39"
   wire \builder_csrbank6_cmd_response8_re
-  attribute \src "ls180.v:2194.12-2194.44"
+  attribute \src "ls180.v:2239.12-2239.44"
   wire width 8 \builder_csrbank6_cmd_response8_w
-  attribute \src "ls180.v:2193.6-2193.39"
+  attribute \src "ls180.v:2238.6-2238.39"
   wire \builder_csrbank6_cmd_response8_we
-  attribute \src "ls180.v:2188.12-2188.44"
+  attribute \src "ls180.v:2233.12-2233.44"
   wire width 8 \builder_csrbank6_cmd_response9_r
-  attribute \src "ls180.v:2187.6-2187.39"
+  attribute \src "ls180.v:2232.6-2232.39"
   wire \builder_csrbank6_cmd_response9_re
-  attribute \src "ls180.v:2190.12-2190.44"
+  attribute \src "ls180.v:2235.12-2235.44"
   wire width 8 \builder_csrbank6_cmd_response9_w
-  attribute \src "ls180.v:2189.6-2189.39"
+  attribute \src "ls180.v:2234.6-2234.39"
   wire \builder_csrbank6_cmd_response9_we
-  attribute \src "ls180.v:2232.12-2232.41"
+  attribute \src "ls180.v:2277.12-2277.41"
   wire width 4 \builder_csrbank6_data_event_r
-  attribute \src "ls180.v:2231.6-2231.36"
+  attribute \src "ls180.v:2276.6-2276.36"
   wire \builder_csrbank6_data_event_re
-  attribute \src "ls180.v:2234.12-2234.41"
+  attribute \src "ls180.v:2279.12-2279.41"
   wire width 4 \builder_csrbank6_data_event_w
-  attribute \src "ls180.v:2233.6-2233.36"
+  attribute \src "ls180.v:2278.6-2278.36"
   wire \builder_csrbank6_data_event_we
-  attribute \src "ls180.v:2259.6-2259.26"
+  attribute \src "ls180.v:2304.6-2304.26"
   wire \builder_csrbank6_sel
-  attribute \src "ls180.v:2293.12-2293.40"
+  attribute \src "ls180.v:2338.12-2338.40"
   wire width 8 \builder_csrbank7_dma_base0_r
-  attribute \src "ls180.v:2292.6-2292.35"
+  attribute \src "ls180.v:2337.6-2337.35"
   wire \builder_csrbank7_dma_base0_re
-  attribute \src "ls180.v:2295.12-2295.40"
+  attribute \src "ls180.v:2340.12-2340.40"
   wire width 8 \builder_csrbank7_dma_base0_w
-  attribute \src "ls180.v:2294.6-2294.35"
+  attribute \src "ls180.v:2339.6-2339.35"
   wire \builder_csrbank7_dma_base0_we
-  attribute \src "ls180.v:2289.12-2289.40"
+  attribute \src "ls180.v:2334.12-2334.40"
   wire width 8 \builder_csrbank7_dma_base1_r
-  attribute \src "ls180.v:2288.6-2288.35"
+  attribute \src "ls180.v:2333.6-2333.35"
   wire \builder_csrbank7_dma_base1_re
-  attribute \src "ls180.v:2291.12-2291.40"
+  attribute \src "ls180.v:2336.12-2336.40"
   wire width 8 \builder_csrbank7_dma_base1_w
-  attribute \src "ls180.v:2290.6-2290.35"
+  attribute \src "ls180.v:2335.6-2335.35"
   wire \builder_csrbank7_dma_base1_we
-  attribute \src "ls180.v:2285.12-2285.40"
+  attribute \src "ls180.v:2330.12-2330.40"
   wire width 8 \builder_csrbank7_dma_base2_r
-  attribute \src "ls180.v:2284.6-2284.35"
+  attribute \src "ls180.v:2329.6-2329.35"
   wire \builder_csrbank7_dma_base2_re
-  attribute \src "ls180.v:2287.12-2287.40"
+  attribute \src "ls180.v:2332.12-2332.40"
   wire width 8 \builder_csrbank7_dma_base2_w
-  attribute \src "ls180.v:2286.6-2286.35"
+  attribute \src "ls180.v:2331.6-2331.35"
   wire \builder_csrbank7_dma_base2_we
-  attribute \src "ls180.v:2281.12-2281.40"
+  attribute \src "ls180.v:2326.12-2326.40"
   wire width 8 \builder_csrbank7_dma_base3_r
-  attribute \src "ls180.v:2280.6-2280.35"
+  attribute \src "ls180.v:2325.6-2325.35"
   wire \builder_csrbank7_dma_base3_re
-  attribute \src "ls180.v:2283.12-2283.40"
+  attribute \src "ls180.v:2328.12-2328.40"
   wire width 8 \builder_csrbank7_dma_base3_w
-  attribute \src "ls180.v:2282.6-2282.35"
+  attribute \src "ls180.v:2327.6-2327.35"
   wire \builder_csrbank7_dma_base3_we
-  attribute \src "ls180.v:2277.12-2277.40"
+  attribute \src "ls180.v:2322.12-2322.40"
   wire width 8 \builder_csrbank7_dma_base4_r
-  attribute \src "ls180.v:2276.6-2276.35"
+  attribute \src "ls180.v:2321.6-2321.35"
   wire \builder_csrbank7_dma_base4_re
-  attribute \src "ls180.v:2279.12-2279.40"
+  attribute \src "ls180.v:2324.12-2324.40"
   wire width 8 \builder_csrbank7_dma_base4_w
-  attribute \src "ls180.v:2278.6-2278.35"
+  attribute \src "ls180.v:2323.6-2323.35"
   wire \builder_csrbank7_dma_base4_we
-  attribute \src "ls180.v:2273.12-2273.40"
+  attribute \src "ls180.v:2318.12-2318.40"
   wire width 8 \builder_csrbank7_dma_base5_r
-  attribute \src "ls180.v:2272.6-2272.35"
+  attribute \src "ls180.v:2317.6-2317.35"
   wire \builder_csrbank7_dma_base5_re
-  attribute \src "ls180.v:2275.12-2275.40"
+  attribute \src "ls180.v:2320.12-2320.40"
   wire width 8 \builder_csrbank7_dma_base5_w
-  attribute \src "ls180.v:2274.6-2274.35"
+  attribute \src "ls180.v:2319.6-2319.35"
   wire \builder_csrbank7_dma_base5_we
-  attribute \src "ls180.v:2269.12-2269.40"
+  attribute \src "ls180.v:2314.12-2314.40"
   wire width 8 \builder_csrbank7_dma_base6_r
-  attribute \src "ls180.v:2268.6-2268.35"
+  attribute \src "ls180.v:2313.6-2313.35"
   wire \builder_csrbank7_dma_base6_re
-  attribute \src "ls180.v:2271.12-2271.40"
+  attribute \src "ls180.v:2316.12-2316.40"
   wire width 8 \builder_csrbank7_dma_base6_w
-  attribute \src "ls180.v:2270.6-2270.35"
+  attribute \src "ls180.v:2315.6-2315.35"
   wire \builder_csrbank7_dma_base6_we
-  attribute \src "ls180.v:2265.12-2265.40"
+  attribute \src "ls180.v:2310.12-2310.40"
   wire width 8 \builder_csrbank7_dma_base7_r
-  attribute \src "ls180.v:2264.6-2264.35"
+  attribute \src "ls180.v:2309.6-2309.35"
   wire \builder_csrbank7_dma_base7_re
-  attribute \src "ls180.v:2267.12-2267.40"
+  attribute \src "ls180.v:2312.12-2312.40"
   wire width 8 \builder_csrbank7_dma_base7_w
-  attribute \src "ls180.v:2266.6-2266.35"
+  attribute \src "ls180.v:2311.6-2311.35"
   wire \builder_csrbank7_dma_base7_we
-  attribute \src "ls180.v:2317.6-2317.33"
+  attribute \src "ls180.v:2362.6-2362.33"
   wire \builder_csrbank7_dma_done_r
-  attribute \src "ls180.v:2316.6-2316.34"
+  attribute \src "ls180.v:2361.6-2361.34"
   wire \builder_csrbank7_dma_done_re
-  attribute \src "ls180.v:2319.6-2319.33"
+  attribute \src "ls180.v:2364.6-2364.33"
   wire \builder_csrbank7_dma_done_w
-  attribute \src "ls180.v:2318.6-2318.34"
+  attribute \src "ls180.v:2363.6-2363.34"
   wire \builder_csrbank7_dma_done_we
-  attribute \src "ls180.v:2313.6-2313.36"
+  attribute \src "ls180.v:2358.6-2358.36"
   wire \builder_csrbank7_dma_enable0_r
-  attribute \src "ls180.v:2312.6-2312.37"
+  attribute \src "ls180.v:2357.6-2357.37"
   wire \builder_csrbank7_dma_enable0_re
-  attribute \src "ls180.v:2315.6-2315.36"
+  attribute \src "ls180.v:2360.6-2360.36"
   wire \builder_csrbank7_dma_enable0_w
-  attribute \src "ls180.v:2314.6-2314.37"
+  attribute \src "ls180.v:2359.6-2359.37"
   wire \builder_csrbank7_dma_enable0_we
-  attribute \src "ls180.v:2309.12-2309.42"
+  attribute \src "ls180.v:2354.12-2354.42"
   wire width 8 \builder_csrbank7_dma_length0_r
-  attribute \src "ls180.v:2308.6-2308.37"
+  attribute \src "ls180.v:2353.6-2353.37"
   wire \builder_csrbank7_dma_length0_re
-  attribute \src "ls180.v:2311.12-2311.42"
+  attribute \src "ls180.v:2356.12-2356.42"
   wire width 8 \builder_csrbank7_dma_length0_w
-  attribute \src "ls180.v:2310.6-2310.37"
+  attribute \src "ls180.v:2355.6-2355.37"
   wire \builder_csrbank7_dma_length0_we
-  attribute \src "ls180.v:2305.12-2305.42"
+  attribute \src "ls180.v:2350.12-2350.42"
   wire width 8 \builder_csrbank7_dma_length1_r
-  attribute \src "ls180.v:2304.6-2304.37"
+  attribute \src "ls180.v:2349.6-2349.37"
   wire \builder_csrbank7_dma_length1_re
-  attribute \src "ls180.v:2307.12-2307.42"
+  attribute \src "ls180.v:2352.12-2352.42"
   wire width 8 \builder_csrbank7_dma_length1_w
-  attribute \src "ls180.v:2306.6-2306.37"
+  attribute \src "ls180.v:2351.6-2351.37"
   wire \builder_csrbank7_dma_length1_we
-  attribute \src "ls180.v:2301.12-2301.42"
+  attribute \src "ls180.v:2346.12-2346.42"
   wire width 8 \builder_csrbank7_dma_length2_r
-  attribute \src "ls180.v:2300.6-2300.37"
+  attribute \src "ls180.v:2345.6-2345.37"
   wire \builder_csrbank7_dma_length2_re
-  attribute \src "ls180.v:2303.12-2303.42"
+  attribute \src "ls180.v:2348.12-2348.42"
   wire width 8 \builder_csrbank7_dma_length2_w
-  attribute \src "ls180.v:2302.6-2302.37"
+  attribute \src "ls180.v:2347.6-2347.37"
   wire \builder_csrbank7_dma_length2_we
-  attribute \src "ls180.v:2297.12-2297.42"
+  attribute \src "ls180.v:2342.12-2342.42"
   wire width 8 \builder_csrbank7_dma_length3_r
-  attribute \src "ls180.v:2296.6-2296.37"
+  attribute \src "ls180.v:2341.6-2341.37"
   wire \builder_csrbank7_dma_length3_re
-  attribute \src "ls180.v:2299.12-2299.42"
+  attribute \src "ls180.v:2344.12-2344.42"
   wire width 8 \builder_csrbank7_dma_length3_w
-  attribute \src "ls180.v:2298.6-2298.37"
+  attribute \src "ls180.v:2343.6-2343.37"
   wire \builder_csrbank7_dma_length3_we
-  attribute \src "ls180.v:2321.6-2321.34"
+  attribute \src "ls180.v:2366.6-2366.34"
   wire \builder_csrbank7_dma_loop0_r
-  attribute \src "ls180.v:2320.6-2320.35"
+  attribute \src "ls180.v:2365.6-2365.35"
   wire \builder_csrbank7_dma_loop0_re
-  attribute \src "ls180.v:2323.6-2323.34"
+  attribute \src "ls180.v:2368.6-2368.34"
   wire \builder_csrbank7_dma_loop0_w
-  attribute \src "ls180.v:2322.6-2322.35"
+  attribute \src "ls180.v:2367.6-2367.35"
   wire \builder_csrbank7_dma_loop0_we
-  attribute \src "ls180.v:2337.12-2337.42"
+  attribute \src "ls180.v:2382.12-2382.42"
   wire width 8 \builder_csrbank7_dma_offset0_r
-  attribute \src "ls180.v:2336.6-2336.37"
+  attribute \src "ls180.v:2381.6-2381.37"
   wire \builder_csrbank7_dma_offset0_re
-  attribute \src "ls180.v:2339.12-2339.42"
+  attribute \src "ls180.v:2384.12-2384.42"
   wire width 8 \builder_csrbank7_dma_offset0_w
-  attribute \src "ls180.v:2338.6-2338.37"
+  attribute \src "ls180.v:2383.6-2383.37"
   wire \builder_csrbank7_dma_offset0_we
-  attribute \src "ls180.v:2333.12-2333.42"
+  attribute \src "ls180.v:2378.12-2378.42"
   wire width 8 \builder_csrbank7_dma_offset1_r
-  attribute \src "ls180.v:2332.6-2332.37"
+  attribute \src "ls180.v:2377.6-2377.37"
   wire \builder_csrbank7_dma_offset1_re
-  attribute \src "ls180.v:2335.12-2335.42"
+  attribute \src "ls180.v:2380.12-2380.42"
   wire width 8 \builder_csrbank7_dma_offset1_w
-  attribute \src "ls180.v:2334.6-2334.37"
+  attribute \src "ls180.v:2379.6-2379.37"
   wire \builder_csrbank7_dma_offset1_we
-  attribute \src "ls180.v:2329.12-2329.42"
+  attribute \src "ls180.v:2374.12-2374.42"
   wire width 8 \builder_csrbank7_dma_offset2_r
-  attribute \src "ls180.v:2328.6-2328.37"
+  attribute \src "ls180.v:2373.6-2373.37"
   wire \builder_csrbank7_dma_offset2_re
-  attribute \src "ls180.v:2331.12-2331.42"
+  attribute \src "ls180.v:2376.12-2376.42"
   wire width 8 \builder_csrbank7_dma_offset2_w
-  attribute \src "ls180.v:2330.6-2330.37"
+  attribute \src "ls180.v:2375.6-2375.37"
   wire \builder_csrbank7_dma_offset2_we
-  attribute \src "ls180.v:2325.12-2325.42"
+  attribute \src "ls180.v:2370.12-2370.42"
   wire width 8 \builder_csrbank7_dma_offset3_r
-  attribute \src "ls180.v:2324.6-2324.37"
+  attribute \src "ls180.v:2369.6-2369.37"
   wire \builder_csrbank7_dma_offset3_re
-  attribute \src "ls180.v:2327.12-2327.42"
+  attribute \src "ls180.v:2372.12-2372.42"
   wire width 8 \builder_csrbank7_dma_offset3_w
-  attribute \src "ls180.v:2326.6-2326.37"
+  attribute \src "ls180.v:2371.6-2371.37"
   wire \builder_csrbank7_dma_offset3_we
-  attribute \src "ls180.v:2340.6-2340.26"
+  attribute \src "ls180.v:2385.6-2385.26"
   wire \builder_csrbank7_sel
-  attribute \src "ls180.v:2346.6-2346.36"
+  attribute \src "ls180.v:2391.6-2391.36"
   wire \builder_csrbank8_card_detect_r
-  attribute \src "ls180.v:2345.6-2345.37"
+  attribute \src "ls180.v:2390.6-2390.37"
   wire \builder_csrbank8_card_detect_re
-  attribute \src "ls180.v:2348.6-2348.36"
+  attribute \src "ls180.v:2393.6-2393.36"
   wire \builder_csrbank8_card_detect_w
-  attribute \src "ls180.v:2347.6-2347.37"
+  attribute \src "ls180.v:2392.6-2392.37"
   wire \builder_csrbank8_card_detect_we
-  attribute \src "ls180.v:2354.12-2354.47"
+  attribute \src "ls180.v:2399.12-2399.47"
   wire width 8 \builder_csrbank8_clocker_divider0_r
-  attribute \src "ls180.v:2353.6-2353.42"
+  attribute \src "ls180.v:2398.6-2398.42"
   wire \builder_csrbank8_clocker_divider0_re
-  attribute \src "ls180.v:2356.12-2356.47"
+  attribute \src "ls180.v:2401.12-2401.47"
   wire width 8 \builder_csrbank8_clocker_divider0_w
-  attribute \src "ls180.v:2355.6-2355.42"
+  attribute \src "ls180.v:2400.6-2400.42"
   wire \builder_csrbank8_clocker_divider0_we
-  attribute \src "ls180.v:2350.6-2350.41"
+  attribute \src "ls180.v:2395.6-2395.41"
   wire \builder_csrbank8_clocker_divider1_r
-  attribute \src "ls180.v:2349.6-2349.42"
+  attribute \src "ls180.v:2394.6-2394.42"
   wire \builder_csrbank8_clocker_divider1_re
-  attribute \src "ls180.v:2352.6-2352.41"
+  attribute \src "ls180.v:2397.6-2397.41"
   wire \builder_csrbank8_clocker_divider1_w
-  attribute \src "ls180.v:2351.6-2351.42"
+  attribute \src "ls180.v:2396.6-2396.42"
   wire \builder_csrbank8_clocker_divider1_we
-  attribute \src "ls180.v:2357.6-2357.26"
+  attribute \src "ls180.v:2402.6-2402.26"
   wire \builder_csrbank8_sel
-  attribute \src "ls180.v:2363.12-2363.44"
+  attribute \src "ls180.v:2408.12-2408.44"
   wire width 4 \builder_csrbank9_dfii_control0_r
-  attribute \src "ls180.v:2362.6-2362.39"
+  attribute \src "ls180.v:2407.6-2407.39"
   wire \builder_csrbank9_dfii_control0_re
-  attribute \src "ls180.v:2365.12-2365.44"
+  attribute \src "ls180.v:2410.12-2410.44"
   wire width 4 \builder_csrbank9_dfii_control0_w
-  attribute \src "ls180.v:2364.6-2364.39"
+  attribute \src "ls180.v:2409.6-2409.39"
   wire \builder_csrbank9_dfii_control0_we
-  attribute \src "ls180.v:2375.12-2375.48"
+  attribute \src "ls180.v:2420.12-2420.48"
   wire width 8 \builder_csrbank9_dfii_pi0_address0_r
-  attribute \src "ls180.v:2374.6-2374.43"
+  attribute \src "ls180.v:2419.6-2419.43"
   wire \builder_csrbank9_dfii_pi0_address0_re
-  attribute \src "ls180.v:2377.12-2377.48"
+  attribute \src "ls180.v:2422.12-2422.48"
   wire width 8 \builder_csrbank9_dfii_pi0_address0_w
-  attribute \src "ls180.v:2376.6-2376.43"
+  attribute \src "ls180.v:2421.6-2421.43"
   wire \builder_csrbank9_dfii_pi0_address0_we
-  attribute \src "ls180.v:2371.12-2371.48"
+  attribute \src "ls180.v:2416.12-2416.48"
   wire width 5 \builder_csrbank9_dfii_pi0_address1_r
-  attribute \src "ls180.v:2370.6-2370.43"
+  attribute \src "ls180.v:2415.6-2415.43"
   wire \builder_csrbank9_dfii_pi0_address1_re
-  attribute \src "ls180.v:2373.12-2373.48"
+  attribute \src "ls180.v:2418.12-2418.48"
   wire width 5 \builder_csrbank9_dfii_pi0_address1_w
-  attribute \src "ls180.v:2372.6-2372.43"
+  attribute \src "ls180.v:2417.6-2417.43"
   wire \builder_csrbank9_dfii_pi0_address1_we
-  attribute \src "ls180.v:2379.12-2379.49"
+  attribute \src "ls180.v:2424.12-2424.49"
   wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r
-  attribute \src "ls180.v:2378.6-2378.44"
+  attribute \src "ls180.v:2423.6-2423.44"
   wire \builder_csrbank9_dfii_pi0_baddress0_re
-  attribute \src "ls180.v:2381.12-2381.49"
+  attribute \src "ls180.v:2426.12-2426.49"
   wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w
-  attribute \src "ls180.v:2380.6-2380.44"
+  attribute \src "ls180.v:2425.6-2425.44"
   wire \builder_csrbank9_dfii_pi0_baddress0_we
-  attribute \src "ls180.v:2367.12-2367.48"
+  attribute \src "ls180.v:2412.12-2412.48"
   wire width 6 \builder_csrbank9_dfii_pi0_command0_r
-  attribute \src "ls180.v:2366.6-2366.43"
+  attribute \src "ls180.v:2411.6-2411.43"
   wire \builder_csrbank9_dfii_pi0_command0_re
-  attribute \src "ls180.v:2369.12-2369.48"
+  attribute \src "ls180.v:2414.12-2414.48"
   wire width 6 \builder_csrbank9_dfii_pi0_command0_w
-  attribute \src "ls180.v:2368.6-2368.43"
+  attribute \src "ls180.v:2413.6-2413.43"
   wire \builder_csrbank9_dfii_pi0_command0_we
-  attribute \src "ls180.v:2395.12-2395.47"
+  attribute \src "ls180.v:2440.12-2440.47"
   wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r
-  attribute \src "ls180.v:2394.6-2394.42"
+  attribute \src "ls180.v:2439.6-2439.42"
   wire \builder_csrbank9_dfii_pi0_rddata0_re
-  attribute \src "ls180.v:2397.12-2397.47"
+  attribute \src "ls180.v:2442.12-2442.47"
   wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w
-  attribute \src "ls180.v:2396.6-2396.42"
+  attribute \src "ls180.v:2441.6-2441.42"
   wire \builder_csrbank9_dfii_pi0_rddata0_we
-  attribute \src "ls180.v:2391.12-2391.47"
+  attribute \src "ls180.v:2436.12-2436.47"
   wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r
-  attribute \src "ls180.v:2390.6-2390.42"
+  attribute \src "ls180.v:2435.6-2435.42"
   wire \builder_csrbank9_dfii_pi0_rddata1_re
-  attribute \src "ls180.v:2393.12-2393.47"
+  attribute \src "ls180.v:2438.12-2438.47"
   wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w
-  attribute \src "ls180.v:2392.6-2392.42"
+  attribute \src "ls180.v:2437.6-2437.42"
   wire \builder_csrbank9_dfii_pi0_rddata1_we
-  attribute \src "ls180.v:2387.12-2387.47"
+  attribute \src "ls180.v:2432.12-2432.47"
   wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r
-  attribute \src "ls180.v:2386.6-2386.42"
+  attribute \src "ls180.v:2431.6-2431.42"
   wire \builder_csrbank9_dfii_pi0_wrdata0_re
-  attribute \src "ls180.v:2389.12-2389.47"
+  attribute \src "ls180.v:2434.12-2434.47"
   wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w
-  attribute \src "ls180.v:2388.6-2388.42"
+  attribute \src "ls180.v:2433.6-2433.42"
   wire \builder_csrbank9_dfii_pi0_wrdata0_we
-  attribute \src "ls180.v:2383.12-2383.47"
+  attribute \src "ls180.v:2428.12-2428.47"
   wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r
-  attribute \src "ls180.v:2382.6-2382.42"
+  attribute \src "ls180.v:2427.6-2427.42"
   wire \builder_csrbank9_dfii_pi0_wrdata1_re
-  attribute \src "ls180.v:2385.12-2385.47"
+  attribute \src "ls180.v:2430.12-2430.47"
   wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w
-  attribute \src "ls180.v:2384.6-2384.42"
+  attribute \src "ls180.v:2429.6-2429.42"
   wire \builder_csrbank9_dfii_pi0_wrdata1_we
-  attribute \src "ls180.v:2398.6-2398.26"
+  attribute \src "ls180.v:2443.6-2443.26"
   wire \builder_csrbank9_sel
-  attribute \src "ls180.v:1895.6-1895.18"
+  attribute \src "ls180.v:1940.6-1940.18"
   wire \builder_done
-  attribute \src "ls180.v:1893.5-1893.18"
+  attribute \src "ls180.v:1938.5-1938.18"
   wire \builder_error
-  attribute \src "ls180.v:1890.11-1890.24"
+  attribute \src "ls180.v:1935.11-1935.24"
   wire width 3 \builder_grant
-  attribute \src "ls180.v:1897.13-1897.44"
+  attribute \src "ls180.v:1942.13-1942.44"
   wire width 14 \builder_interface0_bank_bus_adr
-  attribute \src "ls180.v:1900.11-1900.44"
+  attribute \src "ls180.v:1945.11-1945.44"
   wire width 8 \builder_interface0_bank_bus_dat_r
-  attribute \src "ls180.v:1899.12-1899.45"
+  attribute \src "ls180.v:1944.12-1944.45"
   wire width 8 \builder_interface0_bank_bus_dat_w
-  attribute \src "ls180.v:1898.6-1898.36"
+  attribute \src "ls180.v:1943.6-1943.36"
   wire \builder_interface0_bank_bus_we
-  attribute \src "ls180.v:2399.13-2399.45"
+  attribute \src "ls180.v:2444.13-2444.45"
   wire width 14 \builder_interface10_bank_bus_adr
-  attribute \src "ls180.v:2402.11-2402.45"
+  attribute \src "ls180.v:2447.11-2447.45"
   wire width 8 \builder_interface10_bank_bus_dat_r
-  attribute \src "ls180.v:2401.12-2401.46"
+  attribute \src "ls180.v:2446.12-2446.46"
   wire width 8 \builder_interface10_bank_bus_dat_w
-  attribute \src "ls180.v:2400.6-2400.37"
+  attribute \src "ls180.v:2445.6-2445.37"
   wire \builder_interface10_bank_bus_we
-  attribute \src "ls180.v:2432.13-2432.45"
+  attribute \src "ls180.v:2477.13-2477.45"
   wire width 14 \builder_interface11_bank_bus_adr
-  attribute \src "ls180.v:2435.11-2435.45"
+  attribute \src "ls180.v:2480.11-2480.45"
   wire width 8 \builder_interface11_bank_bus_dat_r
-  attribute \src "ls180.v:2434.12-2434.46"
+  attribute \src "ls180.v:2479.12-2479.46"
   wire width 8 \builder_interface11_bank_bus_dat_w
-  attribute \src "ls180.v:2433.6-2433.37"
+  attribute \src "ls180.v:2478.6-2478.37"
   wire \builder_interface11_bank_bus_we
-  attribute \src "ls180.v:2473.13-2473.45"
+  attribute \src "ls180.v:2518.13-2518.45"
   wire width 14 \builder_interface12_bank_bus_adr
-  attribute \src "ls180.v:2476.11-2476.45"
+  attribute \src "ls180.v:2521.11-2521.45"
   wire width 8 \builder_interface12_bank_bus_dat_r
-  attribute \src "ls180.v:2475.12-2475.46"
+  attribute \src "ls180.v:2520.12-2520.46"
   wire width 8 \builder_interface12_bank_bus_dat_w
-  attribute \src "ls180.v:2474.6-2474.37"
+  attribute \src "ls180.v:2519.6-2519.37"
   wire \builder_interface12_bank_bus_we
-  attribute \src "ls180.v:2538.13-2538.45"
+  attribute \src "ls180.v:2583.13-2583.45"
   wire width 14 \builder_interface13_bank_bus_adr
-  attribute \src "ls180.v:2541.11-2541.45"
+  attribute \src "ls180.v:2586.11-2586.45"
   wire width 8 \builder_interface13_bank_bus_dat_r
-  attribute \src "ls180.v:2540.12-2540.46"
+  attribute \src "ls180.v:2585.12-2585.46"
   wire width 8 \builder_interface13_bank_bus_dat_w
-  attribute \src "ls180.v:2539.6-2539.37"
+  attribute \src "ls180.v:2584.6-2584.37"
   wire \builder_interface13_bank_bus_we
-  attribute \src "ls180.v:2563.13-2563.45"
+  attribute \src "ls180.v:2608.13-2608.45"
   wire width 14 \builder_interface14_bank_bus_adr
-  attribute \src "ls180.v:2566.11-2566.45"
+  attribute \src "ls180.v:2611.11-2611.45"
   wire width 8 \builder_interface14_bank_bus_dat_r
-  attribute \src "ls180.v:2565.12-2565.46"
+  attribute \src "ls180.v:2610.12-2610.46"
   wire width 8 \builder_interface14_bank_bus_dat_w
-  attribute \src "ls180.v:2564.6-2564.37"
+  attribute \src "ls180.v:2609.6-2609.37"
   wire \builder_interface14_bank_bus_we
-  attribute \src "ls180.v:1938.13-1938.44"
+  attribute \src "ls180.v:1983.13-1983.44"
   wire width 14 \builder_interface1_bank_bus_adr
-  attribute \src "ls180.v:1941.11-1941.44"
+  attribute \src "ls180.v:1986.11-1986.44"
   wire width 8 \builder_interface1_bank_bus_dat_r
-  attribute \src "ls180.v:1940.12-1940.45"
+  attribute \src "ls180.v:1985.12-1985.45"
   wire width 8 \builder_interface1_bank_bus_dat_w
-  attribute \src "ls180.v:1939.6-1939.36"
+  attribute \src "ls180.v:1984.6-1984.36"
   wire \builder_interface1_bank_bus_we
-  attribute \src "ls180.v:1967.13-1967.44"
+  attribute \src "ls180.v:2012.13-2012.44"
   wire width 14 \builder_interface2_bank_bus_adr
-  attribute \src "ls180.v:1970.11-1970.44"
+  attribute \src "ls180.v:2015.11-2015.44"
   wire width 8 \builder_interface2_bank_bus_dat_r
-  attribute \src "ls180.v:1969.12-1969.45"
+  attribute \src "ls180.v:2014.12-2014.45"
   wire width 8 \builder_interface2_bank_bus_dat_w
-  attribute \src "ls180.v:1968.6-1968.36"
+  attribute \src "ls180.v:2013.6-2013.36"
   wire \builder_interface2_bank_bus_we
-  attribute \src "ls180.v:1980.13-1980.44"
+  attribute \src "ls180.v:2025.13-2025.44"
   wire width 14 \builder_interface3_bank_bus_adr
-  attribute \src "ls180.v:1983.11-1983.44"
+  attribute \src "ls180.v:2028.11-2028.44"
   wire width 8 \builder_interface3_bank_bus_dat_r
-  attribute \src "ls180.v:1982.12-1982.45"
+  attribute \src "ls180.v:2027.12-2027.45"
   wire width 8 \builder_interface3_bank_bus_dat_w
-  attribute \src "ls180.v:1981.6-1981.36"
+  attribute \src "ls180.v:2026.6-2026.36"
   wire \builder_interface3_bank_bus_we
-  attribute \src "ls180.v:2021.13-2021.44"
+  attribute \src "ls180.v:2066.13-2066.44"
   wire width 14 \builder_interface4_bank_bus_adr
-  attribute \src "ls180.v:2024.11-2024.44"
+  attribute \src "ls180.v:2069.11-2069.44"
   wire width 8 \builder_interface4_bank_bus_dat_r
-  attribute \src "ls180.v:2023.12-2023.45"
+  attribute \src "ls180.v:2068.12-2068.45"
   wire width 8 \builder_interface4_bank_bus_dat_w
-  attribute \src "ls180.v:2022.6-2022.36"
+  attribute \src "ls180.v:2067.6-2067.36"
   wire \builder_interface4_bank_bus_we
-  attribute \src "ls180.v:2062.13-2062.44"
+  attribute \src "ls180.v:2107.13-2107.44"
   wire width 14 \builder_interface5_bank_bus_adr
-  attribute \src "ls180.v:2065.11-2065.44"
+  attribute \src "ls180.v:2110.11-2110.44"
   wire width 8 \builder_interface5_bank_bus_dat_r
-  attribute \src "ls180.v:2064.12-2064.45"
+  attribute \src "ls180.v:2109.12-2109.45"
   wire width 8 \builder_interface5_bank_bus_dat_w
-  attribute \src "ls180.v:2063.6-2063.36"
+  attribute \src "ls180.v:2108.6-2108.36"
   wire \builder_interface5_bank_bus_we
-  attribute \src "ls180.v:2127.13-2127.44"
+  attribute \src "ls180.v:2172.13-2172.44"
   wire width 14 \builder_interface6_bank_bus_adr
-  attribute \src "ls180.v:2130.11-2130.44"
+  attribute \src "ls180.v:2175.11-2175.44"
   wire width 8 \builder_interface6_bank_bus_dat_r
-  attribute \src "ls180.v:2129.12-2129.45"
+  attribute \src "ls180.v:2174.12-2174.45"
   wire width 8 \builder_interface6_bank_bus_dat_w
-  attribute \src "ls180.v:2128.6-2128.36"
+  attribute \src "ls180.v:2173.6-2173.36"
   wire \builder_interface6_bank_bus_we
-  attribute \src "ls180.v:2260.13-2260.44"
+  attribute \src "ls180.v:2305.13-2305.44"
   wire width 14 \builder_interface7_bank_bus_adr
-  attribute \src "ls180.v:2263.11-2263.44"
+  attribute \src "ls180.v:2308.11-2308.44"
   wire width 8 \builder_interface7_bank_bus_dat_r
-  attribute \src "ls180.v:2262.12-2262.45"
+  attribute \src "ls180.v:2307.12-2307.45"
   wire width 8 \builder_interface7_bank_bus_dat_w
-  attribute \src "ls180.v:2261.6-2261.36"
+  attribute \src "ls180.v:2306.6-2306.36"
   wire \builder_interface7_bank_bus_we
-  attribute \src "ls180.v:2341.13-2341.44"
+  attribute \src "ls180.v:2386.13-2386.44"
   wire width 14 \builder_interface8_bank_bus_adr
-  attribute \src "ls180.v:2344.11-2344.44"
+  attribute \src "ls180.v:2389.11-2389.44"
   wire width 8 \builder_interface8_bank_bus_dat_r
-  attribute \src "ls180.v:2343.12-2343.45"
+  attribute \src "ls180.v:2388.12-2388.45"
   wire width 8 \builder_interface8_bank_bus_dat_w
-  attribute \src "ls180.v:2342.6-2342.36"
+  attribute \src "ls180.v:2387.6-2387.36"
   wire \builder_interface8_bank_bus_we
-  attribute \src "ls180.v:2358.13-2358.44"
+  attribute \src "ls180.v:2403.13-2403.44"
   wire width 14 \builder_interface9_bank_bus_adr
-  attribute \src "ls180.v:2361.11-2361.44"
+  attribute \src "ls180.v:2406.11-2406.44"
   wire width 8 \builder_interface9_bank_bus_dat_r
-  attribute \src "ls180.v:2360.12-2360.45"
+  attribute \src "ls180.v:2405.12-2405.45"
   wire width 8 \builder_interface9_bank_bus_dat_w
-  attribute \src "ls180.v:2359.6-2359.36"
+  attribute \src "ls180.v:2404.6-2404.36"
   wire \builder_interface9_bank_bus_we
-  attribute \src "ls180.v:1863.12-1863.35"
+  attribute \src "ls180.v:1908.12-1908.35"
   wire width 14 \builder_libresocsim_adr
-  attribute \src "ls180.v:2592.12-2592.47"
+  attribute \src "ls180.v:2637.12-2637.47"
   wire width 14 \builder_libresocsim_adr_next_value1
-  attribute \src "ls180.v:2593.5-2593.43"
+  attribute \src "ls180.v:2638.5-2638.43"
   wire \builder_libresocsim_adr_next_value_ce1
-  attribute \src "ls180.v:1866.12-1866.37"
+  attribute \src "ls180.v:1911.12-1911.37"
   wire width 8 \builder_libresocsim_dat_r
-  attribute \src "ls180.v:1865.11-1865.36"
+  attribute \src "ls180.v:1910.11-1910.36"
   wire width 8 \builder_libresocsim_dat_w
-  attribute \src "ls180.v:2590.11-2590.48"
+  attribute \src "ls180.v:2635.11-2635.48"
   wire width 8 \builder_libresocsim_dat_w_next_value0
-  attribute \src "ls180.v:2591.5-2591.45"
+  attribute \src "ls180.v:2636.5-2636.45"
   wire \builder_libresocsim_dat_w_next_value_ce0
-  attribute \src "ls180.v:1864.5-1864.27"
+  attribute \src "ls180.v:1909.5-1909.27"
   wire \builder_libresocsim_we
-  attribute \src "ls180.v:2594.5-2594.39"
+  attribute \src "ls180.v:2639.5-2639.39"
   wire \builder_libresocsim_we_next_value2
-  attribute \src "ls180.v:2595.5-2595.42"
+  attribute \src "ls180.v:2640.5-2640.42"
   wire \builder_libresocsim_we_next_value_ce2
-  attribute \src "ls180.v:1873.5-1873.37"
+  attribute \src "ls180.v:1918.5-1918.37"
   wire \builder_libresocsim_wishbone_ack
-  attribute \src "ls180.v:1867.13-1867.45"
+  attribute \src "ls180.v:1912.13-1912.45"
   wire width 30 \builder_libresocsim_wishbone_adr
-  attribute \src "ls180.v:1876.12-1876.44"
+  attribute \src "ls180.v:1921.12-1921.44"
   wire width 2 \builder_libresocsim_wishbone_bte
-  attribute \src "ls180.v:1875.12-1875.44"
+  attribute \src "ls180.v:1920.12-1920.44"
   wire width 3 \builder_libresocsim_wishbone_cti
-  attribute \src "ls180.v:1871.6-1871.38"
+  attribute \src "ls180.v:1916.6-1916.38"
   wire \builder_libresocsim_wishbone_cyc
-  attribute \src "ls180.v:1869.12-1869.46"
+  attribute \src "ls180.v:1914.12-1914.46"
   wire width 32 \builder_libresocsim_wishbone_dat_r
-  attribute \src "ls180.v:1868.13-1868.47"
+  attribute \src "ls180.v:1913.13-1913.47"
   wire width 32 \builder_libresocsim_wishbone_dat_w
-  attribute \src "ls180.v:1877.5-1877.37"
+  attribute \src "ls180.v:1922.5-1922.37"
   wire \builder_libresocsim_wishbone_err
-  attribute \src "ls180.v:1870.12-1870.44"
+  attribute \src "ls180.v:1915.12-1915.44"
   wire width 4 \builder_libresocsim_wishbone_sel
-  attribute \src "ls180.v:1872.6-1872.38"
+  attribute \src "ls180.v:1917.6-1917.38"
   wire \builder_libresocsim_wishbone_stb
-  attribute \src "ls180.v:1874.6-1874.37"
+  attribute \src "ls180.v:1919.6-1919.37"
   wire \builder_libresocsim_wishbone_we
-  attribute \src "ls180.v:1766.5-1766.20"
+  attribute \src "ls180.v:1811.5-1811.20"
   wire \builder_locked0
-  attribute \src "ls180.v:1767.5-1767.20"
+  attribute \src "ls180.v:1812.5-1812.20"
   wire \builder_locked1
-  attribute \src "ls180.v:1768.5-1768.20"
+  attribute \src "ls180.v:1813.5-1813.20"
   wire \builder_locked2
-  attribute \src "ls180.v:1769.5-1769.20"
+  attribute \src "ls180.v:1814.5-1814.20"
   wire \builder_locked3
-  attribute \src "ls180.v:1753.11-1753.41"
+  attribute \src "ls180.v:1798.11-1798.41"
   wire width 3 \builder_multiplexer_next_state
-  attribute \src "ls180.v:1752.11-1752.36"
+  attribute \src "ls180.v:1797.11-1797.36"
   wire width 3 \builder_multiplexer_state
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2699.32-2699.59"
+  attribute \src "ls180.v:2744.32-2744.59"
   wire \builder_multiregimpl0_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2700.32-2700.59"
+  attribute \src "ls180.v:2745.32-2745.59"
   wire \builder_multiregimpl0_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2719.32-2719.60"
+  attribute \src "ls180.v:2764.32-2764.60"
   wire \builder_multiregimpl10_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2720.32-2720.60"
+  attribute \src "ls180.v:2765.32-2765.60"
   wire \builder_multiregimpl10_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2721.32-2721.60"
+  attribute \src "ls180.v:2766.32-2766.60"
   wire \builder_multiregimpl11_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2722.32-2722.60"
+  attribute \src "ls180.v:2767.32-2767.60"
   wire \builder_multiregimpl11_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2723.32-2723.60"
+  attribute \src "ls180.v:2768.32-2768.60"
   wire \builder_multiregimpl12_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2724.32-2724.60"
+  attribute \src "ls180.v:2769.32-2769.60"
   wire \builder_multiregimpl12_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2725.32-2725.60"
+  attribute \src "ls180.v:2770.32-2770.60"
   wire \builder_multiregimpl13_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2726.32-2726.60"
+  attribute \src "ls180.v:2771.32-2771.60"
   wire \builder_multiregimpl13_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2727.32-2727.60"
+  attribute \src "ls180.v:2772.32-2772.60"
   wire \builder_multiregimpl14_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2728.32-2728.60"
+  attribute \src "ls180.v:2773.32-2773.60"
   wire \builder_multiregimpl14_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2729.32-2729.60"
+  attribute \src "ls180.v:2774.32-2774.60"
   wire \builder_multiregimpl15_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2730.32-2730.60"
+  attribute \src "ls180.v:2775.32-2775.60"
   wire \builder_multiregimpl15_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2731.32-2731.60"
+  attribute \src "ls180.v:2776.32-2776.60"
   wire \builder_multiregimpl16_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2732.32-2732.60"
+  attribute \src "ls180.v:2777.32-2777.60"
   wire \builder_multiregimpl16_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2701.32-2701.59"
+  attribute \src "ls180.v:2746.32-2746.59"
   wire \builder_multiregimpl1_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2702.32-2702.59"
+  attribute \src "ls180.v:2747.32-2747.59"
   wire \builder_multiregimpl1_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2703.32-2703.59"
+  attribute \src "ls180.v:2748.32-2748.59"
   wire \builder_multiregimpl2_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2704.32-2704.59"
+  attribute \src "ls180.v:2749.32-2749.59"
   wire \builder_multiregimpl2_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2705.32-2705.59"
+  attribute \src "ls180.v:2750.32-2750.59"
   wire \builder_multiregimpl3_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2706.32-2706.59"
+  attribute \src "ls180.v:2751.32-2751.59"
   wire \builder_multiregimpl3_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2707.32-2707.59"
+  attribute \src "ls180.v:2752.32-2752.59"
   wire \builder_multiregimpl4_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2708.32-2708.59"
+  attribute \src "ls180.v:2753.32-2753.59"
   wire \builder_multiregimpl4_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2709.32-2709.59"
+  attribute \src "ls180.v:2754.32-2754.59"
   wire \builder_multiregimpl5_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2710.32-2710.59"
+  attribute \src "ls180.v:2755.32-2755.59"
   wire \builder_multiregimpl5_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2711.32-2711.59"
+  attribute \src "ls180.v:2756.32-2756.59"
   wire \builder_multiregimpl6_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2712.32-2712.59"
+  attribute \src "ls180.v:2757.32-2757.59"
   wire \builder_multiregimpl6_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2713.32-2713.59"
+  attribute \src "ls180.v:2758.32-2758.59"
   wire \builder_multiregimpl7_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2714.32-2714.59"
+  attribute \src "ls180.v:2759.32-2759.59"
   wire \builder_multiregimpl7_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2715.32-2715.59"
+  attribute \src "ls180.v:2760.32-2760.59"
   wire \builder_multiregimpl8_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2716.32-2716.59"
+  attribute \src "ls180.v:2761.32-2761.59"
   wire \builder_multiregimpl8_regs1
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2717.32-2717.59"
+  attribute \src "ls180.v:2762.32-2762.59"
   wire \builder_multiregimpl9_regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:2718.32-2718.59"
+  attribute \src "ls180.v:2763.32-2763.59"
   wire \builder_multiregimpl9_regs1
-  attribute \src "ls180.v:1771.5-1771.36"
+  attribute \src "ls180.v:1816.5-1816.36"
   wire \builder_new_master_rdata_valid0
-  attribute \src "ls180.v:1772.5-1772.36"
+  attribute \src "ls180.v:1817.5-1817.36"
   wire \builder_new_master_rdata_valid1
-  attribute \src "ls180.v:1773.5-1773.36"
+  attribute \src "ls180.v:1818.5-1818.36"
   wire \builder_new_master_rdata_valid2
-  attribute \src "ls180.v:1774.5-1774.36"
+  attribute \src "ls180.v:1819.5-1819.36"
   wire \builder_new_master_rdata_valid3
-  attribute \src "ls180.v:1770.5-1770.35"
+  attribute \src "ls180.v:1815.5-1815.35"
   wire \builder_new_master_wdata_ready
-  attribute \src "ls180.v:2589.11-2589.29"
+  attribute \src "ls180.v:2634.11-2634.29"
   wire width 2 \builder_next_state
-  attribute \src "ls180.v:1743.11-1743.39"
+  attribute \src "ls180.v:1788.11-1788.39"
   wire width 2 \builder_refresher_next_state
-  attribute \src "ls180.v:1742.11-1742.34"
+  attribute \src "ls180.v:1787.11-1787.34"
   wire width 2 \builder_refresher_state
-  attribute \src "ls180.v:1889.12-1889.27"
+  attribute \src "ls180.v:1934.12-1934.27"
   wire width 5 \builder_request
-  attribute \src "ls180.v:1756.6-1756.28"
+  attribute \src "ls180.v:1801.6-1801.28"
   wire \builder_roundrobin0_ce
-  attribute \src "ls180.v:1755.6-1755.31"
+  attribute \src "ls180.v:1800.6-1800.31"
   wire \builder_roundrobin0_grant
-  attribute \src "ls180.v:1754.6-1754.33"
+  attribute \src "ls180.v:1799.6-1799.33"
   wire \builder_roundrobin0_request
-  attribute \src "ls180.v:1759.6-1759.28"
+  attribute \src "ls180.v:1804.6-1804.28"
   wire \builder_roundrobin1_ce
-  attribute \src "ls180.v:1758.6-1758.31"
+  attribute \src "ls180.v:1803.6-1803.31"
   wire \builder_roundrobin1_grant
-  attribute \src "ls180.v:1757.6-1757.33"
+  attribute \src "ls180.v:1802.6-1802.33"
   wire \builder_roundrobin1_request
-  attribute \src "ls180.v:1762.6-1762.28"
+  attribute \src "ls180.v:1807.6-1807.28"
   wire \builder_roundrobin2_ce
-  attribute \src "ls180.v:1761.6-1761.31"
+  attribute \src "ls180.v:1806.6-1806.31"
   wire \builder_roundrobin2_grant
-  attribute \src "ls180.v:1760.6-1760.33"
+  attribute \src "ls180.v:1805.6-1805.33"
   wire \builder_roundrobin2_request
-  attribute \src "ls180.v:1765.6-1765.28"
+  attribute \src "ls180.v:1810.6-1810.28"
   wire \builder_roundrobin3_ce
-  attribute \src "ls180.v:1764.6-1764.31"
+  attribute \src "ls180.v:1809.6-1809.31"
   wire \builder_roundrobin3_grant
-  attribute \src "ls180.v:1763.6-1763.33"
+  attribute \src "ls180.v:1808.6-1808.33"
   wire \builder_roundrobin3_request
-  attribute \src "ls180.v:1852.11-1852.44"
+  attribute \src "ls180.v:1897.11-1897.44"
   wire width 2 \builder_sdblock2memdma_next_state
-  attribute \src "ls180.v:1851.11-1851.39"
+  attribute \src "ls180.v:1896.11-1896.39"
   wire width 2 \builder_sdblock2memdma_state
-  attribute \src "ls180.v:1820.5-1820.50"
+  attribute \src "ls180.v:1865.5-1865.50"
   wire \builder_sdcore_crcupstreaminserter_next_state
-  attribute \src "ls180.v:1819.5-1819.45"
+  attribute \src "ls180.v:1864.5-1864.45"
   wire \builder_sdcore_crcupstreaminserter_state
-  attribute \src "ls180.v:1832.11-1832.40"
+  attribute \src "ls180.v:1877.11-1877.40"
   wire width 3 \builder_sdcore_fsm_next_state
-  attribute \src "ls180.v:1831.11-1831.35"
+  attribute \src "ls180.v:1876.11-1876.35"
   wire width 3 \builder_sdcore_fsm_state
-  attribute \src "ls180.v:1856.5-1856.42"
+  attribute \src "ls180.v:1901.5-1901.42"
   wire \builder_sdmem2blockdma_fsm_next_state
-  attribute \src "ls180.v:1855.5-1855.37"
+  attribute \src "ls180.v:1900.5-1900.37"
   wire \builder_sdmem2blockdma_fsm_state
-  attribute \src "ls180.v:1860.11-1860.58"
+  attribute \src "ls180.v:1905.11-1905.58"
   wire width 2 \builder_sdmem2blockdma_resetinserter_next_state
-  attribute \src "ls180.v:1859.11-1859.53"
+  attribute \src "ls180.v:1904.11-1904.53"
   wire width 2 \builder_sdmem2blockdma_resetinserter_state
-  attribute \src "ls180.v:1808.11-1808.39"
+  attribute \src "ls180.v:1853.11-1853.39"
   wire width 3 \builder_sdphy_fsm_next_state
-  attribute \src "ls180.v:1807.11-1807.34"
+  attribute \src "ls180.v:1852.11-1852.34"
   wire width 3 \builder_sdphy_fsm_state
-  attribute \src "ls180.v:1796.11-1796.45"
+  attribute \src "ls180.v:1841.11-1841.45"
   wire width 3 \builder_sdphy_sdphycmdr_next_state
-  attribute \src "ls180.v:1795.11-1795.40"
+  attribute \src "ls180.v:1840.11-1840.40"
   wire width 3 \builder_sdphy_sdphycmdr_state
-  attribute \src "ls180.v:1792.11-1792.45"
+  attribute \src "ls180.v:1837.11-1837.45"
   wire width 2 \builder_sdphy_sdphycmdw_next_state
-  attribute \src "ls180.v:1791.11-1791.40"
+  attribute \src "ls180.v:1836.11-1836.40"
   wire width 2 \builder_sdphy_sdphycmdw_state
-  attribute \src "ls180.v:1804.5-1804.39"
+  attribute \src "ls180.v:1849.5-1849.39"
   wire \builder_sdphy_sdphycrcr_next_state
-  attribute \src "ls180.v:1803.5-1803.34"
+  attribute \src "ls180.v:1848.5-1848.34"
   wire \builder_sdphy_sdphycrcr_state
-  attribute \src "ls180.v:1812.11-1812.46"
+  attribute \src "ls180.v:1857.11-1857.46"
   wire width 3 \builder_sdphy_sdphydatar_next_state
-  attribute \src "ls180.v:1811.11-1811.41"
+  attribute \src "ls180.v:1856.11-1856.41"
   wire width 3 \builder_sdphy_sdphydatar_state
-  attribute \src "ls180.v:1788.5-1788.39"
+  attribute \src "ls180.v:1833.5-1833.39"
   wire \builder_sdphy_sdphyinit_next_state
-  attribute \src "ls180.v:1787.5-1787.34"
+  attribute \src "ls180.v:1832.5-1832.34"
   wire \builder_sdphy_sdphyinit_state
-  attribute \src "ls180.v:1884.5-1884.23"
+  attribute \src "ls180.v:1929.5-1929.23"
   wire \builder_shared_ack
-  attribute \src "ls180.v:1878.13-1878.31"
+  attribute \src "ls180.v:1923.13-1923.31"
   wire width 30 \builder_shared_adr
-  attribute \src "ls180.v:1887.12-1887.30"
+  attribute \src "ls180.v:1932.12-1932.30"
   wire width 2 \builder_shared_bte
-  attribute \src "ls180.v:1886.12-1886.30"
+  attribute \src "ls180.v:1931.12-1931.30"
   wire width 3 \builder_shared_cti
-  attribute \src "ls180.v:1882.6-1882.24"
+  attribute \src "ls180.v:1927.6-1927.24"
   wire \builder_shared_cyc
-  attribute \src "ls180.v:1880.12-1880.32"
+  attribute \src "ls180.v:1925.12-1925.32"
   wire width 32 \builder_shared_dat_r
-  attribute \src "ls180.v:1879.13-1879.33"
+  attribute \src "ls180.v:1924.13-1924.33"
   wire width 32 \builder_shared_dat_w
-  attribute \src "ls180.v:1888.6-1888.24"
+  attribute \src "ls180.v:1933.6-1933.24"
   wire \builder_shared_err
-  attribute \src "ls180.v:1881.12-1881.30"
+  attribute \src "ls180.v:1926.12-1926.30"
   wire width 4 \builder_shared_sel
-  attribute \src "ls180.v:1883.6-1883.24"
+  attribute \src "ls180.v:1928.6-1928.24"
   wire \builder_shared_stb
-  attribute \src "ls180.v:1885.6-1885.23"
+  attribute \src "ls180.v:1930.6-1930.23"
   wire \builder_shared_we
-  attribute \src "ls180.v:1891.11-1891.28"
-  wire width 5 \builder_slave_sel
-  attribute \src "ls180.v:1892.11-1892.30"
-  wire width 5 \builder_slave_sel_r
-  attribute \src "ls180.v:1780.11-1780.40"
+  attribute \src "ls180.v:1936.11-1936.28"
+  wire width 8 \builder_slave_sel
+  attribute \src "ls180.v:1937.11-1937.30"
+  wire width 8 \builder_slave_sel_r
+  attribute \src "ls180.v:1825.11-1825.40"
   wire width 2 \builder_spimaster0_next_state
-  attribute \src "ls180.v:1779.11-1779.35"
+  attribute \src "ls180.v:1824.11-1824.35"
   wire width 2 \builder_spimaster0_state
-  attribute \src "ls180.v:1784.11-1784.40"
+  attribute \src "ls180.v:1829.11-1829.40"
   wire width 2 \builder_spimaster1_next_state
-  attribute \src "ls180.v:1783.11-1783.35"
+  attribute \src "ls180.v:1828.11-1828.35"
   wire width 2 \builder_spimaster1_state
-  attribute \src "ls180.v:2588.11-2588.24"
+  attribute \src "ls180.v:2633.11-2633.24"
   wire width 2 \builder_state
-  attribute \src "ls180.v:2641.5-2641.32"
+  attribute \src "ls180.v:2686.5-2686.32"
   wire \builder_sync_f_array_muxed0
-  attribute \src "ls180.v:2642.5-2642.32"
+  attribute \src "ls180.v:2687.5-2687.32"
   wire \builder_sync_f_array_muxed1
-  attribute \src "ls180.v:2634.11-2634.40"
+  attribute \src "ls180.v:2679.11-2679.40"
   wire width 2 \builder_sync_rhs_array_muxed0
-  attribute \src "ls180.v:2635.12-2635.41"
+  attribute \src "ls180.v:2680.12-2680.41"
   wire width 13 \builder_sync_rhs_array_muxed1
-  attribute \src "ls180.v:2636.5-2636.34"
+  attribute \src "ls180.v:2681.5-2681.34"
   wire \builder_sync_rhs_array_muxed2
-  attribute \src "ls180.v:2637.5-2637.34"
+  attribute \src "ls180.v:2682.5-2682.34"
   wire \builder_sync_rhs_array_muxed3
-  attribute \src "ls180.v:2638.5-2638.34"
+  attribute \src "ls180.v:2683.5-2683.34"
   wire \builder_sync_rhs_array_muxed4
-  attribute \src "ls180.v:2639.5-2639.34"
+  attribute \src "ls180.v:2684.5-2684.34"
   wire \builder_sync_rhs_array_muxed5
-  attribute \src "ls180.v:2640.5-2640.34"
+  attribute \src "ls180.v:2685.5-2685.34"
   wire \builder_sync_rhs_array_muxed6
-  attribute \src "ls180.v:1894.6-1894.18"
+  attribute \src "ls180.v:1939.6-1939.18"
   wire \builder_wait
-  attribute \src "ls180.v:22.19-22.23"
-  wire width 3 input 18 \eint
-  attribute \src "ls180.v:142.12-142.18"
+  attribute \src "ls180.v:19.19-19.23"
+  wire width 3 input 15 \eint
+  attribute \src "ls180.v:137.12-137.18"
   wire width 3 \eint_1
-  attribute \src "ls180.v:32.20-32.26"
-  wire width 16 input 28 \gpio_i
-  attribute \src "ls180.v:33.21-33.27"
-  wire width 16 output 29 \gpio_o
-  attribute \src "ls180.v:34.21-34.28"
-  wire width 16 output 30 \gpio_oe
-  attribute \src "ls180.v:35.14-35.21"
-  wire output 31 \i2c_scl
-  attribute \src "ls180.v:36.13-36.22"
-  wire input 32 \i2c_sda_i
-  attribute \src "ls180.v:37.14-37.23"
-  wire output 33 \i2c_sda_o
-  attribute \src "ls180.v:38.14-38.24"
-  wire output 34 \i2c_sda_oe
+  attribute \src "ls180.v:28.20-28.26"
+  wire width 16 input 24 \gpio_i
+  attribute \src "ls180.v:29.21-29.27"
+  wire width 16 output 25 \gpio_o
+  attribute \src "ls180.v:30.21-30.28"
+  wire width 16 output 26 \gpio_oe
+  attribute \src "ls180.v:31.14-31.21"
+  wire output 27 \i2c_scl
+  attribute \src "ls180.v:32.13-32.22"
+  wire input 28 \i2c_sda_i
+  attribute \src "ls180.v:33.14-33.23"
+  wire output 29 \i2c_sda_o
+  attribute \src "ls180.v:34.14-34.24"
+  wire output 30 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -231361,140 +231673,206 @@ module \ls180
   wire output 47 \jtag_tdo
   attribute \src "ls180.v:48.13-48.21"
   wire input 44 \jtag_tms
-  attribute \src "ls180.v:834.6-834.18"
+  attribute \src "ls180.v:879.6-879.18"
   wire \main_ack_cmd
-  attribute \src "ls180.v:836.6-836.20"
+  attribute \src "ls180.v:881.6-881.20"
   wire \main_ack_rdata
-  attribute \src "ls180.v:835.6-835.20"
+  attribute \src "ls180.v:880.6-880.20"
   wire \main_ack_wdata
-  attribute \src "ls180.v:832.5-832.22"
+  attribute \src "ls180.v:877.5-877.22"
   wire \main_cmd_consumed
-  attribute \src "ls180.v:829.5-829.27"
+  attribute \src "ls180.v:874.5-874.27"
   wire \main_converter_counter
-  attribute \src "ls180.v:1777.5-1777.48"
+  attribute \src "ls180.v:1822.5-1822.48"
   wire \main_converter_counter_converter_next_value
-  attribute \src "ls180.v:1778.5-1778.51"
+  attribute \src "ls180.v:1823.5-1823.51"
   wire \main_converter_counter_converter_next_value_ce
-  attribute \src "ls180.v:831.12-831.32"
+  attribute \src "ls180.v:876.12-876.32"
   wire width 32 \main_converter_dat_r
-  attribute \src "ls180.v:830.6-830.26"
+  attribute \src "ls180.v:875.6-875.26"
   wire \main_converter_reset
-  attribute \src "ls180.v:828.5-828.24"
+  attribute \src "ls180.v:873.5-873.24"
   wire \main_converter_skip
-  attribute \src "ls180.v:258.6-258.23"
+  attribute \src "ls180.v:303.6-303.23"
   wire \main_dfi_p0_act_n
-  attribute \src "ls180.v:249.13-249.32"
+  attribute \src "ls180.v:294.13-294.32"
   wire width 13 \main_dfi_p0_address
-  attribute \src "ls180.v:250.12-250.28"
+  attribute \src "ls180.v:295.12-295.28"
   wire width 2 \main_dfi_p0_bank
-  attribute \src "ls180.v:251.6-251.23"
+  attribute \src "ls180.v:296.6-296.23"
   wire \main_dfi_p0_cas_n
-  attribute \src "ls180.v:255.6-255.21"
+  attribute \src "ls180.v:300.6-300.21"
   wire \main_dfi_p0_cke
-  attribute \src "ls180.v:252.6-252.22"
+  attribute \src "ls180.v:297.6-297.22"
   wire \main_dfi_p0_cs_n
-  attribute \src "ls180.v:256.6-256.21"
+  attribute \src "ls180.v:301.6-301.21"
   wire \main_dfi_p0_odt
-  attribute \src "ls180.v:253.6-253.23"
+  attribute \src "ls180.v:298.6-298.23"
   wire \main_dfi_p0_ras_n
-  attribute \src "ls180.v:263.12-263.30"
+  attribute \src "ls180.v:308.12-308.30"
   wire width 16 \main_dfi_p0_rddata
-  attribute \src "ls180.v:262.6-262.27"
+  attribute \src "ls180.v:307.6-307.27"
   wire \main_dfi_p0_rddata_en
-  attribute \src "ls180.v:264.5-264.29"
+  attribute \src "ls180.v:309.5-309.29"
   wire \main_dfi_p0_rddata_valid
-  attribute \src "ls180.v:257.6-257.25"
+  attribute \src "ls180.v:302.6-302.25"
   wire \main_dfi_p0_reset_n
-  attribute \src "ls180.v:254.6-254.22"
+  attribute \src "ls180.v:299.6-299.22"
   wire \main_dfi_p0_we_n
-  attribute \src "ls180.v:259.13-259.31"
+  attribute \src "ls180.v:304.13-304.31"
   wire width 16 \main_dfi_p0_wrdata
-  attribute \src "ls180.v:260.6-260.27"
+  attribute \src "ls180.v:305.6-305.27"
   wire \main_dfi_p0_wrdata_en
-  attribute \src "ls180.v:261.12-261.35"
+  attribute \src "ls180.v:306.12-306.35"
   wire width 2 \main_dfi_p0_wrdata_mask
-  attribute \src "ls180.v:1063.12-1063.22"
+  attribute \src "ls180.v:1108.12-1108.22"
   wire width 24 \main_dummy
-  attribute \src "ls180.v:980.5-980.20"
+  attribute \src "ls180.v:1025.5-1025.20"
   wire \main_gpio_oe_re
-  attribute \src "ls180.v:979.12-979.32"
+  attribute \src "ls180.v:1024.12-1024.32"
   wire width 16 \main_gpio_oe_storage
-  attribute \src "ls180.v:984.5-984.21"
+  attribute \src "ls180.v:1029.5-1029.21"
   wire \main_gpio_out_re
-  attribute \src "ls180.v:983.12-983.33"
+  attribute \src "ls180.v:1028.12-1028.33"
   wire width 16 \main_gpio_out_storage
-  attribute \src "ls180.v:985.13-985.29"
+  attribute \src "ls180.v:1030.13-1030.29"
   wire width 16 \main_gpio_pads_i
-  attribute \src "ls180.v:986.13-986.29"
+  attribute \src "ls180.v:1031.13-1031.29"
   wire width 16 \main_gpio_pads_o
-  attribute \src "ls180.v:987.13-987.30"
+  attribute \src "ls180.v:1032.13-1032.30"
   wire width 16 \main_gpio_pads_oe
-  attribute \src "ls180.v:981.12-981.28"
+  attribute \src "ls180.v:1026.12-1026.28"
   wire width 16 \main_gpio_status
-  attribute \src "ls180.v:982.6-982.18"
+  attribute \src "ls180.v:1027.6-1027.18"
   wire \main_gpio_we
-  attribute \src "ls180.v:1085.6-1085.17"
+  attribute \src "ls180.v:1130.6-1130.17"
   wire \main_i2c_oe
-  attribute \src "ls180.v:1088.5-1088.16"
+  attribute \src "ls180.v:1133.5-1133.16"
   wire \main_i2c_re
-  attribute \src "ls180.v:1084.6-1084.18"
+  attribute \src "ls180.v:1129.6-1129.18"
   wire \main_i2c_scl
-  attribute \src "ls180.v:1086.6-1086.19"
+  attribute \src "ls180.v:1131.6-1131.19"
   wire \main_i2c_sda0
-  attribute \src "ls180.v:1089.6-1089.19"
+  attribute \src "ls180.v:1134.6-1134.19"
   wire \main_i2c_sda1
-  attribute \src "ls180.v:1090.6-1090.21"
+  attribute \src "ls180.v:1135.6-1135.21"
   wire \main_i2c_status
-  attribute \src "ls180.v:1087.11-1087.27"
+  attribute \src "ls180.v:1132.11-1132.27"
   wire width 3 \main_i2c_storage
-  attribute \src "ls180.v:1091.6-1091.17"
+  attribute \src "ls180.v:1136.6-1136.17"
   wire \main_i2c_we
-  attribute \src "ls180.v:248.5-248.17"
+  attribute \src "ls180.v:293.5-293.17"
   wire \main_int_rst
-  attribute \src "ls180.v:1551.6-1551.29"
+  attribute \src "ls180.v:1596.6-1596.29"
   wire \main_interface0_bus_ack
-  attribute \src "ls180.v:1545.13-1545.36"
+  attribute \src "ls180.v:1590.13-1590.36"
   wire width 32 \main_interface0_bus_adr
-  attribute \src "ls180.v:1554.11-1554.34"
+  attribute \src "ls180.v:1599.11-1599.34"
   wire width 2 \main_interface0_bus_bte
-  attribute \src "ls180.v:1553.11-1553.34"
+  attribute \src "ls180.v:1598.11-1598.34"
   wire width 3 \main_interface0_bus_cti
-  attribute \src "ls180.v:1549.6-1549.29"
+  attribute \src "ls180.v:1594.6-1594.29"
   wire \main_interface0_bus_cyc
-  attribute \src "ls180.v:1547.13-1547.38"
+  attribute \src "ls180.v:1592.13-1592.38"
   wire width 32 \main_interface0_bus_dat_r
-  attribute \src "ls180.v:1546.13-1546.38"
+  attribute \src "ls180.v:1591.13-1591.38"
   wire width 32 \main_interface0_bus_dat_w
-  attribute \src "ls180.v:1555.6-1555.29"
+  attribute \src "ls180.v:1600.6-1600.29"
   wire \main_interface0_bus_err
-  attribute \src "ls180.v:1548.12-1548.35"
+  attribute \src "ls180.v:1593.12-1593.35"
   wire width 4 \main_interface0_bus_sel
-  attribute \src "ls180.v:1550.6-1550.29"
+  attribute \src "ls180.v:1595.6-1595.29"
   wire \main_interface0_bus_stb
-  attribute \src "ls180.v:1552.6-1552.28"
+  attribute \src "ls180.v:1597.6-1597.28"
   wire \main_interface0_bus_we
-  attribute \src "ls180.v:1642.6-1642.29"
+  attribute \src "ls180.v:251.5-251.32"
+  wire \main_interface0_ram_bus_ack
+  attribute \src "ls180.v:245.13-245.40"
+  wire width 30 \main_interface0_ram_bus_adr
+  attribute \src "ls180.v:254.12-254.39"
+  wire width 2 \main_interface0_ram_bus_bte
+  attribute \src "ls180.v:253.12-253.39"
+  wire width 3 \main_interface0_ram_bus_cti
+  attribute \src "ls180.v:249.6-249.33"
+  wire \main_interface0_ram_bus_cyc
+  attribute \src "ls180.v:247.13-247.42"
+  wire width 32 \main_interface0_ram_bus_dat_r
+  attribute \src "ls180.v:246.13-246.42"
+  wire width 32 \main_interface0_ram_bus_dat_w
+  attribute \src "ls180.v:255.5-255.32"
+  wire \main_interface0_ram_bus_err
+  attribute \src "ls180.v:248.12-248.39"
+  wire width 4 \main_interface0_ram_bus_sel
+  attribute \src "ls180.v:250.6-250.33"
+  wire \main_interface0_ram_bus_stb
+  attribute \src "ls180.v:252.6-252.32"
+  wire \main_interface0_ram_bus_we
+  attribute \src "ls180.v:1687.6-1687.29"
   wire \main_interface1_bus_ack
-  attribute \src "ls180.v:1636.12-1636.35"
+  attribute \src "ls180.v:1681.12-1681.35"
   wire width 32 \main_interface1_bus_adr
-  attribute \src "ls180.v:1645.11-1645.34"
+  attribute \src "ls180.v:1690.11-1690.34"
   wire width 2 \main_interface1_bus_bte
-  attribute \src "ls180.v:1644.11-1644.34"
+  attribute \src "ls180.v:1689.11-1689.34"
   wire width 3 \main_interface1_bus_cti
-  attribute \src "ls180.v:1640.5-1640.28"
+  attribute \src "ls180.v:1685.5-1685.28"
   wire \main_interface1_bus_cyc
-  attribute \src "ls180.v:1638.13-1638.38"
+  attribute \src "ls180.v:1683.13-1683.38"
   wire width 32 \main_interface1_bus_dat_r
-  attribute \src "ls180.v:1637.12-1637.37"
+  attribute \src "ls180.v:1682.12-1682.37"
   wire width 32 \main_interface1_bus_dat_w
-  attribute \src "ls180.v:1646.6-1646.29"
+  attribute \src "ls180.v:1691.6-1691.29"
   wire \main_interface1_bus_err
-  attribute \src "ls180.v:1639.11-1639.34"
+  attribute \src "ls180.v:1684.11-1684.34"
   wire width 4 \main_interface1_bus_sel
-  attribute \src "ls180.v:1641.5-1641.28"
+  attribute \src "ls180.v:1686.5-1686.28"
   wire \main_interface1_bus_stb
-  attribute \src "ls180.v:1643.5-1643.27"
+  attribute \src "ls180.v:1688.5-1688.27"
   wire \main_interface1_bus_we
+  attribute \src "ls180.v:266.5-266.32"
+  wire \main_interface1_ram_bus_ack
+  attribute \src "ls180.v:260.13-260.40"
+  wire width 30 \main_interface1_ram_bus_adr
+  attribute \src "ls180.v:269.12-269.39"
+  wire width 2 \main_interface1_ram_bus_bte
+  attribute \src "ls180.v:268.12-268.39"
+  wire width 3 \main_interface1_ram_bus_cti
+  attribute \src "ls180.v:264.6-264.33"
+  wire \main_interface1_ram_bus_cyc
+  attribute \src "ls180.v:262.13-262.42"
+  wire width 32 \main_interface1_ram_bus_dat_r
+  attribute \src "ls180.v:261.13-261.42"
+  wire width 32 \main_interface1_ram_bus_dat_w
+  attribute \src "ls180.v:270.5-270.32"
+  wire \main_interface1_ram_bus_err
+  attribute \src "ls180.v:263.12-263.39"
+  wire width 4 \main_interface1_ram_bus_sel
+  attribute \src "ls180.v:265.6-265.33"
+  wire \main_interface1_ram_bus_stb
+  attribute \src "ls180.v:267.6-267.32"
+  wire \main_interface1_ram_bus_we
+  attribute \src "ls180.v:281.5-281.32"
+  wire \main_interface2_ram_bus_ack
+  attribute \src "ls180.v:275.13-275.40"
+  wire width 30 \main_interface2_ram_bus_adr
+  attribute \src "ls180.v:284.12-284.39"
+  wire width 2 \main_interface2_ram_bus_bte
+  attribute \src "ls180.v:283.12-283.39"
+  wire width 3 \main_interface2_ram_bus_cti
+  attribute \src "ls180.v:279.6-279.33"
+  wire \main_interface2_ram_bus_cyc
+  attribute \src "ls180.v:277.13-277.42"
+  wire width 32 \main_interface2_ram_bus_dat_r
+  attribute \src "ls180.v:276.13-276.42"
+  wire width 32 \main_interface2_ram_bus_dat_w
+  attribute \src "ls180.v:285.5-285.32"
+  wire \main_interface2_ram_bus_err
+  attribute \src "ls180.v:278.12-278.39"
+  wire width 4 \main_interface2_ram_bus_sel
+  attribute \src "ls180.v:280.6-280.33"
+  wire \main_interface2_ram_bus_stb
+  attribute \src "ls180.v:282.6-282.32"
+  wire \main_interface2_ram_bus_we
   attribute \src "ls180.v:214.12-214.32"
   wire width 7 \main_libresocsim_adr
   attribute \src "ls180.v:62.6-62.32"
@@ -231507,9 +231885,9 @@ module \ls180
   wire \main_libresocsim_bus_errors_we
   attribute \src "ls180.v:170.5-170.40"
   wire \main_libresocsim_converter0_counter
-  attribute \src "ls180.v:1732.5-1732.62"
+  attribute \src "ls180.v:1777.5-1777.62"
   wire \main_libresocsim_converter0_counter_converter0_next_value
-  attribute \src "ls180.v:1733.5-1733.65"
+  attribute \src "ls180.v:1778.5-1778.65"
   wire \main_libresocsim_converter0_counter_converter0_next_value_ce
   attribute \src "ls180.v:172.12-172.45"
   wire width 64 \main_libresocsim_converter0_dat_r
@@ -231519,9 +231897,9 @@ module \ls180
   wire \main_libresocsim_converter0_skip
   attribute \src "ls180.v:185.5-185.40"
   wire \main_libresocsim_converter1_counter
-  attribute \src "ls180.v:1736.5-1736.62"
+  attribute \src "ls180.v:1781.5-1781.62"
   wire \main_libresocsim_converter1_counter_converter1_next_value
-  attribute \src "ls180.v:1737.5-1737.65"
+  attribute \src "ls180.v:1782.5-1782.65"
   wire \main_libresocsim_converter1_counter_converter1_next_value_ce
   attribute \src "ls180.v:187.12-187.45"
   wire width 64 \main_libresocsim_converter1_dat_r
@@ -231531,9 +231909,9 @@ module \ls180
   wire \main_libresocsim_converter1_skip
   attribute \src "ls180.v:200.5-200.40"
   wire \main_libresocsim_converter2_counter
-  attribute \src "ls180.v:1740.5-1740.62"
+  attribute \src "ls180.v:1785.5-1785.62"
   wire \main_libresocsim_converter2_counter_converter2_next_value
-  attribute \src "ls180.v:1741.5-1741.65"
+  attribute \src "ls180.v:1786.5-1786.65"
   wire \main_libresocsim_converter2_counter_converter2_next_value_ce
   attribute \src "ls180.v:202.12-202.45"
   wire width 64 \main_libresocsim_converter2_dat_r
@@ -231645,65 +232023,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:123.12-123.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:147.13-147.67"
+  attribute \src "ls180.v:146.13-146.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:148.13-148.67"
+  attribute \src "ls180.v:147.13-147.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:149.13-149.68"
+  attribute \src "ls180.v:148.13-148.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:150.6-150.61"
+  attribute \src "ls180.v:149.6-149.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:151.6-151.63"
+  attribute \src "ls180.v:150.6-150.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:152.6-152.63"
+  attribute \src "ls180.v:151.6-151.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:153.6-153.64"
+  attribute \src "ls180.v:152.6-152.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:143.6-143.64"
+  attribute \src "ls180.v:153.6-153.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:144.6-144.66"
+  attribute \src "ls180.v:154.6-154.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:145.6-145.66"
+  attribute \src "ls180.v:155.6-155.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:146.6-146.67"
+  attribute \src "ls180.v:156.6-156.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:129.13-129.68"
+  attribute \src "ls180.v:125.13-125.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:138.12-138.68"
+  attribute \src "ls180.v:134.12-134.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:135.6-135.65"
+  attribute \src "ls180.v:131.6-131.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:137.6-137.63"
+  attribute \src "ls180.v:133.6-133.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:136.6-136.64"
+  attribute \src "ls180.v:132.6-132.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:139.12-139.68"
+  attribute \src "ls180.v:135.12-135.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:130.13-130.71"
+  attribute \src "ls180.v:126.13-126.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:131.13-131.71"
+  attribute \src "ls180.v:127.13-127.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:132.6-132.65"
+  attribute \src "ls180.v:128.6-128.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:134.6-134.65"
+  attribute \src "ls180.v:130.6-130.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:133.6-133.64"
+  attribute \src "ls180.v:129.6-129.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:125.6-125.67"
+  attribute \src "ls180.v:142.6-142.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:127.6-127.68"
+  attribute \src "ls180.v:144.6-144.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:128.6-128.68"
+  attribute \src "ls180.v:145.6-145.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:126.6-126.68"
+  attribute \src "ls180.v:143.6-143.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:154.6-154.67"
+  attribute \src "ls180.v:138.6-138.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:156.6-156.68"
+  attribute \src "ls180.v:140.6-140.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:157.6-157.68"
+  attribute \src "ls180.v:141.6-141.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:155.6-155.68"
+  attribute \src "ls180.v:139.6-139.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.5-72.39"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -231881,3199 +232259,3229 @@ module \ls180
   wire \main_libresocsim_zero_status
   attribute \src "ls180.v:231.6-231.35"
   wire \main_libresocsim_zero_trigger
-  attribute \src "ls180.v:826.6-826.26"
+  attribute \src "ls180.v:871.6-871.26"
   wire \main_litedram_wb_ack
-  attribute \src "ls180.v:820.12-820.32"
+  attribute \src "ls180.v:865.12-865.32"
   wire width 30 \main_litedram_wb_adr
-  attribute \src "ls180.v:824.5-824.25"
+  attribute \src "ls180.v:869.5-869.25"
   wire \main_litedram_wb_cyc
-  attribute \src "ls180.v:822.13-822.35"
+  attribute \src "ls180.v:867.13-867.35"
   wire width 16 \main_litedram_wb_dat_r
-  attribute \src "ls180.v:821.12-821.34"
+  attribute \src "ls180.v:866.12-866.34"
   wire width 16 \main_litedram_wb_dat_w
-  attribute \src "ls180.v:823.11-823.31"
+  attribute \src "ls180.v:868.11-868.31"
   wire width 2 \main_litedram_wb_sel
-  attribute \src "ls180.v:825.5-825.25"
+  attribute \src "ls180.v:870.5-870.25"
   wire \main_litedram_wb_stb
-  attribute \src "ls180.v:827.5-827.24"
+  attribute \src "ls180.v:872.5-872.24"
   wire \main_litedram_wb_we
-  attribute \src "ls180.v:1062.13-1062.20"
+  attribute \src "ls180.v:1107.13-1107.20"
   wire width 24 \main_nc
-  attribute \src "ls180.v:799.6-799.24"
+  attribute \src "ls180.v:844.6-844.24"
   wire \main_port_cmd_last
-  attribute \src "ls180.v:801.13-801.39"
+  attribute \src "ls180.v:846.13-846.39"
   wire width 24 \main_port_cmd_payload_addr
-  attribute \src "ls180.v:800.6-800.30"
+  attribute \src "ls180.v:845.6-845.30"
   wire \main_port_cmd_payload_we
-  attribute \src "ls180.v:798.6-798.25"
+  attribute \src "ls180.v:843.6-843.25"
   wire \main_port_cmd_ready
-  attribute \src "ls180.v:797.6-797.25"
+  attribute \src "ls180.v:842.6-842.25"
   wire \main_port_cmd_valid
-  attribute \src "ls180.v:796.6-796.21"
+  attribute \src "ls180.v:841.6-841.21"
   wire \main_port_flush
-  attribute \src "ls180.v:808.13-808.41"
+  attribute \src "ls180.v:853.13-853.41"
   wire width 16 \main_port_rdata_payload_data
-  attribute \src "ls180.v:807.6-807.27"
+  attribute \src "ls180.v:852.6-852.27"
   wire \main_port_rdata_ready
-  attribute \src "ls180.v:806.6-806.27"
+  attribute \src "ls180.v:851.6-851.27"
   wire \main_port_rdata_valid
-  attribute \src "ls180.v:804.13-804.41"
+  attribute \src "ls180.v:849.13-849.41"
   wire width 16 \main_port_wdata_payload_data
-  attribute \src "ls180.v:805.12-805.38"
+  attribute \src "ls180.v:850.12-850.38"
   wire width 2 \main_port_wdata_payload_we
-  attribute \src "ls180.v:803.6-803.27"
+  attribute \src "ls180.v:848.6-848.27"
   wire \main_port_wdata_ready
-  attribute \src "ls180.v:802.6-802.27"
+  attribute \src "ls180.v:847.6-847.27"
   wire \main_port_wdata_valid
-  attribute \src "ls180.v:1067.12-1067.29"
+  attribute \src "ls180.v:1112.12-1112.29"
   wire width 32 \main_pwm0_counter
-  attribute \src "ls180.v:1064.6-1064.22"
+  attribute \src "ls180.v:1109.6-1109.22"
   wire \main_pwm0_enable
-  attribute \src "ls180.v:1069.5-1069.24"
+  attribute \src "ls180.v:1114.5-1114.24"
   wire \main_pwm0_enable_re
-  attribute \src "ls180.v:1068.5-1068.29"
+  attribute \src "ls180.v:1113.5-1113.29"
   wire \main_pwm0_enable_storage
-  attribute \src "ls180.v:1066.13-1066.29"
+  attribute \src "ls180.v:1111.13-1111.29"
   wire width 32 \main_pwm0_period
-  attribute \src "ls180.v:1073.5-1073.24"
+  attribute \src "ls180.v:1118.5-1118.24"
   wire \main_pwm0_period_re
-  attribute \src "ls180.v:1072.12-1072.36"
+  attribute \src "ls180.v:1117.12-1117.36"
   wire width 32 \main_pwm0_period_storage
-  attribute \src "ls180.v:1065.13-1065.28"
+  attribute \src "ls180.v:1110.13-1110.28"
   wire width 32 \main_pwm0_width
-  attribute \src "ls180.v:1071.5-1071.23"
+  attribute \src "ls180.v:1116.5-1116.23"
   wire \main_pwm0_width_re
-  attribute \src "ls180.v:1070.12-1070.35"
+  attribute \src "ls180.v:1115.12-1115.35"
   wire width 32 \main_pwm0_width_storage
-  attribute \src "ls180.v:1077.12-1077.29"
+  attribute \src "ls180.v:1122.12-1122.29"
   wire width 32 \main_pwm1_counter
-  attribute \src "ls180.v:1074.6-1074.22"
+  attribute \src "ls180.v:1119.6-1119.22"
   wire \main_pwm1_enable
-  attribute \src "ls180.v:1079.5-1079.24"
+  attribute \src "ls180.v:1124.5-1124.24"
   wire \main_pwm1_enable_re
-  attribute \src "ls180.v:1078.5-1078.29"
+  attribute \src "ls180.v:1123.5-1123.29"
   wire \main_pwm1_enable_storage
-  attribute \src "ls180.v:1076.13-1076.29"
+  attribute \src "ls180.v:1121.13-1121.29"
   wire width 32 \main_pwm1_period
-  attribute \src "ls180.v:1083.5-1083.24"
+  attribute \src "ls180.v:1128.5-1128.24"
   wire \main_pwm1_period_re
-  attribute \src "ls180.v:1082.12-1082.36"
+  attribute \src "ls180.v:1127.12-1127.36"
   wire width 32 \main_pwm1_period_storage
-  attribute \src "ls180.v:1075.13-1075.28"
+  attribute \src "ls180.v:1120.13-1120.28"
   wire width 32 \main_pwm1_width
-  attribute \src "ls180.v:1081.5-1081.23"
+  attribute \src "ls180.v:1126.5-1126.23"
   wire \main_pwm1_width_re
-  attribute \src "ls180.v:1080.12-1080.35"
+  attribute \src "ls180.v:1125.12-1125.35"
   wire width 32 \main_pwm1_width_storage
-  attribute \src "ls180.v:265.11-265.25"
+  attribute \src "ls180.v:310.11-310.25"
   wire width 3 \main_rddata_en
-  attribute \src "ls180.v:1605.11-1605.43"
+  attribute \src "ls180.v:1650.11-1650.43"
   wire width 2 \main_sdblock2mem_converter_demux
-  attribute \src "ls180.v:1606.6-1606.42"
+  attribute \src "ls180.v:1651.6-1651.42"
   wire \main_sdblock2mem_converter_load_part
-  attribute \src "ls180.v:1596.6-1596.43"
+  attribute \src "ls180.v:1641.6-1641.43"
   wire \main_sdblock2mem_converter_sink_first
-  attribute \src "ls180.v:1597.6-1597.42"
+  attribute \src "ls180.v:1642.6-1642.42"
   wire \main_sdblock2mem_converter_sink_last
-  attribute \src "ls180.v:1598.12-1598.56"
+  attribute \src "ls180.v:1643.12-1643.56"
   wire width 8 \main_sdblock2mem_converter_sink_payload_data
-  attribute \src "ls180.v:1595.6-1595.43"
+  attribute \src "ls180.v:1640.6-1640.43"
   wire \main_sdblock2mem_converter_sink_ready
-  attribute \src "ls180.v:1594.6-1594.43"
+  attribute \src "ls180.v:1639.6-1639.43"
   wire \main_sdblock2mem_converter_sink_valid
-  attribute \src "ls180.v:1601.5-1601.44"
+  attribute \src "ls180.v:1646.5-1646.44"
   wire \main_sdblock2mem_converter_source_first
-  attribute \src "ls180.v:1602.5-1602.43"
+  attribute \src "ls180.v:1647.5-1647.43"
   wire \main_sdblock2mem_converter_source_last
-  attribute \src "ls180.v:1603.12-1603.58"
+  attribute \src "ls180.v:1648.12-1648.58"
   wire width 32 \main_sdblock2mem_converter_source_payload_data
-  attribute \src "ls180.v:1604.11-1604.70"
+  attribute \src "ls180.v:1649.11-1649.70"
   wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count
-  attribute \src "ls180.v:1600.6-1600.45"
+  attribute \src "ls180.v:1645.6-1645.45"
   wire \main_sdblock2mem_converter_source_ready
-  attribute \src "ls180.v:1599.6-1599.45"
+  attribute \src "ls180.v:1644.6-1644.45"
   wire \main_sdblock2mem_converter_source_valid
-  attribute \src "ls180.v:1607.5-1607.42"
+  attribute \src "ls180.v:1652.5-1652.42"
   wire \main_sdblock2mem_converter_strobe_all
-  attribute \src "ls180.v:1580.11-1580.40"
+  attribute \src "ls180.v:1625.11-1625.40"
   wire width 5 \main_sdblock2mem_fifo_consume
-  attribute \src "ls180.v:1585.6-1585.35"
+  attribute \src "ls180.v:1630.6-1630.35"
   wire \main_sdblock2mem_fifo_do_read
-  attribute \src "ls180.v:1589.6-1589.41"
+  attribute \src "ls180.v:1634.6-1634.41"
   wire \main_sdblock2mem_fifo_fifo_in_first
-  attribute \src "ls180.v:1590.6-1590.40"
+  attribute \src "ls180.v:1635.6-1635.40"
   wire \main_sdblock2mem_fifo_fifo_in_last
-  attribute \src "ls180.v:1588.12-1588.54"
+  attribute \src "ls180.v:1633.12-1633.54"
   wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:1592.6-1592.42"
+  attribute \src "ls180.v:1637.6-1637.42"
   wire \main_sdblock2mem_fifo_fifo_out_first
-  attribute \src "ls180.v:1593.6-1593.41"
+  attribute \src "ls180.v:1638.6-1638.41"
   wire \main_sdblock2mem_fifo_fifo_out_last
-  attribute \src "ls180.v:1591.12-1591.55"
+  attribute \src "ls180.v:1636.12-1636.55"
   wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:1577.11-1577.38"
+  attribute \src "ls180.v:1622.11-1622.38"
   wire width 6 \main_sdblock2mem_fifo_level
-  attribute \src "ls180.v:1579.11-1579.40"
+  attribute \src "ls180.v:1624.11-1624.40"
   wire width 5 \main_sdblock2mem_fifo_produce
-  attribute \src "ls180.v:1586.12-1586.44"
+  attribute \src "ls180.v:1631.12-1631.44"
   wire width 5 \main_sdblock2mem_fifo_rdport_adr
-  attribute \src "ls180.v:1587.12-1587.46"
+  attribute \src "ls180.v:1632.12-1632.46"
   wire width 10 \main_sdblock2mem_fifo_rdport_dat_r
-  attribute \src "ls180.v:1578.5-1578.34"
+  attribute \src "ls180.v:1623.5-1623.34"
   wire \main_sdblock2mem_fifo_replace
-  attribute \src "ls180.v:1563.6-1563.38"
+  attribute \src "ls180.v:1608.6-1608.38"
   wire \main_sdblock2mem_fifo_sink_first
-  attribute \src "ls180.v:1564.6-1564.37"
+  attribute \src "ls180.v:1609.6-1609.37"
   wire \main_sdblock2mem_fifo_sink_last
-  attribute \src "ls180.v:1565.12-1565.51"
+  attribute \src "ls180.v:1610.12-1610.51"
   wire width 8 \main_sdblock2mem_fifo_sink_payload_data
-  attribute \src "ls180.v:1562.6-1562.38"
+  attribute \src "ls180.v:1607.6-1607.38"
   wire \main_sdblock2mem_fifo_sink_ready
-  attribute \src "ls180.v:1561.6-1561.38"
+  attribute \src "ls180.v:1606.6-1606.38"
   wire \main_sdblock2mem_fifo_sink_valid
-  attribute \src "ls180.v:1568.6-1568.40"
+  attribute \src "ls180.v:1613.6-1613.40"
   wire \main_sdblock2mem_fifo_source_first
-  attribute \src "ls180.v:1569.6-1569.39"
+  attribute \src "ls180.v:1614.6-1614.39"
   wire \main_sdblock2mem_fifo_source_last
-  attribute \src "ls180.v:1570.12-1570.53"
+  attribute \src "ls180.v:1615.12-1615.53"
   wire width 8 \main_sdblock2mem_fifo_source_payload_data
-  attribute \src "ls180.v:1567.6-1567.40"
+  attribute \src "ls180.v:1612.6-1612.40"
   wire \main_sdblock2mem_fifo_source_ready
-  attribute \src "ls180.v:1566.6-1566.40"
+  attribute \src "ls180.v:1611.6-1611.40"
   wire \main_sdblock2mem_fifo_source_valid
-  attribute \src "ls180.v:1575.12-1575.46"
+  attribute \src "ls180.v:1620.12-1620.46"
   wire width 10 \main_sdblock2mem_fifo_syncfifo_din
-  attribute \src "ls180.v:1576.12-1576.47"
+  attribute \src "ls180.v:1621.12-1621.47"
   wire width 10 \main_sdblock2mem_fifo_syncfifo_dout
-  attribute \src "ls180.v:1573.6-1573.39"
+  attribute \src "ls180.v:1618.6-1618.39"
   wire \main_sdblock2mem_fifo_syncfifo_re
-  attribute \src "ls180.v:1574.6-1574.45"
+  attribute \src "ls180.v:1619.6-1619.45"
   wire \main_sdblock2mem_fifo_syncfifo_readable
-  attribute \src "ls180.v:1571.6-1571.39"
+  attribute \src "ls180.v:1616.6-1616.39"
   wire \main_sdblock2mem_fifo_syncfifo_we
-  attribute \src "ls180.v:1572.6-1572.45"
+  attribute \src "ls180.v:1617.6-1617.45"
   wire \main_sdblock2mem_fifo_syncfifo_writable
-  attribute \src "ls180.v:1581.11-1581.43"
+  attribute \src "ls180.v:1626.11-1626.43"
   wire width 5 \main_sdblock2mem_fifo_wrport_adr
-  attribute \src "ls180.v:1582.12-1582.46"
+  attribute \src "ls180.v:1627.12-1627.46"
   wire width 10 \main_sdblock2mem_fifo_wrport_dat_r
-  attribute \src "ls180.v:1584.12-1584.46"
+  attribute \src "ls180.v:1629.12-1629.46"
   wire width 10 \main_sdblock2mem_fifo_wrport_dat_w
-  attribute \src "ls180.v:1583.6-1583.37"
+  attribute \src "ls180.v:1628.6-1628.37"
   wire \main_sdblock2mem_fifo_wrport_we
-  attribute \src "ls180.v:1558.6-1558.38"
+  attribute \src "ls180.v:1603.6-1603.38"
   wire \main_sdblock2mem_sink_sink_first
-  attribute \src "ls180.v:1559.6-1559.37"
+  attribute \src "ls180.v:1604.6-1604.37"
   wire \main_sdblock2mem_sink_sink_last
-  attribute \src "ls180.v:1615.12-1615.54"
+  attribute \src "ls180.v:1660.12-1660.54"
   wire width 32 \main_sdblock2mem_sink_sink_payload_address
-  attribute \src "ls180.v:1560.12-1560.52"
+  attribute \src "ls180.v:1605.12-1605.52"
   wire width 8 \main_sdblock2mem_sink_sink_payload_data0
-  attribute \src "ls180.v:1616.12-1616.52"
+  attribute \src "ls180.v:1661.12-1661.52"
   wire width 32 \main_sdblock2mem_sink_sink_payload_data1
-  attribute \src "ls180.v:1557.6-1557.39"
+  attribute \src "ls180.v:1602.6-1602.39"
   wire \main_sdblock2mem_sink_sink_ready0
-  attribute \src "ls180.v:1614.6-1614.39"
+  attribute \src "ls180.v:1659.6-1659.39"
   wire \main_sdblock2mem_sink_sink_ready1
-  attribute \src "ls180.v:1556.6-1556.39"
+  attribute \src "ls180.v:1601.6-1601.39"
   wire \main_sdblock2mem_sink_sink_valid0
-  attribute \src "ls180.v:1613.5-1613.38"
+  attribute \src "ls180.v:1658.5-1658.38"
   wire \main_sdblock2mem_sink_sink_valid1
-  attribute \src "ls180.v:1610.6-1610.42"
+  attribute \src "ls180.v:1655.6-1655.42"
   wire \main_sdblock2mem_source_source_first
-  attribute \src "ls180.v:1611.6-1611.41"
+  attribute \src "ls180.v:1656.6-1656.41"
   wire \main_sdblock2mem_source_source_last
-  attribute \src "ls180.v:1612.13-1612.56"
+  attribute \src "ls180.v:1657.13-1657.56"
   wire width 32 \main_sdblock2mem_source_source_payload_data
-  attribute \src "ls180.v:1609.6-1609.42"
+  attribute \src "ls180.v:1654.6-1654.42"
   wire \main_sdblock2mem_source_source_ready
-  attribute \src "ls180.v:1608.6-1608.42"
+  attribute \src "ls180.v:1653.6-1653.42"
   wire \main_sdblock2mem_source_source_valid
-  attribute \src "ls180.v:1632.13-1632.52"
+  attribute \src "ls180.v:1677.13-1677.52"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_base
-  attribute \src "ls180.v:1623.5-1623.47"
+  attribute \src "ls180.v:1668.5-1668.47"
   wire \main_sdblock2mem_wishbonedmawriter_base_re
-  attribute \src "ls180.v:1622.12-1622.59"
+  attribute \src "ls180.v:1667.12-1667.59"
   wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage
-  attribute \src "ls180.v:1627.5-1627.49"
+  attribute \src "ls180.v:1672.5-1672.49"
   wire \main_sdblock2mem_wishbonedmawriter_enable_re
-  attribute \src "ls180.v:1626.5-1626.54"
+  attribute \src "ls180.v:1671.5-1671.54"
   wire \main_sdblock2mem_wishbonedmawriter_enable_storage
-  attribute \src "ls180.v:1634.13-1634.54"
+  attribute \src "ls180.v:1679.13-1679.54"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_length
-  attribute \src "ls180.v:1625.5-1625.49"
+  attribute \src "ls180.v:1670.5-1670.49"
   wire \main_sdblock2mem_wishbonedmawriter_length_re
-  attribute \src "ls180.v:1624.12-1624.61"
+  attribute \src "ls180.v:1669.12-1669.61"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage
-  attribute \src "ls180.v:1631.5-1631.47"
+  attribute \src "ls180.v:1676.5-1676.47"
   wire \main_sdblock2mem_wishbonedmawriter_loop_re
-  attribute \src "ls180.v:1630.5-1630.52"
+  attribute \src "ls180.v:1675.5-1675.52"
   wire \main_sdblock2mem_wishbonedmawriter_loop_storage
-  attribute \src "ls180.v:1633.12-1633.53"
+  attribute \src "ls180.v:1678.12-1678.53"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_offset
-  attribute \src "ls180.v:1853.12-1853.79"
+  attribute \src "ls180.v:1898.12-1898.79"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
-  attribute \src "ls180.v:1854.5-1854.75"
+  attribute \src "ls180.v:1899.5-1899.75"
   wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
-  attribute \src "ls180.v:1635.6-1635.46"
+  attribute \src "ls180.v:1680.6-1680.46"
   wire \main_sdblock2mem_wishbonedmawriter_reset
-  attribute \src "ls180.v:1619.6-1619.51"
+  attribute \src "ls180.v:1664.6-1664.51"
   wire \main_sdblock2mem_wishbonedmawriter_sink_first
-  attribute \src "ls180.v:1620.6-1620.50"
+  attribute \src "ls180.v:1665.6-1665.50"
   wire \main_sdblock2mem_wishbonedmawriter_sink_last
-  attribute \src "ls180.v:1621.13-1621.65"
+  attribute \src "ls180.v:1666.13-1666.65"
   wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data
-  attribute \src "ls180.v:1618.5-1618.50"
+  attribute \src "ls180.v:1663.5-1663.50"
   wire \main_sdblock2mem_wishbonedmawriter_sink_ready
-  attribute \src "ls180.v:1617.6-1617.51"
+  attribute \src "ls180.v:1662.6-1662.51"
   wire \main_sdblock2mem_wishbonedmawriter_sink_valid
-  attribute \src "ls180.v:1628.5-1628.46"
+  attribute \src "ls180.v:1673.5-1673.46"
   wire \main_sdblock2mem_wishbonedmawriter_status
-  attribute \src "ls180.v:1629.6-1629.43"
+  attribute \src "ls180.v:1674.6-1674.43"
   wire \main_sdblock2mem_wishbonedmawriter_we
-  attribute \src "ls180.v:1397.5-1397.31"
+  attribute \src "ls180.v:1442.5-1442.31"
   wire \main_sdcore_block_count_re
-  attribute \src "ls180.v:1396.12-1396.43"
+  attribute \src "ls180.v:1441.12-1441.43"
   wire width 32 \main_sdcore_block_count_storage
-  attribute \src "ls180.v:1395.5-1395.32"
+  attribute \src "ls180.v:1440.5-1440.32"
   wire \main_sdcore_block_length_re
-  attribute \src "ls180.v:1394.11-1394.43"
+  attribute \src "ls180.v:1439.11-1439.43"
   wire width 10 \main_sdcore_block_length_storage
-  attribute \src "ls180.v:1381.5-1381.32"
+  attribute \src "ls180.v:1426.5-1426.32"
   wire \main_sdcore_cmd_argument_re
-  attribute \src "ls180.v:1380.12-1380.44"
+  attribute \src "ls180.v:1425.12-1425.44"
   wire width 32 \main_sdcore_cmd_argument_storage
-  attribute \src "ls180.v:1383.5-1383.31"
+  attribute \src "ls180.v:1428.5-1428.31"
   wire \main_sdcore_cmd_command_re
-  attribute \src "ls180.v:1382.12-1382.43"
+  attribute \src "ls180.v:1427.12-1427.43"
   wire width 32 \main_sdcore_cmd_command_storage
-  attribute \src "ls180.v:1536.11-1536.32"
+  attribute \src "ls180.v:1581.11-1581.32"
   wire width 3 \main_sdcore_cmd_count
-  attribute \src "ls180.v:1837.11-1837.55"
+  attribute \src "ls180.v:1882.11-1882.55"
   wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2
-  attribute \src "ls180.v:1838.5-1838.52"
+  attribute \src "ls180.v:1883.5-1883.52"
   wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
-  attribute \src "ls180.v:1537.5-1537.25"
+  attribute \src "ls180.v:1582.5-1582.25"
   wire \main_sdcore_cmd_done
-  attribute \src "ls180.v:1833.5-1833.48"
+  attribute \src "ls180.v:1878.5-1878.48"
   wire \main_sdcore_cmd_done_sdcore_fsm_next_value0
-  attribute \src "ls180.v:1834.5-1834.51"
+  attribute \src "ls180.v:1879.5-1879.51"
   wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
-  attribute \src "ls180.v:1538.5-1538.26"
+  attribute \src "ls180.v:1583.5-1583.26"
   wire \main_sdcore_cmd_error
-  attribute \src "ls180.v:1841.5-1841.49"
+  attribute \src "ls180.v:1886.5-1886.49"
   wire \main_sdcore_cmd_error_sdcore_fsm_next_value4
-  attribute \src "ls180.v:1842.5-1842.52"
+  attribute \src "ls180.v:1887.5-1887.52"
   wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
-  attribute \src "ls180.v:1390.12-1390.40"
+  attribute \src "ls180.v:1435.12-1435.40"
   wire width 4 \main_sdcore_cmd_event_status
-  attribute \src "ls180.v:1391.6-1391.30"
+  attribute \src "ls180.v:1436.6-1436.30"
   wire \main_sdcore_cmd_event_we
-  attribute \src "ls180.v:1388.13-1388.44"
+  attribute \src "ls180.v:1433.13-1433.44"
   wire width 128 \main_sdcore_cmd_response_status
-  attribute \src "ls180.v:1849.13-1849.67"
+  attribute \src "ls180.v:1894.13-1894.67"
   wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
-  attribute \src "ls180.v:1850.5-1850.62"
+  attribute \src "ls180.v:1895.5-1895.62"
   wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
-  attribute \src "ls180.v:1389.6-1389.33"
+  attribute \src "ls180.v:1434.6-1434.33"
   wire \main_sdcore_cmd_response_we
-  attribute \src "ls180.v:1385.6-1385.28"
+  attribute \src "ls180.v:1430.6-1430.28"
   wire \main_sdcore_cmd_send_r
-  attribute \src "ls180.v:1384.6-1384.29"
+  attribute \src "ls180.v:1429.6-1429.29"
   wire \main_sdcore_cmd_send_re
-  attribute \src "ls180.v:1387.5-1387.27"
+  attribute \src "ls180.v:1432.5-1432.27"
   wire \main_sdcore_cmd_send_w
-  attribute \src "ls180.v:1386.6-1386.29"
+  attribute \src "ls180.v:1431.6-1431.29"
   wire \main_sdcore_cmd_send_we
-  attribute \src "ls180.v:1539.5-1539.28"
+  attribute \src "ls180.v:1584.5-1584.28"
   wire \main_sdcore_cmd_timeout
-  attribute \src "ls180.v:1843.5-1843.51"
+  attribute \src "ls180.v:1888.5-1888.51"
   wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
-  attribute \src "ls180.v:1844.5-1844.54"
+  attribute \src "ls180.v:1889.5-1889.54"
   wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
-  attribute \src "ls180.v:1535.12-1535.32"
+  attribute \src "ls180.v:1580.12-1580.32"
   wire width 2 \main_sdcore_cmd_type
-  attribute \src "ls180.v:1497.11-1497.40"
+  attribute \src "ls180.v:1542.11-1542.40"
   wire width 4 \main_sdcore_crc16_checker_cnt
-  attribute \src "ls180.v:1503.5-1503.39"
+  attribute \src "ls180.v:1548.5-1548.39"
   wire \main_sdcore_crc16_checker_crc0_clr
-  attribute \src "ls180.v:1502.12-1502.46"
+  attribute \src "ls180.v:1547.12-1547.46"
   wire width 16 \main_sdcore_crc16_checker_crc0_crc
-  attribute \src "ls180.v:1498.12-1498.50"
+  attribute \src "ls180.v:1543.12-1543.50"
   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0
-  attribute \src "ls180.v:1499.13-1499.51"
+  attribute \src "ls180.v:1544.13-1544.51"
   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1
-  attribute \src "ls180.v:1500.13-1500.51"
+  attribute \src "ls180.v:1545.13-1545.51"
   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2
-  attribute \src "ls180.v:1504.6-1504.43"
+  attribute \src "ls180.v:1549.6-1549.43"
   wire \main_sdcore_crc16_checker_crc0_enable
-  attribute \src "ls180.v:1501.12-1501.46"
+  attribute \src "ls180.v:1546.12-1546.46"
   wire width 2 \main_sdcore_crc16_checker_crc0_val
-  attribute \src "ls180.v:1510.5-1510.39"
+  attribute \src "ls180.v:1555.5-1555.39"
   wire \main_sdcore_crc16_checker_crc1_clr
-  attribute \src "ls180.v:1509.12-1509.46"
+  attribute \src "ls180.v:1554.12-1554.46"
   wire width 16 \main_sdcore_crc16_checker_crc1_crc
-  attribute \src "ls180.v:1505.12-1505.50"
+  attribute \src "ls180.v:1550.12-1550.50"
   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0
-  attribute \src "ls180.v:1506.13-1506.51"
+  attribute \src "ls180.v:1551.13-1551.51"
   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1
-  attribute \src "ls180.v:1507.13-1507.51"
+  attribute \src "ls180.v:1552.13-1552.51"
   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2
-  attribute \src "ls180.v:1511.6-1511.43"
+  attribute \src "ls180.v:1556.6-1556.43"
   wire \main_sdcore_crc16_checker_crc1_enable
-  attribute \src "ls180.v:1508.12-1508.46"
+  attribute \src "ls180.v:1553.12-1553.46"
   wire width 2 \main_sdcore_crc16_checker_crc1_val
-  attribute \src "ls180.v:1517.5-1517.39"
+  attribute \src "ls180.v:1562.5-1562.39"
   wire \main_sdcore_crc16_checker_crc2_clr
-  attribute \src "ls180.v:1516.12-1516.46"
+  attribute \src "ls180.v:1561.12-1561.46"
   wire width 16 \main_sdcore_crc16_checker_crc2_crc
-  attribute \src "ls180.v:1512.12-1512.50"
+  attribute \src "ls180.v:1557.12-1557.50"
   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0
-  attribute \src "ls180.v:1513.13-1513.51"
+  attribute \src "ls180.v:1558.13-1558.51"
   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1
-  attribute \src "ls180.v:1514.13-1514.51"
+  attribute \src "ls180.v:1559.13-1559.51"
   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2
-  attribute \src "ls180.v:1518.6-1518.43"
+  attribute \src "ls180.v:1563.6-1563.43"
   wire \main_sdcore_crc16_checker_crc2_enable
-  attribute \src "ls180.v:1515.12-1515.46"
+  attribute \src "ls180.v:1560.12-1560.46"
   wire width 2 \main_sdcore_crc16_checker_crc2_val
-  attribute \src "ls180.v:1524.5-1524.39"
+  attribute \src "ls180.v:1569.5-1569.39"
   wire \main_sdcore_crc16_checker_crc3_clr
-  attribute \src "ls180.v:1523.12-1523.46"
+  attribute \src "ls180.v:1568.12-1568.46"
   wire width 16 \main_sdcore_crc16_checker_crc3_crc
-  attribute \src "ls180.v:1519.12-1519.50"
+  attribute \src "ls180.v:1564.12-1564.50"
   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0
-  attribute \src "ls180.v:1520.13-1520.51"
+  attribute \src "ls180.v:1565.13-1565.51"
   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1
-  attribute \src "ls180.v:1521.13-1521.51"
+  attribute \src "ls180.v:1566.13-1566.51"
   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2
-  attribute \src "ls180.v:1525.6-1525.43"
+  attribute \src "ls180.v:1570.6-1570.43"
   wire \main_sdcore_crc16_checker_crc3_enable
-  attribute \src "ls180.v:1522.12-1522.46"
+  attribute \src "ls180.v:1567.12-1567.46"
   wire width 2 \main_sdcore_crc16_checker_crc3_val
-  attribute \src "ls180.v:1526.12-1526.45"
+  attribute \src "ls180.v:1571.12-1571.45"
   wire width 16 \main_sdcore_crc16_checker_crctmp0
-  attribute \src "ls180.v:1527.12-1527.45"
+  attribute \src "ls180.v:1572.12-1572.45"
   wire width 16 \main_sdcore_crc16_checker_crctmp1
-  attribute \src "ls180.v:1528.12-1528.45"
+  attribute \src "ls180.v:1573.12-1573.45"
   wire width 16 \main_sdcore_crc16_checker_crctmp2
-  attribute \src "ls180.v:1529.12-1529.45"
+  attribute \src "ls180.v:1574.12-1574.45"
   wire width 16 \main_sdcore_crc16_checker_crctmp3
-  attribute \src "ls180.v:1531.12-1531.43"
+  attribute \src "ls180.v:1576.12-1576.43"
   wire width 16 \main_sdcore_crc16_checker_fifo0
-  attribute \src "ls180.v:1532.12-1532.43"
+  attribute \src "ls180.v:1577.12-1577.43"
   wire width 16 \main_sdcore_crc16_checker_fifo1
-  attribute \src "ls180.v:1533.12-1533.43"
+  attribute \src "ls180.v:1578.12-1578.43"
   wire width 16 \main_sdcore_crc16_checker_fifo2
-  attribute \src "ls180.v:1534.12-1534.43"
+  attribute \src "ls180.v:1579.12-1579.43"
   wire width 16 \main_sdcore_crc16_checker_fifo3
-  attribute \src "ls180.v:1488.5-1488.41"
+  attribute \src "ls180.v:1533.5-1533.41"
   wire \main_sdcore_crc16_checker_sink_first
-  attribute \src "ls180.v:1489.5-1489.40"
+  attribute \src "ls180.v:1534.5-1534.40"
   wire \main_sdcore_crc16_checker_sink_last
-  attribute \src "ls180.v:1490.11-1490.54"
+  attribute \src "ls180.v:1535.11-1535.54"
   wire width 8 \main_sdcore_crc16_checker_sink_payload_data
-  attribute \src "ls180.v:1487.5-1487.41"
+  attribute \src "ls180.v:1532.5-1532.41"
   wire \main_sdcore_crc16_checker_sink_ready
-  attribute \src "ls180.v:1486.5-1486.41"
+  attribute \src "ls180.v:1531.5-1531.41"
   wire \main_sdcore_crc16_checker_sink_valid
-  attribute \src "ls180.v:1493.5-1493.43"
+  attribute \src "ls180.v:1538.5-1538.43"
   wire \main_sdcore_crc16_checker_source_first
-  attribute \src "ls180.v:1494.6-1494.43"
+  attribute \src "ls180.v:1539.6-1539.43"
   wire \main_sdcore_crc16_checker_source_last
-  attribute \src "ls180.v:1495.12-1495.57"
+  attribute \src "ls180.v:1540.12-1540.57"
   wire width 8 \main_sdcore_crc16_checker_source_payload_data
-  attribute \src "ls180.v:1492.6-1492.44"
+  attribute \src "ls180.v:1537.6-1537.44"
   wire \main_sdcore_crc16_checker_source_ready
-  attribute \src "ls180.v:1491.5-1491.43"
+  attribute \src "ls180.v:1536.5-1536.43"
   wire \main_sdcore_crc16_checker_source_valid
-  attribute \src "ls180.v:1496.11-1496.40"
+  attribute \src "ls180.v:1541.11-1541.40"
   wire width 8 \main_sdcore_crc16_checker_val
-  attribute \src "ls180.v:1530.5-1530.36"
+  attribute \src "ls180.v:1575.5-1575.36"
   wire \main_sdcore_crc16_checker_valid
-  attribute \src "ls180.v:1453.11-1453.41"
+  attribute \src "ls180.v:1498.11-1498.41"
   wire width 3 \main_sdcore_crc16_inserter_cnt
-  attribute \src "ls180.v:1829.11-1829.80"
+  attribute \src "ls180.v:1874.11-1874.80"
   wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
-  attribute \src "ls180.v:1830.5-1830.77"
+  attribute \src "ls180.v:1875.5-1875.77"
   wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
-  attribute \src "ls180.v:1459.6-1459.41"
+  attribute \src "ls180.v:1504.6-1504.41"
   wire \main_sdcore_crc16_inserter_crc0_clr
-  attribute \src "ls180.v:1458.12-1458.47"
+  attribute \src "ls180.v:1503.12-1503.47"
   wire width 16 \main_sdcore_crc16_inserter_crc0_crc
-  attribute \src "ls180.v:1454.12-1454.51"
+  attribute \src "ls180.v:1499.12-1499.51"
   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0
-  attribute \src "ls180.v:1455.13-1455.52"
+  attribute \src "ls180.v:1500.13-1500.52"
   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1
-  attribute \src "ls180.v:1456.13-1456.52"
+  attribute \src "ls180.v:1501.13-1501.52"
   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2
-  attribute \src "ls180.v:1460.6-1460.44"
+  attribute \src "ls180.v:1505.6-1505.44"
   wire \main_sdcore_crc16_inserter_crc0_enable
-  attribute \src "ls180.v:1457.12-1457.47"
+  attribute \src "ls180.v:1502.12-1502.47"
   wire width 2 \main_sdcore_crc16_inserter_crc0_val
-  attribute \src "ls180.v:1466.6-1466.41"
+  attribute \src "ls180.v:1511.6-1511.41"
   wire \main_sdcore_crc16_inserter_crc1_clr
-  attribute \src "ls180.v:1465.12-1465.47"
+  attribute \src "ls180.v:1510.12-1510.47"
   wire width 16 \main_sdcore_crc16_inserter_crc1_crc
-  attribute \src "ls180.v:1461.12-1461.51"
+  attribute \src "ls180.v:1506.12-1506.51"
   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0
-  attribute \src "ls180.v:1462.13-1462.52"
+  attribute \src "ls180.v:1507.13-1507.52"
   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1
-  attribute \src "ls180.v:1463.13-1463.52"
+  attribute \src "ls180.v:1508.13-1508.52"
   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2
-  attribute \src "ls180.v:1467.6-1467.44"
+  attribute \src "ls180.v:1512.6-1512.44"
   wire \main_sdcore_crc16_inserter_crc1_enable
-  attribute \src "ls180.v:1464.12-1464.47"
+  attribute \src "ls180.v:1509.12-1509.47"
   wire width 2 \main_sdcore_crc16_inserter_crc1_val
-  attribute \src "ls180.v:1473.6-1473.41"
+  attribute \src "ls180.v:1518.6-1518.41"
   wire \main_sdcore_crc16_inserter_crc2_clr
-  attribute \src "ls180.v:1472.12-1472.47"
+  attribute \src "ls180.v:1517.12-1517.47"
   wire width 16 \main_sdcore_crc16_inserter_crc2_crc
-  attribute \src "ls180.v:1468.12-1468.51"
+  attribute \src "ls180.v:1513.12-1513.51"
   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0
-  attribute \src "ls180.v:1469.13-1469.52"
+  attribute \src "ls180.v:1514.13-1514.52"
   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1
-  attribute \src "ls180.v:1470.13-1470.52"
+  attribute \src "ls180.v:1515.13-1515.52"
   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2
-  attribute \src "ls180.v:1474.6-1474.44"
+  attribute \src "ls180.v:1519.6-1519.44"
   wire \main_sdcore_crc16_inserter_crc2_enable
-  attribute \src "ls180.v:1471.12-1471.47"
+  attribute \src "ls180.v:1516.12-1516.47"
   wire width 2 \main_sdcore_crc16_inserter_crc2_val
-  attribute \src "ls180.v:1480.6-1480.41"
+  attribute \src "ls180.v:1525.6-1525.41"
   wire \main_sdcore_crc16_inserter_crc3_clr
-  attribute \src "ls180.v:1479.12-1479.47"
+  attribute \src "ls180.v:1524.12-1524.47"
   wire width 16 \main_sdcore_crc16_inserter_crc3_crc
-  attribute \src "ls180.v:1475.12-1475.51"
+  attribute \src "ls180.v:1520.12-1520.51"
   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0
-  attribute \src "ls180.v:1476.13-1476.52"
+  attribute \src "ls180.v:1521.13-1521.52"
   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1
-  attribute \src "ls180.v:1477.13-1477.52"
+  attribute \src "ls180.v:1522.13-1522.52"
   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2
-  attribute \src "ls180.v:1481.6-1481.44"
+  attribute \src "ls180.v:1526.6-1526.44"
   wire \main_sdcore_crc16_inserter_crc3_enable
-  attribute \src "ls180.v:1478.12-1478.47"
+  attribute \src "ls180.v:1523.12-1523.47"
   wire width 2 \main_sdcore_crc16_inserter_crc3_val
-  attribute \src "ls180.v:1482.12-1482.46"
+  attribute \src "ls180.v:1527.12-1527.46"
   wire width 16 \main_sdcore_crc16_inserter_crctmp0
-  attribute \src "ls180.v:1821.12-1821.85"
+  attribute \src "ls180.v:1866.12-1866.85"
   wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
-  attribute \src "ls180.v:1822.5-1822.81"
+  attribute \src "ls180.v:1867.5-1867.81"
   wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
-  attribute \src "ls180.v:1483.12-1483.46"
+  attribute \src "ls180.v:1528.12-1528.46"
   wire width 16 \main_sdcore_crc16_inserter_crctmp1
-  attribute \src "ls180.v:1823.12-1823.85"
+  attribute \src "ls180.v:1868.12-1868.85"
   wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
-  attribute \src "ls180.v:1824.5-1824.81"
+  attribute \src "ls180.v:1869.5-1869.81"
   wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
-  attribute \src "ls180.v:1484.12-1484.46"
+  attribute \src "ls180.v:1529.12-1529.46"
   wire width 16 \main_sdcore_crc16_inserter_crctmp2
-  attribute \src "ls180.v:1825.12-1825.85"
+  attribute \src "ls180.v:1870.12-1870.85"
   wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
-  attribute \src "ls180.v:1826.5-1826.81"
+  attribute \src "ls180.v:1871.5-1871.81"
   wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
-  attribute \src "ls180.v:1485.12-1485.46"
+  attribute \src "ls180.v:1530.12-1530.46"
   wire width 16 \main_sdcore_crc16_inserter_crctmp3
-  attribute \src "ls180.v:1827.12-1827.85"
+  attribute \src "ls180.v:1872.12-1872.85"
   wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
-  attribute \src "ls180.v:1828.5-1828.81"
+  attribute \src "ls180.v:1873.5-1873.81"
   wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
-  attribute \src "ls180.v:1445.6-1445.43"
+  attribute \src "ls180.v:1490.6-1490.43"
   wire \main_sdcore_crc16_inserter_sink_first
-  attribute \src "ls180.v:1446.6-1446.42"
+  attribute \src "ls180.v:1491.6-1491.42"
   wire \main_sdcore_crc16_inserter_sink_last
-  attribute \src "ls180.v:1447.12-1447.56"
+  attribute \src "ls180.v:1492.12-1492.56"
   wire width 8 \main_sdcore_crc16_inserter_sink_payload_data
-  attribute \src "ls180.v:1444.5-1444.42"
+  attribute \src "ls180.v:1489.5-1489.42"
   wire \main_sdcore_crc16_inserter_sink_ready
-  attribute \src "ls180.v:1443.6-1443.43"
+  attribute \src "ls180.v:1488.6-1488.43"
   wire \main_sdcore_crc16_inserter_sink_valid
-  attribute \src "ls180.v:1450.5-1450.44"
+  attribute \src "ls180.v:1495.5-1495.44"
   wire \main_sdcore_crc16_inserter_source_first
-  attribute \src "ls180.v:1451.5-1451.43"
+  attribute \src "ls180.v:1496.5-1496.43"
   wire \main_sdcore_crc16_inserter_source_last
-  attribute \src "ls180.v:1452.11-1452.57"
+  attribute \src "ls180.v:1497.11-1497.57"
   wire width 8 \main_sdcore_crc16_inserter_source_payload_data
-  attribute \src "ls180.v:1449.5-1449.44"
+  attribute \src "ls180.v:1494.5-1494.44"
   wire \main_sdcore_crc16_inserter_source_ready
-  attribute \src "ls180.v:1448.5-1448.44"
+  attribute \src "ls180.v:1493.5-1493.44"
   wire \main_sdcore_crc16_inserter_source_valid
-  attribute \src "ls180.v:1441.6-1441.35"
+  attribute \src "ls180.v:1486.6-1486.35"
   wire \main_sdcore_crc7_inserter_clr
-  attribute \src "ls180.v:1440.11-1440.40"
+  attribute \src "ls180.v:1485.11-1485.40"
   wire width 7 \main_sdcore_crc7_inserter_crc
-  attribute \src "ls180.v:1398.11-1398.44"
+  attribute \src "ls180.v:1443.11-1443.44"
   wire width 7 \main_sdcore_crc7_inserter_crcreg0
-  attribute \src "ls180.v:1399.12-1399.45"
+  attribute \src "ls180.v:1444.12-1444.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg1
-  attribute \src "ls180.v:1408.12-1408.46"
+  attribute \src "ls180.v:1453.12-1453.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg10
-  attribute \src "ls180.v:1409.12-1409.46"
+  attribute \src "ls180.v:1454.12-1454.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg11
-  attribute \src "ls180.v:1410.12-1410.46"
+  attribute \src "ls180.v:1455.12-1455.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg12
-  attribute \src "ls180.v:1411.12-1411.46"
+  attribute \src "ls180.v:1456.12-1456.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg13
-  attribute \src "ls180.v:1412.12-1412.46"
+  attribute \src "ls180.v:1457.12-1457.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg14
-  attribute \src "ls180.v:1413.12-1413.46"
+  attribute \src "ls180.v:1458.12-1458.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg15
-  attribute \src "ls180.v:1414.12-1414.46"
+  attribute \src "ls180.v:1459.12-1459.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg16
-  attribute \src "ls180.v:1415.12-1415.46"
+  attribute \src "ls180.v:1460.12-1460.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg17
-  attribute \src "ls180.v:1416.12-1416.46"
+  attribute \src "ls180.v:1461.12-1461.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg18
-  attribute \src "ls180.v:1417.12-1417.46"
+  attribute \src "ls180.v:1462.12-1462.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg19
-  attribute \src "ls180.v:1400.12-1400.45"
+  attribute \src "ls180.v:1445.12-1445.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg2
-  attribute \src "ls180.v:1418.12-1418.46"
+  attribute \src "ls180.v:1463.12-1463.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg20
-  attribute \src "ls180.v:1419.12-1419.46"
+  attribute \src "ls180.v:1464.12-1464.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg21
-  attribute \src "ls180.v:1420.12-1420.46"
+  attribute \src "ls180.v:1465.12-1465.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg22
-  attribute \src "ls180.v:1421.12-1421.46"
+  attribute \src "ls180.v:1466.12-1466.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg23
-  attribute \src "ls180.v:1422.12-1422.46"
+  attribute \src "ls180.v:1467.12-1467.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg24
-  attribute \src "ls180.v:1423.12-1423.46"
+  attribute \src "ls180.v:1468.12-1468.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg25
-  attribute \src "ls180.v:1424.12-1424.46"
+  attribute \src "ls180.v:1469.12-1469.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg26
-  attribute \src "ls180.v:1425.12-1425.46"
+  attribute \src "ls180.v:1470.12-1470.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg27
-  attribute \src "ls180.v:1426.12-1426.46"
+  attribute \src "ls180.v:1471.12-1471.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg28
-  attribute \src "ls180.v:1427.12-1427.46"
+  attribute \src "ls180.v:1472.12-1472.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg29
-  attribute \src "ls180.v:1401.12-1401.45"
+  attribute \src "ls180.v:1446.12-1446.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg3
-  attribute \src "ls180.v:1428.12-1428.46"
+  attribute \src "ls180.v:1473.12-1473.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg30
-  attribute \src "ls180.v:1429.12-1429.46"
+  attribute \src "ls180.v:1474.12-1474.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg31
-  attribute \src "ls180.v:1430.12-1430.46"
+  attribute \src "ls180.v:1475.12-1475.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg32
-  attribute \src "ls180.v:1431.12-1431.46"
+  attribute \src "ls180.v:1476.12-1476.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg33
-  attribute \src "ls180.v:1432.12-1432.46"
+  attribute \src "ls180.v:1477.12-1477.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg34
-  attribute \src "ls180.v:1433.12-1433.46"
+  attribute \src "ls180.v:1478.12-1478.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg35
-  attribute \src "ls180.v:1434.12-1434.46"
+  attribute \src "ls180.v:1479.12-1479.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg36
-  attribute \src "ls180.v:1435.12-1435.46"
+  attribute \src "ls180.v:1480.12-1480.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg37
-  attribute \src "ls180.v:1436.12-1436.46"
+  attribute \src "ls180.v:1481.12-1481.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg38
-  attribute \src "ls180.v:1437.12-1437.46"
+  attribute \src "ls180.v:1482.12-1482.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg39
-  attribute \src "ls180.v:1402.12-1402.45"
+  attribute \src "ls180.v:1447.12-1447.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg4
-  attribute \src "ls180.v:1438.12-1438.46"
+  attribute \src "ls180.v:1483.12-1483.46"
   wire width 7 \main_sdcore_crc7_inserter_crcreg40
-  attribute \src "ls180.v:1403.12-1403.45"
+  attribute \src "ls180.v:1448.12-1448.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg5
-  attribute \src "ls180.v:1404.12-1404.45"
+  attribute \src "ls180.v:1449.12-1449.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg6
-  attribute \src "ls180.v:1405.12-1405.45"
+  attribute \src "ls180.v:1450.12-1450.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg7
-  attribute \src "ls180.v:1406.12-1406.45"
+  attribute \src "ls180.v:1451.12-1451.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg8
-  attribute \src "ls180.v:1407.12-1407.45"
+  attribute \src "ls180.v:1452.12-1452.45"
   wire width 7 \main_sdcore_crc7_inserter_crcreg9
-  attribute \src "ls180.v:1442.6-1442.38"
+  attribute \src "ls180.v:1487.6-1487.38"
   wire \main_sdcore_crc7_inserter_enable
-  attribute \src "ls180.v:1439.13-1439.42"
+  attribute \src "ls180.v:1484.13-1484.42"
   wire width 40 \main_sdcore_crc7_inserter_val
-  attribute \src "ls180.v:1541.12-1541.34"
+  attribute \src "ls180.v:1586.12-1586.34"
   wire width 32 \main_sdcore_data_count
-  attribute \src "ls180.v:1839.12-1839.57"
+  attribute \src "ls180.v:1884.12-1884.57"
   wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3
-  attribute \src "ls180.v:1840.5-1840.53"
+  attribute \src "ls180.v:1885.5-1885.53"
   wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3
-  attribute \src "ls180.v:1542.5-1542.26"
+  attribute \src "ls180.v:1587.5-1587.26"
   wire \main_sdcore_data_done
-  attribute \src "ls180.v:1835.5-1835.49"
+  attribute \src "ls180.v:1880.5-1880.49"
   wire \main_sdcore_data_done_sdcore_fsm_next_value1
-  attribute \src "ls180.v:1836.5-1836.52"
+  attribute \src "ls180.v:1881.5-1881.52"
   wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1
-  attribute \src "ls180.v:1543.5-1543.27"
+  attribute \src "ls180.v:1588.5-1588.27"
   wire \main_sdcore_data_error
-  attribute \src "ls180.v:1845.5-1845.50"
+  attribute \src "ls180.v:1890.5-1890.50"
   wire \main_sdcore_data_error_sdcore_fsm_next_value6
-  attribute \src "ls180.v:1846.5-1846.53"
+  attribute \src "ls180.v:1891.5-1891.53"
   wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6
-  attribute \src "ls180.v:1392.12-1392.41"
+  attribute \src "ls180.v:1437.12-1437.41"
   wire width 4 \main_sdcore_data_event_status
-  attribute \src "ls180.v:1393.6-1393.31"
+  attribute \src "ls180.v:1438.6-1438.31"
   wire \main_sdcore_data_event_we
-  attribute \src "ls180.v:1544.5-1544.29"
+  attribute \src "ls180.v:1589.5-1589.29"
   wire \main_sdcore_data_timeout
-  attribute \src "ls180.v:1847.5-1847.52"
+  attribute \src "ls180.v:1892.5-1892.52"
   wire \main_sdcore_data_timeout_sdcore_fsm_next_value7
-  attribute \src "ls180.v:1848.5-1848.55"
+  attribute \src "ls180.v:1893.5-1893.55"
   wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
-  attribute \src "ls180.v:1540.12-1540.33"
+  attribute \src "ls180.v:1585.12-1585.33"
   wire width 2 \main_sdcore_data_type
-  attribute \src "ls180.v:1372.6-1372.33"
+  attribute \src "ls180.v:1417.6-1417.33"
   wire \main_sdcore_sink_sink_first
-  attribute \src "ls180.v:1373.6-1373.32"
+  attribute \src "ls180.v:1418.6-1418.32"
   wire \main_sdcore_sink_sink_last
-  attribute \src "ls180.v:1374.12-1374.46"
+  attribute \src "ls180.v:1419.12-1419.46"
   wire width 8 \main_sdcore_sink_sink_payload_data
-  attribute \src "ls180.v:1371.6-1371.33"
+  attribute \src "ls180.v:1416.6-1416.33"
   wire \main_sdcore_sink_sink_ready
-  attribute \src "ls180.v:1370.6-1370.33"
+  attribute \src "ls180.v:1415.6-1415.33"
   wire \main_sdcore_sink_sink_valid
-  attribute \src "ls180.v:1377.6-1377.37"
+  attribute \src "ls180.v:1422.6-1422.37"
   wire \main_sdcore_source_source_first
-  attribute \src "ls180.v:1378.6-1378.36"
+  attribute \src "ls180.v:1423.6-1423.36"
   wire \main_sdcore_source_source_last
-  attribute \src "ls180.v:1379.12-1379.50"
+  attribute \src "ls180.v:1424.12-1424.50"
   wire width 8 \main_sdcore_source_source_payload_data
-  attribute \src "ls180.v:1376.6-1376.37"
+  attribute \src "ls180.v:1421.6-1421.37"
   wire \main_sdcore_source_source_ready
-  attribute \src "ls180.v:1375.6-1375.37"
+  attribute \src "ls180.v:1420.6-1420.37"
   wire \main_sdcore_source_source_valid
-  attribute \src "ls180.v:1690.6-1690.38"
+  attribute \src "ls180.v:1735.6-1735.38"
   wire \main_sdmem2block_converter_first
-  attribute \src "ls180.v:1691.6-1691.37"
+  attribute \src "ls180.v:1736.6-1736.37"
   wire \main_sdmem2block_converter_last
-  attribute \src "ls180.v:1689.11-1689.41"
+  attribute \src "ls180.v:1734.11-1734.41"
   wire width 2 \main_sdmem2block_converter_mux
-  attribute \src "ls180.v:1680.6-1680.43"
+  attribute \src "ls180.v:1725.6-1725.43"
   wire \main_sdmem2block_converter_sink_first
-  attribute \src "ls180.v:1681.6-1681.42"
+  attribute \src "ls180.v:1726.6-1726.42"
   wire \main_sdmem2block_converter_sink_last
-  attribute \src "ls180.v:1682.13-1682.57"
+  attribute \src "ls180.v:1727.13-1727.57"
   wire width 32 \main_sdmem2block_converter_sink_payload_data
-  attribute \src "ls180.v:1679.6-1679.43"
+  attribute \src "ls180.v:1724.6-1724.43"
   wire \main_sdmem2block_converter_sink_ready
-  attribute \src "ls180.v:1678.6-1678.43"
+  attribute \src "ls180.v:1723.6-1723.43"
   wire \main_sdmem2block_converter_sink_valid
-  attribute \src "ls180.v:1685.6-1685.45"
+  attribute \src "ls180.v:1730.6-1730.45"
   wire \main_sdmem2block_converter_source_first
-  attribute \src "ls180.v:1686.6-1686.44"
+  attribute \src "ls180.v:1731.6-1731.44"
   wire \main_sdmem2block_converter_source_last
-  attribute \src "ls180.v:1687.11-1687.57"
+  attribute \src "ls180.v:1732.11-1732.57"
   wire width 8 \main_sdmem2block_converter_source_payload_data
-  attribute \src "ls180.v:1688.6-1688.65"
+  attribute \src "ls180.v:1733.6-1733.65"
   wire \main_sdmem2block_converter_source_payload_valid_token_count
-  attribute \src "ls180.v:1684.6-1684.45"
+  attribute \src "ls180.v:1729.6-1729.45"
   wire \main_sdmem2block_converter_source_ready
-  attribute \src "ls180.v:1683.6-1683.45"
+  attribute \src "ls180.v:1728.6-1728.45"
   wire \main_sdmem2block_converter_source_valid
-  attribute \src "ls180.v:1674.13-1674.38"
+  attribute \src "ls180.v:1719.13-1719.38"
   wire width 32 \main_sdmem2block_dma_base
-  attribute \src "ls180.v:1663.5-1663.33"
+  attribute \src "ls180.v:1708.5-1708.33"
   wire \main_sdmem2block_dma_base_re
-  attribute \src "ls180.v:1662.12-1662.45"
+  attribute \src "ls180.v:1707.12-1707.45"
   wire width 64 \main_sdmem2block_dma_base_storage
-  attribute \src "ls180.v:1661.12-1661.37"
+  attribute \src "ls180.v:1706.12-1706.37"
   wire width 32 \main_sdmem2block_dma_data
-  attribute \src "ls180.v:1857.12-1857.67"
+  attribute \src "ls180.v:1902.12-1902.67"
   wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
-  attribute \src "ls180.v:1858.5-1858.63"
+  attribute \src "ls180.v:1903.5-1903.63"
   wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
-  attribute \src "ls180.v:1668.5-1668.37"
+  attribute \src "ls180.v:1713.5-1713.37"
   wire \main_sdmem2block_dma_done_status
-  attribute \src "ls180.v:1669.6-1669.34"
+  attribute \src "ls180.v:1714.6-1714.34"
   wire \main_sdmem2block_dma_done_we
-  attribute \src "ls180.v:1667.5-1667.35"
+  attribute \src "ls180.v:1712.5-1712.35"
   wire \main_sdmem2block_dma_enable_re
-  attribute \src "ls180.v:1666.5-1666.40"
+  attribute \src "ls180.v:1711.5-1711.40"
   wire \main_sdmem2block_dma_enable_storage
-  attribute \src "ls180.v:1676.13-1676.40"
+  attribute \src "ls180.v:1721.13-1721.40"
   wire width 32 \main_sdmem2block_dma_length
-  attribute \src "ls180.v:1665.5-1665.35"
+  attribute \src "ls180.v:1710.5-1710.35"
   wire \main_sdmem2block_dma_length_re
-  attribute \src "ls180.v:1664.12-1664.47"
+  attribute \src "ls180.v:1709.12-1709.47"
   wire width 32 \main_sdmem2block_dma_length_storage
-  attribute \src "ls180.v:1671.5-1671.33"
+  attribute \src "ls180.v:1716.5-1716.33"
   wire \main_sdmem2block_dma_loop_re
-  attribute \src "ls180.v:1670.5-1670.38"
+  attribute \src "ls180.v:1715.5-1715.38"
   wire \main_sdmem2block_dma_loop_storage
-  attribute \src "ls180.v:1675.12-1675.39"
+  attribute \src "ls180.v:1720.12-1720.39"
   wire width 32 \main_sdmem2block_dma_offset
-  attribute \src "ls180.v:1861.12-1861.79"
+  attribute \src "ls180.v:1906.12-1906.79"
   wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
-  attribute \src "ls180.v:1862.5-1862.75"
+  attribute \src "ls180.v:1907.5-1907.75"
   wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
-  attribute \src "ls180.v:1672.13-1672.47"
+  attribute \src "ls180.v:1717.13-1717.47"
   wire width 32 \main_sdmem2block_dma_offset_status
-  attribute \src "ls180.v:1673.6-1673.36"
+  attribute \src "ls180.v:1718.6-1718.36"
   wire \main_sdmem2block_dma_offset_we
-  attribute \src "ls180.v:1677.6-1677.32"
+  attribute \src "ls180.v:1722.6-1722.32"
   wire \main_sdmem2block_dma_reset
-  attribute \src "ls180.v:1654.5-1654.35"
+  attribute \src "ls180.v:1699.5-1699.35"
   wire \main_sdmem2block_dma_sink_last
-  attribute \src "ls180.v:1655.12-1655.53"
+  attribute \src "ls180.v:1700.12-1700.53"
   wire width 32 \main_sdmem2block_dma_sink_payload_address
-  attribute \src "ls180.v:1653.5-1653.36"
+  attribute \src "ls180.v:1698.5-1698.36"
   wire \main_sdmem2block_dma_sink_ready
-  attribute \src "ls180.v:1652.5-1652.36"
+  attribute \src "ls180.v:1697.5-1697.36"
   wire \main_sdmem2block_dma_sink_valid
-  attribute \src "ls180.v:1658.5-1658.38"
+  attribute \src "ls180.v:1703.5-1703.38"
   wire \main_sdmem2block_dma_source_first
-  attribute \src "ls180.v:1659.5-1659.37"
+  attribute \src "ls180.v:1704.5-1704.37"
   wire \main_sdmem2block_dma_source_last
-  attribute \src "ls180.v:1660.12-1660.52"
+  attribute \src "ls180.v:1705.12-1705.52"
   wire width 32 \main_sdmem2block_dma_source_payload_data
-  attribute \src "ls180.v:1657.6-1657.39"
+  attribute \src "ls180.v:1702.6-1702.39"
   wire \main_sdmem2block_dma_source_ready
-  attribute \src "ls180.v:1656.5-1656.38"
+  attribute \src "ls180.v:1701.5-1701.38"
   wire \main_sdmem2block_dma_source_valid
-  attribute \src "ls180.v:1716.11-1716.40"
+  attribute \src "ls180.v:1761.11-1761.40"
   wire width 5 \main_sdmem2block_fifo_consume
-  attribute \src "ls180.v:1721.6-1721.35"
+  attribute \src "ls180.v:1766.6-1766.35"
   wire \main_sdmem2block_fifo_do_read
-  attribute \src "ls180.v:1725.6-1725.41"
+  attribute \src "ls180.v:1770.6-1770.41"
   wire \main_sdmem2block_fifo_fifo_in_first
-  attribute \src "ls180.v:1726.6-1726.40"
+  attribute \src "ls180.v:1771.6-1771.40"
   wire \main_sdmem2block_fifo_fifo_in_last
-  attribute \src "ls180.v:1724.12-1724.54"
+  attribute \src "ls180.v:1769.12-1769.54"
   wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:1728.6-1728.42"
+  attribute \src "ls180.v:1773.6-1773.42"
   wire \main_sdmem2block_fifo_fifo_out_first
-  attribute \src "ls180.v:1729.6-1729.41"
+  attribute \src "ls180.v:1774.6-1774.41"
   wire \main_sdmem2block_fifo_fifo_out_last
-  attribute \src "ls180.v:1727.12-1727.55"
+  attribute \src "ls180.v:1772.12-1772.55"
   wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:1713.11-1713.38"
+  attribute \src "ls180.v:1758.11-1758.38"
   wire width 6 \main_sdmem2block_fifo_level
-  attribute \src "ls180.v:1715.11-1715.40"
+  attribute \src "ls180.v:1760.11-1760.40"
   wire width 5 \main_sdmem2block_fifo_produce
-  attribute \src "ls180.v:1722.12-1722.44"
+  attribute \src "ls180.v:1767.12-1767.44"
   wire width 5 \main_sdmem2block_fifo_rdport_adr
-  attribute \src "ls180.v:1723.12-1723.46"
+  attribute \src "ls180.v:1768.12-1768.46"
   wire width 10 \main_sdmem2block_fifo_rdport_dat_r
-  attribute \src "ls180.v:1714.5-1714.34"
+  attribute \src "ls180.v:1759.5-1759.34"
   wire \main_sdmem2block_fifo_replace
-  attribute \src "ls180.v:1699.6-1699.38"
+  attribute \src "ls180.v:1744.6-1744.38"
   wire \main_sdmem2block_fifo_sink_first
-  attribute \src "ls180.v:1700.6-1700.37"
+  attribute \src "ls180.v:1745.6-1745.37"
   wire \main_sdmem2block_fifo_sink_last
-  attribute \src "ls180.v:1701.12-1701.51"
+  attribute \src "ls180.v:1746.12-1746.51"
   wire width 8 \main_sdmem2block_fifo_sink_payload_data
-  attribute \src "ls180.v:1698.6-1698.38"
+  attribute \src "ls180.v:1743.6-1743.38"
   wire \main_sdmem2block_fifo_sink_ready
-  attribute \src "ls180.v:1697.6-1697.38"
+  attribute \src "ls180.v:1742.6-1742.38"
   wire \main_sdmem2block_fifo_sink_valid
-  attribute \src "ls180.v:1704.6-1704.40"
+  attribute \src "ls180.v:1749.6-1749.40"
   wire \main_sdmem2block_fifo_source_first
-  attribute \src "ls180.v:1705.6-1705.39"
+  attribute \src "ls180.v:1750.6-1750.39"
   wire \main_sdmem2block_fifo_source_last
-  attribute \src "ls180.v:1706.12-1706.53"
+  attribute \src "ls180.v:1751.12-1751.53"
   wire width 8 \main_sdmem2block_fifo_source_payload_data
-  attribute \src "ls180.v:1703.6-1703.40"
+  attribute \src "ls180.v:1748.6-1748.40"
   wire \main_sdmem2block_fifo_source_ready
-  attribute \src "ls180.v:1702.6-1702.40"
+  attribute \src "ls180.v:1747.6-1747.40"
   wire \main_sdmem2block_fifo_source_valid
-  attribute \src "ls180.v:1711.12-1711.46"
+  attribute \src "ls180.v:1756.12-1756.46"
   wire width 10 \main_sdmem2block_fifo_syncfifo_din
-  attribute \src "ls180.v:1712.12-1712.47"
+  attribute \src "ls180.v:1757.12-1757.47"
   wire width 10 \main_sdmem2block_fifo_syncfifo_dout
-  attribute \src "ls180.v:1709.6-1709.39"
+  attribute \src "ls180.v:1754.6-1754.39"
   wire \main_sdmem2block_fifo_syncfifo_re
-  attribute \src "ls180.v:1710.6-1710.45"
+  attribute \src "ls180.v:1755.6-1755.45"
   wire \main_sdmem2block_fifo_syncfifo_readable
-  attribute \src "ls180.v:1707.6-1707.39"
+  attribute \src "ls180.v:1752.6-1752.39"
   wire \main_sdmem2block_fifo_syncfifo_we
-  attribute \src "ls180.v:1708.6-1708.45"
+  attribute \src "ls180.v:1753.6-1753.45"
   wire \main_sdmem2block_fifo_syncfifo_writable
-  attribute \src "ls180.v:1717.11-1717.43"
+  attribute \src "ls180.v:1762.11-1762.43"
   wire width 5 \main_sdmem2block_fifo_wrport_adr
-  attribute \src "ls180.v:1718.12-1718.46"
+  attribute \src "ls180.v:1763.12-1763.46"
   wire width 10 \main_sdmem2block_fifo_wrport_dat_r
-  attribute \src "ls180.v:1720.12-1720.46"
+  attribute \src "ls180.v:1765.12-1765.46"
   wire width 10 \main_sdmem2block_fifo_wrport_dat_w
-  attribute \src "ls180.v:1719.6-1719.37"
+  attribute \src "ls180.v:1764.6-1764.37"
   wire \main_sdmem2block_fifo_wrport_we
-  attribute \src "ls180.v:1649.6-1649.43"
-  wire \main_sdmem2block_source_source_first0
   attribute \src "ls180.v:1694.6-1694.43"
+  wire \main_sdmem2block_source_source_first0
+  attribute \src "ls180.v:1739.6-1739.43"
   wire \main_sdmem2block_source_source_first1
-  attribute \src "ls180.v:1650.6-1650.42"
-  wire \main_sdmem2block_source_source_last0
   attribute \src "ls180.v:1695.6-1695.42"
+  wire \main_sdmem2block_source_source_last0
+  attribute \src "ls180.v:1740.6-1740.42"
   wire \main_sdmem2block_source_source_last1
-  attribute \src "ls180.v:1651.12-1651.56"
-  wire width 8 \main_sdmem2block_source_source_payload_data0
   attribute \src "ls180.v:1696.12-1696.56"
+  wire width 8 \main_sdmem2block_source_source_payload_data0
+  attribute \src "ls180.v:1741.12-1741.56"
   wire width 8 \main_sdmem2block_source_source_payload_data1
-  attribute \src "ls180.v:1648.6-1648.43"
-  wire \main_sdmem2block_source_source_ready0
   attribute \src "ls180.v:1693.6-1693.43"
+  wire \main_sdmem2block_source_source_ready0
+  attribute \src "ls180.v:1738.6-1738.43"
   wire \main_sdmem2block_source_source_ready1
-  attribute \src "ls180.v:1647.6-1647.43"
-  wire \main_sdmem2block_source_source_valid0
   attribute \src "ls180.v:1692.6-1692.43"
+  wire \main_sdmem2block_source_source_valid0
+  attribute \src "ls180.v:1737.6-1737.43"
   wire \main_sdmem2block_source_source_valid1
-  attribute \src "ls180.v:1098.6-1098.27"
+  attribute \src "ls180.v:1143.6-1143.27"
   wire \main_sdphy_clocker_ce
-  attribute \src "ls180.v:1097.5-1097.28"
+  attribute \src "ls180.v:1142.5-1142.28"
   wire \main_sdphy_clocker_clk0
-  attribute \src "ls180.v:1100.5-1100.28"
+  attribute \src "ls180.v:1145.5-1145.28"
   wire \main_sdphy_clocker_clk1
-  attribute \src "ls180.v:1101.5-1101.29"
+  attribute \src "ls180.v:1146.5-1146.29"
   wire \main_sdphy_clocker_clk_d
-  attribute \src "ls180.v:1099.11-1099.34"
+  attribute \src "ls180.v:1144.11-1144.34"
   wire width 9 \main_sdphy_clocker_clks
-  attribute \src "ls180.v:1095.5-1095.26"
+  attribute \src "ls180.v:1140.5-1140.26"
   wire \main_sdphy_clocker_re
-  attribute \src "ls180.v:1096.6-1096.29"
+  attribute \src "ls180.v:1141.6-1141.29"
   wire \main_sdphy_clocker_stop
-  attribute \src "ls180.v:1094.11-1094.37"
+  attribute \src "ls180.v:1139.11-1139.37"
   wire width 9 \main_sdphy_clocker_storage
-  attribute \src "ls180.v:1198.6-1198.41"
+  attribute \src "ls180.v:1243.6-1243.41"
   wire \main_sdphy_cmdr_cmdr_buf_sink_first
-  attribute \src "ls180.v:1199.6-1199.40"
+  attribute \src "ls180.v:1244.6-1244.40"
   wire \main_sdphy_cmdr_cmdr_buf_sink_last
-  attribute \src "ls180.v:1200.12-1200.54"
+  attribute \src "ls180.v:1245.12-1245.54"
   wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data
-  attribute \src "ls180.v:1197.6-1197.41"
+  attribute \src "ls180.v:1242.6-1242.41"
   wire \main_sdphy_cmdr_cmdr_buf_sink_ready
-  attribute \src "ls180.v:1196.6-1196.41"
+  attribute \src "ls180.v:1241.6-1241.41"
   wire \main_sdphy_cmdr_cmdr_buf_sink_valid
-  attribute \src "ls180.v:1203.5-1203.42"
+  attribute \src "ls180.v:1248.5-1248.42"
   wire \main_sdphy_cmdr_cmdr_buf_source_first
-  attribute \src "ls180.v:1204.5-1204.41"
+  attribute \src "ls180.v:1249.5-1249.41"
   wire \main_sdphy_cmdr_cmdr_buf_source_last
-  attribute \src "ls180.v:1205.11-1205.55"
+  attribute \src "ls180.v:1250.11-1250.55"
   wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data
-  attribute \src "ls180.v:1202.6-1202.43"
+  attribute \src "ls180.v:1247.6-1247.43"
   wire \main_sdphy_cmdr_cmdr_buf_source_ready
-  attribute \src "ls180.v:1201.5-1201.42"
+  attribute \src "ls180.v:1246.5-1246.42"
   wire \main_sdphy_cmdr_cmdr_buf_source_valid
-  attribute \src "ls180.v:1188.11-1188.47"
+  attribute \src "ls180.v:1233.11-1233.47"
   wire width 3 \main_sdphy_cmdr_cmdr_converter_demux
-  attribute \src "ls180.v:1189.6-1189.46"
+  attribute \src "ls180.v:1234.6-1234.46"
   wire \main_sdphy_cmdr_cmdr_converter_load_part
-  attribute \src "ls180.v:1179.5-1179.46"
+  attribute \src "ls180.v:1224.5-1224.46"
   wire \main_sdphy_cmdr_cmdr_converter_sink_first
-  attribute \src "ls180.v:1180.5-1180.45"
+  attribute \src "ls180.v:1225.5-1225.45"
   wire \main_sdphy_cmdr_cmdr_converter_sink_last
-  attribute \src "ls180.v:1181.6-1181.54"
+  attribute \src "ls180.v:1226.6-1226.54"
   wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data
-  attribute \src "ls180.v:1178.6-1178.47"
+  attribute \src "ls180.v:1223.6-1223.47"
   wire \main_sdphy_cmdr_cmdr_converter_sink_ready
-  attribute \src "ls180.v:1177.6-1177.47"
+  attribute \src "ls180.v:1222.6-1222.47"
   wire \main_sdphy_cmdr_cmdr_converter_sink_valid
-  attribute \src "ls180.v:1184.5-1184.48"
+  attribute \src "ls180.v:1229.5-1229.48"
   wire \main_sdphy_cmdr_cmdr_converter_source_first
-  attribute \src "ls180.v:1185.5-1185.47"
+  attribute \src "ls180.v:1230.5-1230.47"
   wire \main_sdphy_cmdr_cmdr_converter_source_last
-  attribute \src "ls180.v:1186.11-1186.61"
+  attribute \src "ls180.v:1231.11-1231.61"
   wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data
-  attribute \src "ls180.v:1187.11-1187.74"
+  attribute \src "ls180.v:1232.11-1232.74"
   wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count
-  attribute \src "ls180.v:1183.6-1183.49"
+  attribute \src "ls180.v:1228.6-1228.49"
   wire \main_sdphy_cmdr_cmdr_converter_source_ready
-  attribute \src "ls180.v:1182.6-1182.49"
+  attribute \src "ls180.v:1227.6-1227.49"
   wire \main_sdphy_cmdr_cmdr_converter_source_valid
-  attribute \src "ls180.v:1190.5-1190.46"
+  attribute \src "ls180.v:1235.5-1235.46"
   wire \main_sdphy_cmdr_cmdr_converter_strobe_all
-  attribute \src "ls180.v:1161.6-1161.40"
+  attribute \src "ls180.v:1206.6-1206.40"
   wire \main_sdphy_cmdr_cmdr_pads_in_first
-  attribute \src "ls180.v:1162.6-1162.39"
+  attribute \src "ls180.v:1207.6-1207.39"
   wire \main_sdphy_cmdr_cmdr_pads_in_last
-  attribute \src "ls180.v:1163.6-1163.46"
+  attribute \src "ls180.v:1208.6-1208.46"
   wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk
-  attribute \src "ls180.v:1164.6-1164.48"
+  attribute \src "ls180.v:1209.6-1209.48"
   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1165.6-1165.48"
+  attribute \src "ls180.v:1210.6-1210.48"
   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1166.6-1166.49"
+  attribute \src "ls180.v:1211.6-1211.49"
   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1167.12-1167.55"
+  attribute \src "ls180.v:1212.12-1212.55"
   wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i
-  attribute \src "ls180.v:1168.12-1168.55"
+  attribute \src "ls180.v:1213.12-1213.55"
   wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o
-  attribute \src "ls180.v:1169.6-1169.50"
+  attribute \src "ls180.v:1214.6-1214.50"
   wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe
-  attribute \src "ls180.v:1160.5-1160.39"
+  attribute \src "ls180.v:1205.5-1205.39"
   wire \main_sdphy_cmdr_cmdr_pads_in_ready
-  attribute \src "ls180.v:1159.6-1159.40"
+  attribute \src "ls180.v:1204.6-1204.40"
   wire \main_sdphy_cmdr_cmdr_pads_in_valid
-  attribute \src "ls180.v:1206.5-1206.31"
+  attribute \src "ls180.v:1251.5-1251.31"
   wire \main_sdphy_cmdr_cmdr_reset
-  attribute \src "ls180.v:1801.5-1801.59"
+  attribute \src "ls180.v:1846.5-1846.59"
   wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
-  attribute \src "ls180.v:1802.5-1802.62"
+  attribute \src "ls180.v:1847.5-1847.62"
   wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
-  attribute \src "ls180.v:1176.5-1176.29"
+  attribute \src "ls180.v:1221.5-1221.29"
   wire \main_sdphy_cmdr_cmdr_run
-  attribute \src "ls180.v:1172.6-1172.47"
+  attribute \src "ls180.v:1217.6-1217.47"
   wire \main_sdphy_cmdr_cmdr_source_source_first0
-  attribute \src "ls180.v:1193.6-1193.47"
+  attribute \src "ls180.v:1238.6-1238.47"
   wire \main_sdphy_cmdr_cmdr_source_source_first1
-  attribute \src "ls180.v:1173.6-1173.46"
+  attribute \src "ls180.v:1218.6-1218.46"
   wire \main_sdphy_cmdr_cmdr_source_source_last0
-  attribute \src "ls180.v:1194.6-1194.46"
+  attribute \src "ls180.v:1239.6-1239.46"
   wire \main_sdphy_cmdr_cmdr_source_source_last1
-  attribute \src "ls180.v:1174.12-1174.60"
+  attribute \src "ls180.v:1219.12-1219.60"
   wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0
-  attribute \src "ls180.v:1195.12-1195.60"
+  attribute \src "ls180.v:1240.12-1240.60"
   wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1
-  attribute \src "ls180.v:1171.5-1171.46"
+  attribute \src "ls180.v:1216.5-1216.46"
   wire \main_sdphy_cmdr_cmdr_source_source_ready0
-  attribute \src "ls180.v:1192.6-1192.47"
+  attribute \src "ls180.v:1237.6-1237.47"
   wire \main_sdphy_cmdr_cmdr_source_source_ready1
-  attribute \src "ls180.v:1170.6-1170.47"
+  attribute \src "ls180.v:1215.6-1215.47"
   wire \main_sdphy_cmdr_cmdr_source_source_valid0
-  attribute \src "ls180.v:1191.6-1191.47"
+  attribute \src "ls180.v:1236.6-1236.47"
   wire \main_sdphy_cmdr_cmdr_source_source_valid1
-  attribute \src "ls180.v:1175.6-1175.32"
+  attribute \src "ls180.v:1220.6-1220.32"
   wire \main_sdphy_cmdr_cmdr_start
-  attribute \src "ls180.v:1158.11-1158.32"
+  attribute \src "ls180.v:1203.11-1203.32"
   wire width 8 \main_sdphy_cmdr_count
-  attribute \src "ls180.v:1797.11-1797.60"
+  attribute \src "ls180.v:1842.11-1842.60"
   wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
-  attribute \src "ls180.v:1798.5-1798.57"
+  attribute \src "ls180.v:1843.5-1843.57"
   wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
-  attribute \src "ls180.v:1133.5-1133.42"
+  attribute \src "ls180.v:1178.5-1178.42"
   wire \main_sdphy_cmdr_pads_in_pads_in_first
-  attribute \src "ls180.v:1134.5-1134.41"
+  attribute \src "ls180.v:1179.5-1179.41"
   wire \main_sdphy_cmdr_pads_in_pads_in_last
-  attribute \src "ls180.v:1135.5-1135.48"
+  attribute \src "ls180.v:1180.5-1180.48"
   wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk
-  attribute \src "ls180.v:1136.6-1136.51"
+  attribute \src "ls180.v:1181.6-1181.51"
   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1137.5-1137.50"
+  attribute \src "ls180.v:1182.5-1182.50"
   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1138.5-1138.51"
+  attribute \src "ls180.v:1183.5-1183.51"
   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1139.12-1139.58"
+  attribute \src "ls180.v:1184.12-1184.58"
   wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
-  attribute \src "ls180.v:1140.11-1140.57"
+  attribute \src "ls180.v:1185.11-1185.57"
   wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
-  attribute \src "ls180.v:1141.5-1141.52"
+  attribute \src "ls180.v:1186.5-1186.52"
   wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
-  attribute \src "ls180.v:1132.6-1132.43"
+  attribute \src "ls180.v:1177.6-1177.43"
   wire \main_sdphy_cmdr_pads_in_pads_in_ready
-  attribute \src "ls180.v:1131.6-1131.43"
+  attribute \src "ls180.v:1176.6-1176.43"
   wire \main_sdphy_cmdr_pads_in_pads_in_valid
-  attribute \src "ls180.v:1143.5-1143.41"
+  attribute \src "ls180.v:1188.5-1188.41"
   wire \main_sdphy_cmdr_pads_out_payload_clk
-  attribute \src "ls180.v:1144.5-1144.43"
+  attribute \src "ls180.v:1189.5-1189.43"
   wire \main_sdphy_cmdr_pads_out_payload_cmd_o
-  attribute \src "ls180.v:1145.5-1145.44"
+  attribute \src "ls180.v:1190.5-1190.44"
   wire \main_sdphy_cmdr_pads_out_payload_cmd_oe
-  attribute \src "ls180.v:1146.11-1146.50"
+  attribute \src "ls180.v:1191.11-1191.50"
   wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o
-  attribute \src "ls180.v:1147.5-1147.45"
+  attribute \src "ls180.v:1192.5-1192.45"
   wire \main_sdphy_cmdr_pads_out_payload_data_oe
-  attribute \src "ls180.v:1142.6-1142.36"
+  attribute \src "ls180.v:1187.6-1187.36"
   wire \main_sdphy_cmdr_pads_out_ready
-  attribute \src "ls180.v:1150.5-1150.30"
+  attribute \src "ls180.v:1195.5-1195.30"
   wire \main_sdphy_cmdr_sink_last
-  attribute \src "ls180.v:1151.11-1151.46"
+  attribute \src "ls180.v:1196.11-1196.46"
   wire width 8 \main_sdphy_cmdr_sink_payload_length
-  attribute \src "ls180.v:1149.5-1149.31"
+  attribute \src "ls180.v:1194.5-1194.31"
   wire \main_sdphy_cmdr_sink_ready
-  attribute \src "ls180.v:1148.5-1148.31"
+  attribute \src "ls180.v:1193.5-1193.31"
   wire \main_sdphy_cmdr_sink_valid
-  attribute \src "ls180.v:1154.5-1154.32"
+  attribute \src "ls180.v:1199.5-1199.32"
   wire \main_sdphy_cmdr_source_last
-  attribute \src "ls180.v:1155.11-1155.46"
+  attribute \src "ls180.v:1200.11-1200.46"
   wire width 8 \main_sdphy_cmdr_source_payload_data
-  attribute \src "ls180.v:1156.11-1156.48"
+  attribute \src "ls180.v:1201.11-1201.48"
   wire width 3 \main_sdphy_cmdr_source_payload_status
-  attribute \src "ls180.v:1153.5-1153.33"
+  attribute \src "ls180.v:1198.5-1198.33"
   wire \main_sdphy_cmdr_source_ready
-  attribute \src "ls180.v:1152.5-1152.33"
+  attribute \src "ls180.v:1197.5-1197.33"
   wire \main_sdphy_cmdr_source_valid
-  attribute \src "ls180.v:1157.12-1157.35"
+  attribute \src "ls180.v:1202.12-1202.35"
   wire width 32 \main_sdphy_cmdr_timeout
-  attribute \src "ls180.v:1799.12-1799.63"
+  attribute \src "ls180.v:1844.12-1844.63"
   wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
-  attribute \src "ls180.v:1800.5-1800.59"
+  attribute \src "ls180.v:1845.5-1845.59"
   wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
-  attribute \src "ls180.v:1130.11-1130.32"
+  attribute \src "ls180.v:1175.11-1175.32"
   wire width 8 \main_sdphy_cmdw_count
-  attribute \src "ls180.v:1793.11-1793.59"
+  attribute \src "ls180.v:1838.11-1838.59"
   wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
-  attribute \src "ls180.v:1794.5-1794.56"
+  attribute \src "ls180.v:1839.5-1839.56"
   wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
-  attribute \src "ls180.v:1129.5-1129.25"
+  attribute \src "ls180.v:1174.5-1174.25"
   wire \main_sdphy_cmdw_done
-  attribute \src "ls180.v:1117.6-1117.43"
+  attribute \src "ls180.v:1162.6-1162.43"
   wire \main_sdphy_cmdw_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1118.12-1118.50"
+  attribute \src "ls180.v:1163.12-1163.50"
   wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i
-  attribute \src "ls180.v:1116.6-1116.35"
+  attribute \src "ls180.v:1161.6-1161.35"
   wire \main_sdphy_cmdw_pads_in_valid
-  attribute \src "ls180.v:1120.5-1120.41"
+  attribute \src "ls180.v:1165.5-1165.41"
   wire \main_sdphy_cmdw_pads_out_payload_clk
-  attribute \src "ls180.v:1121.5-1121.43"
+  attribute \src "ls180.v:1166.5-1166.43"
   wire \main_sdphy_cmdw_pads_out_payload_cmd_o
-  attribute \src "ls180.v:1122.5-1122.44"
+  attribute \src "ls180.v:1167.5-1167.44"
   wire \main_sdphy_cmdw_pads_out_payload_cmd_oe
-  attribute \src "ls180.v:1123.11-1123.50"
+  attribute \src "ls180.v:1168.11-1168.50"
   wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o
-  attribute \src "ls180.v:1124.5-1124.45"
+  attribute \src "ls180.v:1169.5-1169.45"
   wire \main_sdphy_cmdw_pads_out_payload_data_oe
-  attribute \src "ls180.v:1119.6-1119.36"
+  attribute \src "ls180.v:1164.6-1164.36"
   wire \main_sdphy_cmdw_pads_out_ready
-  attribute \src "ls180.v:1127.5-1127.30"
+  attribute \src "ls180.v:1172.5-1172.30"
   wire \main_sdphy_cmdw_sink_last
-  attribute \src "ls180.v:1128.11-1128.44"
+  attribute \src "ls180.v:1173.11-1173.44"
   wire width 8 \main_sdphy_cmdw_sink_payload_data
-  attribute \src "ls180.v:1126.5-1126.31"
+  attribute \src "ls180.v:1171.5-1171.31"
   wire \main_sdphy_cmdw_sink_ready
-  attribute \src "ls180.v:1125.5-1125.31"
+  attribute \src "ls180.v:1170.5-1170.31"
   wire \main_sdphy_cmdw_sink_valid
-  attribute \src "ls180.v:1314.11-1314.33"
+  attribute \src "ls180.v:1359.11-1359.33"
   wire width 10 \main_sdphy_datar_count
-  attribute \src "ls180.v:1813.11-1813.62"
+  attribute \src "ls180.v:1858.11-1858.62"
   wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
-  attribute \src "ls180.v:1814.5-1814.59"
+  attribute \src "ls180.v:1859.5-1859.59"
   wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
-  attribute \src "ls180.v:1354.6-1354.43"
+  attribute \src "ls180.v:1399.6-1399.43"
   wire \main_sdphy_datar_datar_buf_sink_first
-  attribute \src "ls180.v:1355.6-1355.42"
+  attribute \src "ls180.v:1400.6-1400.42"
   wire \main_sdphy_datar_datar_buf_sink_last
-  attribute \src "ls180.v:1356.12-1356.56"
+  attribute \src "ls180.v:1401.12-1401.56"
   wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data
-  attribute \src "ls180.v:1353.6-1353.43"
+  attribute \src "ls180.v:1398.6-1398.43"
   wire \main_sdphy_datar_datar_buf_sink_ready
-  attribute \src "ls180.v:1352.6-1352.43"
+  attribute \src "ls180.v:1397.6-1397.43"
   wire \main_sdphy_datar_datar_buf_sink_valid
-  attribute \src "ls180.v:1359.5-1359.44"
+  attribute \src "ls180.v:1404.5-1404.44"
   wire \main_sdphy_datar_datar_buf_source_first
-  attribute \src "ls180.v:1360.5-1360.43"
+  attribute \src "ls180.v:1405.5-1405.43"
   wire \main_sdphy_datar_datar_buf_source_last
-  attribute \src "ls180.v:1361.11-1361.57"
+  attribute \src "ls180.v:1406.11-1406.57"
   wire width 8 \main_sdphy_datar_datar_buf_source_payload_data
-  attribute \src "ls180.v:1358.6-1358.45"
+  attribute \src "ls180.v:1403.6-1403.45"
   wire \main_sdphy_datar_datar_buf_source_ready
-  attribute \src "ls180.v:1357.5-1357.44"
+  attribute \src "ls180.v:1402.5-1402.44"
   wire \main_sdphy_datar_datar_buf_source_valid
-  attribute \src "ls180.v:1344.5-1344.43"
+  attribute \src "ls180.v:1389.5-1389.43"
   wire \main_sdphy_datar_datar_converter_demux
-  attribute \src "ls180.v:1345.6-1345.48"
+  attribute \src "ls180.v:1390.6-1390.48"
   wire \main_sdphy_datar_datar_converter_load_part
-  attribute \src "ls180.v:1335.5-1335.48"
+  attribute \src "ls180.v:1380.5-1380.48"
   wire \main_sdphy_datar_datar_converter_sink_first
-  attribute \src "ls180.v:1336.5-1336.47"
+  attribute \src "ls180.v:1381.5-1381.47"
   wire \main_sdphy_datar_datar_converter_sink_last
-  attribute \src "ls180.v:1337.12-1337.62"
+  attribute \src "ls180.v:1382.12-1382.62"
   wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data
-  attribute \src "ls180.v:1334.6-1334.49"
+  attribute \src "ls180.v:1379.6-1379.49"
   wire \main_sdphy_datar_datar_converter_sink_ready
-  attribute \src "ls180.v:1333.6-1333.49"
+  attribute \src "ls180.v:1378.6-1378.49"
   wire \main_sdphy_datar_datar_converter_sink_valid
-  attribute \src "ls180.v:1340.5-1340.50"
+  attribute \src "ls180.v:1385.5-1385.50"
   wire \main_sdphy_datar_datar_converter_source_first
-  attribute \src "ls180.v:1341.5-1341.49"
+  attribute \src "ls180.v:1386.5-1386.49"
   wire \main_sdphy_datar_datar_converter_source_last
-  attribute \src "ls180.v:1342.11-1342.63"
+  attribute \src "ls180.v:1387.11-1387.63"
   wire width 8 \main_sdphy_datar_datar_converter_source_payload_data
-  attribute \src "ls180.v:1343.11-1343.76"
+  attribute \src "ls180.v:1388.11-1388.76"
   wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count
-  attribute \src "ls180.v:1339.6-1339.51"
+  attribute \src "ls180.v:1384.6-1384.51"
   wire \main_sdphy_datar_datar_converter_source_ready
-  attribute \src "ls180.v:1338.6-1338.51"
+  attribute \src "ls180.v:1383.6-1383.51"
   wire \main_sdphy_datar_datar_converter_source_valid
-  attribute \src "ls180.v:1346.5-1346.48"
+  attribute \src "ls180.v:1391.5-1391.48"
   wire \main_sdphy_datar_datar_converter_strobe_all
-  attribute \src "ls180.v:1317.6-1317.42"
+  attribute \src "ls180.v:1362.6-1362.42"
   wire \main_sdphy_datar_datar_pads_in_first
-  attribute \src "ls180.v:1318.6-1318.41"
+  attribute \src "ls180.v:1363.6-1363.41"
   wire \main_sdphy_datar_datar_pads_in_last
-  attribute \src "ls180.v:1319.6-1319.48"
+  attribute \src "ls180.v:1364.6-1364.48"
   wire \main_sdphy_datar_datar_pads_in_payload_clk
-  attribute \src "ls180.v:1320.6-1320.50"
+  attribute \src "ls180.v:1365.6-1365.50"
   wire \main_sdphy_datar_datar_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1321.6-1321.50"
+  attribute \src "ls180.v:1366.6-1366.50"
   wire \main_sdphy_datar_datar_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1322.6-1322.51"
+  attribute \src "ls180.v:1367.6-1367.51"
   wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1323.12-1323.57"
+  attribute \src "ls180.v:1368.12-1368.57"
   wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i
-  attribute \src "ls180.v:1324.12-1324.57"
+  attribute \src "ls180.v:1369.12-1369.57"
   wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o
-  attribute \src "ls180.v:1325.6-1325.52"
+  attribute \src "ls180.v:1370.6-1370.52"
   wire \main_sdphy_datar_datar_pads_in_payload_data_oe
-  attribute \src "ls180.v:1316.5-1316.41"
+  attribute \src "ls180.v:1361.5-1361.41"
   wire \main_sdphy_datar_datar_pads_in_ready
-  attribute \src "ls180.v:1315.6-1315.42"
+  attribute \src "ls180.v:1360.6-1360.42"
   wire \main_sdphy_datar_datar_pads_in_valid
-  attribute \src "ls180.v:1362.5-1362.33"
+  attribute \src "ls180.v:1407.5-1407.33"
   wire \main_sdphy_datar_datar_reset
-  attribute \src "ls180.v:1817.5-1817.62"
+  attribute \src "ls180.v:1862.5-1862.62"
   wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
-  attribute \src "ls180.v:1818.5-1818.65"
+  attribute \src "ls180.v:1863.5-1863.65"
   wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
-  attribute \src "ls180.v:1332.5-1332.31"
+  attribute \src "ls180.v:1377.5-1377.31"
   wire \main_sdphy_datar_datar_run
-  attribute \src "ls180.v:1328.6-1328.49"
+  attribute \src "ls180.v:1373.6-1373.49"
   wire \main_sdphy_datar_datar_source_source_first0
-  attribute \src "ls180.v:1349.6-1349.49"
+  attribute \src "ls180.v:1394.6-1394.49"
   wire \main_sdphy_datar_datar_source_source_first1
-  attribute \src "ls180.v:1329.6-1329.48"
+  attribute \src "ls180.v:1374.6-1374.48"
   wire \main_sdphy_datar_datar_source_source_last0
-  attribute \src "ls180.v:1350.6-1350.48"
+  attribute \src "ls180.v:1395.6-1395.48"
   wire \main_sdphy_datar_datar_source_source_last1
-  attribute \src "ls180.v:1330.12-1330.62"
+  attribute \src "ls180.v:1375.12-1375.62"
   wire width 8 \main_sdphy_datar_datar_source_source_payload_data0
-  attribute \src "ls180.v:1351.12-1351.62"
+  attribute \src "ls180.v:1396.12-1396.62"
   wire width 8 \main_sdphy_datar_datar_source_source_payload_data1
-  attribute \src "ls180.v:1327.5-1327.48"
+  attribute \src "ls180.v:1372.5-1372.48"
   wire \main_sdphy_datar_datar_source_source_ready0
-  attribute \src "ls180.v:1348.6-1348.49"
+  attribute \src "ls180.v:1393.6-1393.49"
   wire \main_sdphy_datar_datar_source_source_ready1
-  attribute \src "ls180.v:1326.6-1326.49"
+  attribute \src "ls180.v:1371.6-1371.49"
   wire \main_sdphy_datar_datar_source_source_valid0
-  attribute \src "ls180.v:1347.6-1347.49"
+  attribute \src "ls180.v:1392.6-1392.49"
   wire \main_sdphy_datar_datar_source_source_valid1
-  attribute \src "ls180.v:1331.6-1331.34"
+  attribute \src "ls180.v:1376.6-1376.34"
   wire \main_sdphy_datar_datar_start
-  attribute \src "ls180.v:1287.5-1287.43"
+  attribute \src "ls180.v:1332.5-1332.43"
   wire \main_sdphy_datar_pads_in_pads_in_first
-  attribute \src "ls180.v:1288.5-1288.42"
+  attribute \src "ls180.v:1333.5-1333.42"
   wire \main_sdphy_datar_pads_in_pads_in_last
-  attribute \src "ls180.v:1289.5-1289.49"
+  attribute \src "ls180.v:1334.5-1334.49"
   wire \main_sdphy_datar_pads_in_pads_in_payload_clk
-  attribute \src "ls180.v:1290.6-1290.52"
+  attribute \src "ls180.v:1335.6-1335.52"
   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1291.5-1291.51"
+  attribute \src "ls180.v:1336.5-1336.51"
   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1292.5-1292.52"
+  attribute \src "ls180.v:1337.5-1337.52"
   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1293.12-1293.59"
+  attribute \src "ls180.v:1338.12-1338.59"
   wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i
-  attribute \src "ls180.v:1294.11-1294.58"
+  attribute \src "ls180.v:1339.11-1339.58"
   wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o
-  attribute \src "ls180.v:1295.5-1295.53"
+  attribute \src "ls180.v:1340.5-1340.53"
   wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe
-  attribute \src "ls180.v:1286.6-1286.44"
+  attribute \src "ls180.v:1331.6-1331.44"
   wire \main_sdphy_datar_pads_in_pads_in_ready
-  attribute \src "ls180.v:1285.6-1285.44"
+  attribute \src "ls180.v:1330.6-1330.44"
   wire \main_sdphy_datar_pads_in_pads_in_valid
-  attribute \src "ls180.v:1297.5-1297.42"
+  attribute \src "ls180.v:1342.5-1342.42"
   wire \main_sdphy_datar_pads_out_payload_clk
-  attribute \src "ls180.v:1298.5-1298.44"
+  attribute \src "ls180.v:1343.5-1343.44"
   wire \main_sdphy_datar_pads_out_payload_cmd_o
-  attribute \src "ls180.v:1299.5-1299.45"
+  attribute \src "ls180.v:1344.5-1344.45"
   wire \main_sdphy_datar_pads_out_payload_cmd_oe
-  attribute \src "ls180.v:1300.11-1300.51"
+  attribute \src "ls180.v:1345.11-1345.51"
   wire width 4 \main_sdphy_datar_pads_out_payload_data_o
-  attribute \src "ls180.v:1301.5-1301.46"
+  attribute \src "ls180.v:1346.5-1346.46"
   wire \main_sdphy_datar_pads_out_payload_data_oe
-  attribute \src "ls180.v:1296.6-1296.37"
+  attribute \src "ls180.v:1341.6-1341.37"
   wire \main_sdphy_datar_pads_out_ready
-  attribute \src "ls180.v:1304.5-1304.31"
+  attribute \src "ls180.v:1349.5-1349.31"
   wire \main_sdphy_datar_sink_last
-  attribute \src "ls180.v:1305.11-1305.53"
+  attribute \src "ls180.v:1350.11-1350.53"
   wire width 10 \main_sdphy_datar_sink_payload_block_length
-  attribute \src "ls180.v:1303.5-1303.32"
+  attribute \src "ls180.v:1348.5-1348.32"
   wire \main_sdphy_datar_sink_ready
-  attribute \src "ls180.v:1302.5-1302.32"
+  attribute \src "ls180.v:1347.5-1347.32"
   wire \main_sdphy_datar_sink_valid
-  attribute \src "ls180.v:1308.5-1308.34"
+  attribute \src "ls180.v:1353.5-1353.34"
   wire \main_sdphy_datar_source_first
-  attribute \src "ls180.v:1309.5-1309.33"
+  attribute \src "ls180.v:1354.5-1354.33"
   wire \main_sdphy_datar_source_last
-  attribute \src "ls180.v:1310.11-1310.47"
+  attribute \src "ls180.v:1355.11-1355.47"
   wire width 8 \main_sdphy_datar_source_payload_data
-  attribute \src "ls180.v:1311.11-1311.49"
+  attribute \src "ls180.v:1356.11-1356.49"
   wire width 3 \main_sdphy_datar_source_payload_status
-  attribute \src "ls180.v:1307.5-1307.34"
+  attribute \src "ls180.v:1352.5-1352.34"
   wire \main_sdphy_datar_source_ready
-  attribute \src "ls180.v:1306.5-1306.34"
+  attribute \src "ls180.v:1351.5-1351.34"
   wire \main_sdphy_datar_source_valid
-  attribute \src "ls180.v:1312.5-1312.26"
+  attribute \src "ls180.v:1357.5-1357.26"
   wire \main_sdphy_datar_stop
-  attribute \src "ls180.v:1313.12-1313.36"
+  attribute \src "ls180.v:1358.12-1358.36"
   wire width 32 \main_sdphy_datar_timeout
-  attribute \src "ls180.v:1815.12-1815.65"
+  attribute \src "ls180.v:1860.12-1860.65"
   wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
-  attribute \src "ls180.v:1816.5-1816.61"
+  attribute \src "ls180.v:1861.5-1861.61"
   wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
-  attribute \src "ls180.v:1222.11-1222.33"
+  attribute \src "ls180.v:1267.11-1267.33"
   wire width 8 \main_sdphy_dataw_count
-  attribute \src "ls180.v:1809.11-1809.54"
+  attribute \src "ls180.v:1854.11-1854.54"
   wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value
-  attribute \src "ls180.v:1810.5-1810.51"
+  attribute \src "ls180.v:1855.5-1855.51"
   wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
-  attribute \src "ls180.v:1276.6-1276.42"
+  attribute \src "ls180.v:1321.6-1321.42"
   wire \main_sdphy_dataw_crcr_buf_sink_first
-  attribute \src "ls180.v:1277.6-1277.41"
+  attribute \src "ls180.v:1322.6-1322.41"
   wire \main_sdphy_dataw_crcr_buf_sink_last
-  attribute \src "ls180.v:1278.12-1278.55"
+  attribute \src "ls180.v:1323.12-1323.55"
   wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data
-  attribute \src "ls180.v:1275.6-1275.42"
+  attribute \src "ls180.v:1320.6-1320.42"
   wire \main_sdphy_dataw_crcr_buf_sink_ready
-  attribute \src "ls180.v:1274.6-1274.42"
+  attribute \src "ls180.v:1319.6-1319.42"
   wire \main_sdphy_dataw_crcr_buf_sink_valid
-  attribute \src "ls180.v:1281.5-1281.43"
+  attribute \src "ls180.v:1326.5-1326.43"
   wire \main_sdphy_dataw_crcr_buf_source_first
-  attribute \src "ls180.v:1282.5-1282.42"
+  attribute \src "ls180.v:1327.5-1327.42"
   wire \main_sdphy_dataw_crcr_buf_source_last
-  attribute \src "ls180.v:1283.11-1283.56"
+  attribute \src "ls180.v:1328.11-1328.56"
   wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data
-  attribute \src "ls180.v:1280.6-1280.44"
+  attribute \src "ls180.v:1325.6-1325.44"
   wire \main_sdphy_dataw_crcr_buf_source_ready
-  attribute \src "ls180.v:1279.5-1279.43"
+  attribute \src "ls180.v:1324.5-1324.43"
   wire \main_sdphy_dataw_crcr_buf_source_valid
-  attribute \src "ls180.v:1266.11-1266.48"
+  attribute \src "ls180.v:1311.11-1311.48"
   wire width 3 \main_sdphy_dataw_crcr_converter_demux
-  attribute \src "ls180.v:1267.6-1267.47"
+  attribute \src "ls180.v:1312.6-1312.47"
   wire \main_sdphy_dataw_crcr_converter_load_part
-  attribute \src "ls180.v:1257.5-1257.47"
+  attribute \src "ls180.v:1302.5-1302.47"
   wire \main_sdphy_dataw_crcr_converter_sink_first
-  attribute \src "ls180.v:1258.5-1258.46"
+  attribute \src "ls180.v:1303.5-1303.46"
   wire \main_sdphy_dataw_crcr_converter_sink_last
-  attribute \src "ls180.v:1259.6-1259.55"
+  attribute \src "ls180.v:1304.6-1304.55"
   wire \main_sdphy_dataw_crcr_converter_sink_payload_data
-  attribute \src "ls180.v:1256.6-1256.48"
+  attribute \src "ls180.v:1301.6-1301.48"
   wire \main_sdphy_dataw_crcr_converter_sink_ready
-  attribute \src "ls180.v:1255.6-1255.48"
+  attribute \src "ls180.v:1300.6-1300.48"
   wire \main_sdphy_dataw_crcr_converter_sink_valid
-  attribute \src "ls180.v:1262.5-1262.49"
+  attribute \src "ls180.v:1307.5-1307.49"
   wire \main_sdphy_dataw_crcr_converter_source_first
-  attribute \src "ls180.v:1263.5-1263.48"
+  attribute \src "ls180.v:1308.5-1308.48"
   wire \main_sdphy_dataw_crcr_converter_source_last
-  attribute \src "ls180.v:1264.11-1264.62"
+  attribute \src "ls180.v:1309.11-1309.62"
   wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data
-  attribute \src "ls180.v:1265.11-1265.75"
+  attribute \src "ls180.v:1310.11-1310.75"
   wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count
-  attribute \src "ls180.v:1261.6-1261.50"
+  attribute \src "ls180.v:1306.6-1306.50"
   wire \main_sdphy_dataw_crcr_converter_source_ready
-  attribute \src "ls180.v:1260.6-1260.50"
+  attribute \src "ls180.v:1305.6-1305.50"
   wire \main_sdphy_dataw_crcr_converter_source_valid
-  attribute \src "ls180.v:1268.5-1268.47"
+  attribute \src "ls180.v:1313.5-1313.47"
   wire \main_sdphy_dataw_crcr_converter_strobe_all
-  attribute \src "ls180.v:1239.6-1239.41"
+  attribute \src "ls180.v:1284.6-1284.41"
   wire \main_sdphy_dataw_crcr_pads_in_first
-  attribute \src "ls180.v:1240.6-1240.40"
+  attribute \src "ls180.v:1285.6-1285.40"
   wire \main_sdphy_dataw_crcr_pads_in_last
-  attribute \src "ls180.v:1241.6-1241.47"
+  attribute \src "ls180.v:1286.6-1286.47"
   wire \main_sdphy_dataw_crcr_pads_in_payload_clk
-  attribute \src "ls180.v:1242.6-1242.49"
+  attribute \src "ls180.v:1287.6-1287.49"
   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1243.6-1243.49"
+  attribute \src "ls180.v:1288.6-1288.49"
   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1244.6-1244.50"
+  attribute \src "ls180.v:1289.6-1289.50"
   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1245.12-1245.56"
+  attribute \src "ls180.v:1290.12-1290.56"
   wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i
-  attribute \src "ls180.v:1246.12-1246.56"
+  attribute \src "ls180.v:1291.12-1291.56"
   wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o
-  attribute \src "ls180.v:1247.6-1247.51"
+  attribute \src "ls180.v:1292.6-1292.51"
   wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe
-  attribute \src "ls180.v:1238.5-1238.40"
+  attribute \src "ls180.v:1283.5-1283.40"
   wire \main_sdphy_dataw_crcr_pads_in_ready
-  attribute \src "ls180.v:1237.6-1237.41"
+  attribute \src "ls180.v:1282.6-1282.41"
   wire \main_sdphy_dataw_crcr_pads_in_valid
-  attribute \src "ls180.v:1284.5-1284.32"
+  attribute \src "ls180.v:1329.5-1329.32"
   wire \main_sdphy_dataw_crcr_reset
-  attribute \src "ls180.v:1805.5-1805.59"
+  attribute \src "ls180.v:1850.5-1850.59"
   wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
-  attribute \src "ls180.v:1806.5-1806.62"
+  attribute \src "ls180.v:1851.5-1851.62"
   wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
-  attribute \src "ls180.v:1254.5-1254.30"
+  attribute \src "ls180.v:1299.5-1299.30"
   wire \main_sdphy_dataw_crcr_run
-  attribute \src "ls180.v:1250.6-1250.48"
+  attribute \src "ls180.v:1295.6-1295.48"
   wire \main_sdphy_dataw_crcr_source_source_first0
-  attribute \src "ls180.v:1271.6-1271.48"
+  attribute \src "ls180.v:1316.6-1316.48"
   wire \main_sdphy_dataw_crcr_source_source_first1
-  attribute \src "ls180.v:1251.6-1251.47"
+  attribute \src "ls180.v:1296.6-1296.47"
   wire \main_sdphy_dataw_crcr_source_source_last0
-  attribute \src "ls180.v:1272.6-1272.47"
+  attribute \src "ls180.v:1317.6-1317.47"
   wire \main_sdphy_dataw_crcr_source_source_last1
-  attribute \src "ls180.v:1252.12-1252.61"
+  attribute \src "ls180.v:1297.12-1297.61"
   wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0
-  attribute \src "ls180.v:1273.12-1273.61"
+  attribute \src "ls180.v:1318.12-1318.61"
   wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1
-  attribute \src "ls180.v:1249.5-1249.47"
+  attribute \src "ls180.v:1294.5-1294.47"
   wire \main_sdphy_dataw_crcr_source_source_ready0
-  attribute \src "ls180.v:1270.6-1270.48"
+  attribute \src "ls180.v:1315.6-1315.48"
   wire \main_sdphy_dataw_crcr_source_source_ready1
-  attribute \src "ls180.v:1248.6-1248.48"
+  attribute \src "ls180.v:1293.6-1293.48"
   wire \main_sdphy_dataw_crcr_source_source_valid0
-  attribute \src "ls180.v:1269.6-1269.48"
+  attribute \src "ls180.v:1314.6-1314.48"
   wire \main_sdphy_dataw_crcr_source_source_valid1
-  attribute \src "ls180.v:1253.6-1253.33"
+  attribute \src "ls180.v:1298.6-1298.33"
   wire \main_sdphy_dataw_crcr_start
-  attribute \src "ls180.v:1236.5-1236.27"
+  attribute \src "ls180.v:1281.5-1281.27"
   wire \main_sdphy_dataw_error
-  attribute \src "ls180.v:1225.5-1225.43"
+  attribute \src "ls180.v:1270.5-1270.43"
   wire \main_sdphy_dataw_pads_in_pads_in_first
-  attribute \src "ls180.v:1226.5-1226.42"
+  attribute \src "ls180.v:1271.5-1271.42"
   wire \main_sdphy_dataw_pads_in_pads_in_last
-  attribute \src "ls180.v:1227.5-1227.49"
+  attribute \src "ls180.v:1272.5-1272.49"
   wire \main_sdphy_dataw_pads_in_pads_in_payload_clk
-  attribute \src "ls180.v:1228.5-1228.51"
+  attribute \src "ls180.v:1273.5-1273.51"
   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1229.5-1229.51"
+  attribute \src "ls180.v:1274.5-1274.51"
   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o
-  attribute \src "ls180.v:1230.5-1230.52"
+  attribute \src "ls180.v:1275.5-1275.52"
   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe
-  attribute \src "ls180.v:1231.11-1231.58"
+  attribute \src "ls180.v:1276.11-1276.58"
   wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i
-  attribute \src "ls180.v:1232.11-1232.58"
+  attribute \src "ls180.v:1277.11-1277.58"
   wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o
-  attribute \src "ls180.v:1233.5-1233.53"
+  attribute \src "ls180.v:1278.5-1278.53"
   wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
-  attribute \src "ls180.v:1224.6-1224.44"
+  attribute \src "ls180.v:1269.6-1269.44"
   wire \main_sdphy_dataw_pads_in_pads_in_ready
-  attribute \src "ls180.v:1223.5-1223.43"
+  attribute \src "ls180.v:1268.5-1268.43"
   wire \main_sdphy_dataw_pads_in_pads_in_valid
-  attribute \src "ls180.v:1208.6-1208.44"
+  attribute \src "ls180.v:1253.6-1253.44"
   wire \main_sdphy_dataw_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1209.12-1209.51"
+  attribute \src "ls180.v:1254.12-1254.51"
   wire width 4 \main_sdphy_dataw_pads_in_payload_data_i
-  attribute \src "ls180.v:1207.6-1207.36"
+  attribute \src "ls180.v:1252.6-1252.36"
   wire \main_sdphy_dataw_pads_in_valid
-  attribute \src "ls180.v:1211.5-1211.42"
+  attribute \src "ls180.v:1256.5-1256.42"
   wire \main_sdphy_dataw_pads_out_payload_clk
-  attribute \src "ls180.v:1212.5-1212.44"
+  attribute \src "ls180.v:1257.5-1257.44"
   wire \main_sdphy_dataw_pads_out_payload_cmd_o
-  attribute \src "ls180.v:1213.5-1213.45"
+  attribute \src "ls180.v:1258.5-1258.45"
   wire \main_sdphy_dataw_pads_out_payload_cmd_oe
-  attribute \src "ls180.v:1214.11-1214.51"
+  attribute \src "ls180.v:1259.11-1259.51"
   wire width 4 \main_sdphy_dataw_pads_out_payload_data_o
-  attribute \src "ls180.v:1215.5-1215.46"
+  attribute \src "ls180.v:1260.5-1260.46"
   wire \main_sdphy_dataw_pads_out_payload_data_oe
-  attribute \src "ls180.v:1210.6-1210.37"
+  attribute \src "ls180.v:1255.6-1255.37"
   wire \main_sdphy_dataw_pads_out_ready
-  attribute \src "ls180.v:1218.5-1218.32"
+  attribute \src "ls180.v:1263.5-1263.32"
   wire \main_sdphy_dataw_sink_first
-  attribute \src "ls180.v:1219.5-1219.31"
+  attribute \src "ls180.v:1264.5-1264.31"
   wire \main_sdphy_dataw_sink_last
-  attribute \src "ls180.v:1220.11-1220.45"
+  attribute \src "ls180.v:1265.11-1265.45"
   wire width 8 \main_sdphy_dataw_sink_payload_data
-  attribute \src "ls180.v:1217.5-1217.32"
+  attribute \src "ls180.v:1262.5-1262.32"
   wire \main_sdphy_dataw_sink_ready
-  attribute \src "ls180.v:1216.5-1216.32"
+  attribute \src "ls180.v:1261.5-1261.32"
   wire \main_sdphy_dataw_sink_valid
-  attribute \src "ls180.v:1234.5-1234.27"
+  attribute \src "ls180.v:1279.5-1279.27"
   wire \main_sdphy_dataw_start
-  attribute \src "ls180.v:1221.5-1221.26"
+  attribute \src "ls180.v:1266.5-1266.26"
   wire \main_sdphy_dataw_stop
-  attribute \src "ls180.v:1235.5-1235.27"
+  attribute \src "ls180.v:1280.5-1280.27"
   wire \main_sdphy_dataw_valid
-  attribute \src "ls180.v:1115.11-1115.32"
+  attribute \src "ls180.v:1160.11-1160.32"
   wire width 8 \main_sdphy_init_count
-  attribute \src "ls180.v:1789.11-1789.59"
+  attribute \src "ls180.v:1834.11-1834.59"
   wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value
-  attribute \src "ls180.v:1790.5-1790.56"
+  attribute \src "ls180.v:1835.5-1835.56"
   wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
-  attribute \src "ls180.v:1103.6-1103.34"
+  attribute \src "ls180.v:1148.6-1148.34"
   wire \main_sdphy_init_initialize_r
-  attribute \src "ls180.v:1102.6-1102.35"
+  attribute \src "ls180.v:1147.6-1147.35"
   wire \main_sdphy_init_initialize_re
-  attribute \src "ls180.v:1105.5-1105.33"
+  attribute \src "ls180.v:1150.5-1150.33"
   wire \main_sdphy_init_initialize_w
-  attribute \src "ls180.v:1104.6-1104.35"
+  attribute \src "ls180.v:1149.6-1149.35"
   wire \main_sdphy_init_initialize_we
-  attribute \src "ls180.v:1107.6-1107.43"
+  attribute \src "ls180.v:1152.6-1152.43"
   wire \main_sdphy_init_pads_in_payload_cmd_i
-  attribute \src "ls180.v:1108.12-1108.50"
+  attribute \src "ls180.v:1153.12-1153.50"
   wire width 4 \main_sdphy_init_pads_in_payload_data_i
-  attribute \src "ls180.v:1106.6-1106.35"
+  attribute \src "ls180.v:1151.6-1151.35"
   wire \main_sdphy_init_pads_in_valid
-  attribute \src "ls180.v:1110.5-1110.41"
+  attribute \src "ls180.v:1155.5-1155.41"
   wire \main_sdphy_init_pads_out_payload_clk
-  attribute \src "ls180.v:1111.5-1111.43"
+  attribute \src "ls180.v:1156.5-1156.43"
   wire \main_sdphy_init_pads_out_payload_cmd_o
-  attribute \src "ls180.v:1112.5-1112.44"
+  attribute \src "ls180.v:1157.5-1157.44"
   wire \main_sdphy_init_pads_out_payload_cmd_oe
-  attribute \src "ls180.v:1113.11-1113.50"
+  attribute \src "ls180.v:1158.11-1158.50"
   wire width 4 \main_sdphy_init_pads_out_payload_data_o
-  attribute \src "ls180.v:1114.5-1114.45"
+  attribute \src "ls180.v:1159.5-1159.45"
   wire \main_sdphy_init_pads_out_payload_data_oe
-  attribute \src "ls180.v:1109.6-1109.36"
+  attribute \src "ls180.v:1154.6-1154.36"
   wire \main_sdphy_init_pads_out_ready
-  attribute \src "ls180.v:1363.6-1363.27"
+  attribute \src "ls180.v:1408.6-1408.27"
   wire \main_sdphy_sdpads_clk
-  attribute \src "ls180.v:1364.5-1364.28"
+  attribute \src "ls180.v:1409.5-1409.28"
   wire \main_sdphy_sdpads_cmd_i
-  attribute \src "ls180.v:1365.6-1365.29"
+  attribute \src "ls180.v:1410.6-1410.29"
   wire \main_sdphy_sdpads_cmd_o
-  attribute \src "ls180.v:1366.6-1366.30"
+  attribute \src "ls180.v:1411.6-1411.30"
   wire \main_sdphy_sdpads_cmd_oe
-  attribute \src "ls180.v:1367.11-1367.35"
+  attribute \src "ls180.v:1412.11-1412.35"
   wire width 4 \main_sdphy_sdpads_data_i
-  attribute \src "ls180.v:1368.12-1368.36"
+  attribute \src "ls180.v:1413.12-1413.36"
   wire width 4 \main_sdphy_sdpads_data_o
-  attribute \src "ls180.v:1369.6-1369.31"
+  attribute \src "ls180.v:1414.6-1414.31"
   wire \main_sdphy_sdpads_data_oe
-  attribute \src "ls180.v:1092.6-1092.23"
+  attribute \src "ls180.v:1137.6-1137.23"
   wire \main_sdphy_status
-  attribute \src "ls180.v:1093.6-1093.19"
+  attribute \src "ls180.v:1138.6-1138.19"
   wire \main_sdphy_we
-  attribute \src "ls180.v:327.5-327.26"
+  attribute \src "ls180.v:372.5-372.26"
   wire \main_sdram_address_re
-  attribute \src "ls180.v:326.12-326.38"
+  attribute \src "ls180.v:371.12-371.38"
   wire width 13 \main_sdram_address_storage
-  attribute \src "ls180.v:329.5-329.27"
+  attribute \src "ls180.v:374.5-374.27"
   wire \main_sdram_baddress_re
-  attribute \src "ls180.v:328.11-328.38"
+  attribute \src "ls180.v:373.11-373.38"
   wire width 2 \main_sdram_baddress_storage
-  attribute \src "ls180.v:425.5-425.43"
+  attribute \src "ls180.v:470.5-470.43"
   wire \main_sdram_bankmachine0_auto_precharge
-  attribute \src "ls180.v:447.11-447.63"
+  attribute \src "ls180.v:492.11-492.63"
   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:452.6-452.58"
+  attribute \src "ls180.v:497.6-497.58"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:457.6-457.64"
+  attribute \src "ls180.v:502.6-502.64"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:458.6-458.63"
+  attribute \src "ls180.v:503.6-503.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:456.13-456.78"
+  attribute \src "ls180.v:501.13-501.78"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:455.6-455.69"
+  attribute \src "ls180.v:500.6-500.69"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:461.6-461.65"
+  attribute \src "ls180.v:506.6-506.65"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:462.6-462.64"
+  attribute \src "ls180.v:507.6-507.64"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:460.13-460.79"
+  attribute \src "ls180.v:505.13-505.79"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:459.6-459.70"
+  attribute \src "ls180.v:504.6-504.70"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:444.11-444.61"
+  attribute \src "ls180.v:489.11-489.61"
   wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:446.11-446.63"
+  attribute \src "ls180.v:491.11-491.63"
   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:453.12-453.67"
+  attribute \src "ls180.v:498.12-498.67"
   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:454.13-454.70"
+  attribute \src "ls180.v:499.13-499.70"
   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:445.5-445.57"
+  attribute \src "ls180.v:490.5-490.57"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:428.5-428.60"
+  attribute \src "ls180.v:473.5-473.60"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:429.5-429.59"
+  attribute \src "ls180.v:474.5-474.59"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:431.13-431.75"
+  attribute \src "ls180.v:476.13-476.75"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:430.6-430.66"
+  attribute \src "ls180.v:475.6-475.66"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:427.6-427.61"
+  attribute \src "ls180.v:472.6-472.61"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:426.6-426.61"
+  attribute \src "ls180.v:471.6-471.61"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:434.6-434.63"
+  attribute \src "ls180.v:479.6-479.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:435.6-435.62"
+  attribute \src "ls180.v:480.6-480.62"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:437.13-437.77"
+  attribute \src "ls180.v:482.13-482.77"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:436.6-436.68"
+  attribute \src "ls180.v:481.6-481.68"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:433.6-433.63"
+  attribute \src "ls180.v:478.6-478.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:432.6-432.63"
+  attribute \src "ls180.v:477.6-477.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:442.13-442.71"
+  attribute \src "ls180.v:487.13-487.71"
   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
-  attribute \src "ls180.v:443.13-443.72"
+  attribute \src "ls180.v:488.13-488.72"
   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
-  attribute \src "ls180.v:440.6-440.63"
+  attribute \src "ls180.v:485.6-485.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
-  attribute \src "ls180.v:441.6-441.69"
+  attribute \src "ls180.v:486.6-486.69"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
-  attribute \src "ls180.v:438.6-438.63"
+  attribute \src "ls180.v:483.6-483.63"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
-  attribute \src "ls180.v:439.6-439.69"
+  attribute \src "ls180.v:484.6-484.69"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-  attribute \src "ls180.v:448.11-448.66"
+  attribute \src "ls180.v:493.11-493.66"
   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:449.13-449.70"
+  attribute \src "ls180.v:494.13-494.70"
   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:451.13-451.70"
+  attribute \src "ls180.v:496.13-496.70"
   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:450.6-450.60"
+  attribute \src "ls180.v:495.6-495.60"
   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:465.6-465.51"
+  attribute \src "ls180.v:510.6-510.51"
   wire \main_sdram_bankmachine0_cmd_buffer_sink_first
-  attribute \src "ls180.v:466.6-466.50"
+  attribute \src "ls180.v:511.6-511.50"
   wire \main_sdram_bankmachine0_cmd_buffer_sink_last
-  attribute \src "ls180.v:468.13-468.65"
+  attribute \src "ls180.v:513.13-513.65"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:467.6-467.56"
+  attribute \src "ls180.v:512.6-512.56"
   wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:464.6-464.51"
+  attribute \src "ls180.v:509.6-509.51"
   wire \main_sdram_bankmachine0_cmd_buffer_sink_ready
-  attribute \src "ls180.v:463.6-463.51"
+  attribute \src "ls180.v:508.6-508.51"
   wire \main_sdram_bankmachine0_cmd_buffer_sink_valid
-  attribute \src "ls180.v:471.5-471.52"
+  attribute \src "ls180.v:516.5-516.52"
   wire \main_sdram_bankmachine0_cmd_buffer_source_first
-  attribute \src "ls180.v:472.5-472.51"
+  attribute \src "ls180.v:517.5-517.51"
   wire \main_sdram_bankmachine0_cmd_buffer_source_last
-  attribute \src "ls180.v:474.12-474.66"
+  attribute \src "ls180.v:519.12-519.66"
   wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:473.5-473.57"
+  attribute \src "ls180.v:518.5-518.57"
   wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:470.6-470.53"
+  attribute \src "ls180.v:515.6-515.53"
   wire \main_sdram_bankmachine0_cmd_buffer_source_ready
-  attribute \src "ls180.v:469.5-469.52"
+  attribute \src "ls180.v:514.5-514.52"
   wire \main_sdram_bankmachine0_cmd_buffer_source_valid
-  attribute \src "ls180.v:417.12-417.49"
+  attribute \src "ls180.v:462.12-462.49"
   wire width 13 \main_sdram_bankmachine0_cmd_payload_a
-  attribute \src "ls180.v:418.12-418.50"
+  attribute \src "ls180.v:463.12-463.50"
   wire width 2 \main_sdram_bankmachine0_cmd_payload_ba
-  attribute \src "ls180.v:419.5-419.44"
+  attribute \src "ls180.v:464.5-464.44"
   wire \main_sdram_bankmachine0_cmd_payload_cas
-  attribute \src "ls180.v:422.5-422.47"
+  attribute \src "ls180.v:467.5-467.47"
   wire \main_sdram_bankmachine0_cmd_payload_is_cmd
-  attribute \src "ls180.v:423.5-423.48"
+  attribute \src "ls180.v:468.5-468.48"
   wire \main_sdram_bankmachine0_cmd_payload_is_read
-  attribute \src "ls180.v:424.5-424.49"
+  attribute \src "ls180.v:469.5-469.49"
   wire \main_sdram_bankmachine0_cmd_payload_is_write
-  attribute \src "ls180.v:420.5-420.44"
+  attribute \src "ls180.v:465.5-465.44"
   wire \main_sdram_bankmachine0_cmd_payload_ras
-  attribute \src "ls180.v:421.5-421.43"
+  attribute \src "ls180.v:466.5-466.43"
   wire \main_sdram_bankmachine0_cmd_payload_we
-  attribute \src "ls180.v:416.5-416.38"
+  attribute \src "ls180.v:461.5-461.38"
   wire \main_sdram_bankmachine0_cmd_ready
-  attribute \src "ls180.v:415.5-415.38"
+  attribute \src "ls180.v:460.5-460.38"
   wire \main_sdram_bankmachine0_cmd_valid
-  attribute \src "ls180.v:414.5-414.40"
+  attribute \src "ls180.v:459.5-459.40"
   wire \main_sdram_bankmachine0_refresh_gnt
-  attribute \src "ls180.v:413.6-413.41"
+  attribute \src "ls180.v:458.6-458.41"
   wire \main_sdram_bankmachine0_refresh_req
-  attribute \src "ls180.v:409.13-409.45"
+  attribute \src "ls180.v:454.13-454.45"
   wire width 22 \main_sdram_bankmachine0_req_addr
-  attribute \src "ls180.v:410.6-410.38"
+  attribute \src "ls180.v:455.6-455.38"
   wire \main_sdram_bankmachine0_req_lock
-  attribute \src "ls180.v:412.5-412.44"
+  attribute \src "ls180.v:457.5-457.44"
   wire \main_sdram_bankmachine0_req_rdata_valid
-  attribute \src "ls180.v:407.6-407.39"
+  attribute \src "ls180.v:452.6-452.39"
   wire \main_sdram_bankmachine0_req_ready
-  attribute \src "ls180.v:406.6-406.39"
+  attribute \src "ls180.v:451.6-451.39"
   wire \main_sdram_bankmachine0_req_valid
-  attribute \src "ls180.v:411.5-411.44"
+  attribute \src "ls180.v:456.5-456.44"
   wire \main_sdram_bankmachine0_req_wdata_ready
-  attribute \src "ls180.v:408.6-408.36"
+  attribute \src "ls180.v:453.6-453.36"
   wire \main_sdram_bankmachine0_req_we
-  attribute \src "ls180.v:475.12-475.39"
+  attribute \src "ls180.v:520.12-520.39"
   wire width 13 \main_sdram_bankmachine0_row
-  attribute \src "ls180.v:479.5-479.38"
+  attribute \src "ls180.v:524.5-524.38"
   wire \main_sdram_bankmachine0_row_close
-  attribute \src "ls180.v:480.5-480.47"
+  attribute \src "ls180.v:525.5-525.47"
   wire \main_sdram_bankmachine0_row_col_n_addr_sel
-  attribute \src "ls180.v:477.6-477.37"
+  attribute \src "ls180.v:522.6-522.37"
   wire \main_sdram_bankmachine0_row_hit
-  attribute \src "ls180.v:478.5-478.37"
+  attribute \src "ls180.v:523.5-523.37"
   wire \main_sdram_bankmachine0_row_open
-  attribute \src "ls180.v:476.5-476.39"
+  attribute \src "ls180.v:521.5-521.39"
   wire \main_sdram_bankmachine0_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:487.32-487.69"
+  attribute \src "ls180.v:532.32-532.69"
   wire \main_sdram_bankmachine0_trascon_ready
-  attribute \src "ls180.v:486.6-486.43"
+  attribute \src "ls180.v:531.6-531.43"
   wire \main_sdram_bankmachine0_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:485.32-485.68"
+  attribute \src "ls180.v:530.32-530.68"
   wire \main_sdram_bankmachine0_trccon_ready
-  attribute \src "ls180.v:484.6-484.42"
+  attribute \src "ls180.v:529.6-529.42"
   wire \main_sdram_bankmachine0_trccon_valid
-  attribute \src "ls180.v:483.11-483.48"
+  attribute \src "ls180.v:528.11-528.48"
   wire width 3 \main_sdram_bankmachine0_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:482.32-482.69"
+  attribute \src "ls180.v:527.32-527.69"
   wire \main_sdram_bankmachine0_twtpcon_ready
-  attribute \src "ls180.v:481.6-481.43"
+  attribute \src "ls180.v:526.6-526.43"
   wire \main_sdram_bankmachine0_twtpcon_valid
-  attribute \src "ls180.v:507.5-507.43"
+  attribute \src "ls180.v:552.5-552.43"
   wire \main_sdram_bankmachine1_auto_precharge
-  attribute \src "ls180.v:529.11-529.63"
+  attribute \src "ls180.v:574.11-574.63"
   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:534.6-534.58"
+  attribute \src "ls180.v:579.6-579.58"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:539.6-539.64"
+  attribute \src "ls180.v:584.6-584.64"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:540.6-540.63"
+  attribute \src "ls180.v:585.6-585.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:538.13-538.78"
+  attribute \src "ls180.v:583.13-583.78"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:537.6-537.69"
+  attribute \src "ls180.v:582.6-582.69"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:543.6-543.65"
+  attribute \src "ls180.v:588.6-588.65"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:544.6-544.64"
+  attribute \src "ls180.v:589.6-589.64"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:542.13-542.79"
+  attribute \src "ls180.v:587.13-587.79"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:541.6-541.70"
+  attribute \src "ls180.v:586.6-586.70"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:526.11-526.61"
+  attribute \src "ls180.v:571.11-571.61"
   wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:528.11-528.63"
+  attribute \src "ls180.v:573.11-573.63"
   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:535.12-535.67"
+  attribute \src "ls180.v:580.12-580.67"
   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:536.13-536.70"
+  attribute \src "ls180.v:581.13-581.70"
   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:527.5-527.57"
+  attribute \src "ls180.v:572.5-572.57"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:510.5-510.60"
+  attribute \src "ls180.v:555.5-555.60"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:511.5-511.59"
+  attribute \src "ls180.v:556.5-556.59"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:513.13-513.75"
+  attribute \src "ls180.v:558.13-558.75"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:512.6-512.66"
+  attribute \src "ls180.v:557.6-557.66"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:509.6-509.61"
+  attribute \src "ls180.v:554.6-554.61"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:508.6-508.61"
+  attribute \src "ls180.v:553.6-553.61"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:516.6-516.63"
+  attribute \src "ls180.v:561.6-561.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:517.6-517.62"
+  attribute \src "ls180.v:562.6-562.62"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:519.13-519.77"
+  attribute \src "ls180.v:564.13-564.77"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:518.6-518.68"
+  attribute \src "ls180.v:563.6-563.68"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:515.6-515.63"
+  attribute \src "ls180.v:560.6-560.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:514.6-514.63"
+  attribute \src "ls180.v:559.6-559.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:524.13-524.71"
+  attribute \src "ls180.v:569.13-569.71"
   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
-  attribute \src "ls180.v:525.13-525.72"
+  attribute \src "ls180.v:570.13-570.72"
   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
-  attribute \src "ls180.v:522.6-522.63"
+  attribute \src "ls180.v:567.6-567.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
-  attribute \src "ls180.v:523.6-523.69"
+  attribute \src "ls180.v:568.6-568.69"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
-  attribute \src "ls180.v:520.6-520.63"
+  attribute \src "ls180.v:565.6-565.63"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
-  attribute \src "ls180.v:521.6-521.69"
+  attribute \src "ls180.v:566.6-566.69"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-  attribute \src "ls180.v:530.11-530.66"
+  attribute \src "ls180.v:575.11-575.66"
   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:531.13-531.70"
+  attribute \src "ls180.v:576.13-576.70"
   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:533.13-533.70"
+  attribute \src "ls180.v:578.13-578.70"
   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:532.6-532.60"
+  attribute \src "ls180.v:577.6-577.60"
   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:547.6-547.51"
+  attribute \src "ls180.v:592.6-592.51"
   wire \main_sdram_bankmachine1_cmd_buffer_sink_first
-  attribute \src "ls180.v:548.6-548.50"
+  attribute \src "ls180.v:593.6-593.50"
   wire \main_sdram_bankmachine1_cmd_buffer_sink_last
-  attribute \src "ls180.v:550.13-550.65"
+  attribute \src "ls180.v:595.13-595.65"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:549.6-549.56"
+  attribute \src "ls180.v:594.6-594.56"
   wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:546.6-546.51"
+  attribute \src "ls180.v:591.6-591.51"
   wire \main_sdram_bankmachine1_cmd_buffer_sink_ready
-  attribute \src "ls180.v:545.6-545.51"
+  attribute \src "ls180.v:590.6-590.51"
   wire \main_sdram_bankmachine1_cmd_buffer_sink_valid
-  attribute \src "ls180.v:553.5-553.52"
+  attribute \src "ls180.v:598.5-598.52"
   wire \main_sdram_bankmachine1_cmd_buffer_source_first
-  attribute \src "ls180.v:554.5-554.51"
+  attribute \src "ls180.v:599.5-599.51"
   wire \main_sdram_bankmachine1_cmd_buffer_source_last
-  attribute \src "ls180.v:556.12-556.66"
+  attribute \src "ls180.v:601.12-601.66"
   wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:555.5-555.57"
+  attribute \src "ls180.v:600.5-600.57"
   wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:552.6-552.53"
+  attribute \src "ls180.v:597.6-597.53"
   wire \main_sdram_bankmachine1_cmd_buffer_source_ready
-  attribute \src "ls180.v:551.5-551.52"
+  attribute \src "ls180.v:596.5-596.52"
   wire \main_sdram_bankmachine1_cmd_buffer_source_valid
-  attribute \src "ls180.v:499.12-499.49"
+  attribute \src "ls180.v:544.12-544.49"
   wire width 13 \main_sdram_bankmachine1_cmd_payload_a
-  attribute \src "ls180.v:500.12-500.50"
+  attribute \src "ls180.v:545.12-545.50"
   wire width 2 \main_sdram_bankmachine1_cmd_payload_ba
-  attribute \src "ls180.v:501.5-501.44"
+  attribute \src "ls180.v:546.5-546.44"
   wire \main_sdram_bankmachine1_cmd_payload_cas
-  attribute \src "ls180.v:504.5-504.47"
+  attribute \src "ls180.v:549.5-549.47"
   wire \main_sdram_bankmachine1_cmd_payload_is_cmd
-  attribute \src "ls180.v:505.5-505.48"
+  attribute \src "ls180.v:550.5-550.48"
   wire \main_sdram_bankmachine1_cmd_payload_is_read
-  attribute \src "ls180.v:506.5-506.49"
+  attribute \src "ls180.v:551.5-551.49"
   wire \main_sdram_bankmachine1_cmd_payload_is_write
-  attribute \src "ls180.v:502.5-502.44"
+  attribute \src "ls180.v:547.5-547.44"
   wire \main_sdram_bankmachine1_cmd_payload_ras
-  attribute \src "ls180.v:503.5-503.43"
+  attribute \src "ls180.v:548.5-548.43"
   wire \main_sdram_bankmachine1_cmd_payload_we
-  attribute \src "ls180.v:498.5-498.38"
+  attribute \src "ls180.v:543.5-543.38"
   wire \main_sdram_bankmachine1_cmd_ready
-  attribute \src "ls180.v:497.5-497.38"
+  attribute \src "ls180.v:542.5-542.38"
   wire \main_sdram_bankmachine1_cmd_valid
-  attribute \src "ls180.v:496.5-496.40"
+  attribute \src "ls180.v:541.5-541.40"
   wire \main_sdram_bankmachine1_refresh_gnt
-  attribute \src "ls180.v:495.6-495.41"
+  attribute \src "ls180.v:540.6-540.41"
   wire \main_sdram_bankmachine1_refresh_req
-  attribute \src "ls180.v:491.13-491.45"
+  attribute \src "ls180.v:536.13-536.45"
   wire width 22 \main_sdram_bankmachine1_req_addr
-  attribute \src "ls180.v:492.6-492.38"
+  attribute \src "ls180.v:537.6-537.38"
   wire \main_sdram_bankmachine1_req_lock
-  attribute \src "ls180.v:494.5-494.44"
+  attribute \src "ls180.v:539.5-539.44"
   wire \main_sdram_bankmachine1_req_rdata_valid
-  attribute \src "ls180.v:489.6-489.39"
+  attribute \src "ls180.v:534.6-534.39"
   wire \main_sdram_bankmachine1_req_ready
-  attribute \src "ls180.v:488.6-488.39"
+  attribute \src "ls180.v:533.6-533.39"
   wire \main_sdram_bankmachine1_req_valid
-  attribute \src "ls180.v:493.5-493.44"
+  attribute \src "ls180.v:538.5-538.44"
   wire \main_sdram_bankmachine1_req_wdata_ready
-  attribute \src "ls180.v:490.6-490.36"
+  attribute \src "ls180.v:535.6-535.36"
   wire \main_sdram_bankmachine1_req_we
-  attribute \src "ls180.v:557.12-557.39"
+  attribute \src "ls180.v:602.12-602.39"
   wire width 13 \main_sdram_bankmachine1_row
-  attribute \src "ls180.v:561.5-561.38"
+  attribute \src "ls180.v:606.5-606.38"
   wire \main_sdram_bankmachine1_row_close
-  attribute \src "ls180.v:562.5-562.47"
+  attribute \src "ls180.v:607.5-607.47"
   wire \main_sdram_bankmachine1_row_col_n_addr_sel
-  attribute \src "ls180.v:559.6-559.37"
+  attribute \src "ls180.v:604.6-604.37"
   wire \main_sdram_bankmachine1_row_hit
-  attribute \src "ls180.v:560.5-560.37"
+  attribute \src "ls180.v:605.5-605.37"
   wire \main_sdram_bankmachine1_row_open
-  attribute \src "ls180.v:558.5-558.39"
+  attribute \src "ls180.v:603.5-603.39"
   wire \main_sdram_bankmachine1_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:569.32-569.69"
+  attribute \src "ls180.v:614.32-614.69"
   wire \main_sdram_bankmachine1_trascon_ready
-  attribute \src "ls180.v:568.6-568.43"
+  attribute \src "ls180.v:613.6-613.43"
   wire \main_sdram_bankmachine1_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:567.32-567.68"
+  attribute \src "ls180.v:612.32-612.68"
   wire \main_sdram_bankmachine1_trccon_ready
-  attribute \src "ls180.v:566.6-566.42"
+  attribute \src "ls180.v:611.6-611.42"
   wire \main_sdram_bankmachine1_trccon_valid
-  attribute \src "ls180.v:565.11-565.48"
+  attribute \src "ls180.v:610.11-610.48"
   wire width 3 \main_sdram_bankmachine1_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:564.32-564.69"
+  attribute \src "ls180.v:609.32-609.69"
   wire \main_sdram_bankmachine1_twtpcon_ready
-  attribute \src "ls180.v:563.6-563.43"
+  attribute \src "ls180.v:608.6-608.43"
   wire \main_sdram_bankmachine1_twtpcon_valid
-  attribute \src "ls180.v:589.5-589.43"
+  attribute \src "ls180.v:634.5-634.43"
   wire \main_sdram_bankmachine2_auto_precharge
-  attribute \src "ls180.v:611.11-611.63"
+  attribute \src "ls180.v:656.11-656.63"
   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:616.6-616.58"
+  attribute \src "ls180.v:661.6-661.58"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:621.6-621.64"
+  attribute \src "ls180.v:666.6-666.64"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:622.6-622.63"
+  attribute \src "ls180.v:667.6-667.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:620.13-620.78"
+  attribute \src "ls180.v:665.13-665.78"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:619.6-619.69"
+  attribute \src "ls180.v:664.6-664.69"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:625.6-625.65"
+  attribute \src "ls180.v:670.6-670.65"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:626.6-626.64"
+  attribute \src "ls180.v:671.6-671.64"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:624.13-624.79"
+  attribute \src "ls180.v:669.13-669.79"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:623.6-623.70"
+  attribute \src "ls180.v:668.6-668.70"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:608.11-608.61"
+  attribute \src "ls180.v:653.11-653.61"
   wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:610.11-610.63"
+  attribute \src "ls180.v:655.11-655.63"
   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:617.12-617.67"
+  attribute \src "ls180.v:662.12-662.67"
   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:618.13-618.70"
+  attribute \src "ls180.v:663.13-663.70"
   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:609.5-609.57"
+  attribute \src "ls180.v:654.5-654.57"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:592.5-592.60"
+  attribute \src "ls180.v:637.5-637.60"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:593.5-593.59"
+  attribute \src "ls180.v:638.5-638.59"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:595.13-595.75"
+  attribute \src "ls180.v:640.13-640.75"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:594.6-594.66"
+  attribute \src "ls180.v:639.6-639.66"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:591.6-591.61"
+  attribute \src "ls180.v:636.6-636.61"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:590.6-590.61"
+  attribute \src "ls180.v:635.6-635.61"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:598.6-598.63"
+  attribute \src "ls180.v:643.6-643.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:599.6-599.62"
+  attribute \src "ls180.v:644.6-644.62"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:601.13-601.77"
+  attribute \src "ls180.v:646.13-646.77"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:600.6-600.68"
+  attribute \src "ls180.v:645.6-645.68"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:597.6-597.63"
+  attribute \src "ls180.v:642.6-642.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:596.6-596.63"
+  attribute \src "ls180.v:641.6-641.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:606.13-606.71"
+  attribute \src "ls180.v:651.13-651.71"
   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
-  attribute \src "ls180.v:607.13-607.72"
+  attribute \src "ls180.v:652.13-652.72"
   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
-  attribute \src "ls180.v:604.6-604.63"
+  attribute \src "ls180.v:649.6-649.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
-  attribute \src "ls180.v:605.6-605.69"
+  attribute \src "ls180.v:650.6-650.69"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
-  attribute \src "ls180.v:602.6-602.63"
+  attribute \src "ls180.v:647.6-647.63"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
-  attribute \src "ls180.v:603.6-603.69"
+  attribute \src "ls180.v:648.6-648.69"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-  attribute \src "ls180.v:612.11-612.66"
+  attribute \src "ls180.v:657.11-657.66"
   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:613.13-613.70"
+  attribute \src "ls180.v:658.13-658.70"
   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:615.13-615.70"
+  attribute \src "ls180.v:660.13-660.70"
   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:614.6-614.60"
+  attribute \src "ls180.v:659.6-659.60"
   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:629.6-629.51"
+  attribute \src "ls180.v:674.6-674.51"
   wire \main_sdram_bankmachine2_cmd_buffer_sink_first
-  attribute \src "ls180.v:630.6-630.50"
+  attribute \src "ls180.v:675.6-675.50"
   wire \main_sdram_bankmachine2_cmd_buffer_sink_last
-  attribute \src "ls180.v:632.13-632.65"
+  attribute \src "ls180.v:677.13-677.65"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:631.6-631.56"
+  attribute \src "ls180.v:676.6-676.56"
   wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:628.6-628.51"
+  attribute \src "ls180.v:673.6-673.51"
   wire \main_sdram_bankmachine2_cmd_buffer_sink_ready
-  attribute \src "ls180.v:627.6-627.51"
+  attribute \src "ls180.v:672.6-672.51"
   wire \main_sdram_bankmachine2_cmd_buffer_sink_valid
-  attribute \src "ls180.v:635.5-635.52"
+  attribute \src "ls180.v:680.5-680.52"
   wire \main_sdram_bankmachine2_cmd_buffer_source_first
-  attribute \src "ls180.v:636.5-636.51"
+  attribute \src "ls180.v:681.5-681.51"
   wire \main_sdram_bankmachine2_cmd_buffer_source_last
-  attribute \src "ls180.v:638.12-638.66"
+  attribute \src "ls180.v:683.12-683.66"
   wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:637.5-637.57"
+  attribute \src "ls180.v:682.5-682.57"
   wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:634.6-634.53"
+  attribute \src "ls180.v:679.6-679.53"
   wire \main_sdram_bankmachine2_cmd_buffer_source_ready
-  attribute \src "ls180.v:633.5-633.52"
+  attribute \src "ls180.v:678.5-678.52"
   wire \main_sdram_bankmachine2_cmd_buffer_source_valid
-  attribute \src "ls180.v:581.12-581.49"
+  attribute \src "ls180.v:626.12-626.49"
   wire width 13 \main_sdram_bankmachine2_cmd_payload_a
-  attribute \src "ls180.v:582.12-582.50"
+  attribute \src "ls180.v:627.12-627.50"
   wire width 2 \main_sdram_bankmachine2_cmd_payload_ba
-  attribute \src "ls180.v:583.5-583.44"
+  attribute \src "ls180.v:628.5-628.44"
   wire \main_sdram_bankmachine2_cmd_payload_cas
-  attribute \src "ls180.v:586.5-586.47"
+  attribute \src "ls180.v:631.5-631.47"
   wire \main_sdram_bankmachine2_cmd_payload_is_cmd
-  attribute \src "ls180.v:587.5-587.48"
+  attribute \src "ls180.v:632.5-632.48"
   wire \main_sdram_bankmachine2_cmd_payload_is_read
-  attribute \src "ls180.v:588.5-588.49"
+  attribute \src "ls180.v:633.5-633.49"
   wire \main_sdram_bankmachine2_cmd_payload_is_write
-  attribute \src "ls180.v:584.5-584.44"
+  attribute \src "ls180.v:629.5-629.44"
   wire \main_sdram_bankmachine2_cmd_payload_ras
-  attribute \src "ls180.v:585.5-585.43"
+  attribute \src "ls180.v:630.5-630.43"
   wire \main_sdram_bankmachine2_cmd_payload_we
-  attribute \src "ls180.v:580.5-580.38"
+  attribute \src "ls180.v:625.5-625.38"
   wire \main_sdram_bankmachine2_cmd_ready
-  attribute \src "ls180.v:579.5-579.38"
+  attribute \src "ls180.v:624.5-624.38"
   wire \main_sdram_bankmachine2_cmd_valid
-  attribute \src "ls180.v:578.5-578.40"
+  attribute \src "ls180.v:623.5-623.40"
   wire \main_sdram_bankmachine2_refresh_gnt
-  attribute \src "ls180.v:577.6-577.41"
+  attribute \src "ls180.v:622.6-622.41"
   wire \main_sdram_bankmachine2_refresh_req
-  attribute \src "ls180.v:573.13-573.45"
+  attribute \src "ls180.v:618.13-618.45"
   wire width 22 \main_sdram_bankmachine2_req_addr
-  attribute \src "ls180.v:574.6-574.38"
+  attribute \src "ls180.v:619.6-619.38"
   wire \main_sdram_bankmachine2_req_lock
-  attribute \src "ls180.v:576.5-576.44"
+  attribute \src "ls180.v:621.5-621.44"
   wire \main_sdram_bankmachine2_req_rdata_valid
-  attribute \src "ls180.v:571.6-571.39"
+  attribute \src "ls180.v:616.6-616.39"
   wire \main_sdram_bankmachine2_req_ready
-  attribute \src "ls180.v:570.6-570.39"
+  attribute \src "ls180.v:615.6-615.39"
   wire \main_sdram_bankmachine2_req_valid
-  attribute \src "ls180.v:575.5-575.44"
+  attribute \src "ls180.v:620.5-620.44"
   wire \main_sdram_bankmachine2_req_wdata_ready
-  attribute \src "ls180.v:572.6-572.36"
+  attribute \src "ls180.v:617.6-617.36"
   wire \main_sdram_bankmachine2_req_we
-  attribute \src "ls180.v:639.12-639.39"
+  attribute \src "ls180.v:684.12-684.39"
   wire width 13 \main_sdram_bankmachine2_row
-  attribute \src "ls180.v:643.5-643.38"
+  attribute \src "ls180.v:688.5-688.38"
   wire \main_sdram_bankmachine2_row_close
-  attribute \src "ls180.v:644.5-644.47"
+  attribute \src "ls180.v:689.5-689.47"
   wire \main_sdram_bankmachine2_row_col_n_addr_sel
-  attribute \src "ls180.v:641.6-641.37"
+  attribute \src "ls180.v:686.6-686.37"
   wire \main_sdram_bankmachine2_row_hit
-  attribute \src "ls180.v:642.5-642.37"
+  attribute \src "ls180.v:687.5-687.37"
   wire \main_sdram_bankmachine2_row_open
-  attribute \src "ls180.v:640.5-640.39"
+  attribute \src "ls180.v:685.5-685.39"
   wire \main_sdram_bankmachine2_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:651.32-651.69"
+  attribute \src "ls180.v:696.32-696.69"
   wire \main_sdram_bankmachine2_trascon_ready
-  attribute \src "ls180.v:650.6-650.43"
+  attribute \src "ls180.v:695.6-695.43"
   wire \main_sdram_bankmachine2_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:649.32-649.68"
+  attribute \src "ls180.v:694.32-694.68"
   wire \main_sdram_bankmachine2_trccon_ready
-  attribute \src "ls180.v:648.6-648.42"
+  attribute \src "ls180.v:693.6-693.42"
   wire \main_sdram_bankmachine2_trccon_valid
-  attribute \src "ls180.v:647.11-647.48"
+  attribute \src "ls180.v:692.11-692.48"
   wire width 3 \main_sdram_bankmachine2_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:646.32-646.69"
+  attribute \src "ls180.v:691.32-691.69"
   wire \main_sdram_bankmachine2_twtpcon_ready
-  attribute \src "ls180.v:645.6-645.43"
+  attribute \src "ls180.v:690.6-690.43"
   wire \main_sdram_bankmachine2_twtpcon_valid
-  attribute \src "ls180.v:671.5-671.43"
+  attribute \src "ls180.v:716.5-716.43"
   wire \main_sdram_bankmachine3_auto_precharge
-  attribute \src "ls180.v:693.11-693.63"
+  attribute \src "ls180.v:738.11-738.63"
   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:698.6-698.58"
+  attribute \src "ls180.v:743.6-743.58"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:703.6-703.64"
+  attribute \src "ls180.v:748.6-748.64"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:704.6-704.63"
+  attribute \src "ls180.v:749.6-749.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:702.13-702.78"
+  attribute \src "ls180.v:747.13-747.78"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:701.6-701.69"
+  attribute \src "ls180.v:746.6-746.69"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:707.6-707.65"
+  attribute \src "ls180.v:752.6-752.65"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:708.6-708.64"
+  attribute \src "ls180.v:753.6-753.64"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:706.13-706.79"
+  attribute \src "ls180.v:751.13-751.79"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:705.6-705.70"
+  attribute \src "ls180.v:750.6-750.70"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:690.11-690.61"
+  attribute \src "ls180.v:735.11-735.61"
   wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:692.11-692.63"
+  attribute \src "ls180.v:737.11-737.63"
   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:699.12-699.67"
+  attribute \src "ls180.v:744.12-744.67"
   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:700.13-700.70"
+  attribute \src "ls180.v:745.13-745.70"
   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:691.5-691.57"
+  attribute \src "ls180.v:736.5-736.57"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:674.5-674.60"
+  attribute \src "ls180.v:719.5-719.60"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:675.5-675.59"
+  attribute \src "ls180.v:720.5-720.59"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:677.13-677.75"
+  attribute \src "ls180.v:722.13-722.75"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:676.6-676.66"
+  attribute \src "ls180.v:721.6-721.66"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:673.6-673.61"
+  attribute \src "ls180.v:718.6-718.61"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:672.6-672.61"
+  attribute \src "ls180.v:717.6-717.61"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:680.6-680.63"
+  attribute \src "ls180.v:725.6-725.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:681.6-681.62"
+  attribute \src "ls180.v:726.6-726.62"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:683.13-683.77"
+  attribute \src "ls180.v:728.13-728.77"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:682.6-682.68"
+  attribute \src "ls180.v:727.6-727.68"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:679.6-679.63"
+  attribute \src "ls180.v:724.6-724.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:678.6-678.63"
+  attribute \src "ls180.v:723.6-723.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:688.13-688.71"
+  attribute \src "ls180.v:733.13-733.71"
   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
-  attribute \src "ls180.v:689.13-689.72"
+  attribute \src "ls180.v:734.13-734.72"
   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
-  attribute \src "ls180.v:686.6-686.63"
+  attribute \src "ls180.v:731.6-731.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
-  attribute \src "ls180.v:687.6-687.69"
+  attribute \src "ls180.v:732.6-732.69"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
-  attribute \src "ls180.v:684.6-684.63"
+  attribute \src "ls180.v:729.6-729.63"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
-  attribute \src "ls180.v:685.6-685.69"
+  attribute \src "ls180.v:730.6-730.69"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-  attribute \src "ls180.v:694.11-694.66"
+  attribute \src "ls180.v:739.11-739.66"
   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:695.13-695.70"
+  attribute \src "ls180.v:740.13-740.70"
   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:697.13-697.70"
+  attribute \src "ls180.v:742.13-742.70"
   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:696.6-696.60"
+  attribute \src "ls180.v:741.6-741.60"
   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:711.6-711.51"
+  attribute \src "ls180.v:756.6-756.51"
   wire \main_sdram_bankmachine3_cmd_buffer_sink_first
-  attribute \src "ls180.v:712.6-712.50"
+  attribute \src "ls180.v:757.6-757.50"
   wire \main_sdram_bankmachine3_cmd_buffer_sink_last
-  attribute \src "ls180.v:714.13-714.65"
+  attribute \src "ls180.v:759.13-759.65"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:713.6-713.56"
+  attribute \src "ls180.v:758.6-758.56"
   wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:710.6-710.51"
+  attribute \src "ls180.v:755.6-755.51"
   wire \main_sdram_bankmachine3_cmd_buffer_sink_ready
-  attribute \src "ls180.v:709.6-709.51"
+  attribute \src "ls180.v:754.6-754.51"
   wire \main_sdram_bankmachine3_cmd_buffer_sink_valid
-  attribute \src "ls180.v:717.5-717.52"
+  attribute \src "ls180.v:762.5-762.52"
   wire \main_sdram_bankmachine3_cmd_buffer_source_first
-  attribute \src "ls180.v:718.5-718.51"
+  attribute \src "ls180.v:763.5-763.51"
   wire \main_sdram_bankmachine3_cmd_buffer_source_last
-  attribute \src "ls180.v:720.12-720.66"
+  attribute \src "ls180.v:765.12-765.66"
   wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:719.5-719.57"
+  attribute \src "ls180.v:764.5-764.57"
   wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:716.6-716.53"
+  attribute \src "ls180.v:761.6-761.53"
   wire \main_sdram_bankmachine3_cmd_buffer_source_ready
-  attribute \src "ls180.v:715.5-715.52"
+  attribute \src "ls180.v:760.5-760.52"
   wire \main_sdram_bankmachine3_cmd_buffer_source_valid
-  attribute \src "ls180.v:663.12-663.49"
+  attribute \src "ls180.v:708.12-708.49"
   wire width 13 \main_sdram_bankmachine3_cmd_payload_a
-  attribute \src "ls180.v:664.12-664.50"
+  attribute \src "ls180.v:709.12-709.50"
   wire width 2 \main_sdram_bankmachine3_cmd_payload_ba
-  attribute \src "ls180.v:665.5-665.44"
+  attribute \src "ls180.v:710.5-710.44"
   wire \main_sdram_bankmachine3_cmd_payload_cas
-  attribute \src "ls180.v:668.5-668.47"
+  attribute \src "ls180.v:713.5-713.47"
   wire \main_sdram_bankmachine3_cmd_payload_is_cmd
-  attribute \src "ls180.v:669.5-669.48"
+  attribute \src "ls180.v:714.5-714.48"
   wire \main_sdram_bankmachine3_cmd_payload_is_read
-  attribute \src "ls180.v:670.5-670.49"
+  attribute \src "ls180.v:715.5-715.49"
   wire \main_sdram_bankmachine3_cmd_payload_is_write
-  attribute \src "ls180.v:666.5-666.44"
+  attribute \src "ls180.v:711.5-711.44"
   wire \main_sdram_bankmachine3_cmd_payload_ras
-  attribute \src "ls180.v:667.5-667.43"
+  attribute \src "ls180.v:712.5-712.43"
   wire \main_sdram_bankmachine3_cmd_payload_we
-  attribute \src "ls180.v:662.5-662.38"
+  attribute \src "ls180.v:707.5-707.38"
   wire \main_sdram_bankmachine3_cmd_ready
-  attribute \src "ls180.v:661.5-661.38"
+  attribute \src "ls180.v:706.5-706.38"
   wire \main_sdram_bankmachine3_cmd_valid
-  attribute \src "ls180.v:660.5-660.40"
+  attribute \src "ls180.v:705.5-705.40"
   wire \main_sdram_bankmachine3_refresh_gnt
-  attribute \src "ls180.v:659.6-659.41"
+  attribute \src "ls180.v:704.6-704.41"
   wire \main_sdram_bankmachine3_refresh_req
-  attribute \src "ls180.v:655.13-655.45"
+  attribute \src "ls180.v:700.13-700.45"
   wire width 22 \main_sdram_bankmachine3_req_addr
-  attribute \src "ls180.v:656.6-656.38"
+  attribute \src "ls180.v:701.6-701.38"
   wire \main_sdram_bankmachine3_req_lock
-  attribute \src "ls180.v:658.5-658.44"
+  attribute \src "ls180.v:703.5-703.44"
   wire \main_sdram_bankmachine3_req_rdata_valid
-  attribute \src "ls180.v:653.6-653.39"
+  attribute \src "ls180.v:698.6-698.39"
   wire \main_sdram_bankmachine3_req_ready
-  attribute \src "ls180.v:652.6-652.39"
+  attribute \src "ls180.v:697.6-697.39"
   wire \main_sdram_bankmachine3_req_valid
-  attribute \src "ls180.v:657.5-657.44"
+  attribute \src "ls180.v:702.5-702.44"
   wire \main_sdram_bankmachine3_req_wdata_ready
-  attribute \src "ls180.v:654.6-654.36"
+  attribute \src "ls180.v:699.6-699.36"
   wire \main_sdram_bankmachine3_req_we
-  attribute \src "ls180.v:721.12-721.39"
+  attribute \src "ls180.v:766.12-766.39"
   wire width 13 \main_sdram_bankmachine3_row
-  attribute \src "ls180.v:725.5-725.38"
+  attribute \src "ls180.v:770.5-770.38"
   wire \main_sdram_bankmachine3_row_close
-  attribute \src "ls180.v:726.5-726.47"
+  attribute \src "ls180.v:771.5-771.47"
   wire \main_sdram_bankmachine3_row_col_n_addr_sel
-  attribute \src "ls180.v:723.6-723.37"
+  attribute \src "ls180.v:768.6-768.37"
   wire \main_sdram_bankmachine3_row_hit
-  attribute \src "ls180.v:724.5-724.37"
+  attribute \src "ls180.v:769.5-769.37"
   wire \main_sdram_bankmachine3_row_open
-  attribute \src "ls180.v:722.5-722.39"
+  attribute \src "ls180.v:767.5-767.39"
   wire \main_sdram_bankmachine3_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:733.32-733.69"
+  attribute \src "ls180.v:778.32-778.69"
   wire \main_sdram_bankmachine3_trascon_ready
-  attribute \src "ls180.v:732.6-732.43"
+  attribute \src "ls180.v:777.6-777.43"
   wire \main_sdram_bankmachine3_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:731.32-731.68"
+  attribute \src "ls180.v:776.32-776.68"
   wire \main_sdram_bankmachine3_trccon_ready
-  attribute \src "ls180.v:730.6-730.42"
+  attribute \src "ls180.v:775.6-775.42"
   wire \main_sdram_bankmachine3_trccon_valid
-  attribute \src "ls180.v:729.11-729.48"
+  attribute \src "ls180.v:774.11-774.48"
   wire width 3 \main_sdram_bankmachine3_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:728.32-728.69"
+  attribute \src "ls180.v:773.32-773.69"
   wire \main_sdram_bankmachine3_twtpcon_ready
-  attribute \src "ls180.v:727.6-727.43"
+  attribute \src "ls180.v:772.6-772.43"
   wire \main_sdram_bankmachine3_twtpcon_valid
-  attribute \src "ls180.v:735.6-735.28"
+  attribute \src "ls180.v:780.6-780.28"
   wire \main_sdram_cas_allowed
-  attribute \src "ls180.v:753.6-753.30"
+  attribute \src "ls180.v:798.6-798.30"
   wire \main_sdram_choose_cmd_ce
-  attribute \src "ls180.v:742.13-742.48"
+  attribute \src "ls180.v:787.13-787.48"
   wire width 13 \main_sdram_choose_cmd_cmd_payload_a
-  attribute \src "ls180.v:743.12-743.48"
+  attribute \src "ls180.v:788.12-788.48"
   wire width 2 \main_sdram_choose_cmd_cmd_payload_ba
-  attribute \src "ls180.v:744.5-744.42"
+  attribute \src "ls180.v:789.5-789.42"
   wire \main_sdram_choose_cmd_cmd_payload_cas
-  attribute \src "ls180.v:747.6-747.46"
+  attribute \src "ls180.v:792.6-792.46"
   wire \main_sdram_choose_cmd_cmd_payload_is_cmd
-  attribute \src "ls180.v:748.6-748.47"
+  attribute \src "ls180.v:793.6-793.47"
   wire \main_sdram_choose_cmd_cmd_payload_is_read
-  attribute \src "ls180.v:749.6-749.48"
+  attribute \src "ls180.v:794.6-794.48"
   wire \main_sdram_choose_cmd_cmd_payload_is_write
-  attribute \src "ls180.v:745.5-745.42"
+  attribute \src "ls180.v:790.5-790.42"
   wire \main_sdram_choose_cmd_cmd_payload_ras
-  attribute \src "ls180.v:746.5-746.41"
+  attribute \src "ls180.v:791.5-791.41"
   wire \main_sdram_choose_cmd_cmd_payload_we
-  attribute \src "ls180.v:741.5-741.36"
+  attribute \src "ls180.v:786.5-786.36"
   wire \main_sdram_choose_cmd_cmd_ready
-  attribute \src "ls180.v:740.6-740.37"
+  attribute \src "ls180.v:785.6-785.37"
   wire \main_sdram_choose_cmd_cmd_valid
-  attribute \src "ls180.v:752.11-752.38"
+  attribute \src "ls180.v:797.11-797.38"
   wire width 2 \main_sdram_choose_cmd_grant
-  attribute \src "ls180.v:751.12-751.41"
+  attribute \src "ls180.v:796.12-796.41"
   wire width 4 \main_sdram_choose_cmd_request
-  attribute \src "ls180.v:750.11-750.39"
+  attribute \src "ls180.v:795.11-795.39"
   wire width 4 \main_sdram_choose_cmd_valids
-  attribute \src "ls180.v:739.5-739.41"
+  attribute \src "ls180.v:784.5-784.41"
   wire \main_sdram_choose_cmd_want_activates
-  attribute \src "ls180.v:738.5-738.36"
+  attribute \src "ls180.v:783.5-783.36"
   wire \main_sdram_choose_cmd_want_cmds
-  attribute \src "ls180.v:736.5-736.37"
+  attribute \src "ls180.v:781.5-781.37"
   wire \main_sdram_choose_cmd_want_reads
-  attribute \src "ls180.v:737.5-737.38"
+  attribute \src "ls180.v:782.5-782.38"
   wire \main_sdram_choose_cmd_want_writes
-  attribute \src "ls180.v:771.6-771.30"
+  attribute \src "ls180.v:816.6-816.30"
   wire \main_sdram_choose_req_ce
-  attribute \src "ls180.v:760.13-760.48"
+  attribute \src "ls180.v:805.13-805.48"
   wire width 13 \main_sdram_choose_req_cmd_payload_a
-  attribute \src "ls180.v:761.12-761.48"
+  attribute \src "ls180.v:806.12-806.48"
   wire width 2 \main_sdram_choose_req_cmd_payload_ba
-  attribute \src "ls180.v:762.5-762.42"
+  attribute \src "ls180.v:807.5-807.42"
   wire \main_sdram_choose_req_cmd_payload_cas
-  attribute \src "ls180.v:765.6-765.46"
+  attribute \src "ls180.v:810.6-810.46"
   wire \main_sdram_choose_req_cmd_payload_is_cmd
-  attribute \src "ls180.v:766.6-766.47"
+  attribute \src "ls180.v:811.6-811.47"
   wire \main_sdram_choose_req_cmd_payload_is_read
-  attribute \src "ls180.v:767.6-767.48"
+  attribute \src "ls180.v:812.6-812.48"
   wire \main_sdram_choose_req_cmd_payload_is_write
-  attribute \src "ls180.v:763.5-763.42"
+  attribute \src "ls180.v:808.5-808.42"
   wire \main_sdram_choose_req_cmd_payload_ras
-  attribute \src "ls180.v:764.5-764.41"
+  attribute \src "ls180.v:809.5-809.41"
   wire \main_sdram_choose_req_cmd_payload_we
-  attribute \src "ls180.v:759.5-759.36"
+  attribute \src "ls180.v:804.5-804.36"
   wire \main_sdram_choose_req_cmd_ready
-  attribute \src "ls180.v:758.6-758.37"
+  attribute \src "ls180.v:803.6-803.37"
   wire \main_sdram_choose_req_cmd_valid
-  attribute \src "ls180.v:770.11-770.38"
+  attribute \src "ls180.v:815.11-815.38"
   wire width 2 \main_sdram_choose_req_grant
-  attribute \src "ls180.v:769.12-769.41"
+  attribute \src "ls180.v:814.12-814.41"
   wire width 4 \main_sdram_choose_req_request
-  attribute \src "ls180.v:768.11-768.39"
+  attribute \src "ls180.v:813.11-813.39"
   wire width 4 \main_sdram_choose_req_valids
-  attribute \src "ls180.v:757.5-757.41"
+  attribute \src "ls180.v:802.5-802.41"
   wire \main_sdram_choose_req_want_activates
-  attribute \src "ls180.v:756.6-756.37"
+  attribute \src "ls180.v:801.6-801.37"
   wire \main_sdram_choose_req_want_cmds
-  attribute \src "ls180.v:754.5-754.37"
+  attribute \src "ls180.v:799.5-799.37"
   wire \main_sdram_choose_req_want_reads
-  attribute \src "ls180.v:755.5-755.38"
+  attribute \src "ls180.v:800.5-800.38"
   wire \main_sdram_choose_req_want_writes
-  attribute \src "ls180.v:315.6-315.20"
+  attribute \src "ls180.v:360.6-360.20"
   wire \main_sdram_cke
-  attribute \src "ls180.v:383.5-383.24"
+  attribute \src "ls180.v:428.5-428.24"
   wire \main_sdram_cmd_last
-  attribute \src "ls180.v:384.12-384.36"
+  attribute \src "ls180.v:429.12-429.36"
   wire width 13 \main_sdram_cmd_payload_a
-  attribute \src "ls180.v:385.11-385.36"
+  attribute \src "ls180.v:430.11-430.36"
   wire width 2 \main_sdram_cmd_payload_ba
-  attribute \src "ls180.v:386.5-386.31"
+  attribute \src "ls180.v:431.5-431.31"
   wire \main_sdram_cmd_payload_cas
-  attribute \src "ls180.v:389.5-389.35"
+  attribute \src "ls180.v:434.5-434.35"
   wire \main_sdram_cmd_payload_is_read
-  attribute \src "ls180.v:390.5-390.36"
+  attribute \src "ls180.v:435.5-435.36"
   wire \main_sdram_cmd_payload_is_write
-  attribute \src "ls180.v:387.5-387.31"
+  attribute \src "ls180.v:432.5-432.31"
   wire \main_sdram_cmd_payload_ras
-  attribute \src "ls180.v:388.5-388.30"
+  attribute \src "ls180.v:433.5-433.30"
   wire \main_sdram_cmd_payload_we
-  attribute \src "ls180.v:382.5-382.25"
+  attribute \src "ls180.v:427.5-427.25"
   wire \main_sdram_cmd_ready
-  attribute \src "ls180.v:381.5-381.25"
+  attribute \src "ls180.v:426.5-426.25"
   wire \main_sdram_cmd_valid
-  attribute \src "ls180.v:323.6-323.32"
+  attribute \src "ls180.v:368.6-368.32"
   wire \main_sdram_command_issue_r
-  attribute \src "ls180.v:322.6-322.33"
+  attribute \src "ls180.v:367.6-367.33"
   wire \main_sdram_command_issue_re
-  attribute \src "ls180.v:325.5-325.31"
+  attribute \src "ls180.v:370.5-370.31"
   wire \main_sdram_command_issue_w
-  attribute \src "ls180.v:324.6-324.33"
+  attribute \src "ls180.v:369.6-369.33"
   wire \main_sdram_command_issue_we
-  attribute \src "ls180.v:321.5-321.26"
+  attribute \src "ls180.v:366.5-366.26"
   wire \main_sdram_command_re
-  attribute \src "ls180.v:320.11-320.37"
+  attribute \src "ls180.v:365.11-365.37"
   wire width 6 \main_sdram_command_storage
-  attribute \src "ls180.v:374.5-374.28"
+  attribute \src "ls180.v:419.5-419.28"
   wire \main_sdram_dfi_p0_act_n
-  attribute \src "ls180.v:365.12-365.37"
+  attribute \src "ls180.v:410.12-410.37"
   wire width 13 \main_sdram_dfi_p0_address
-  attribute \src "ls180.v:366.11-366.33"
+  attribute \src "ls180.v:411.11-411.33"
   wire width 2 \main_sdram_dfi_p0_bank
-  attribute \src "ls180.v:367.5-367.28"
+  attribute \src "ls180.v:412.5-412.28"
   wire \main_sdram_dfi_p0_cas_n
-  attribute \src "ls180.v:371.6-371.27"
+  attribute \src "ls180.v:416.6-416.27"
   wire \main_sdram_dfi_p0_cke
-  attribute \src "ls180.v:368.5-368.27"
+  attribute \src "ls180.v:413.5-413.27"
   wire \main_sdram_dfi_p0_cs_n
-  attribute \src "ls180.v:372.6-372.27"
+  attribute \src "ls180.v:417.6-417.27"
   wire \main_sdram_dfi_p0_odt
-  attribute \src "ls180.v:369.5-369.28"
+  attribute \src "ls180.v:414.5-414.28"
   wire \main_sdram_dfi_p0_ras_n
-  attribute \src "ls180.v:379.13-379.37"
+  attribute \src "ls180.v:424.13-424.37"
   wire width 16 \main_sdram_dfi_p0_rddata
-  attribute \src "ls180.v:378.5-378.32"
+  attribute \src "ls180.v:423.5-423.32"
   wire \main_sdram_dfi_p0_rddata_en
-  attribute \src "ls180.v:380.6-380.36"
+  attribute \src "ls180.v:425.6-425.36"
   wire \main_sdram_dfi_p0_rddata_valid
-  attribute \src "ls180.v:373.6-373.31"
+  attribute \src "ls180.v:418.6-418.31"
   wire \main_sdram_dfi_p0_reset_n
-  attribute \src "ls180.v:370.5-370.27"
+  attribute \src "ls180.v:415.5-415.27"
   wire \main_sdram_dfi_p0_we_n
-  attribute \src "ls180.v:375.13-375.37"
+  attribute \src "ls180.v:420.13-420.37"
   wire width 16 \main_sdram_dfi_p0_wrdata
-  attribute \src "ls180.v:376.5-376.32"
+  attribute \src "ls180.v:421.5-421.32"
   wire \main_sdram_dfi_p0_wrdata_en
-  attribute \src "ls180.v:377.12-377.41"
+  attribute \src "ls180.v:422.12-422.41"
   wire width 2 \main_sdram_dfi_p0_wrdata_mask
-  attribute \src "ls180.v:789.5-789.19"
+  attribute \src "ls180.v:834.5-834.19"
   wire \main_sdram_en0
-  attribute \src "ls180.v:792.5-792.19"
+  attribute \src "ls180.v:837.5-837.19"
   wire \main_sdram_en1
-  attribute \src "ls180.v:795.6-795.30"
+  attribute \src "ls180.v:840.6-840.30"
   wire \main_sdram_go_to_refresh
-  attribute \src "ls180.v:337.13-337.44"
+  attribute \src "ls180.v:382.13-382.44"
   wire width 22 \main_sdram_interface_bank0_addr
-  attribute \src "ls180.v:338.6-338.37"
+  attribute \src "ls180.v:383.6-383.37"
   wire \main_sdram_interface_bank0_lock
-  attribute \src "ls180.v:340.6-340.44"
+  attribute \src "ls180.v:385.6-385.44"
   wire \main_sdram_interface_bank0_rdata_valid
-  attribute \src "ls180.v:335.6-335.38"
+  attribute \src "ls180.v:380.6-380.38"
   wire \main_sdram_interface_bank0_ready
-  attribute \src "ls180.v:334.6-334.38"
+  attribute \src "ls180.v:379.6-379.38"
   wire \main_sdram_interface_bank0_valid
-  attribute \src "ls180.v:339.6-339.44"
+  attribute \src "ls180.v:384.6-384.44"
   wire \main_sdram_interface_bank0_wdata_ready
-  attribute \src "ls180.v:336.6-336.35"
+  attribute \src "ls180.v:381.6-381.35"
   wire \main_sdram_interface_bank0_we
-  attribute \src "ls180.v:344.13-344.44"
+  attribute \src "ls180.v:389.13-389.44"
   wire width 22 \main_sdram_interface_bank1_addr
-  attribute \src "ls180.v:345.6-345.37"
+  attribute \src "ls180.v:390.6-390.37"
   wire \main_sdram_interface_bank1_lock
-  attribute \src "ls180.v:347.6-347.44"
+  attribute \src "ls180.v:392.6-392.44"
   wire \main_sdram_interface_bank1_rdata_valid
-  attribute \src "ls180.v:342.6-342.38"
+  attribute \src "ls180.v:387.6-387.38"
   wire \main_sdram_interface_bank1_ready
-  attribute \src "ls180.v:341.6-341.38"
+  attribute \src "ls180.v:386.6-386.38"
   wire \main_sdram_interface_bank1_valid
-  attribute \src "ls180.v:346.6-346.44"
+  attribute \src "ls180.v:391.6-391.44"
   wire \main_sdram_interface_bank1_wdata_ready
-  attribute \src "ls180.v:343.6-343.35"
+  attribute \src "ls180.v:388.6-388.35"
   wire \main_sdram_interface_bank1_we
-  attribute \src "ls180.v:351.13-351.44"
+  attribute \src "ls180.v:396.13-396.44"
   wire width 22 \main_sdram_interface_bank2_addr
-  attribute \src "ls180.v:352.6-352.37"
+  attribute \src "ls180.v:397.6-397.37"
   wire \main_sdram_interface_bank2_lock
-  attribute \src "ls180.v:354.6-354.44"
+  attribute \src "ls180.v:399.6-399.44"
   wire \main_sdram_interface_bank2_rdata_valid
-  attribute \src "ls180.v:349.6-349.38"
+  attribute \src "ls180.v:394.6-394.38"
   wire \main_sdram_interface_bank2_ready
-  attribute \src "ls180.v:348.6-348.38"
+  attribute \src "ls180.v:393.6-393.38"
   wire \main_sdram_interface_bank2_valid
-  attribute \src "ls180.v:353.6-353.44"
+  attribute \src "ls180.v:398.6-398.44"
   wire \main_sdram_interface_bank2_wdata_ready
-  attribute \src "ls180.v:350.6-350.35"
+  attribute \src "ls180.v:395.6-395.35"
   wire \main_sdram_interface_bank2_we
-  attribute \src "ls180.v:358.13-358.44"
+  attribute \src "ls180.v:403.13-403.44"
   wire width 22 \main_sdram_interface_bank3_addr
-  attribute \src "ls180.v:359.6-359.37"
+  attribute \src "ls180.v:404.6-404.37"
   wire \main_sdram_interface_bank3_lock
-  attribute \src "ls180.v:361.6-361.44"
+  attribute \src "ls180.v:406.6-406.44"
   wire \main_sdram_interface_bank3_rdata_valid
-  attribute \src "ls180.v:356.6-356.38"
+  attribute \src "ls180.v:401.6-401.38"
   wire \main_sdram_interface_bank3_ready
-  attribute \src "ls180.v:355.6-355.38"
+  attribute \src "ls180.v:400.6-400.38"
   wire \main_sdram_interface_bank3_valid
-  attribute \src "ls180.v:360.6-360.44"
+  attribute \src "ls180.v:405.6-405.44"
   wire \main_sdram_interface_bank3_wdata_ready
-  attribute \src "ls180.v:357.6-357.35"
+  attribute \src "ls180.v:402.6-402.35"
   wire \main_sdram_interface_bank3_we
-  attribute \src "ls180.v:364.13-364.39"
+  attribute \src "ls180.v:409.13-409.39"
   wire width 16 \main_sdram_interface_rdata
-  attribute \src "ls180.v:362.12-362.38"
+  attribute \src "ls180.v:407.12-407.38"
   wire width 16 \main_sdram_interface_wdata
-  attribute \src "ls180.v:363.11-363.40"
+  attribute \src "ls180.v:408.11-408.40"
   wire width 2 \main_sdram_interface_wdata_we
-  attribute \src "ls180.v:275.5-275.29"
+  attribute \src "ls180.v:320.5-320.29"
   wire \main_sdram_inti_p0_act_n
-  attribute \src "ls180.v:266.13-266.39"
+  attribute \src "ls180.v:311.13-311.39"
   wire width 13 \main_sdram_inti_p0_address
-  attribute \src "ls180.v:267.12-267.35"
+  attribute \src "ls180.v:312.12-312.35"
   wire width 2 \main_sdram_inti_p0_bank
-  attribute \src "ls180.v:268.5-268.29"
+  attribute \src "ls180.v:313.5-313.29"
   wire \main_sdram_inti_p0_cas_n
-  attribute \src "ls180.v:272.6-272.28"
+  attribute \src "ls180.v:317.6-317.28"
   wire \main_sdram_inti_p0_cke
-  attribute \src "ls180.v:269.5-269.28"
+  attribute \src "ls180.v:314.5-314.28"
   wire \main_sdram_inti_p0_cs_n
-  attribute \src "ls180.v:273.6-273.28"
+  attribute \src "ls180.v:318.6-318.28"
   wire \main_sdram_inti_p0_odt
-  attribute \src "ls180.v:270.5-270.29"
+  attribute \src "ls180.v:315.5-315.29"
   wire \main_sdram_inti_p0_ras_n
-  attribute \src "ls180.v:280.12-280.37"
+  attribute \src "ls180.v:325.12-325.37"
   wire width 16 \main_sdram_inti_p0_rddata
-  attribute \src "ls180.v:279.6-279.34"
+  attribute \src "ls180.v:324.6-324.34"
   wire \main_sdram_inti_p0_rddata_en
-  attribute \src "ls180.v:281.5-281.36"
+  attribute \src "ls180.v:326.5-326.36"
   wire \main_sdram_inti_p0_rddata_valid
-  attribute \src "ls180.v:274.6-274.32"
+  attribute \src "ls180.v:319.6-319.32"
   wire \main_sdram_inti_p0_reset_n
-  attribute \src "ls180.v:271.5-271.28"
+  attribute \src "ls180.v:316.5-316.28"
   wire \main_sdram_inti_p0_we_n
-  attribute \src "ls180.v:276.13-276.38"
+  attribute \src "ls180.v:321.13-321.38"
   wire width 16 \main_sdram_inti_p0_wrdata
-  attribute \src "ls180.v:277.6-277.34"
+  attribute \src "ls180.v:322.6-322.34"
   wire \main_sdram_inti_p0_wrdata_en
-  attribute \src "ls180.v:278.12-278.42"
+  attribute \src "ls180.v:323.12-323.42"
   wire width 2 \main_sdram_inti_p0_wrdata_mask
-  attribute \src "ls180.v:307.5-307.31"
+  attribute \src "ls180.v:352.5-352.31"
   wire \main_sdram_master_p0_act_n
-  attribute \src "ls180.v:298.12-298.40"
+  attribute \src "ls180.v:343.12-343.40"
   wire width 13 \main_sdram_master_p0_address
-  attribute \src "ls180.v:299.11-299.36"
+  attribute \src "ls180.v:344.11-344.36"
   wire width 2 \main_sdram_master_p0_bank
-  attribute \src "ls180.v:300.5-300.31"
+  attribute \src "ls180.v:345.5-345.31"
   wire \main_sdram_master_p0_cas_n
-  attribute \src "ls180.v:304.5-304.29"
+  attribute \src "ls180.v:349.5-349.29"
   wire \main_sdram_master_p0_cke
-  attribute \src "ls180.v:301.5-301.30"
+  attribute \src "ls180.v:346.5-346.30"
   wire \main_sdram_master_p0_cs_n
-  attribute \src "ls180.v:305.5-305.29"
+  attribute \src "ls180.v:350.5-350.29"
   wire \main_sdram_master_p0_odt
-  attribute \src "ls180.v:302.5-302.31"
+  attribute \src "ls180.v:347.5-347.31"
   wire \main_sdram_master_p0_ras_n
-  attribute \src "ls180.v:312.13-312.40"
+  attribute \src "ls180.v:357.13-357.40"
   wire width 16 \main_sdram_master_p0_rddata
-  attribute \src "ls180.v:311.5-311.35"
+  attribute \src "ls180.v:356.5-356.35"
   wire \main_sdram_master_p0_rddata_en
-  attribute \src "ls180.v:313.6-313.39"
+  attribute \src "ls180.v:358.6-358.39"
   wire \main_sdram_master_p0_rddata_valid
-  attribute \src "ls180.v:306.5-306.33"
+  attribute \src "ls180.v:351.5-351.33"
   wire \main_sdram_master_p0_reset_n
-  attribute \src "ls180.v:303.5-303.30"
+  attribute \src "ls180.v:348.5-348.30"
   wire \main_sdram_master_p0_we_n
-  attribute \src "ls180.v:308.12-308.39"
+  attribute \src "ls180.v:353.12-353.39"
   wire width 16 \main_sdram_master_p0_wrdata
-  attribute \src "ls180.v:309.5-309.35"
+  attribute \src "ls180.v:354.5-354.35"
   wire \main_sdram_master_p0_wrdata_en
-  attribute \src "ls180.v:310.11-310.43"
+  attribute \src "ls180.v:355.11-355.43"
   wire width 2 \main_sdram_master_p0_wrdata_mask
-  attribute \src "ls180.v:790.6-790.26"
+  attribute \src "ls180.v:835.6-835.26"
   wire \main_sdram_max_time0
-  attribute \src "ls180.v:793.6-793.26"
+  attribute \src "ls180.v:838.6-838.26"
   wire \main_sdram_max_time1
-  attribute \src "ls180.v:772.12-772.28"
+  attribute \src "ls180.v:817.12-817.28"
   wire width 13 \main_sdram_nop_a
-  attribute \src "ls180.v:773.11-773.28"
+  attribute \src "ls180.v:818.11-818.28"
   wire width 2 \main_sdram_nop_ba
-  attribute \src "ls180.v:316.6-316.20"
+  attribute \src "ls180.v:361.6-361.20"
   wire \main_sdram_odt
-  attribute \src "ls180.v:399.5-399.31"
+  attribute \src "ls180.v:444.5-444.31"
   wire \main_sdram_postponer_count
-  attribute \src "ls180.v:397.6-397.32"
+  attribute \src "ls180.v:442.6-442.32"
   wire \main_sdram_postponer_req_i
-  attribute \src "ls180.v:398.5-398.31"
+  attribute \src "ls180.v:443.5-443.31"
   wire \main_sdram_postponer_req_o
-  attribute \src "ls180.v:734.6-734.28"
+  attribute \src "ls180.v:779.6-779.28"
   wire \main_sdram_ras_allowed
-  attribute \src "ls180.v:319.5-319.18"
+  attribute \src "ls180.v:364.5-364.18"
   wire \main_sdram_re
-  attribute \src "ls180.v:787.6-787.31"
+  attribute \src "ls180.v:832.6-832.31"
   wire \main_sdram_read_available
-  attribute \src "ls180.v:317.6-317.24"
+  attribute \src "ls180.v:362.6-362.24"
   wire \main_sdram_reset_n
-  attribute \src "ls180.v:314.6-314.20"
+  attribute \src "ls180.v:359.6-359.20"
   wire \main_sdram_sel
-  attribute \src "ls180.v:405.5-405.31"
+  attribute \src "ls180.v:450.5-450.31"
   wire \main_sdram_sequencer_count
-  attribute \src "ls180.v:404.11-404.39"
+  attribute \src "ls180.v:449.11-449.39"
   wire width 4 \main_sdram_sequencer_counter
-  attribute \src "ls180.v:401.6-401.32"
+  attribute \src "ls180.v:446.6-446.32"
   wire \main_sdram_sequencer_done0
-  attribute \src "ls180.v:403.5-403.31"
+  attribute \src "ls180.v:448.5-448.31"
   wire \main_sdram_sequencer_done1
-  attribute \src "ls180.v:400.5-400.32"
+  attribute \src "ls180.v:445.5-445.32"
   wire \main_sdram_sequencer_start0
-  attribute \src "ls180.v:402.6-402.33"
+  attribute \src "ls180.v:447.6-447.33"
   wire \main_sdram_sequencer_start1
-  attribute \src "ls180.v:291.6-291.31"
+  attribute \src "ls180.v:336.6-336.31"
   wire \main_sdram_slave_p0_act_n
-  attribute \src "ls180.v:282.13-282.40"
+  attribute \src "ls180.v:327.13-327.40"
   wire width 13 \main_sdram_slave_p0_address
-  attribute \src "ls180.v:283.12-283.36"
+  attribute \src "ls180.v:328.12-328.36"
   wire width 2 \main_sdram_slave_p0_bank
-  attribute \src "ls180.v:284.6-284.31"
+  attribute \src "ls180.v:329.6-329.31"
   wire \main_sdram_slave_p0_cas_n
-  attribute \src "ls180.v:288.6-288.29"
+  attribute \src "ls180.v:333.6-333.29"
   wire \main_sdram_slave_p0_cke
-  attribute \src "ls180.v:285.6-285.30"
+  attribute \src "ls180.v:330.6-330.30"
   wire \main_sdram_slave_p0_cs_n
-  attribute \src "ls180.v:289.6-289.29"
+  attribute \src "ls180.v:334.6-334.29"
   wire \main_sdram_slave_p0_odt
-  attribute \src "ls180.v:286.6-286.31"
+  attribute \src "ls180.v:331.6-331.31"
   wire \main_sdram_slave_p0_ras_n
-  attribute \src "ls180.v:296.12-296.38"
+  attribute \src "ls180.v:341.12-341.38"
   wire width 16 \main_sdram_slave_p0_rddata
-  attribute \src "ls180.v:295.6-295.35"
+  attribute \src "ls180.v:340.6-340.35"
   wire \main_sdram_slave_p0_rddata_en
-  attribute \src "ls180.v:297.5-297.37"
+  attribute \src "ls180.v:342.5-342.37"
   wire \main_sdram_slave_p0_rddata_valid
-  attribute \src "ls180.v:290.6-290.33"
+  attribute \src "ls180.v:335.6-335.33"
   wire \main_sdram_slave_p0_reset_n
-  attribute \src "ls180.v:287.6-287.30"
+  attribute \src "ls180.v:332.6-332.30"
   wire \main_sdram_slave_p0_we_n
-  attribute \src "ls180.v:292.13-292.39"
+  attribute \src "ls180.v:337.13-337.39"
   wire width 16 \main_sdram_slave_p0_wrdata
-  attribute \src "ls180.v:293.6-293.35"
+  attribute \src "ls180.v:338.6-338.35"
   wire \main_sdram_slave_p0_wrdata_en
-  attribute \src "ls180.v:294.12-294.43"
+  attribute \src "ls180.v:339.12-339.43"
   wire width 2 \main_sdram_slave_p0_wrdata_mask
-  attribute \src "ls180.v:332.12-332.29"
+  attribute \src "ls180.v:377.12-377.29"
   wire width 16 \main_sdram_status
-  attribute \src "ls180.v:775.5-775.24"
+  attribute \src "ls180.v:820.5-820.24"
   wire \main_sdram_steerer0
-  attribute \src "ls180.v:776.5-776.24"
+  attribute \src "ls180.v:821.5-821.24"
   wire \main_sdram_steerer1
-  attribute \src "ls180.v:774.11-774.33"
+  attribute \src "ls180.v:819.11-819.33"
   wire width 2 \main_sdram_steerer_sel
-  attribute \src "ls180.v:318.11-318.29"
+  attribute \src "ls180.v:363.11-363.29"
   wire width 4 \main_sdram_storage
-  attribute \src "ls180.v:783.5-783.29"
+  attribute \src "ls180.v:828.5-828.29"
   wire \main_sdram_tccdcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:782.32-782.56"
+  attribute \src "ls180.v:827.32-827.56"
   wire \main_sdram_tccdcon_ready
-  attribute \src "ls180.v:781.6-781.30"
+  attribute \src "ls180.v:826.6-826.30"
   wire \main_sdram_tccdcon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:780.32-780.56"
+  attribute \src "ls180.v:825.32-825.56"
   wire \main_sdram_tfawcon_ready
-  attribute \src "ls180.v:779.6-779.30"
+  attribute \src "ls180.v:824.6-824.30"
   wire \main_sdram_tfawcon_valid
-  attribute \src "ls180.v:791.11-791.27"
+  attribute \src "ls180.v:836.11-836.27"
   wire width 5 \main_sdram_time0
-  attribute \src "ls180.v:794.11-794.27"
+  attribute \src "ls180.v:839.11-839.27"
   wire width 4 \main_sdram_time1
-  attribute \src "ls180.v:394.12-394.35"
+  attribute \src "ls180.v:439.12-439.35"
   wire width 10 \main_sdram_timer_count0
-  attribute \src "ls180.v:396.11-396.34"
+  attribute \src "ls180.v:441.11-441.34"
   wire width 10 \main_sdram_timer_count1
-  attribute \src "ls180.v:393.6-393.28"
+  attribute \src "ls180.v:438.6-438.28"
   wire \main_sdram_timer_done0
-  attribute \src "ls180.v:395.6-395.28"
+  attribute \src "ls180.v:440.6-440.28"
   wire \main_sdram_timer_done1
-  attribute \src "ls180.v:392.6-392.27"
+  attribute \src "ls180.v:437.6-437.27"
   wire \main_sdram_timer_wait
   attribute \no_retiming "true"
-  attribute \src "ls180.v:778.32-778.56"
+  attribute \src "ls180.v:823.32-823.56"
   wire \main_sdram_trrdcon_ready
-  attribute \src "ls180.v:777.6-777.30"
+  attribute \src "ls180.v:822.6-822.30"
   wire \main_sdram_trrdcon_valid
-  attribute \src "ls180.v:786.11-786.35"
+  attribute \src "ls180.v:831.11-831.35"
   wire width 3 \main_sdram_twtrcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:785.32-785.56"
+  attribute \src "ls180.v:830.32-830.56"
   wire \main_sdram_twtrcon_ready
-  attribute \src "ls180.v:784.6-784.30"
+  attribute \src "ls180.v:829.6-829.30"
   wire \main_sdram_twtrcon_valid
-  attribute \src "ls180.v:391.6-391.30"
+  attribute \src "ls180.v:436.6-436.30"
   wire \main_sdram_wants_refresh
-  attribute \src "ls180.v:333.6-333.19"
+  attribute \src "ls180.v:378.6-378.19"
   wire \main_sdram_we
-  attribute \src "ls180.v:331.5-331.25"
+  attribute \src "ls180.v:376.5-376.25"
   wire \main_sdram_wrdata_re
-  attribute \src "ls180.v:330.12-330.37"
+  attribute \src "ls180.v:375.12-375.37"
   wire width 16 \main_sdram_wrdata_storage
-  attribute \src "ls180.v:788.6-788.32"
+  attribute \src "ls180.v:833.6-833.32"
   wire \main_sdram_write_available
-  attribute \src "ls180.v:988.6-988.27"
+  attribute \src "ls180.v:1033.6-1033.27"
   wire \main_spimaster0_start
-  attribute \src "ls180.v:998.12-998.35"
+  attribute \src "ls180.v:1043.12-1043.35"
   wire width 8 \main_spimaster10_length
-  attribute \src "ls180.v:999.12-999.36"
+  attribute \src "ls180.v:1044.12-1044.36"
   wire width 16 \main_spimaster11_storage
-  attribute \src "ls180.v:1000.5-1000.24"
+  attribute \src "ls180.v:1045.5-1045.24"
   wire \main_spimaster12_re
-  attribute \src "ls180.v:1001.6-1001.27"
+  attribute \src "ls180.v:1046.6-1046.27"
   wire \main_spimaster13_done
-  attribute \src "ls180.v:1002.6-1002.29"
+  attribute \src "ls180.v:1047.6-1047.29"
   wire \main_spimaster14_status
-  attribute \src "ls180.v:1003.6-1003.25"
+  attribute \src "ls180.v:1048.6-1048.25"
   wire \main_spimaster15_we
-  attribute \src "ls180.v:1004.11-1004.35"
+  attribute \src "ls180.v:1049.11-1049.35"
   wire width 8 \main_spimaster16_storage
-  attribute \src "ls180.v:1005.5-1005.24"
+  attribute \src "ls180.v:1050.5-1050.24"
   wire \main_spimaster17_re
-  attribute \src "ls180.v:1006.12-1006.35"
+  attribute \src "ls180.v:1051.12-1051.35"
   wire width 8 \main_spimaster18_status
-  attribute \src "ls180.v:1007.6-1007.25"
+  attribute \src "ls180.v:1052.6-1052.25"
   wire \main_spimaster19_we
-  attribute \src "ls180.v:989.12-989.34"
+  attribute \src "ls180.v:1034.12-1034.34"
   wire width 8 \main_spimaster1_length
-  attribute \src "ls180.v:1061.5-1061.23"
+  attribute \src "ls180.v:1106.5-1106.23"
   wire \main_spimaster1_re
-  attribute \src "ls180.v:1060.12-1060.35"
+  attribute \src "ls180.v:1105.12-1105.35"
   wire width 16 \main_spimaster1_storage
-  attribute \src "ls180.v:1008.6-1008.26"
+  attribute \src "ls180.v:1053.6-1053.26"
   wire \main_spimaster20_sel
-  attribute \src "ls180.v:1009.5-1009.29"
+  attribute \src "ls180.v:1054.5-1054.29"
   wire \main_spimaster21_storage
-  attribute \src "ls180.v:1010.5-1010.24"
+  attribute \src "ls180.v:1055.5-1055.24"
   wire \main_spimaster22_re
-  attribute \src "ls180.v:1011.5-1011.29"
+  attribute \src "ls180.v:1056.5-1056.29"
   wire \main_spimaster23_storage
-  attribute \src "ls180.v:1012.5-1012.24"
+  attribute \src "ls180.v:1057.5-1057.24"
   wire \main_spimaster24_re
-  attribute \src "ls180.v:1013.5-1013.32"
+  attribute \src "ls180.v:1058.5-1058.32"
   wire \main_spimaster25_clk_enable
-  attribute \src "ls180.v:1014.5-1014.31"
+  attribute \src "ls180.v:1059.5-1059.31"
   wire \main_spimaster26_cs_enable
-  attribute \src "ls180.v:1015.11-1015.33"
+  attribute \src "ls180.v:1060.11-1060.33"
   wire width 3 \main_spimaster27_count
-  attribute \src "ls180.v:1781.11-1781.55"
+  attribute \src "ls180.v:1826.11-1826.55"
   wire width 3 \main_spimaster27_count_spimaster0_next_value
-  attribute \src "ls180.v:1782.5-1782.52"
+  attribute \src "ls180.v:1827.5-1827.52"
   wire \main_spimaster27_count_spimaster0_next_value_ce
-  attribute \src "ls180.v:1016.5-1016.32"
+  attribute \src "ls180.v:1061.5-1061.32"
   wire \main_spimaster28_mosi_latch
-  attribute \src "ls180.v:1017.5-1017.32"
+  attribute \src "ls180.v:1062.5-1062.32"
   wire \main_spimaster29_miso_latch
-  attribute \src "ls180.v:990.5-990.25"
+  attribute \src "ls180.v:1035.5-1035.25"
   wire \main_spimaster2_done
-  attribute \src "ls180.v:1018.12-1018.40"
+  attribute \src "ls180.v:1063.12-1063.40"
   wire width 16 \main_spimaster30_clk_divider
-  attribute \src "ls180.v:1019.6-1019.31"
+  attribute \src "ls180.v:1064.6-1064.31"
   wire \main_spimaster31_clk_rise
-  attribute \src "ls180.v:1020.6-1020.31"
+  attribute \src "ls180.v:1065.6-1065.31"
   wire \main_spimaster32_clk_fall
-  attribute \src "ls180.v:1021.11-1021.37"
+  attribute \src "ls180.v:1066.11-1066.37"
   wire width 8 \main_spimaster33_mosi_data
-  attribute \src "ls180.v:1022.11-1022.36"
+  attribute \src "ls180.v:1067.11-1067.36"
   wire width 3 \main_spimaster34_mosi_sel
-  attribute \src "ls180.v:1023.11-1023.37"
+  attribute \src "ls180.v:1068.11-1068.37"
   wire width 8 \main_spimaster35_miso_data
-  attribute \src "ls180.v:991.5-991.24"
+  attribute \src "ls180.v:1036.5-1036.24"
   wire \main_spimaster3_irq
-  attribute \src "ls180.v:992.12-992.32"
+  attribute \src "ls180.v:1037.12-1037.32"
   wire width 8 \main_spimaster4_mosi
-  attribute \src "ls180.v:993.11-993.31"
+  attribute \src "ls180.v:1038.11-1038.31"
   wire width 8 \main_spimaster5_miso
-  attribute \src "ls180.v:994.6-994.24"
+  attribute \src "ls180.v:1039.6-1039.24"
   wire \main_spimaster6_cs
-  attribute \src "ls180.v:995.6-995.30"
+  attribute \src "ls180.v:1040.6-1040.30"
   wire \main_spimaster7_loopback
-  attribute \src "ls180.v:996.12-996.39"
+  attribute \src "ls180.v:1041.12-1041.39"
   wire width 16 \main_spimaster8_clk_divider
-  attribute \src "ls180.v:997.5-997.26"
+  attribute \src "ls180.v:1042.5-1042.26"
   wire \main_spimaster9_start
-  attribute \src "ls180.v:1032.13-1032.40"
+  attribute \src "ls180.v:1077.13-1077.40"
   wire width 16 \main_spisdcard_clk_divider0
-  attribute \src "ls180.v:1054.12-1054.39"
+  attribute \src "ls180.v:1099.12-1099.39"
   wire width 16 \main_spisdcard_clk_divider1
-  attribute \src "ls180.v:1049.5-1049.30"
+  attribute \src "ls180.v:1094.5-1094.30"
   wire \main_spisdcard_clk_enable
-  attribute \src "ls180.v:1056.6-1056.29"
+  attribute \src "ls180.v:1101.6-1101.29"
   wire \main_spisdcard_clk_fall
-  attribute \src "ls180.v:1055.6-1055.29"
+  attribute \src "ls180.v:1100.6-1100.29"
   wire \main_spisdcard_clk_rise
-  attribute \src "ls180.v:1036.5-1036.30"
+  attribute \src "ls180.v:1081.5-1081.30"
   wire \main_spisdcard_control_re
-  attribute \src "ls180.v:1035.12-1035.42"
+  attribute \src "ls180.v:1080.12-1080.42"
   wire width 16 \main_spisdcard_control_storage
-  attribute \src "ls180.v:1051.11-1051.31"
+  attribute \src "ls180.v:1096.11-1096.31"
   wire width 3 \main_spisdcard_count
-  attribute \src "ls180.v:1785.11-1785.53"
+  attribute \src "ls180.v:1830.11-1830.53"
   wire width 3 \main_spisdcard_count_spimaster1_next_value
-  attribute \src "ls180.v:1786.5-1786.50"
+  attribute \src "ls180.v:1831.5-1831.50"
   wire \main_spisdcard_count_spimaster1_next_value_ce
-  attribute \src "ls180.v:1030.6-1030.23"
+  attribute \src "ls180.v:1075.6-1075.23"
   wire \main_spisdcard_cs
-  attribute \src "ls180.v:1050.5-1050.29"
+  attribute \src "ls180.v:1095.5-1095.29"
   wire \main_spisdcard_cs_enable
-  attribute \src "ls180.v:1046.5-1046.25"
+  attribute \src "ls180.v:1091.5-1091.25"
   wire \main_spisdcard_cs_re
-  attribute \src "ls180.v:1045.5-1045.30"
+  attribute \src "ls180.v:1090.5-1090.30"
   wire \main_spisdcard_cs_storage
-  attribute \src "ls180.v:1026.5-1026.25"
+  attribute \src "ls180.v:1071.5-1071.25"
   wire \main_spisdcard_done0
-  attribute \src "ls180.v:1037.6-1037.26"
+  attribute \src "ls180.v:1082.6-1082.26"
   wire \main_spisdcard_done1
-  attribute \src "ls180.v:1027.5-1027.23"
+  attribute \src "ls180.v:1072.5-1072.23"
   wire \main_spisdcard_irq
-  attribute \src "ls180.v:1025.12-1025.34"
+  attribute \src "ls180.v:1070.12-1070.34"
   wire width 8 \main_spisdcard_length0
-  attribute \src "ls180.v:1034.12-1034.34"
+  attribute \src "ls180.v:1079.12-1079.34"
   wire width 8 \main_spisdcard_length1
-  attribute \src "ls180.v:1031.6-1031.29"
+  attribute \src "ls180.v:1076.6-1076.29"
   wire \main_spisdcard_loopback
-  attribute \src "ls180.v:1048.5-1048.31"
+  attribute \src "ls180.v:1093.5-1093.31"
   wire \main_spisdcard_loopback_re
-  attribute \src "ls180.v:1047.5-1047.36"
+  attribute \src "ls180.v:1092.5-1092.36"
   wire \main_spisdcard_loopback_storage
-  attribute \src "ls180.v:1029.11-1029.30"
+  attribute \src "ls180.v:1074.11-1074.30"
   wire width 8 \main_spisdcard_miso
-  attribute \src "ls180.v:1059.11-1059.35"
+  attribute \src "ls180.v:1104.11-1104.35"
   wire width 8 \main_spisdcard_miso_data
-  attribute \src "ls180.v:1053.5-1053.30"
+  attribute \src "ls180.v:1098.5-1098.30"
   wire \main_spisdcard_miso_latch
-  attribute \src "ls180.v:1042.12-1042.38"
+  attribute \src "ls180.v:1087.12-1087.38"
   wire width 8 \main_spisdcard_miso_status
-  attribute \src "ls180.v:1043.6-1043.28"
+  attribute \src "ls180.v:1088.6-1088.28"
   wire \main_spisdcard_miso_we
-  attribute \src "ls180.v:1028.12-1028.31"
+  attribute \src "ls180.v:1073.12-1073.31"
   wire width 8 \main_spisdcard_mosi
-  attribute \src "ls180.v:1057.11-1057.35"
+  attribute \src "ls180.v:1102.11-1102.35"
   wire width 8 \main_spisdcard_mosi_data
-  attribute \src "ls180.v:1052.5-1052.30"
+  attribute \src "ls180.v:1097.5-1097.30"
   wire \main_spisdcard_mosi_latch
-  attribute \src "ls180.v:1041.5-1041.27"
+  attribute \src "ls180.v:1086.5-1086.27"
   wire \main_spisdcard_mosi_re
-  attribute \src "ls180.v:1058.11-1058.34"
+  attribute \src "ls180.v:1103.11-1103.34"
   wire width 3 \main_spisdcard_mosi_sel
-  attribute \src "ls180.v:1040.11-1040.38"
+  attribute \src "ls180.v:1085.11-1085.38"
   wire width 8 \main_spisdcard_mosi_storage
-  attribute \src "ls180.v:1044.6-1044.24"
+  attribute \src "ls180.v:1089.6-1089.24"
   wire \main_spisdcard_sel
-  attribute \src "ls180.v:1024.6-1024.27"
+  attribute \src "ls180.v:1069.6-1069.27"
   wire \main_spisdcard_start0
-  attribute \src "ls180.v:1033.5-1033.26"
+  attribute \src "ls180.v:1078.5-1078.26"
   wire \main_spisdcard_start1
-  attribute \src "ls180.v:1038.6-1038.34"
+  attribute \src "ls180.v:1083.6-1083.34"
   wire \main_spisdcard_status_status
-  attribute \src "ls180.v:1039.6-1039.30"
+  attribute \src "ls180.v:1084.6-1084.30"
   wire \main_spisdcard_status_we
-  attribute \src "ls180.v:885.12-885.44"
+  attribute \src "ls180.v:256.12-256.26"
+  wire width 7 \main_sram0_adr
+  attribute \src "ls180.v:257.13-257.29"
+  wire width 32 \main_sram0_dat_r
+  attribute \src "ls180.v:259.13-259.29"
+  wire width 32 \main_sram0_dat_w
+  attribute \src "ls180.v:258.11-258.24"
+  wire width 4 \main_sram0_we
+  attribute \src "ls180.v:271.12-271.26"
+  wire width 7 \main_sram1_adr
+  attribute \src "ls180.v:272.13-272.29"
+  wire width 32 \main_sram1_dat_r
+  attribute \src "ls180.v:274.13-274.29"
+  wire width 32 \main_sram1_dat_w
+  attribute \src "ls180.v:273.11-273.24"
+  wire width 4 \main_sram1_we
+  attribute \src "ls180.v:286.12-286.26"
+  wire width 7 \main_sram2_adr
+  attribute \src "ls180.v:287.13-287.29"
+  wire width 32 \main_sram2_dat_r
+  attribute \src "ls180.v:289.13-289.29"
+  wire width 32 \main_sram2_dat_w
+  attribute \src "ls180.v:288.11-288.24"
+  wire width 4 \main_sram2_we
+  attribute \src "ls180.v:930.12-930.44"
   wire width 2 \main_uart_eventmanager_pending_r
-  attribute \src "ls180.v:884.6-884.39"
+  attribute \src "ls180.v:929.6-929.39"
   wire \main_uart_eventmanager_pending_re
-  attribute \src "ls180.v:887.11-887.43"
+  attribute \src "ls180.v:932.11-932.43"
   wire width 2 \main_uart_eventmanager_pending_w
-  attribute \src "ls180.v:886.6-886.39"
+  attribute \src "ls180.v:931.6-931.39"
   wire \main_uart_eventmanager_pending_we
-  attribute \src "ls180.v:889.5-889.30"
+  attribute \src "ls180.v:934.5-934.30"
   wire \main_uart_eventmanager_re
-  attribute \src "ls180.v:881.12-881.43"
+  attribute \src "ls180.v:926.12-926.43"
   wire width 2 \main_uart_eventmanager_status_r
-  attribute \src "ls180.v:880.6-880.38"
+  attribute \src "ls180.v:925.6-925.38"
   wire \main_uart_eventmanager_status_re
-  attribute \src "ls180.v:883.11-883.42"
+  attribute \src "ls180.v:928.11-928.42"
   wire width 2 \main_uart_eventmanager_status_w
-  attribute \src "ls180.v:882.6-882.38"
+  attribute \src "ls180.v:927.6-927.38"
   wire \main_uart_eventmanager_status_we
-  attribute \src "ls180.v:888.11-888.41"
+  attribute \src "ls180.v:933.11-933.41"
   wire width 2 \main_uart_eventmanager_storage
-  attribute \src "ls180.v:869.6-869.19"
+  attribute \src "ls180.v:914.6-914.19"
   wire \main_uart_irq
-  attribute \src "ls180.v:855.12-855.46"
+  attribute \src "ls180.v:900.12-900.46"
   wire width 32 \main_uart_phy_phase_accumulator_rx
-  attribute \src "ls180.v:845.12-845.46"
+  attribute \src "ls180.v:890.12-890.46"
   wire width 32 \main_uart_phy_phase_accumulator_tx
-  attribute \src "ls180.v:838.5-838.21"
+  attribute \src "ls180.v:883.5-883.21"
   wire \main_uart_phy_re
-  attribute \src "ls180.v:856.6-856.22"
+  attribute \src "ls180.v:901.6-901.22"
   wire \main_uart_phy_rx
-  attribute \src "ls180.v:859.11-859.36"
+  attribute \src "ls180.v:904.11-904.36"
   wire width 4 \main_uart_phy_rx_bitcount
-  attribute \src "ls180.v:860.5-860.26"
+  attribute \src "ls180.v:905.5-905.26"
   wire \main_uart_phy_rx_busy
-  attribute \src "ls180.v:857.5-857.23"
+  attribute \src "ls180.v:902.5-902.23"
   wire \main_uart_phy_rx_r
-  attribute \src "ls180.v:858.11-858.31"
+  attribute \src "ls180.v:903.11-903.31"
   wire width 8 \main_uart_phy_rx_reg
-  attribute \src "ls180.v:841.6-841.30"
+  attribute \src "ls180.v:886.6-886.30"
   wire \main_uart_phy_sink_first
-  attribute \src "ls180.v:842.6-842.29"
+  attribute \src "ls180.v:887.6-887.29"
   wire \main_uart_phy_sink_last
-  attribute \src "ls180.v:843.12-843.43"
+  attribute \src "ls180.v:888.12-888.43"
   wire width 8 \main_uart_phy_sink_payload_data
-  attribute \src "ls180.v:840.5-840.29"
+  attribute \src "ls180.v:885.5-885.29"
   wire \main_uart_phy_sink_ready
-  attribute \src "ls180.v:839.6-839.30"
+  attribute \src "ls180.v:884.6-884.30"
   wire \main_uart_phy_sink_valid
-  attribute \src "ls180.v:851.5-851.31"
+  attribute \src "ls180.v:896.5-896.31"
   wire \main_uart_phy_source_first
-  attribute \src "ls180.v:852.5-852.30"
+  attribute \src "ls180.v:897.5-897.30"
   wire \main_uart_phy_source_last
-  attribute \src "ls180.v:853.11-853.44"
+  attribute \src "ls180.v:898.11-898.44"
   wire width 8 \main_uart_phy_source_payload_data
-  attribute \src "ls180.v:850.6-850.32"
+  attribute \src "ls180.v:895.6-895.32"
   wire \main_uart_phy_source_ready
-  attribute \src "ls180.v:849.5-849.31"
+  attribute \src "ls180.v:894.5-894.31"
   wire \main_uart_phy_source_valid
-  attribute \src "ls180.v:837.12-837.33"
+  attribute \src "ls180.v:882.12-882.33"
   wire width 32 \main_uart_phy_storage
-  attribute \src "ls180.v:847.11-847.36"
+  attribute \src "ls180.v:892.11-892.36"
   wire width 4 \main_uart_phy_tx_bitcount
-  attribute \src "ls180.v:848.5-848.26"
+  attribute \src "ls180.v:893.5-893.26"
   wire \main_uart_phy_tx_busy
-  attribute \src "ls180.v:846.11-846.31"
+  attribute \src "ls180.v:891.11-891.31"
   wire width 8 \main_uart_phy_tx_reg
-  attribute \src "ls180.v:854.5-854.32"
+  attribute \src "ls180.v:899.5-899.32"
   wire \main_uart_phy_uart_clk_rxen
-  attribute \src "ls180.v:844.5-844.32"
+  attribute \src "ls180.v:889.5-889.32"
   wire \main_uart_phy_uart_clk_txen
-  attribute \src "ls180.v:978.5-978.20"
+  attribute \src "ls180.v:1023.5-1023.20"
   wire \main_uart_reset
-  attribute \src "ls180.v:878.5-878.23"
+  attribute \src "ls180.v:923.5-923.23"
   wire \main_uart_rx_clear
-  attribute \src "ls180.v:962.11-962.36"
+  attribute \src "ls180.v:1007.11-1007.36"
   wire width 4 \main_uart_rx_fifo_consume
-  attribute \src "ls180.v:967.6-967.31"
+  attribute \src "ls180.v:1012.6-1012.31"
   wire \main_uart_rx_fifo_do_read
-  attribute \src "ls180.v:973.6-973.37"
+  attribute \src "ls180.v:1018.6-1018.37"
   wire \main_uart_rx_fifo_fifo_in_first
-  attribute \src "ls180.v:974.6-974.36"
+  attribute \src "ls180.v:1019.6-1019.36"
   wire \main_uart_rx_fifo_fifo_in_last
-  attribute \src "ls180.v:972.12-972.50"
+  attribute \src "ls180.v:1017.12-1017.50"
   wire width 8 \main_uart_rx_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:976.6-976.38"
+  attribute \src "ls180.v:1021.6-1021.38"
   wire \main_uart_rx_fifo_fifo_out_first
-  attribute \src "ls180.v:977.6-977.37"
+  attribute \src "ls180.v:1022.6-1022.37"
   wire \main_uart_rx_fifo_fifo_out_last
-  attribute \src "ls180.v:975.12-975.51"
+  attribute \src "ls180.v:1020.12-1020.51"
   wire width 8 \main_uart_rx_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:959.11-959.35"
+  attribute \src "ls180.v:1004.11-1004.35"
   wire width 5 \main_uart_rx_fifo_level0
-  attribute \src "ls180.v:971.12-971.36"
+  attribute \src "ls180.v:1016.12-1016.36"
   wire width 5 \main_uart_rx_fifo_level1
-  attribute \src "ls180.v:961.11-961.36"
+  attribute \src "ls180.v:1006.11-1006.36"
   wire width 4 \main_uart_rx_fifo_produce
-  attribute \src "ls180.v:968.12-968.40"
+  attribute \src "ls180.v:1013.12-1013.40"
   wire width 4 \main_uart_rx_fifo_rdport_adr
-  attribute \src "ls180.v:969.12-969.42"
+  attribute \src "ls180.v:1014.12-1014.42"
   wire width 10 \main_uart_rx_fifo_rdport_dat_r
-  attribute \src "ls180.v:970.6-970.33"
+  attribute \src "ls180.v:1015.6-1015.33"
   wire \main_uart_rx_fifo_rdport_re
-  attribute \src "ls180.v:951.6-951.26"
+  attribute \src "ls180.v:996.6-996.26"
   wire \main_uart_rx_fifo_re
-  attribute \src "ls180.v:952.5-952.31"
+  attribute \src "ls180.v:997.5-997.31"
   wire \main_uart_rx_fifo_readable
-  attribute \src "ls180.v:960.5-960.30"
+  attribute \src "ls180.v:1005.5-1005.30"
   wire \main_uart_rx_fifo_replace
-  attribute \src "ls180.v:943.6-943.34"
+  attribute \src "ls180.v:988.6-988.34"
   wire \main_uart_rx_fifo_sink_first
-  attribute \src "ls180.v:944.6-944.33"
+  attribute \src "ls180.v:989.6-989.33"
   wire \main_uart_rx_fifo_sink_last
-  attribute \src "ls180.v:945.12-945.47"
+  attribute \src "ls180.v:990.12-990.47"
   wire width 8 \main_uart_rx_fifo_sink_payload_data
-  attribute \src "ls180.v:942.6-942.34"
+  attribute \src "ls180.v:987.6-987.34"
   wire \main_uart_rx_fifo_sink_ready
-  attribute \src "ls180.v:941.6-941.34"
+  attribute \src "ls180.v:986.6-986.34"
   wire \main_uart_rx_fifo_sink_valid
-  attribute \src "ls180.v:948.6-948.36"
+  attribute \src "ls180.v:993.6-993.36"
   wire \main_uart_rx_fifo_source_first
-  attribute \src "ls180.v:949.6-949.35"
+  attribute \src "ls180.v:994.6-994.35"
   wire \main_uart_rx_fifo_source_last
-  attribute \src "ls180.v:950.12-950.49"
+  attribute \src "ls180.v:995.12-995.49"
   wire width 8 \main_uart_rx_fifo_source_payload_data
-  attribute \src "ls180.v:947.6-947.36"
+  attribute \src "ls180.v:992.6-992.36"
   wire \main_uart_rx_fifo_source_ready
-  attribute \src "ls180.v:946.6-946.36"
+  attribute \src "ls180.v:991.6-991.36"
   wire \main_uart_rx_fifo_source_valid
-  attribute \src "ls180.v:957.12-957.42"
+  attribute \src "ls180.v:1002.12-1002.42"
   wire width 10 \main_uart_rx_fifo_syncfifo_din
-  attribute \src "ls180.v:958.12-958.43"
+  attribute \src "ls180.v:1003.12-1003.43"
   wire width 10 \main_uart_rx_fifo_syncfifo_dout
-  attribute \src "ls180.v:955.6-955.35"
+  attribute \src "ls180.v:1000.6-1000.35"
   wire \main_uart_rx_fifo_syncfifo_re
-  attribute \src "ls180.v:956.6-956.41"
+  attribute \src "ls180.v:1001.6-1001.41"
   wire \main_uart_rx_fifo_syncfifo_readable
-  attribute \src "ls180.v:953.6-953.35"
+  attribute \src "ls180.v:998.6-998.35"
   wire \main_uart_rx_fifo_syncfifo_we
-  attribute \src "ls180.v:954.6-954.41"
+  attribute \src "ls180.v:999.6-999.41"
   wire \main_uart_rx_fifo_syncfifo_writable
-  attribute \src "ls180.v:963.11-963.39"
+  attribute \src "ls180.v:1008.11-1008.39"
   wire width 4 \main_uart_rx_fifo_wrport_adr
-  attribute \src "ls180.v:964.12-964.42"
+  attribute \src "ls180.v:1009.12-1009.42"
   wire width 10 \main_uart_rx_fifo_wrport_dat_r
-  attribute \src "ls180.v:966.12-966.42"
+  attribute \src "ls180.v:1011.12-1011.42"
   wire width 10 \main_uart_rx_fifo_wrport_dat_w
-  attribute \src "ls180.v:965.6-965.33"
+  attribute \src "ls180.v:1010.6-1010.33"
   wire \main_uart_rx_fifo_wrport_we
-  attribute \src "ls180.v:879.5-879.29"
+  attribute \src "ls180.v:924.5-924.29"
   wire \main_uart_rx_old_trigger
-  attribute \src "ls180.v:876.5-876.25"
+  attribute \src "ls180.v:921.5-921.25"
   wire \main_uart_rx_pending
-  attribute \src "ls180.v:875.6-875.25"
+  attribute \src "ls180.v:920.6-920.25"
   wire \main_uart_rx_status
-  attribute \src "ls180.v:877.6-877.26"
+  attribute \src "ls180.v:922.6-922.26"
   wire \main_uart_rx_trigger
-  attribute \src "ls180.v:867.6-867.30"
+  attribute \src "ls180.v:912.6-912.30"
   wire \main_uart_rxempty_status
-  attribute \src "ls180.v:868.6-868.26"
+  attribute \src "ls180.v:913.6-913.26"
   wire \main_uart_rxempty_we
-  attribute \src "ls180.v:892.6-892.29"
+  attribute \src "ls180.v:937.6-937.29"
   wire \main_uart_rxfull_status
-  attribute \src "ls180.v:893.6-893.25"
+  attribute \src "ls180.v:938.6-938.25"
   wire \main_uart_rxfull_we
-  attribute \src "ls180.v:862.12-862.28"
+  attribute \src "ls180.v:907.12-907.28"
   wire width 8 \main_uart_rxtx_r
-  attribute \src "ls180.v:861.6-861.23"
+  attribute \src "ls180.v:906.6-906.23"
   wire \main_uart_rxtx_re
-  attribute \src "ls180.v:864.12-864.28"
+  attribute \src "ls180.v:909.12-909.28"
   wire width 8 \main_uart_rxtx_w
-  attribute \src "ls180.v:863.6-863.23"
+  attribute \src "ls180.v:908.6-908.23"
   wire \main_uart_rxtx_we
-  attribute \src "ls180.v:873.5-873.23"
+  attribute \src "ls180.v:918.5-918.23"
   wire \main_uart_tx_clear
-  attribute \src "ls180.v:925.11-925.36"
+  attribute \src "ls180.v:970.11-970.36"
   wire width 4 \main_uart_tx_fifo_consume
-  attribute \src "ls180.v:930.6-930.31"
+  attribute \src "ls180.v:975.6-975.31"
   wire \main_uart_tx_fifo_do_read
-  attribute \src "ls180.v:936.6-936.37"
+  attribute \src "ls180.v:981.6-981.37"
   wire \main_uart_tx_fifo_fifo_in_first
-  attribute \src "ls180.v:937.6-937.36"
+  attribute \src "ls180.v:982.6-982.36"
   wire \main_uart_tx_fifo_fifo_in_last
-  attribute \src "ls180.v:935.12-935.50"
+  attribute \src "ls180.v:980.12-980.50"
   wire width 8 \main_uart_tx_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:939.6-939.38"
+  attribute \src "ls180.v:984.6-984.38"
   wire \main_uart_tx_fifo_fifo_out_first
-  attribute \src "ls180.v:940.6-940.37"
+  attribute \src "ls180.v:985.6-985.37"
   wire \main_uart_tx_fifo_fifo_out_last
-  attribute \src "ls180.v:938.12-938.51"
+  attribute \src "ls180.v:983.12-983.51"
   wire width 8 \main_uart_tx_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:922.11-922.35"
+  attribute \src "ls180.v:967.11-967.35"
   wire width 5 \main_uart_tx_fifo_level0
-  attribute \src "ls180.v:934.12-934.36"
+  attribute \src "ls180.v:979.12-979.36"
   wire width 5 \main_uart_tx_fifo_level1
-  attribute \src "ls180.v:924.11-924.36"
+  attribute \src "ls180.v:969.11-969.36"
   wire width 4 \main_uart_tx_fifo_produce
-  attribute \src "ls180.v:931.12-931.40"
+  attribute \src "ls180.v:976.12-976.40"
   wire width 4 \main_uart_tx_fifo_rdport_adr
-  attribute \src "ls180.v:932.12-932.42"
+  attribute \src "ls180.v:977.12-977.42"
   wire width 10 \main_uart_tx_fifo_rdport_dat_r
-  attribute \src "ls180.v:933.6-933.33"
+  attribute \src "ls180.v:978.6-978.33"
   wire \main_uart_tx_fifo_rdport_re
-  attribute \src "ls180.v:914.6-914.26"
+  attribute \src "ls180.v:959.6-959.26"
   wire \main_uart_tx_fifo_re
-  attribute \src "ls180.v:915.5-915.31"
+  attribute \src "ls180.v:960.5-960.31"
   wire \main_uart_tx_fifo_readable
-  attribute \src "ls180.v:923.5-923.30"
+  attribute \src "ls180.v:968.5-968.30"
   wire \main_uart_tx_fifo_replace
-  attribute \src "ls180.v:906.5-906.33"
+  attribute \src "ls180.v:951.5-951.33"
   wire \main_uart_tx_fifo_sink_first
-  attribute \src "ls180.v:907.5-907.32"
+  attribute \src "ls180.v:952.5-952.32"
   wire \main_uart_tx_fifo_sink_last
-  attribute \src "ls180.v:908.12-908.47"
+  attribute \src "ls180.v:953.12-953.47"
   wire width 8 \main_uart_tx_fifo_sink_payload_data
-  attribute \src "ls180.v:905.6-905.34"
+  attribute \src "ls180.v:950.6-950.34"
   wire \main_uart_tx_fifo_sink_ready
-  attribute \src "ls180.v:904.6-904.34"
+  attribute \src "ls180.v:949.6-949.34"
   wire \main_uart_tx_fifo_sink_valid
-  attribute \src "ls180.v:911.6-911.36"
+  attribute \src "ls180.v:956.6-956.36"
   wire \main_uart_tx_fifo_source_first
-  attribute \src "ls180.v:912.6-912.35"
+  attribute \src "ls180.v:957.6-957.35"
   wire \main_uart_tx_fifo_source_last
-  attribute \src "ls180.v:913.12-913.49"
+  attribute \src "ls180.v:958.12-958.49"
   wire width 8 \main_uart_tx_fifo_source_payload_data
-  attribute \src "ls180.v:910.6-910.36"
+  attribute \src "ls180.v:955.6-955.36"
   wire \main_uart_tx_fifo_source_ready
-  attribute \src "ls180.v:909.6-909.36"
+  attribute \src "ls180.v:954.6-954.36"
   wire \main_uart_tx_fifo_source_valid
-  attribute \src "ls180.v:920.12-920.42"
+  attribute \src "ls180.v:965.12-965.42"
   wire width 10 \main_uart_tx_fifo_syncfifo_din
-  attribute \src "ls180.v:921.12-921.43"
+  attribute \src "ls180.v:966.12-966.43"
   wire width 10 \main_uart_tx_fifo_syncfifo_dout
-  attribute \src "ls180.v:918.6-918.35"
+  attribute \src "ls180.v:963.6-963.35"
   wire \main_uart_tx_fifo_syncfifo_re
-  attribute \src "ls180.v:919.6-919.41"
+  attribute \src "ls180.v:964.6-964.41"
   wire \main_uart_tx_fifo_syncfifo_readable
-  attribute \src "ls180.v:916.6-916.35"
+  attribute \src "ls180.v:961.6-961.35"
   wire \main_uart_tx_fifo_syncfifo_we
-  attribute \src "ls180.v:917.6-917.41"
+  attribute \src "ls180.v:962.6-962.41"
   wire \main_uart_tx_fifo_syncfifo_writable
-  attribute \src "ls180.v:926.11-926.39"
+  attribute \src "ls180.v:971.11-971.39"
   wire width 4 \main_uart_tx_fifo_wrport_adr
-  attribute \src "ls180.v:927.12-927.42"
+  attribute \src "ls180.v:972.12-972.42"
   wire width 10 \main_uart_tx_fifo_wrport_dat_r
-  attribute \src "ls180.v:929.12-929.42"
+  attribute \src "ls180.v:974.12-974.42"
   wire width 10 \main_uart_tx_fifo_wrport_dat_w
-  attribute \src "ls180.v:928.6-928.33"
+  attribute \src "ls180.v:973.6-973.33"
   wire \main_uart_tx_fifo_wrport_we
-  attribute \src "ls180.v:874.5-874.29"
+  attribute \src "ls180.v:919.5-919.29"
   wire \main_uart_tx_old_trigger
-  attribute \src "ls180.v:871.5-871.25"
+  attribute \src "ls180.v:916.5-916.25"
   wire \main_uart_tx_pending
-  attribute \src "ls180.v:870.6-870.25"
+  attribute \src "ls180.v:915.6-915.25"
   wire \main_uart_tx_status
-  attribute \src "ls180.v:872.6-872.26"
+  attribute \src "ls180.v:917.6-917.26"
   wire \main_uart_tx_trigger
-  attribute \src "ls180.v:890.6-890.30"
+  attribute \src "ls180.v:935.6-935.30"
   wire \main_uart_txempty_status
-  attribute \src "ls180.v:891.6-891.26"
+  attribute \src "ls180.v:936.6-936.26"
   wire \main_uart_txempty_we
-  attribute \src "ls180.v:865.6-865.29"
+  attribute \src "ls180.v:910.6-910.29"
   wire \main_uart_txfull_status
-  attribute \src "ls180.v:866.6-866.25"
+  attribute \src "ls180.v:911.6-911.25"
   wire \main_uart_txfull_we
-  attribute \src "ls180.v:896.6-896.31"
+  attribute \src "ls180.v:941.6-941.31"
   wire \main_uart_uart_sink_first
-  attribute \src "ls180.v:897.6-897.30"
+  attribute \src "ls180.v:942.6-942.30"
   wire \main_uart_uart_sink_last
-  attribute \src "ls180.v:898.12-898.44"
+  attribute \src "ls180.v:943.12-943.44"
   wire width 8 \main_uart_uart_sink_payload_data
-  attribute \src "ls180.v:895.6-895.31"
+  attribute \src "ls180.v:940.6-940.31"
   wire \main_uart_uart_sink_ready
-  attribute \src "ls180.v:894.6-894.31"
+  attribute \src "ls180.v:939.6-939.31"
   wire \main_uart_uart_sink_valid
-  attribute \src "ls180.v:901.6-901.33"
+  attribute \src "ls180.v:946.6-946.33"
   wire \main_uart_uart_source_first
-  attribute \src "ls180.v:902.6-902.32"
+  attribute \src "ls180.v:947.6-947.32"
   wire \main_uart_uart_source_last
-  attribute \src "ls180.v:903.12-903.46"
+  attribute \src "ls180.v:948.12-948.46"
   wire width 8 \main_uart_uart_source_payload_data
-  attribute \src "ls180.v:900.6-900.33"
+  attribute \src "ls180.v:945.6-945.33"
   wire \main_uart_uart_source_ready
-  attribute \src "ls180.v:899.6-899.33"
+  attribute \src "ls180.v:944.6-944.33"
   wire \main_uart_uart_source_valid
-  attribute \src "ls180.v:815.5-815.22"
+  attribute \src "ls180.v:860.5-860.22"
   wire \main_wb_sdram_ack
-  attribute \src "ls180.v:809.13-809.30"
+  attribute \src "ls180.v:854.13-854.30"
   wire width 30 \main_wb_sdram_adr
-  attribute \src "ls180.v:818.12-818.29"
+  attribute \src "ls180.v:863.12-863.29"
   wire width 2 \main_wb_sdram_bte
-  attribute \src "ls180.v:817.12-817.29"
+  attribute \src "ls180.v:862.12-862.29"
   wire width 3 \main_wb_sdram_cti
-  attribute \src "ls180.v:813.6-813.23"
+  attribute \src "ls180.v:858.6-858.23"
   wire \main_wb_sdram_cyc
-  attribute \src "ls180.v:811.13-811.32"
+  attribute \src "ls180.v:856.13-856.32"
   wire width 32 \main_wb_sdram_dat_r
-  attribute \src "ls180.v:810.13-810.32"
+  attribute \src "ls180.v:855.13-855.32"
   wire width 32 \main_wb_sdram_dat_w
-  attribute \src "ls180.v:819.5-819.22"
+  attribute \src "ls180.v:864.5-864.22"
   wire \main_wb_sdram_err
-  attribute \src "ls180.v:812.12-812.29"
+  attribute \src "ls180.v:857.12-857.29"
   wire width 4 \main_wb_sdram_sel
-  attribute \src "ls180.v:814.6-814.23"
+  attribute \src "ls180.v:859.6-859.23"
   wire \main_wb_sdram_stb
-  attribute \src "ls180.v:816.6-816.22"
+  attribute \src "ls180.v:861.6-861.22"
   wire \main_wb_sdram_we
-  attribute \src "ls180.v:833.5-833.24"
+  attribute \src "ls180.v:878.5-878.24"
   wire \main_wdata_consumed
-  attribute \src "ls180.v:10042.11-10042.17"
+  attribute \src "ls180.v:10159.11-10159.17"
   wire width 7 \memadr
-  attribute \src "ls180.v:10062.12-10062.18"
+  attribute \src "ls180.v:10179.11-10179.19"
+  wire width 7 \memadr_1
+  attribute \src "ls180.v:10199.11-10199.19"
+  wire width 7 \memadr_2
+  attribute \src "ls180.v:10219.11-10219.19"
+  wire width 7 \memadr_3
+  attribute \src "ls180.v:10239.12-10239.18"
   wire width 25 \memdat
-  attribute \src "ls180.v:10076.12-10076.20"
+  attribute \src "ls180.v:10253.12-10253.20"
   wire width 25 \memdat_1
-  attribute \src "ls180.v:10090.12-10090.20"
+  attribute \src "ls180.v:10267.12-10267.20"
   wire width 25 \memdat_2
-  attribute \src "ls180.v:10104.12-10104.20"
+  attribute \src "ls180.v:10281.12-10281.20"
   wire width 25 \memdat_3
-  attribute \src "ls180.v:10118.11-10118.19"
+  attribute \src "ls180.v:10295.11-10295.19"
   wire width 10 \memdat_4
-  attribute \src "ls180.v:10119.11-10119.19"
+  attribute \src "ls180.v:10296.11-10296.19"
   wire width 10 \memdat_5
-  attribute \src "ls180.v:10135.11-10135.19"
+  attribute \src "ls180.v:10312.11-10312.19"
   wire width 10 \memdat_6
-  attribute \src "ls180.v:10136.11-10136.19"
+  attribute \src "ls180.v:10313.11-10313.19"
   wire width 10 \memdat_7
-  attribute \src "ls180.v:10152.11-10152.19"
+  attribute \src "ls180.v:10329.11-10329.19"
   wire width 10 \memdat_8
-  attribute \src "ls180.v:10166.11-10166.19"
+  attribute \src "ls180.v:10343.11-10343.19"
   wire width 10 \memdat_9
   attribute \src "ls180.v:52.20-52.22"
   wire width 24 input 48 \nc
-  attribute \src "ls180.v:247.6-247.13"
+  attribute \src "ls180.v:292.6-292.13"
   wire \por_clk
-  attribute \src "ls180.v:21.19-21.22"
-  wire width 2 output 17 \pwm
-  attribute \src "ls180.v:141.12-141.17"
+  attribute \src "ls180.v:42.19-42.22"
+  wire width 2 output 38 \pwm
+  attribute \src "ls180.v:157.12-157.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:25.13-25.23"
-  wire output 21 \sdcard_clk
-  attribute \src "ls180.v:26.13-26.25"
-  wire input 22 \sdcard_cmd_i
-  attribute \src "ls180.v:27.13-27.25"
-  wire output 23 \sdcard_cmd_o
-  attribute \src "ls180.v:28.13-28.26"
-  wire output 24 \sdcard_cmd_oe
-  attribute \src "ls180.v:29.19-29.32"
-  wire width 4 input 25 \sdcard_data_i
-  attribute \src "ls180.v:30.19-30.32"
-  wire width 4 output 26 \sdcard_data_o
-  attribute \src "ls180.v:31.13-31.27"
-  wire output 27 \sdcard_data_oe
-  attribute \src "ls180.v:9.20-9.27"
-  wire width 13 output 5 \sdram_a
-  attribute \src "ls180.v:18.19-18.27"
-  wire width 2 output 14 \sdram_ba
-  attribute \src "ls180.v:15.13-15.24"
-  wire output 11 \sdram_cas_n
-  attribute \src "ls180.v:17.13-17.22"
-  wire output 13 \sdram_cke
-  attribute \src "ls180.v:20.13-20.24"
-  wire output 16 \sdram_clock
-  attribute \src "ls180.v:140.6-140.19"
+  attribute \src "ls180.v:35.13-35.23"
+  wire output 31 \sdcard_clk
+  attribute \src "ls180.v:36.13-36.25"
+  wire input 32 \sdcard_cmd_i
+  attribute \src "ls180.v:37.13-37.25"
+  wire output 33 \sdcard_cmd_o
+  attribute \src "ls180.v:38.13-38.26"
+  wire output 34 \sdcard_cmd_oe
+  attribute \src "ls180.v:39.19-39.32"
+  wire width 4 input 35 \sdcard_data_i
+  attribute \src "ls180.v:40.19-40.32"
+  wire width 4 output 36 \sdcard_data_o
+  attribute \src "ls180.v:41.13-41.27"
+  wire output 37 \sdcard_data_oe
+  attribute \src "ls180.v:5.20-5.27"
+  wire width 13 output 1 \sdram_a
+  attribute \src "ls180.v:14.19-14.27"
+  wire width 2 output 10 \sdram_ba
+  attribute \src "ls180.v:11.13-11.24"
+  wire output 7 \sdram_cas_n
+  attribute \src "ls180.v:13.13-13.22"
+  wire output 9 \sdram_cke
+  attribute \src "ls180.v:16.13-16.24"
+  wire output 12 \sdram_clock
+  attribute \src "ls180.v:136.6-136.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:16.13-16.23"
-  wire output 12 \sdram_cs_n
-  attribute \src "ls180.v:19.19-19.27"
-  wire width 2 output 15 \sdram_dm
-  attribute \src "ls180.v:10.20-10.30"
-  wire width 16 input 6 \sdram_dq_i
-  attribute \src "ls180.v:11.20-11.30"
-  wire width 16 output 7 \sdram_dq_o
-  attribute \src "ls180.v:12.13-12.24"
-  wire output 8 \sdram_dq_oe
-  attribute \src "ls180.v:14.13-14.24"
-  wire output 10 \sdram_ras_n
-  attribute \src "ls180.v:13.13-13.23"
-  wire output 9 \sdram_we_n
-  attribute \src "ls180.v:2643.6-2643.15"
+  attribute \src "ls180.v:12.13-12.23"
+  wire output 8 \sdram_cs_n
+  attribute \src "ls180.v:15.19-15.27"
+  wire width 2 output 11 \sdram_dm
+  attribute \src "ls180.v:6.20-6.30"
+  wire width 16 input 2 \sdram_dq_i
+  attribute \src "ls180.v:7.20-7.30"
+  wire width 16 output 3 \sdram_dq_o
+  attribute \src "ls180.v:8.13-8.24"
+  wire output 4 \sdram_dq_oe
+  attribute \src "ls180.v:10.13-10.24"
+  wire output 6 \sdram_ras_n
+  attribute \src "ls180.v:9.13-9.23"
+  wire output 5 \sdram_we_n
+  attribute \src "ls180.v:2688.6-2688.15"
   wire \sdrio_clk
-  attribute \src "ls180.v:2644.6-2644.17"
+  attribute \src "ls180.v:2689.6-2689.17"
   wire \sdrio_clk_1
-  attribute \src "ls180.v:2653.6-2653.18"
+  attribute \src "ls180.v:2698.6-2698.18"
   wire \sdrio_clk_10
-  attribute \src "ls180.v:2654.6-2654.18"
+  attribute \src "ls180.v:2699.6-2699.18"
   wire \sdrio_clk_11
-  attribute \src "ls180.v:2655.6-2655.18"
+  attribute \src "ls180.v:2700.6-2700.18"
   wire \sdrio_clk_12
-  attribute \src "ls180.v:2656.6-2656.18"
+  attribute \src "ls180.v:2701.6-2701.18"
   wire \sdrio_clk_13
-  attribute \src "ls180.v:2657.6-2657.18"
+  attribute \src "ls180.v:2702.6-2702.18"
   wire \sdrio_clk_14
-  attribute \src "ls180.v:2658.6-2658.18"
+  attribute \src "ls180.v:2703.6-2703.18"
   wire \sdrio_clk_15
-  attribute \src "ls180.v:2659.6-2659.18"
+  attribute \src "ls180.v:2704.6-2704.18"
   wire \sdrio_clk_16
-  attribute \src "ls180.v:2660.6-2660.18"
+  attribute \src "ls180.v:2705.6-2705.18"
   wire \sdrio_clk_17
-  attribute \src "ls180.v:2661.6-2661.18"
+  attribute \src "ls180.v:2706.6-2706.18"
   wire \sdrio_clk_18
-  attribute \src "ls180.v:2662.6-2662.18"
+  attribute \src "ls180.v:2707.6-2707.18"
   wire \sdrio_clk_19
-  attribute \src "ls180.v:2645.6-2645.17"
+  attribute \src "ls180.v:2690.6-2690.17"
   wire \sdrio_clk_2
-  attribute \src "ls180.v:2663.6-2663.18"
+  attribute \src "ls180.v:2708.6-2708.18"
   wire \sdrio_clk_20
-  attribute \src "ls180.v:2664.6-2664.18"
+  attribute \src "ls180.v:2709.6-2709.18"
   wire \sdrio_clk_21
-  attribute \src "ls180.v:2665.6-2665.18"
+  attribute \src "ls180.v:2710.6-2710.18"
   wire \sdrio_clk_22
-  attribute \src "ls180.v:2666.6-2666.18"
+  attribute \src "ls180.v:2711.6-2711.18"
   wire \sdrio_clk_23
-  attribute \src "ls180.v:2667.6-2667.18"
+  attribute \src "ls180.v:2712.6-2712.18"
   wire \sdrio_clk_24
-  attribute \src "ls180.v:2668.6-2668.18"
+  attribute \src "ls180.v:2713.6-2713.18"
   wire \sdrio_clk_25
-  attribute \src "ls180.v:2669.6-2669.18"
+  attribute \src "ls180.v:2714.6-2714.18"
   wire \sdrio_clk_26
-  attribute \src "ls180.v:2670.6-2670.18"
+  attribute \src "ls180.v:2715.6-2715.18"
   wire \sdrio_clk_27
-  attribute \src "ls180.v:2671.6-2671.18"
+  attribute \src "ls180.v:2716.6-2716.18"
   wire \sdrio_clk_28
-  attribute \src "ls180.v:2672.6-2672.18"
+  attribute \src "ls180.v:2717.6-2717.18"
   wire \sdrio_clk_29
-  attribute \src "ls180.v:2646.6-2646.17"
+  attribute \src "ls180.v:2691.6-2691.17"
   wire \sdrio_clk_3
-  attribute \src "ls180.v:2673.6-2673.18"
+  attribute \src "ls180.v:2718.6-2718.18"
   wire \sdrio_clk_30
-  attribute \src "ls180.v:2674.6-2674.18"
+  attribute \src "ls180.v:2719.6-2719.18"
   wire \sdrio_clk_31
-  attribute \src "ls180.v:2675.6-2675.18"
+  attribute \src "ls180.v:2720.6-2720.18"
   wire \sdrio_clk_32
-  attribute \src "ls180.v:2676.6-2676.18"
+  attribute \src "ls180.v:2721.6-2721.18"
   wire \sdrio_clk_33
-  attribute \src "ls180.v:2677.6-2677.18"
+  attribute \src "ls180.v:2722.6-2722.18"
   wire \sdrio_clk_34
-  attribute \src "ls180.v:2678.6-2678.18"
+  attribute \src "ls180.v:2723.6-2723.18"
   wire \sdrio_clk_35
-  attribute \src "ls180.v:2679.6-2679.18"
+  attribute \src "ls180.v:2724.6-2724.18"
   wire \sdrio_clk_36
-  attribute \src "ls180.v:2680.6-2680.18"
+  attribute \src "ls180.v:2725.6-2725.18"
   wire \sdrio_clk_37
-  attribute \src "ls180.v:2681.6-2681.18"
+  attribute \src "ls180.v:2726.6-2726.18"
   wire \sdrio_clk_38
-  attribute \src "ls180.v:2682.6-2682.18"
+  attribute \src "ls180.v:2727.6-2727.18"
   wire \sdrio_clk_39
-  attribute \src "ls180.v:2647.6-2647.17"
+  attribute \src "ls180.v:2692.6-2692.17"
   wire \sdrio_clk_4
-  attribute \src "ls180.v:2683.6-2683.18"
+  attribute \src "ls180.v:2728.6-2728.18"
   wire \sdrio_clk_40
-  attribute \src "ls180.v:2684.6-2684.18"
+  attribute \src "ls180.v:2729.6-2729.18"
   wire \sdrio_clk_41
-  attribute \src "ls180.v:2685.6-2685.18"
+  attribute \src "ls180.v:2730.6-2730.18"
   wire \sdrio_clk_42
-  attribute \src "ls180.v:2686.6-2686.18"
+  attribute \src "ls180.v:2731.6-2731.18"
   wire \sdrio_clk_43
-  attribute \src "ls180.v:2687.6-2687.18"
+  attribute \src "ls180.v:2732.6-2732.18"
   wire \sdrio_clk_44
-  attribute \src "ls180.v:2688.6-2688.18"
+  attribute \src "ls180.v:2733.6-2733.18"
   wire \sdrio_clk_45
-  attribute \src "ls180.v:2689.6-2689.18"
+  attribute \src "ls180.v:2734.6-2734.18"
   wire \sdrio_clk_46
-  attribute \src "ls180.v:2690.6-2690.18"
+  attribute \src "ls180.v:2735.6-2735.18"
   wire \sdrio_clk_47
-  attribute \src "ls180.v:2691.6-2691.18"
+  attribute \src "ls180.v:2736.6-2736.18"
   wire \sdrio_clk_48
-  attribute \src "ls180.v:2692.6-2692.18"
+  attribute \src "ls180.v:2737.6-2737.18"
   wire \sdrio_clk_49
-  attribute \src "ls180.v:2648.6-2648.17"
+  attribute \src "ls180.v:2693.6-2693.17"
   wire \sdrio_clk_5
-  attribute \src "ls180.v:2693.6-2693.18"
+  attribute \src "ls180.v:2738.6-2738.18"
   wire \sdrio_clk_50
-  attribute \src "ls180.v:2694.6-2694.18"
+  attribute \src "ls180.v:2739.6-2739.18"
   wire \sdrio_clk_51
-  attribute \src "ls180.v:2695.6-2695.18"
+  attribute \src "ls180.v:2740.6-2740.18"
   wire \sdrio_clk_52
-  attribute \src "ls180.v:2696.6-2696.18"
+  attribute \src "ls180.v:2741.6-2741.18"
   wire \sdrio_clk_53
-  attribute \src "ls180.v:2697.6-2697.18"
+  attribute \src "ls180.v:2742.6-2742.18"
   wire \sdrio_clk_54
-  attribute \src "ls180.v:2698.6-2698.18"
+  attribute \src "ls180.v:2743.6-2743.18"
   wire \sdrio_clk_55
-  attribute \src "ls180.v:2733.6-2733.18"
+  attribute \src "ls180.v:2778.6-2778.18"
   wire \sdrio_clk_56
-  attribute \src "ls180.v:2734.6-2734.18"
+  attribute \src "ls180.v:2779.6-2779.18"
   wire \sdrio_clk_57
-  attribute \src "ls180.v:2735.6-2735.18"
+  attribute \src "ls180.v:2780.6-2780.18"
   wire \sdrio_clk_58
-  attribute \src "ls180.v:2736.6-2736.18"
+  attribute \src "ls180.v:2781.6-2781.18"
   wire \sdrio_clk_59
-  attribute \src "ls180.v:2649.6-2649.17"
+  attribute \src "ls180.v:2694.6-2694.17"
   wire \sdrio_clk_6
-  attribute \src "ls180.v:2737.6-2737.18"
+  attribute \src "ls180.v:2782.6-2782.18"
   wire \sdrio_clk_60
-  attribute \src "ls180.v:2738.6-2738.18"
+  attribute \src "ls180.v:2783.6-2783.18"
   wire \sdrio_clk_61
-  attribute \src "ls180.v:2739.6-2739.18"
+  attribute \src "ls180.v:2784.6-2784.18"
   wire \sdrio_clk_62
-  attribute \src "ls180.v:2740.6-2740.18"
+  attribute \src "ls180.v:2785.6-2785.18"
   wire \sdrio_clk_63
-  attribute \src "ls180.v:2741.6-2741.18"
+  attribute \src "ls180.v:2786.6-2786.18"
   wire \sdrio_clk_64
-  attribute \src "ls180.v:2742.6-2742.18"
+  attribute \src "ls180.v:2787.6-2787.18"
   wire \sdrio_clk_65
-  attribute \src "ls180.v:2743.6-2743.18"
+  attribute \src "ls180.v:2788.6-2788.18"
   wire \sdrio_clk_66
-  attribute \src "ls180.v:2744.6-2744.18"
+  attribute \src "ls180.v:2789.6-2789.18"
   wire \sdrio_clk_67
-  attribute \src "ls180.v:2745.6-2745.18"
+  attribute \src "ls180.v:2790.6-2790.18"
   wire \sdrio_clk_68
-  attribute \src "ls180.v:2650.6-2650.17"
+  attribute \src "ls180.v:2695.6-2695.17"
   wire \sdrio_clk_7
-  attribute \src "ls180.v:2651.6-2651.17"
+  attribute \src "ls180.v:2696.6-2696.17"
   wire \sdrio_clk_8
-  attribute \src "ls180.v:2652.6-2652.17"
+  attribute \src "ls180.v:2697.6-2697.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:5.13-5.26"
-  wire output 1 \spimaster_clk
-  attribute \src "ls180.v:7.13-7.27"
-  wire output 3 \spimaster_cs_n
-  attribute \src "ls180.v:8.13-8.27"
-  wire input 4 \spimaster_miso
-  attribute \src "ls180.v:6.13-6.27"
-  wire output 2 \spimaster_mosi
-  attribute \src "ls180.v:39.13-39.26"
-  wire output 35 \spisdcard_clk
-  attribute \src "ls180.v:41.13-41.27"
-  wire output 37 \spisdcard_cs_n
-  attribute \src "ls180.v:42.13-42.27"
-  wire input 38 \spisdcard_miso
-  attribute \src "ls180.v:40.13-40.27"
-  wire output 36 \spisdcard_mosi
+  attribute \src "ls180.v:24.13-24.26"
+  wire output 20 \spimaster_clk
+  attribute \src "ls180.v:26.13-26.27"
+  wire output 22 \spimaster_cs_n
+  attribute \src "ls180.v:27.13-27.27"
+  wire input 23 \spimaster_miso
+  attribute \src "ls180.v:25.13-25.27"
+  wire output 21 \spimaster_mosi
+  attribute \src "ls180.v:20.13-20.26"
+  wire output 16 \spisdcard_clk
+  attribute \src "ls180.v:22.13-22.27"
+  wire output 18 \spisdcard_cs_n
+  attribute \src "ls180.v:23.13-23.27"
+  wire input 19 \spisdcard_miso
+  attribute \src "ls180.v:21.13-21.27"
+  wire output 17 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
-  attribute \src "ls180.v:245.6-245.15"
+  attribute \src "ls180.v:290.6-290.15"
   wire \sys_clk_1
   attribute \src "ls180.v:45.19-45.31"
   wire width 2 input 41 \sys_clksel_i
@@ -235083,32 +235491,38 @@ module \ls180
   wire output 43 \sys_pll_lck_o
   attribute \src "ls180.v:44.13-44.20"
   wire input 40 \sys_rst
-  attribute \src "ls180.v:246.6-246.15"
+  attribute \src "ls180.v:291.6-291.15"
   wire \sys_rst_1
-  attribute \src "ls180.v:24.13-24.20"
-  wire input 20 \uart_rx
-  attribute \src "ls180.v:23.13-23.20"
-  wire output 19 \uart_tx
-  attribute \src "ls180.v:10041.12-10041.15"
+  attribute \src "ls180.v:18.13-18.20"
+  wire input 14 \uart_rx
+  attribute \src "ls180.v:17.13-17.20"
+  wire output 13 \uart_tx
+  attribute \src "ls180.v:10158.12-10158.15"
   memory width 32 size 128 \mem
-  attribute \src "ls180.v:10061.12-10061.19"
+  attribute \src "ls180.v:10178.12-10178.17"
+  memory width 32 size 128 \mem_1
+  attribute \src "ls180.v:10198.12-10198.17"
+  memory width 32 size 128 \mem_2
+  attribute \src "ls180.v:10218.12-10218.17"
+  memory width 32 size 128 \mem_3
+  attribute \src "ls180.v:10238.12-10238.19"
   memory width 25 size 8 \storage
-  attribute \src "ls180.v:10075.12-10075.21"
+  attribute \src "ls180.v:10252.12-10252.21"
   memory width 25 size 8 \storage_1
-  attribute \src "ls180.v:10089.12-10089.21"
+  attribute \src "ls180.v:10266.12-10266.21"
   memory width 25 size 8 \storage_2
-  attribute \src "ls180.v:10103.12-10103.21"
+  attribute \src "ls180.v:10280.12-10280.21"
   memory width 25 size 8 \storage_3
-  attribute \src "ls180.v:10117.11-10117.20"
+  attribute \src "ls180.v:10294.11-10294.20"
   memory width 10 size 16 \storage_4
-  attribute \src "ls180.v:10134.11-10134.20"
+  attribute \src "ls180.v:10311.11-10311.20"
   memory width 10 size 16 \storage_5
-  attribute \src "ls180.v:10151.11-10151.20"
+  attribute \src "ls180.v:10328.11-10328.20"
   memory width 10 size 32 \storage_6
-  attribute \src "ls180.v:10165.11-10165.20"
+  attribute \src "ls180.v:10342.11-10342.20"
   memory width 10 size 32 \storage_7
-  attribute \src "ls180.v:2815.68-2815.110"
-  cell $add $add$ls180.v:2815$22
+  attribute \src "ls180.v:2860.68-2860.110"
+  cell $add $add$ls180.v:2860$34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235116,10 +235530,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter0_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:2815$22_Y
+    connect \Y $add$ls180.v:2860$34_Y
   end
-  attribute \src "ls180.v:2875.68-2875.110"
-  cell $add $add$ls180.v:2875$33
+  attribute \src "ls180.v:2920.68-2920.110"
+  cell $add $add$ls180.v:2920$45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235127,10 +235541,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter1_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:2875$33_Y
+    connect \Y $add$ls180.v:2920$45_Y
   end
-  attribute \src "ls180.v:2935.68-2935.110"
-  cell $add $add$ls180.v:2935$44
+  attribute \src "ls180.v:2980.68-2980.110"
+  cell $add $add$ls180.v:2980$56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235138,10 +235552,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter2_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:2935$44_Y
+    connect \Y $add$ls180.v:2980$56_Y
   end
-  attribute \src "ls180.v:4068.54-4068.83"
-  cell $add $add$ls180.v:4068$537
+  attribute \src "ls180.v:4143.54-4143.83"
+  cell $add $add$ls180.v:4143$588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235149,10 +235563,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_converter_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:4068$537_Y
+    connect \Y $add$ls180.v:4143$588_Y
   end
-  attribute \src "ls180.v:4168.36-4168.89"
-  cell $add $add$ls180.v:4168$583
+  attribute \src "ls180.v:4243.36-4243.89"
+  cell $add $add$ls180.v:4243$634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235160,10 +235574,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_tx_fifo_level0
     connect \B \main_uart_tx_fifo_readable
-    connect \Y $add$ls180.v:4168$583_Y
+    connect \Y $add$ls180.v:4243$634_Y
   end
-  attribute \src "ls180.v:4198.36-4198.89"
-  cell $add $add$ls180.v:4198$594
+  attribute \src "ls180.v:4273.36-4273.89"
+  cell $add $add$ls180.v:4273$645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235171,10 +235585,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_rx_fifo_level0
     connect \B \main_uart_rx_fifo_readable
-    connect \Y $add$ls180.v:4198$594_Y
+    connect \Y $add$ls180.v:4273$645_Y
   end
-  attribute \src "ls180.v:4253.54-4253.83"
-  cell $add $add$ls180.v:4253$607
+  attribute \src "ls180.v:4328.54-4328.83"
+  cell $add $add$ls180.v:4328$658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235182,10 +235596,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spimaster27_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4253$607_Y
+    connect \Y $add$ls180.v:4328$658_Y
   end
-  attribute \src "ls180.v:4312.52-4312.79"
-  cell $add $add$ls180.v:4312$615
+  attribute \src "ls180.v:4387.52-4387.79"
+  cell $add $add$ls180.v:4387$666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235193,10 +235607,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spisdcard_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4312$615_Y
+    connect \Y $add$ls180.v:4387$666_Y
   end
-  attribute \src "ls180.v:4416.58-4416.86"
-  cell $add $add$ls180.v:4416$643
+  attribute \src "ls180.v:4491.58-4491.86"
+  cell $add $add$ls180.v:4491$694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235204,10 +235618,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_init_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4416$643_Y
+    connect \Y $add$ls180.v:4491$694_Y
   end
-  attribute \src "ls180.v:4473.58-4473.86"
-  cell $add $add$ls180.v:4473$646
+  attribute \src "ls180.v:4548.58-4548.86"
+  cell $add $add$ls180.v:4548$697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235215,10 +235629,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_cmdw_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4473$646_Y
+    connect \Y $add$ls180.v:4548$697_Y
   end
-  attribute \src "ls180.v:4490.58-4490.86"
-  cell $add $add$ls180.v:4490$648
+  attribute \src "ls180.v:4565.58-4565.86"
+  cell $add $add$ls180.v:4565$699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235226,10 +235640,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_cmdw_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4490$648_Y
+    connect \Y $add$ls180.v:4565$699_Y
   end
-  attribute \src "ls180.v:4583.59-4583.87"
-  cell $add $add$ls180.v:4583$665
+  attribute \src "ls180.v:4658.59-4658.87"
+  cell $add $add$ls180.v:4658$716
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235237,10 +235651,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_cmdr_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4583$665_Y
+    connect \Y $add$ls180.v:4658$716_Y
   end
-  attribute \src "ls180.v:4608.59-4608.87"
-  cell $add $add$ls180.v:4608$668
+  attribute \src "ls180.v:4683.59-4683.87"
+  cell $add $add$ls180.v:4683$719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235248,10 +235662,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_cmdr_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4608$668_Y
+    connect \Y $add$ls180.v:4683$719_Y
   end
-  attribute \src "ls180.v:4730.53-4730.82"
-  cell $add $add$ls180.v:4730$685
+  attribute \src "ls180.v:4805.53-4805.82"
+  cell $add $add$ls180.v:4805$736
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -235259,10 +235673,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_dataw_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4730$685_Y
+    connect \Y $add$ls180.v:4805$736_Y
   end
-  attribute \src "ls180.v:4841.65-4841.114"
-  cell $add $add$ls180.v:4841$699
+  attribute \src "ls180.v:4916.65-4916.114"
+  cell $add $add$ls180.v:4916$750
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -235270,10 +235684,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \main_sdphy_datar_sink_payload_block_length
     connect \B 4'1000
-    connect \Y $add$ls180.v:4841$699_Y
+    connect \Y $add$ls180.v:4916$750_Y
   end
-  attribute \src "ls180.v:4846.62-4846.91"
-  cell $add $add$ls180.v:4846$702
+  attribute \src "ls180.v:4921.62-4921.91"
+  cell $add $add$ls180.v:4921$753
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -235281,10 +235695,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \main_sdphy_datar_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4846$702_Y
+    connect \Y $add$ls180.v:4921$753_Y
   end
-  attribute \src "ls180.v:4872.61-4872.90"
-  cell $add $add$ls180.v:4872$705
+  attribute \src "ls180.v:4947.61-4947.90"
+  cell $add $add$ls180.v:4947$756
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -235292,10 +235706,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \main_sdphy_datar_count
     connect \B 1'1
-    connect \Y $add$ls180.v:4872$705_Y
+    connect \Y $add$ls180.v:4947$756_Y
   end
-  attribute \src "ls180.v:5076.80-5076.117"
-  cell $add $add$ls180.v:5076$890
+  attribute \src "ls180.v:5151.80-5151.117"
+  cell $add $add$ls180.v:5151$941
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235303,10 +235717,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdcore_crc16_inserter_cnt
     connect \B 1'1
-    connect \Y $add$ls180.v:5076$890_Y
+    connect \Y $add$ls180.v:5151$941_Y
   end
-  attribute \src "ls180.v:5270.54-5270.82"
-  cell $add $add$ls180.v:5270$965
+  attribute \src "ls180.v:5345.54-5345.82"
+  cell $add $add$ls180.v:5345$1016
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235314,10 +235728,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdcore_cmd_count
     connect \B 1'1
-    connect \Y $add$ls180.v:5270$965_Y
+    connect \Y $add$ls180.v:5345$1016_Y
   end
-  attribute \src "ls180.v:5322.55-5322.84"
-  cell $add $add$ls180.v:5322$975
+  attribute \src "ls180.v:5397.55-5397.84"
+  cell $add $add$ls180.v:5397$1026
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235325,10 +235739,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdcore_data_count
     connect \B 1'1
-    connect \Y $add$ls180.v:5322$975_Y
+    connect \Y $add$ls180.v:5397$1026_Y
   end
-  attribute \src "ls180.v:5348.57-5348.86"
-  cell $add $add$ls180.v:5348$983
+  attribute \src "ls180.v:5423.57-5423.86"
+  cell $add $add$ls180.v:5423$1034
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235336,10 +235750,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdcore_data_count
     connect \B 1'1
-    connect \Y $add$ls180.v:5348$983_Y
+    connect \Y $add$ls180.v:5423$1034_Y
   end
-  attribute \src "ls180.v:5469.51-5469.134"
-  cell $add $add$ls180.v:5469$999
+  attribute \src "ls180.v:5544.51-5544.134"
+  cell $add $add$ls180.v:5544$1050
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235347,10 +235761,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdblock2mem_wishbonedmawriter_base
     connect \B \main_sdblock2mem_wishbonedmawriter_offset
-    connect \Y $add$ls180.v:5469$999_Y
+    connect \Y $add$ls180.v:5544$1050_Y
   end
-  attribute \src "ls180.v:5472.77-5472.125"
-  cell $add $add$ls180.v:5472$1001
+  attribute \src "ls180.v:5547.77-5547.125"
+  cell $add $add$ls180.v:5547$1052
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235358,10 +235772,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdblock2mem_wishbonedmawriter_offset
     connect \B 1'1
-    connect \Y $add$ls180.v:5472$1001_Y
+    connect \Y $add$ls180.v:5547$1052_Y
   end
-  attribute \src "ls180.v:5565.50-5565.105"
-  cell $add $add$ls180.v:5565$1010
+  attribute \src "ls180.v:5640.50-5640.105"
+  cell $add $add$ls180.v:5640$1061
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235369,10 +235783,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdmem2block_dma_base
     connect \B \main_sdmem2block_dma_offset
-    connect \Y $add$ls180.v:5565$1010_Y
+    connect \Y $add$ls180.v:5640$1061_Y
   end
-  attribute \src "ls180.v:5567.77-5567.111"
-  cell $add $add$ls180.v:5567$1011
+  attribute \src "ls180.v:5642.77-5642.111"
+  cell $add $add$ls180.v:5642$1062
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235380,10 +235794,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdmem2block_dma_offset
     connect \B 1'1
-    connect \Y $add$ls180.v:5567$1011_Y
+    connect \Y $add$ls180.v:5642$1062_Y
   end
-  attribute \src "ls180.v:7487.36-7487.70"
-  cell $add $add$ls180.v:7487$2403
+  attribute \src "ls180.v:7589.36-7589.70"
+  cell $add $add$ls180.v:7589$2472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235391,10 +235805,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_libresocsim_bus_errors
     connect \B 1'1
-    connect \Y $add$ls180.v:7487$2403_Y
+    connect \Y $add$ls180.v:7589$2472_Y
   end
-  attribute \src "ls180.v:7572.37-7572.72"
-  cell $add $add$ls180.v:7572$2424
+  attribute \src "ls180.v:7686.37-7686.72"
+  cell $add $add$ls180.v:7686$2502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235402,10 +235816,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_sequencer_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:7572$2424_Y
+    connect \Y $add$ls180.v:7686$2502_Y
   end
-  attribute \src "ls180.v:7589.60-7589.119"
-  cell $add $add$ls180.v:7589$2428
+  attribute \src "ls180.v:7703.60-7703.119"
+  cell $add $add$ls180.v:7703$2506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235413,10 +235827,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7589$2428_Y
+    connect \Y $add$ls180.v:7703$2506_Y
   end
-  attribute \src "ls180.v:7592.60-7592.119"
-  cell $add $add$ls180.v:7592$2429
+  attribute \src "ls180.v:7706.60-7706.119"
+  cell $add $add$ls180.v:7706$2507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235424,10 +235838,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7592$2429_Y
+    connect \Y $add$ls180.v:7706$2507_Y
   end
-  attribute \src "ls180.v:7596.59-7596.116"
-  cell $add $add$ls180.v:7596$2434
+  attribute \src "ls180.v:7710.59-7710.116"
+  cell $add $add$ls180.v:7710$2512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235435,10 +235849,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7596$2434_Y
+    connect \Y $add$ls180.v:7710$2512_Y
   end
-  attribute \src "ls180.v:7635.60-7635.119"
-  cell $add $add$ls180.v:7635$2444
+  attribute \src "ls180.v:7749.60-7749.119"
+  cell $add $add$ls180.v:7749$2522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235446,10 +235860,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7635$2444_Y
+    connect \Y $add$ls180.v:7749$2522_Y
   end
-  attribute \src "ls180.v:7638.60-7638.119"
-  cell $add $add$ls180.v:7638$2445
+  attribute \src "ls180.v:7752.60-7752.119"
+  cell $add $add$ls180.v:7752$2523
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235457,10 +235871,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7638$2445_Y
+    connect \Y $add$ls180.v:7752$2523_Y
   end
-  attribute \src "ls180.v:7642.59-7642.116"
-  cell $add $add$ls180.v:7642$2450
+  attribute \src "ls180.v:7756.59-7756.116"
+  cell $add $add$ls180.v:7756$2528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235468,10 +235882,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7642$2450_Y
+    connect \Y $add$ls180.v:7756$2528_Y
   end
-  attribute \src "ls180.v:7681.60-7681.119"
-  cell $add $add$ls180.v:7681$2460
+  attribute \src "ls180.v:7795.60-7795.119"
+  cell $add $add$ls180.v:7795$2538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235479,10 +235893,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7681$2460_Y
+    connect \Y $add$ls180.v:7795$2538_Y
   end
-  attribute \src "ls180.v:7684.60-7684.119"
-  cell $add $add$ls180.v:7684$2461
+  attribute \src "ls180.v:7798.60-7798.119"
+  cell $add $add$ls180.v:7798$2539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235490,10 +235904,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7684$2461_Y
+    connect \Y $add$ls180.v:7798$2539_Y
   end
-  attribute \src "ls180.v:7688.59-7688.116"
-  cell $add $add$ls180.v:7688$2466
+  attribute \src "ls180.v:7802.59-7802.116"
+  cell $add $add$ls180.v:7802$2544
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235501,10 +235915,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7688$2466_Y
+    connect \Y $add$ls180.v:7802$2544_Y
   end
-  attribute \src "ls180.v:7727.60-7727.119"
-  cell $add $add$ls180.v:7727$2476
+  attribute \src "ls180.v:7841.60-7841.119"
+  cell $add $add$ls180.v:7841$2554
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235512,10 +235926,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7727$2476_Y
+    connect \Y $add$ls180.v:7841$2554_Y
   end
-  attribute \src "ls180.v:7730.60-7730.119"
-  cell $add $add$ls180.v:7730$2477
+  attribute \src "ls180.v:7844.60-7844.119"
+  cell $add $add$ls180.v:7844$2555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235523,10 +235937,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7730$2477_Y
+    connect \Y $add$ls180.v:7844$2555_Y
   end
-  attribute \src "ls180.v:7734.59-7734.116"
-  cell $add $add$ls180.v:7734$2482
+  attribute \src "ls180.v:7848.59-7848.116"
+  cell $add $add$ls180.v:7848$2560
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235534,10 +235948,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7734$2482_Y
+    connect \Y $add$ls180.v:7848$2560_Y
   end
-  attribute \src "ls180.v:7964.34-7964.66"
-  cell $add $add$ls180.v:7964$2536
+  attribute \src "ls180.v:8078.34-8078.66"
+  cell $add $add$ls180.v:8078$2614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235545,10 +235959,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_phy_tx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:7964$2536_Y
+    connect \Y $add$ls180.v:8078$2614_Y
   end
-  attribute \src "ls180.v:7980.73-7980.131"
-  cell $add $add$ls180.v:7980$2539
+  attribute \src "ls180.v:8094.73-8094.131"
+  cell $add $add$ls180.v:8094$2617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235556,10 +235970,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \main_uart_phy_phase_accumulator_tx
     connect \B \main_uart_phy_storage
-    connect \Y $add$ls180.v:7980$2539_Y
+    connect \Y $add$ls180.v:8094$2617_Y
   end
-  attribute \src "ls180.v:7993.34-7993.66"
-  cell $add $add$ls180.v:7993$2543
+  attribute \src "ls180.v:8107.34-8107.66"
+  cell $add $add$ls180.v:8107$2621
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235567,10 +235981,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_phy_rx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:7993$2543_Y
+    connect \Y $add$ls180.v:8107$2621_Y
   end
-  attribute \src "ls180.v:8012.73-8012.131"
-  cell $add $add$ls180.v:8012$2546
+  attribute \src "ls180.v:8126.73-8126.131"
+  cell $add $add$ls180.v:8126$2624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235578,10 +235992,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \main_uart_phy_phase_accumulator_rx
     connect \B \main_uart_phy_storage
-    connect \Y $add$ls180.v:8012$2546_Y
+    connect \Y $add$ls180.v:8126$2624_Y
   end
-  attribute \src "ls180.v:8038.33-8038.65"
-  cell $add $add$ls180.v:8038$2554
+  attribute \src "ls180.v:8152.33-8152.65"
+  cell $add $add$ls180.v:8152$2632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235589,10 +236003,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_tx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8038$2554_Y
+    connect \Y $add$ls180.v:8152$2632_Y
   end
-  attribute \src "ls180.v:8041.33-8041.65"
-  cell $add $add$ls180.v:8041$2555
+  attribute \src "ls180.v:8155.33-8155.65"
+  cell $add $add$ls180.v:8155$2633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235600,10 +236014,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_tx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8041$2555_Y
+    connect \Y $add$ls180.v:8155$2633_Y
   end
-  attribute \src "ls180.v:8045.33-8045.64"
-  cell $add $add$ls180.v:8045$2560
+  attribute \src "ls180.v:8159.33-8159.64"
+  cell $add $add$ls180.v:8159$2638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235611,10 +236025,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_tx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:8045$2560_Y
+    connect \Y $add$ls180.v:8159$2638_Y
   end
-  attribute \src "ls180.v:8060.33-8060.65"
-  cell $add $add$ls180.v:8060$2565
+  attribute \src "ls180.v:8174.33-8174.65"
+  cell $add $add$ls180.v:8174$2643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235622,10 +236036,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_rx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8060$2565_Y
+    connect \Y $add$ls180.v:8174$2643_Y
   end
-  attribute \src "ls180.v:8063.33-8063.65"
-  cell $add $add$ls180.v:8063$2566
+  attribute \src "ls180.v:8177.33-8177.65"
+  cell $add $add$ls180.v:8177$2644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235633,10 +236047,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_rx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8063$2566_Y
+    connect \Y $add$ls180.v:8177$2644_Y
   end
-  attribute \src "ls180.v:8067.33-8067.64"
-  cell $add $add$ls180.v:8067$2571
+  attribute \src "ls180.v:8181.33-8181.64"
+  cell $add $add$ls180.v:8181$2649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235644,10 +236058,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_rx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:8067$2571_Y
+    connect \Y $add$ls180.v:8181$2649_Y
   end
-  attribute \src "ls180.v:8088.35-8088.70"
-  cell $add $add$ls180.v:8088$2573
+  attribute \src "ls180.v:8202.35-8202.70"
+  cell $add $add$ls180.v:8202$2651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -235655,10 +236069,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spimaster30_clk_divider
     connect \B 1'1
-    connect \Y $add$ls180.v:8088$2573_Y
+    connect \Y $add$ls180.v:8202$2651_Y
   end
-  attribute \src "ls180.v:8123.34-8123.68"
-  cell $add $add$ls180.v:8123$2578
+  attribute \src "ls180.v:8237.34-8237.68"
+  cell $add $add$ls180.v:8237$2656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -235666,10 +236080,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spisdcard_clk_divider1
     connect \B 1'1
-    connect \Y $add$ls180.v:8123$2578_Y
+    connect \Y $add$ls180.v:8237$2656_Y
   end
-  attribute \src "ls180.v:8159.25-8159.49"
-  cell $add $add$ls180.v:8159$2583
+  attribute \src "ls180.v:8273.25-8273.49"
+  cell $add $add$ls180.v:8273$2661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235677,10 +236091,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm0_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:8159$2583_Y
+    connect \Y $add$ls180.v:8273$2661_Y
   end
-  attribute \src "ls180.v:8173.25-8173.49"
-  cell $add $add$ls180.v:8173$2587
+  attribute \src "ls180.v:8287.25-8287.49"
+  cell $add $add$ls180.v:8287$2665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -235688,10 +236102,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm1_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:8173$2587_Y
+    connect \Y $add$ls180.v:8287$2665_Y
   end
-  attribute \src "ls180.v:8187.31-8187.61"
-  cell $add $add$ls180.v:8187$2592
+  attribute \src "ls180.v:8301.31-8301.61"
+  cell $add $add$ls180.v:8301$2670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 9
     parameter \B_SIGNED 0
@@ -235699,10 +236113,10 @@ module \ls180
     parameter \Y_WIDTH 9
     connect \A \main_sdphy_clocker_clks
     connect \B 1'1
-    connect \Y $add$ls180.v:8187$2592_Y
+    connect \Y $add$ls180.v:8301$2670_Y
   end
-  attribute \src "ls180.v:8210.45-8210.88"
-  cell $add $add$ls180.v:8210$2596
+  attribute \src "ls180.v:8324.45-8324.88"
+  cell $add $add$ls180.v:8324$2674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235710,10 +236124,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8210$2596_Y
+    connect \Y $add$ls180.v:8324$2674_Y
   end
-  attribute \src "ls180.v:8256.71-8256.114"
-  cell $add $add$ls180.v:8256$2602
+  attribute \src "ls180.v:8370.71-8370.114"
+  cell $add $add$ls180.v:8370$2680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235721,10 +236135,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8256$2602_Y
+    connect \Y $add$ls180.v:8370$2680_Y
   end
-  attribute \src "ls180.v:8291.46-8291.90"
-  cell $add $add$ls180.v:8291$2608
+  attribute \src "ls180.v:8405.46-8405.90"
+  cell $add $add$ls180.v:8405$2686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235732,10 +236146,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8291$2608_Y
+    connect \Y $add$ls180.v:8405$2686_Y
   end
-  attribute \src "ls180.v:8337.72-8337.116"
-  cell $add $add$ls180.v:8337$2614
+  attribute \src "ls180.v:8451.72-8451.116"
+  cell $add $add$ls180.v:8451$2692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -235743,10 +236157,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8337$2614_Y
+    connect \Y $add$ls180.v:8451$2692_Y
   end
-  attribute \src "ls180.v:8370.47-8370.92"
-  cell $add $add$ls180.v:8370$2620
+  attribute \src "ls180.v:8484.47-8484.92"
+  cell $add $add$ls180.v:8484$2698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235754,10 +236168,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8370$2620_Y
+    connect \Y $add$ls180.v:8484$2698_Y
   end
-  attribute \src "ls180.v:8398.73-8398.118"
-  cell $add $add$ls180.v:8398$2626
+  attribute \src "ls180.v:8512.73-8512.118"
+  cell $add $add$ls180.v:8512$2704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235765,10 +236179,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8398$2626_Y
+    connect \Y $add$ls180.v:8512$2704_Y
   end
-  attribute \src "ls180.v:8510.39-8510.75"
-  cell $add $add$ls180.v:8510$2639
+  attribute \src "ls180.v:8624.39-8624.75"
+  cell $add $add$ls180.v:8624$2717
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -235776,10 +236190,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 1'1
-    connect \Y $add$ls180.v:8510$2639_Y
+    connect \Y $add$ls180.v:8624$2717_Y
   end
-  attribute \src "ls180.v:8571.37-8571.73"
-  cell $add $add$ls180.v:8571$2643
+  attribute \src "ls180.v:8685.37-8685.73"
+  cell $add $add$ls180.v:8685$2721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235787,10 +236201,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdblock2mem_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8571$2643_Y
+    connect \Y $add$ls180.v:8685$2721_Y
   end
-  attribute \src "ls180.v:8574.37-8574.73"
-  cell $add $add$ls180.v:8574$2644
+  attribute \src "ls180.v:8688.37-8688.73"
+  cell $add $add$ls180.v:8688$2722
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235798,10 +236212,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdblock2mem_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8574$2644_Y
+    connect \Y $add$ls180.v:8688$2722_Y
   end
-  attribute \src "ls180.v:8578.36-8578.70"
-  cell $add $add$ls180.v:8578$2649
+  attribute \src "ls180.v:8692.36-8692.70"
+  cell $add $add$ls180.v:8692$2727
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -235809,10 +236223,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdblock2mem_fifo_level
     connect \B 1'1
-    connect \Y $add$ls180.v:8578$2649_Y
+    connect \Y $add$ls180.v:8692$2727_Y
   end
-  attribute \src "ls180.v:8593.41-8593.80"
-  cell $add $add$ls180.v:8593$2653
+  attribute \src "ls180.v:8707.41-8707.80"
+  cell $add $add$ls180.v:8707$2731
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -235820,10 +236234,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdblock2mem_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8593$2653_Y
+    connect \Y $add$ls180.v:8707$2731_Y
   end
-  attribute \src "ls180.v:8627.67-8627.106"
-  cell $add $add$ls180.v:8627$2659
+  attribute \src "ls180.v:8741.67-8741.106"
+  cell $add $add$ls180.v:8741$2737
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -235831,10 +236245,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdblock2mem_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8627$2659_Y
+    connect \Y $add$ls180.v:8741$2737_Y
   end
-  attribute \src "ls180.v:8653.39-8653.76"
-  cell $add $add$ls180.v:8653$2661
+  attribute \src "ls180.v:8767.39-8767.76"
+  cell $add $add$ls180.v:8767$2739
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -235842,10 +236256,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdmem2block_converter_mux
     connect \B 1'1
-    connect \Y $add$ls180.v:8653$2661_Y
+    connect \Y $add$ls180.v:8767$2739_Y
   end
-  attribute \src "ls180.v:8657.37-8657.73"
-  cell $add $add$ls180.v:8657$2665
+  attribute \src "ls180.v:8771.37-8771.73"
+  cell $add $add$ls180.v:8771$2743
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235853,10 +236267,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdmem2block_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8657$2665_Y
+    connect \Y $add$ls180.v:8771$2743_Y
   end
-  attribute \src "ls180.v:8660.37-8660.73"
-  cell $add $add$ls180.v:8660$2666
+  attribute \src "ls180.v:8774.37-8774.73"
+  cell $add $add$ls180.v:8774$2744
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -235864,10 +236278,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdmem2block_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8660$2666_Y
+    connect \Y $add$ls180.v:8774$2744_Y
   end
-  attribute \src "ls180.v:8664.36-8664.70"
-  cell $add $add$ls180.v:8664$2671
+  attribute \src "ls180.v:8778.36-8778.70"
+  cell $add $add$ls180.v:8778$2749
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -235875,10 +236289,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdmem2block_fifo_level
     connect \B 1'1
-    connect \Y $add$ls180.v:8664$2671_Y
+    connect \Y $add$ls180.v:8778$2749_Y
   end
-  attribute \src "ls180.v:2809.9-2809.80"
-  cell $and $and$ls180.v:2809$17
+  attribute \src "ls180.v:2854.9-2854.80"
+  cell $and $and$ls180.v:2854$29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235886,10 +236300,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_ibus_stb
     connect \B \main_libresocsim_libresoc_ibus_cyc
-    connect \Y $and$ls180.v:2809$17_Y
+    connect \Y $and$ls180.v:2854$29_Y
   end
-  attribute \src "ls180.v:2827.9-2827.80"
-  cell $and $and$ls180.v:2827$24
+  attribute \src "ls180.v:2872.9-2872.80"
+  cell $and $and$ls180.v:2872$36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235897,10 +236311,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_ibus_stb
     connect \B \main_libresocsim_libresoc_ibus_cyc
-    connect \Y $and$ls180.v:2827$24_Y
+    connect \Y $and$ls180.v:2872$36_Y
   end
-  attribute \src "ls180.v:2869.9-2869.80"
-  cell $and $and$ls180.v:2869$28
+  attribute \src "ls180.v:2914.9-2914.80"
+  cell $and $and$ls180.v:2914$40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235908,10 +236322,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_dbus_stb
     connect \B \main_libresocsim_libresoc_dbus_cyc
-    connect \Y $and$ls180.v:2869$28_Y
+    connect \Y $and$ls180.v:2914$40_Y
   end
-  attribute \src "ls180.v:2887.9-2887.80"
-  cell $and $and$ls180.v:2887$35
+  attribute \src "ls180.v:2932.9-2932.80"
+  cell $and $and$ls180.v:2932$47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235919,10 +236333,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_dbus_stb
     connect \B \main_libresocsim_libresoc_dbus_cyc
-    connect \Y $and$ls180.v:2887$35_Y
+    connect \Y $and$ls180.v:2932$47_Y
   end
-  attribute \src "ls180.v:2929.9-2929.86"
-  cell $and $and$ls180.v:2929$39
+  attribute \src "ls180.v:2974.9-2974.86"
+  cell $and $and$ls180.v:2974$51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235930,10 +236344,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_jtag_wb_stb
     connect \B \main_libresocsim_libresoc_jtag_wb_cyc
-    connect \Y $and$ls180.v:2929$39_Y
+    connect \Y $and$ls180.v:2974$51_Y
   end
-  attribute \src "ls180.v:2947.9-2947.86"
-  cell $and $and$ls180.v:2947$46
+  attribute \src "ls180.v:2992.9-2992.86"
+  cell $and $and$ls180.v:2992$58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235941,10 +236355,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_jtag_wb_stb
     connect \B \main_libresocsim_libresoc_jtag_wb_cyc
-    connect \Y $and$ls180.v:2947$46_Y
+    connect \Y $and$ls180.v:2992$58_Y
   end
-  attribute \src "ls180.v:2957.31-2957.90"
-  cell $and $and$ls180.v:2957$48
+  attribute \src "ls180.v:3002.31-3002.90"
+  cell $and $and$ls180.v:3002$60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235952,32 +236366,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:2957$48_Y
+    connect \Y $and$ls180.v:3002$60_Y
   end
-  attribute \src "ls180.v:2957.30-2957.121"
-  cell $and $and$ls180.v:2957$49
+  attribute \src "ls180.v:3002.30-3002.121"
+  cell $and $and$ls180.v:3002$61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2957$48_Y
+    connect \A $and$ls180.v:3002$60_Y
     connect \B \main_libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:2957$49_Y
+    connect \Y $and$ls180.v:3002$61_Y
   end
-  attribute \src "ls180.v:2957.29-2957.156"
-  cell $and $and$ls180.v:2957$50
+  attribute \src "ls180.v:3002.29-3002.156"
+  cell $and $and$ls180.v:3002$62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2957$49_Y
+    connect \A $and$ls180.v:3002$61_Y
     connect \B \main_libresocsim_ram_bus_sel [0]
-    connect \Y $and$ls180.v:2957$50_Y
+    connect \Y $and$ls180.v:3002$62_Y
   end
-  attribute \src "ls180.v:2958.31-2958.90"
-  cell $and $and$ls180.v:2958$51
+  attribute \src "ls180.v:3003.31-3003.90"
+  cell $and $and$ls180.v:3003$63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -235985,32 +236399,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:2958$51_Y
+    connect \Y $and$ls180.v:3003$63_Y
   end
-  attribute \src "ls180.v:2958.30-2958.121"
-  cell $and $and$ls180.v:2958$52
+  attribute \src "ls180.v:3003.30-3003.121"
+  cell $and $and$ls180.v:3003$64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2958$51_Y
+    connect \A $and$ls180.v:3003$63_Y
     connect \B \main_libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:2958$52_Y
+    connect \Y $and$ls180.v:3003$64_Y
   end
-  attribute \src "ls180.v:2958.29-2958.156"
-  cell $and $and$ls180.v:2958$53
+  attribute \src "ls180.v:3003.29-3003.156"
+  cell $and $and$ls180.v:3003$65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2958$52_Y
+    connect \A $and$ls180.v:3003$64_Y
     connect \B \main_libresocsim_ram_bus_sel [1]
-    connect \Y $and$ls180.v:2958$53_Y
+    connect \Y $and$ls180.v:3003$65_Y
   end
-  attribute \src "ls180.v:2959.31-2959.90"
-  cell $and $and$ls180.v:2959$54
+  attribute \src "ls180.v:3004.31-3004.90"
+  cell $and $and$ls180.v:3004$66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236018,32 +236432,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:2959$54_Y
+    connect \Y $and$ls180.v:3004$66_Y
   end
-  attribute \src "ls180.v:2959.30-2959.121"
-  cell $and $and$ls180.v:2959$55
+  attribute \src "ls180.v:3004.30-3004.121"
+  cell $and $and$ls180.v:3004$67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2959$54_Y
+    connect \A $and$ls180.v:3004$66_Y
     connect \B \main_libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:2959$55_Y
+    connect \Y $and$ls180.v:3004$67_Y
   end
-  attribute \src "ls180.v:2959.29-2959.156"
-  cell $and $and$ls180.v:2959$56
+  attribute \src "ls180.v:3004.29-3004.156"
+  cell $and $and$ls180.v:3004$68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2959$55_Y
+    connect \A $and$ls180.v:3004$67_Y
     connect \B \main_libresocsim_ram_bus_sel [2]
-    connect \Y $and$ls180.v:2959$56_Y
+    connect \Y $and$ls180.v:3004$68_Y
   end
-  attribute \src "ls180.v:2960.31-2960.90"
-  cell $and $and$ls180.v:2960$57
+  attribute \src "ls180.v:3005.31-3005.90"
+  cell $and $and$ls180.v:3005$69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236051,32 +236465,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:2960$57_Y
+    connect \Y $and$ls180.v:3005$69_Y
   end
-  attribute \src "ls180.v:2960.30-2960.121"
-  cell $and $and$ls180.v:2960$58
+  attribute \src "ls180.v:3005.30-3005.121"
+  cell $and $and$ls180.v:3005$70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2960$57_Y
+    connect \A $and$ls180.v:3005$69_Y
     connect \B \main_libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:2960$58_Y
+    connect \Y $and$ls180.v:3005$70_Y
   end
-  attribute \src "ls180.v:2960.29-2960.156"
-  cell $and $and$ls180.v:2960$59
+  attribute \src "ls180.v:3005.29-3005.156"
+  cell $and $and$ls180.v:3005$71
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2960$58_Y
+    connect \A $and$ls180.v:3005$70_Y
     connect \B \main_libresocsim_ram_bus_sel [3]
-    connect \Y $and$ls180.v:2960$59_Y
+    connect \Y $and$ls180.v:3005$71_Y
   end
-  attribute \src "ls180.v:2969.7-2969.89"
-  cell $and $and$ls180.v:2969$62
+  attribute \src "ls180.v:3014.7-3014.89"
+  cell $and $and$ls180.v:3014$74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236084,10 +236498,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_eventmanager_pending_re
     connect \B \main_libresocsim_eventmanager_pending_r
-    connect \Y $and$ls180.v:2969$62_Y
+    connect \Y $and$ls180.v:3014$74_Y
   end
-  attribute \src "ls180.v:2974.32-2974.111"
-  cell $and $and$ls180.v:2974$63
+  attribute \src "ls180.v:3019.32-3019.111"
+  cell $and $and$ls180.v:3019$75
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236095,10 +236509,406 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_eventmanager_pending_w
     connect \B \main_libresocsim_eventmanager_storage
-    connect \Y $and$ls180.v:2974$63_Y
+    connect \Y $and$ls180.v:3019$75_Y
+  end
+  attribute \src "ls180.v:3023.25-3023.82"
+  cell $and $and$ls180.v:3023$77
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_cyc
+    connect \B \main_interface0_ram_bus_stb
+    connect \Y $and$ls180.v:3023$77_Y
+  end
+  attribute \src "ls180.v:3023.24-3023.112"
+  cell $and $and$ls180.v:3023$78
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3023$77_Y
+    connect \B \main_interface0_ram_bus_we
+    connect \Y $and$ls180.v:3023$78_Y
+  end
+  attribute \src "ls180.v:3023.23-3023.146"
+  cell $and $and$ls180.v:3023$79
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3023$78_Y
+    connect \B \main_interface0_ram_bus_sel [0]
+    connect \Y $and$ls180.v:3023$79_Y
+  end
+  attribute \src "ls180.v:3024.25-3024.82"
+  cell $and $and$ls180.v:3024$80
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_cyc
+    connect \B \main_interface0_ram_bus_stb
+    connect \Y $and$ls180.v:3024$80_Y
+  end
+  attribute \src "ls180.v:3024.24-3024.112"
+  cell $and $and$ls180.v:3024$81
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3024$80_Y
+    connect \B \main_interface0_ram_bus_we
+    connect \Y $and$ls180.v:3024$81_Y
+  end
+  attribute \src "ls180.v:3024.23-3024.146"
+  cell $and $and$ls180.v:3024$82
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3024$81_Y
+    connect \B \main_interface0_ram_bus_sel [1]
+    connect \Y $and$ls180.v:3024$82_Y
   end
-  attribute \src "ls180.v:3088.40-3088.99"
-  cell $and $and$ls180.v:3088$70
+  attribute \src "ls180.v:3025.25-3025.82"
+  cell $and $and$ls180.v:3025$83
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_cyc
+    connect \B \main_interface0_ram_bus_stb
+    connect \Y $and$ls180.v:3025$83_Y
+  end
+  attribute \src "ls180.v:3025.24-3025.112"
+  cell $and $and$ls180.v:3025$84
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3025$83_Y
+    connect \B \main_interface0_ram_bus_we
+    connect \Y $and$ls180.v:3025$84_Y
+  end
+  attribute \src "ls180.v:3025.23-3025.146"
+  cell $and $and$ls180.v:3025$85
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3025$84_Y
+    connect \B \main_interface0_ram_bus_sel [2]
+    connect \Y $and$ls180.v:3025$85_Y
+  end
+  attribute \src "ls180.v:3026.25-3026.82"
+  cell $and $and$ls180.v:3026$86
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_cyc
+    connect \B \main_interface0_ram_bus_stb
+    connect \Y $and$ls180.v:3026$86_Y
+  end
+  attribute \src "ls180.v:3026.24-3026.112"
+  cell $and $and$ls180.v:3026$87
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3026$86_Y
+    connect \B \main_interface0_ram_bus_we
+    connect \Y $and$ls180.v:3026$87_Y
+  end
+  attribute \src "ls180.v:3026.23-3026.146"
+  cell $and $and$ls180.v:3026$88
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3026$87_Y
+    connect \B \main_interface0_ram_bus_sel [3]
+    connect \Y $and$ls180.v:3026$88_Y
+  end
+  attribute \src "ls180.v:3033.25-3033.82"
+  cell $and $and$ls180.v:3033$90
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_cyc
+    connect \B \main_interface1_ram_bus_stb
+    connect \Y $and$ls180.v:3033$90_Y
+  end
+  attribute \src "ls180.v:3033.24-3033.112"
+  cell $and $and$ls180.v:3033$91
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3033$90_Y
+    connect \B \main_interface1_ram_bus_we
+    connect \Y $and$ls180.v:3033$91_Y
+  end
+  attribute \src "ls180.v:3033.23-3033.146"
+  cell $and $and$ls180.v:3033$92
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3033$91_Y
+    connect \B \main_interface1_ram_bus_sel [0]
+    connect \Y $and$ls180.v:3033$92_Y
+  end
+  attribute \src "ls180.v:3034.25-3034.82"
+  cell $and $and$ls180.v:3034$93
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_cyc
+    connect \B \main_interface1_ram_bus_stb
+    connect \Y $and$ls180.v:3034$93_Y
+  end
+  attribute \src "ls180.v:3034.24-3034.112"
+  cell $and $and$ls180.v:3034$94
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3034$93_Y
+    connect \B \main_interface1_ram_bus_we
+    connect \Y $and$ls180.v:3034$94_Y
+  end
+  attribute \src "ls180.v:3034.23-3034.146"
+  cell $and $and$ls180.v:3034$95
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3034$94_Y
+    connect \B \main_interface1_ram_bus_sel [1]
+    connect \Y $and$ls180.v:3034$95_Y
+  end
+  attribute \src "ls180.v:3035.25-3035.82"
+  cell $and $and$ls180.v:3035$96
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_cyc
+    connect \B \main_interface1_ram_bus_stb
+    connect \Y $and$ls180.v:3035$96_Y
+  end
+  attribute \src "ls180.v:3035.24-3035.112"
+  cell $and $and$ls180.v:3035$97
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3035$96_Y
+    connect \B \main_interface1_ram_bus_we
+    connect \Y $and$ls180.v:3035$97_Y
+  end
+  attribute \src "ls180.v:3035.23-3035.146"
+  cell $and $and$ls180.v:3035$98
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3035$97_Y
+    connect \B \main_interface1_ram_bus_sel [2]
+    connect \Y $and$ls180.v:3035$98_Y
+  end
+  attribute \src "ls180.v:3036.24-3036.112"
+  cell $and $and$ls180.v:3036$100
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3036$99_Y
+    connect \B \main_interface1_ram_bus_we
+    connect \Y $and$ls180.v:3036$100_Y
+  end
+  attribute \src "ls180.v:3036.23-3036.146"
+  cell $and $and$ls180.v:3036$101
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3036$100_Y
+    connect \B \main_interface1_ram_bus_sel [3]
+    connect \Y $and$ls180.v:3036$101_Y
+  end
+  attribute \src "ls180.v:3036.25-3036.82"
+  cell $and $and$ls180.v:3036$99
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_cyc
+    connect \B \main_interface1_ram_bus_stb
+    connect \Y $and$ls180.v:3036$99_Y
+  end
+  attribute \src "ls180.v:3043.25-3043.82"
+  cell $and $and$ls180.v:3043$103
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_cyc
+    connect \B \main_interface2_ram_bus_stb
+    connect \Y $and$ls180.v:3043$103_Y
+  end
+  attribute \src "ls180.v:3043.24-3043.112"
+  cell $and $and$ls180.v:3043$104
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3043$103_Y
+    connect \B \main_interface2_ram_bus_we
+    connect \Y $and$ls180.v:3043$104_Y
+  end
+  attribute \src "ls180.v:3043.23-3043.146"
+  cell $and $and$ls180.v:3043$105
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3043$104_Y
+    connect \B \main_interface2_ram_bus_sel [0]
+    connect \Y $and$ls180.v:3043$105_Y
+  end
+  attribute \src "ls180.v:3044.25-3044.82"
+  cell $and $and$ls180.v:3044$106
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_cyc
+    connect \B \main_interface2_ram_bus_stb
+    connect \Y $and$ls180.v:3044$106_Y
+  end
+  attribute \src "ls180.v:3044.24-3044.112"
+  cell $and $and$ls180.v:3044$107
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3044$106_Y
+    connect \B \main_interface2_ram_bus_we
+    connect \Y $and$ls180.v:3044$107_Y
+  end
+  attribute \src "ls180.v:3044.23-3044.146"
+  cell $and $and$ls180.v:3044$108
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3044$107_Y
+    connect \B \main_interface2_ram_bus_sel [1]
+    connect \Y $and$ls180.v:3044$108_Y
+  end
+  attribute \src "ls180.v:3045.25-3045.82"
+  cell $and $and$ls180.v:3045$109
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_cyc
+    connect \B \main_interface2_ram_bus_stb
+    connect \Y $and$ls180.v:3045$109_Y
+  end
+  attribute \src "ls180.v:3045.24-3045.112"
+  cell $and $and$ls180.v:3045$110
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3045$109_Y
+    connect \B \main_interface2_ram_bus_we
+    connect \Y $and$ls180.v:3045$110_Y
+  end
+  attribute \src "ls180.v:3045.23-3045.146"
+  cell $and $and$ls180.v:3045$111
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3045$110_Y
+    connect \B \main_interface2_ram_bus_sel [2]
+    connect \Y $and$ls180.v:3045$111_Y
+  end
+  attribute \src "ls180.v:3046.25-3046.82"
+  cell $and $and$ls180.v:3046$112
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_cyc
+    connect \B \main_interface2_ram_bus_stb
+    connect \Y $and$ls180.v:3046$112_Y
+  end
+  attribute \src "ls180.v:3046.24-3046.112"
+  cell $and $and$ls180.v:3046$113
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3046$112_Y
+    connect \B \main_interface2_ram_bus_we
+    connect \Y $and$ls180.v:3046$113_Y
+  end
+  attribute \src "ls180.v:3046.23-3046.146"
+  cell $and $and$ls180.v:3046$114
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:3046$113_Y
+    connect \B \main_interface2_ram_bus_sel [3]
+    connect \Y $and$ls180.v:3046$114_Y
+  end
+  attribute \src "ls180.v:3163.40-3163.99"
+  cell $and $and$ls180.v:3163$121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236106,10 +236916,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_issue_re
     connect \B \main_sdram_command_storage [4]
-    connect \Y $and$ls180.v:3088$70_Y
+    connect \Y $and$ls180.v:3163$121_Y
   end
-  attribute \src "ls180.v:3089.40-3089.99"
-  cell $and $and$ls180.v:3089$71
+  attribute \src "ls180.v:3164.40-3164.99"
+  cell $and $and$ls180.v:3164$122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236117,21 +236927,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_issue_re
     connect \B \main_sdram_command_storage [5]
-    connect \Y $and$ls180.v:3089$71_Y
+    connect \Y $and$ls180.v:3164$122_Y
   end
-  attribute \src "ls180.v:3127.38-3127.103"
-  cell $and $and$ls180.v:3127$77
+  attribute \src "ls180.v:3202.38-3202.103"
+  cell $and $and$ls180.v:3202$128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_done1
-    connect \B $eq$ls180.v:3127$76_Y
-    connect \Y $and$ls180.v:3127$77_Y
+    connect \B $eq$ls180.v:3202$127_Y
+    connect \Y $and$ls180.v:3202$128_Y
   end
-  attribute \src "ls180.v:3181.50-3181.119"
-  cell $and $and$ls180.v:3181$85
+  attribute \src "ls180.v:3256.50-3256.119"
+  cell $and $and$ls180.v:3256$136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236139,21 +236949,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
     connect \B \main_sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:3181$85_Y
+    connect \Y $and$ls180.v:3256$136_Y
   end
-  attribute \src "ls180.v:3181.49-3181.167"
-  cell $and $and$ls180.v:3181$86
+  attribute \src "ls180.v:3256.49-3256.167"
+  cell $and $and$ls180.v:3256$137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3181$85_Y
+    connect \A $and$ls180.v:3256$136_Y
     connect \B \main_sdram_bankmachine0_cmd_payload_is_write
-    connect \Y $and$ls180.v:3181$86_Y
+    connect \Y $and$ls180.v:3256$137_Y
   end
-  attribute \src "ls180.v:3182.49-3182.118"
-  cell $and $and$ls180.v:3182$87
+  attribute \src "ls180.v:3257.49-3257.118"
+  cell $and $and$ls180.v:3257$138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236161,21 +236971,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
     connect \B \main_sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:3182$87_Y
+    connect \Y $and$ls180.v:3257$138_Y
   end
-  attribute \src "ls180.v:3182.48-3182.154"
-  cell $and $and$ls180.v:3182$88
+  attribute \src "ls180.v:3257.48-3257.154"
+  cell $and $and$ls180.v:3257$139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3182$87_Y
+    connect \A $and$ls180.v:3257$138_Y
     connect \B \main_sdram_bankmachine0_row_open
-    connect \Y $and$ls180.v:3182$88_Y
+    connect \Y $and$ls180.v:3257$139_Y
   end
-  attribute \src "ls180.v:3183.50-3183.119"
-  cell $and $and$ls180.v:3183$89
+  attribute \src "ls180.v:3258.50-3258.119"
+  cell $and $and$ls180.v:3258$140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236183,21 +236993,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
     connect \B \main_sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:3183$89_Y
+    connect \Y $and$ls180.v:3258$140_Y
   end
-  attribute \src "ls180.v:3183.49-3183.155"
-  cell $and $and$ls180.v:3183$90
+  attribute \src "ls180.v:3258.49-3258.155"
+  cell $and $and$ls180.v:3258$141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3183$89_Y
+    connect \A $and$ls180.v:3258$140_Y
     connect \B \main_sdram_bankmachine0_row_open
-    connect \Y $and$ls180.v:3183$90_Y
+    connect \Y $and$ls180.v:3258$141_Y
   end
-  attribute \src "ls180.v:3186.7-3186.114"
-  cell $and $and$ls180.v:3186$92
+  attribute \src "ls180.v:3261.7-3261.114"
+  cell $and $and$ls180.v:3261$143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236205,21 +237015,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:3186$92_Y
+    connect \Y $and$ls180.v:3261$143_Y
   end
-  attribute \src "ls180.v:3215.66-3215.246"
-  cell $and $and$ls180.v:3215$98
+  attribute \src "ls180.v:3290.66-3290.246"
+  cell $and $and$ls180.v:3290$149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
-    connect \B $or$ls180.v:3215$97_Y
-    connect \Y $and$ls180.v:3215$98_Y
+    connect \B $or$ls180.v:3290$148_Y
+    connect \Y $and$ls180.v:3290$149_Y
   end
-  attribute \src "ls180.v:3216.64-3216.187"
-  cell $and $and$ls180.v:3216$99
+  attribute \src "ls180.v:3291.64-3291.187"
+  cell $and $and$ls180.v:3291$150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236227,10 +237037,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
-    connect \Y $and$ls180.v:3216$99_Y
+    connect \Y $and$ls180.v:3291$150_Y
   end
-  attribute \src "ls180.v:3240.9-3240.86"
-  cell $and $and$ls180.v:3240$105
+  attribute \src "ls180.v:3315.9-3315.86"
+  cell $and $and$ls180.v:3315$156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236238,10 +237048,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_ready
     connect \B \main_sdram_bankmachine0_trascon_ready
-    connect \Y $and$ls180.v:3240$105_Y
+    connect \Y $and$ls180.v:3315$156_Y
   end
-  attribute \src "ls180.v:3252.9-3252.86"
-  cell $and $and$ls180.v:3252$106
+  attribute \src "ls180.v:3327.9-3327.86"
+  cell $and $and$ls180.v:3327$157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236249,10 +237059,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_ready
     connect \B \main_sdram_bankmachine0_trascon_ready
-    connect \Y $and$ls180.v:3252$106_Y
+    connect \Y $and$ls180.v:3327$157_Y
   end
-  attribute \src "ls180.v:3302.13-3302.87"
-  cell $and $and$ls180.v:3302$108
+  attribute \src "ls180.v:3377.13-3377.87"
+  cell $and $and$ls180.v:3377$159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236260,10 +237070,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_ready
     connect \B \main_sdram_bankmachine0_auto_precharge
-    connect \Y $and$ls180.v:3302$108_Y
+    connect \Y $and$ls180.v:3377$159_Y
   end
-  attribute \src "ls180.v:3338.50-3338.119"
-  cell $and $and$ls180.v:3338$115
+  attribute \src "ls180.v:3413.50-3413.119"
+  cell $and $and$ls180.v:3413$166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236271,21 +237081,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
     connect \B \main_sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:3338$115_Y
+    connect \Y $and$ls180.v:3413$166_Y
   end
-  attribute \src "ls180.v:3338.49-3338.167"
-  cell $and $and$ls180.v:3338$116
+  attribute \src "ls180.v:3413.49-3413.167"
+  cell $and $and$ls180.v:3413$167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3338$115_Y
+    connect \A $and$ls180.v:3413$166_Y
     connect \B \main_sdram_bankmachine1_cmd_payload_is_write
-    connect \Y $and$ls180.v:3338$116_Y
+    connect \Y $and$ls180.v:3413$167_Y
   end
-  attribute \src "ls180.v:3339.49-3339.118"
-  cell $and $and$ls180.v:3339$117
+  attribute \src "ls180.v:3414.49-3414.118"
+  cell $and $and$ls180.v:3414$168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236293,21 +237103,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
     connect \B \main_sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:3339$117_Y
+    connect \Y $and$ls180.v:3414$168_Y
   end
-  attribute \src "ls180.v:3339.48-3339.154"
-  cell $and $and$ls180.v:3339$118
+  attribute \src "ls180.v:3414.48-3414.154"
+  cell $and $and$ls180.v:3414$169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3339$117_Y
+    connect \A $and$ls180.v:3414$168_Y
     connect \B \main_sdram_bankmachine1_row_open
-    connect \Y $and$ls180.v:3339$118_Y
+    connect \Y $and$ls180.v:3414$169_Y
   end
-  attribute \src "ls180.v:3340.50-3340.119"
-  cell $and $and$ls180.v:3340$119
+  attribute \src "ls180.v:3415.50-3415.119"
+  cell $and $and$ls180.v:3415$170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236315,21 +237125,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
     connect \B \main_sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:3340$119_Y
+    connect \Y $and$ls180.v:3415$170_Y
   end
-  attribute \src "ls180.v:3340.49-3340.155"
-  cell $and $and$ls180.v:3340$120
+  attribute \src "ls180.v:3415.49-3415.155"
+  cell $and $and$ls180.v:3415$171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3340$119_Y
+    connect \A $and$ls180.v:3415$170_Y
     connect \B \main_sdram_bankmachine1_row_open
-    connect \Y $and$ls180.v:3340$120_Y
+    connect \Y $and$ls180.v:3415$171_Y
   end
-  attribute \src "ls180.v:3343.7-3343.114"
-  cell $and $and$ls180.v:3343$122
+  attribute \src "ls180.v:3418.7-3418.114"
+  cell $and $and$ls180.v:3418$173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236337,21 +237147,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:3343$122_Y
+    connect \Y $and$ls180.v:3418$173_Y
   end
-  attribute \src "ls180.v:3372.66-3372.246"
-  cell $and $and$ls180.v:3372$128
+  attribute \src "ls180.v:3447.66-3447.246"
+  cell $and $and$ls180.v:3447$179
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
-    connect \B $or$ls180.v:3372$127_Y
-    connect \Y $and$ls180.v:3372$128_Y
+    connect \B $or$ls180.v:3447$178_Y
+    connect \Y $and$ls180.v:3447$179_Y
   end
-  attribute \src "ls180.v:3373.64-3373.187"
-  cell $and $and$ls180.v:3373$129
+  attribute \src "ls180.v:3448.64-3448.187"
+  cell $and $and$ls180.v:3448$180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236359,10 +237169,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
-    connect \Y $and$ls180.v:3373$129_Y
+    connect \Y $and$ls180.v:3448$180_Y
   end
-  attribute \src "ls180.v:3397.9-3397.86"
-  cell $and $and$ls180.v:3397$135
+  attribute \src "ls180.v:3472.9-3472.86"
+  cell $and $and$ls180.v:3472$186
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236370,10 +237180,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_ready
     connect \B \main_sdram_bankmachine1_trascon_ready
-    connect \Y $and$ls180.v:3397$135_Y
+    connect \Y $and$ls180.v:3472$186_Y
   end
-  attribute \src "ls180.v:3409.9-3409.86"
-  cell $and $and$ls180.v:3409$136
+  attribute \src "ls180.v:3484.9-3484.86"
+  cell $and $and$ls180.v:3484$187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236381,10 +237191,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_ready
     connect \B \main_sdram_bankmachine1_trascon_ready
-    connect \Y $and$ls180.v:3409$136_Y
+    connect \Y $and$ls180.v:3484$187_Y
   end
-  attribute \src "ls180.v:3459.13-3459.87"
-  cell $and $and$ls180.v:3459$138
+  attribute \src "ls180.v:3534.13-3534.87"
+  cell $and $and$ls180.v:3534$189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236392,10 +237202,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_ready
     connect \B \main_sdram_bankmachine1_auto_precharge
-    connect \Y $and$ls180.v:3459$138_Y
+    connect \Y $and$ls180.v:3534$189_Y
   end
-  attribute \src "ls180.v:3495.50-3495.119"
-  cell $and $and$ls180.v:3495$145
+  attribute \src "ls180.v:3570.50-3570.119"
+  cell $and $and$ls180.v:3570$196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236403,21 +237213,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
     connect \B \main_sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:3495$145_Y
+    connect \Y $and$ls180.v:3570$196_Y
   end
-  attribute \src "ls180.v:3495.49-3495.167"
-  cell $and $and$ls180.v:3495$146
+  attribute \src "ls180.v:3570.49-3570.167"
+  cell $and $and$ls180.v:3570$197
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3495$145_Y
+    connect \A $and$ls180.v:3570$196_Y
     connect \B \main_sdram_bankmachine2_cmd_payload_is_write
-    connect \Y $and$ls180.v:3495$146_Y
+    connect \Y $and$ls180.v:3570$197_Y
   end
-  attribute \src "ls180.v:3496.49-3496.118"
-  cell $and $and$ls180.v:3496$147
+  attribute \src "ls180.v:3571.49-3571.118"
+  cell $and $and$ls180.v:3571$198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236425,21 +237235,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
     connect \B \main_sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:3496$147_Y
+    connect \Y $and$ls180.v:3571$198_Y
   end
-  attribute \src "ls180.v:3496.48-3496.154"
-  cell $and $and$ls180.v:3496$148
+  attribute \src "ls180.v:3571.48-3571.154"
+  cell $and $and$ls180.v:3571$199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3496$147_Y
+    connect \A $and$ls180.v:3571$198_Y
     connect \B \main_sdram_bankmachine2_row_open
-    connect \Y $and$ls180.v:3496$148_Y
+    connect \Y $and$ls180.v:3571$199_Y
   end
-  attribute \src "ls180.v:3497.50-3497.119"
-  cell $and $and$ls180.v:3497$149
+  attribute \src "ls180.v:3572.50-3572.119"
+  cell $and $and$ls180.v:3572$200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236447,21 +237257,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
     connect \B \main_sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:3497$149_Y
+    connect \Y $and$ls180.v:3572$200_Y
   end
-  attribute \src "ls180.v:3497.49-3497.155"
-  cell $and $and$ls180.v:3497$150
+  attribute \src "ls180.v:3572.49-3572.155"
+  cell $and $and$ls180.v:3572$201
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3497$149_Y
+    connect \A $and$ls180.v:3572$200_Y
     connect \B \main_sdram_bankmachine2_row_open
-    connect \Y $and$ls180.v:3497$150_Y
+    connect \Y $and$ls180.v:3572$201_Y
   end
-  attribute \src "ls180.v:3500.7-3500.114"
-  cell $and $and$ls180.v:3500$152
+  attribute \src "ls180.v:3575.7-3575.114"
+  cell $and $and$ls180.v:3575$203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236469,21 +237279,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:3500$152_Y
+    connect \Y $and$ls180.v:3575$203_Y
   end
-  attribute \src "ls180.v:3529.66-3529.246"
-  cell $and $and$ls180.v:3529$158
+  attribute \src "ls180.v:3604.66-3604.246"
+  cell $and $and$ls180.v:3604$209
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
-    connect \B $or$ls180.v:3529$157_Y
-    connect \Y $and$ls180.v:3529$158_Y
+    connect \B $or$ls180.v:3604$208_Y
+    connect \Y $and$ls180.v:3604$209_Y
   end
-  attribute \src "ls180.v:3530.64-3530.187"
-  cell $and $and$ls180.v:3530$159
+  attribute \src "ls180.v:3605.64-3605.187"
+  cell $and $and$ls180.v:3605$210
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236491,10 +237301,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
-    connect \Y $and$ls180.v:3530$159_Y
+    connect \Y $and$ls180.v:3605$210_Y
   end
-  attribute \src "ls180.v:3554.9-3554.86"
-  cell $and $and$ls180.v:3554$165
+  attribute \src "ls180.v:3629.9-3629.86"
+  cell $and $and$ls180.v:3629$216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236502,10 +237312,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_ready
     connect \B \main_sdram_bankmachine2_trascon_ready
-    connect \Y $and$ls180.v:3554$165_Y
+    connect \Y $and$ls180.v:3629$216_Y
   end
-  attribute \src "ls180.v:3566.9-3566.86"
-  cell $and $and$ls180.v:3566$166
+  attribute \src "ls180.v:3641.9-3641.86"
+  cell $and $and$ls180.v:3641$217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236513,10 +237323,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_ready
     connect \B \main_sdram_bankmachine2_trascon_ready
-    connect \Y $and$ls180.v:3566$166_Y
+    connect \Y $and$ls180.v:3641$217_Y
   end
-  attribute \src "ls180.v:3616.13-3616.87"
-  cell $and $and$ls180.v:3616$168
+  attribute \src "ls180.v:3691.13-3691.87"
+  cell $and $and$ls180.v:3691$219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236524,10 +237334,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_ready
     connect \B \main_sdram_bankmachine2_auto_precharge
-    connect \Y $and$ls180.v:3616$168_Y
+    connect \Y $and$ls180.v:3691$219_Y
   end
-  attribute \src "ls180.v:3652.50-3652.119"
-  cell $and $and$ls180.v:3652$175
+  attribute \src "ls180.v:3727.50-3727.119"
+  cell $and $and$ls180.v:3727$226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236535,21 +237345,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
     connect \B \main_sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:3652$175_Y
+    connect \Y $and$ls180.v:3727$226_Y
   end
-  attribute \src "ls180.v:3652.49-3652.167"
-  cell $and $and$ls180.v:3652$176
+  attribute \src "ls180.v:3727.49-3727.167"
+  cell $and $and$ls180.v:3727$227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3652$175_Y
+    connect \A $and$ls180.v:3727$226_Y
     connect \B \main_sdram_bankmachine3_cmd_payload_is_write
-    connect \Y $and$ls180.v:3652$176_Y
+    connect \Y $and$ls180.v:3727$227_Y
   end
-  attribute \src "ls180.v:3653.49-3653.118"
-  cell $and $and$ls180.v:3653$177
+  attribute \src "ls180.v:3728.49-3728.118"
+  cell $and $and$ls180.v:3728$228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236557,21 +237367,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
     connect \B \main_sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:3653$177_Y
+    connect \Y $and$ls180.v:3728$228_Y
   end
-  attribute \src "ls180.v:3653.48-3653.154"
-  cell $and $and$ls180.v:3653$178
+  attribute \src "ls180.v:3728.48-3728.154"
+  cell $and $and$ls180.v:3728$229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3653$177_Y
+    connect \A $and$ls180.v:3728$228_Y
     connect \B \main_sdram_bankmachine3_row_open
-    connect \Y $and$ls180.v:3653$178_Y
+    connect \Y $and$ls180.v:3728$229_Y
   end
-  attribute \src "ls180.v:3654.50-3654.119"
-  cell $and $and$ls180.v:3654$179
+  attribute \src "ls180.v:3729.50-3729.119"
+  cell $and $and$ls180.v:3729$230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236579,21 +237389,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
     connect \B \main_sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:3654$179_Y
+    connect \Y $and$ls180.v:3729$230_Y
   end
-  attribute \src "ls180.v:3654.49-3654.155"
-  cell $and $and$ls180.v:3654$180
+  attribute \src "ls180.v:3729.49-3729.155"
+  cell $and $and$ls180.v:3729$231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3654$179_Y
+    connect \A $and$ls180.v:3729$230_Y
     connect \B \main_sdram_bankmachine3_row_open
-    connect \Y $and$ls180.v:3654$180_Y
+    connect \Y $and$ls180.v:3729$231_Y
   end
-  attribute \src "ls180.v:3657.7-3657.114"
-  cell $and $and$ls180.v:3657$182
+  attribute \src "ls180.v:3732.7-3732.114"
+  cell $and $and$ls180.v:3732$233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236601,21 +237411,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:3657$182_Y
+    connect \Y $and$ls180.v:3732$233_Y
   end
-  attribute \src "ls180.v:3686.66-3686.246"
-  cell $and $and$ls180.v:3686$188
+  attribute \src "ls180.v:3761.66-3761.246"
+  cell $and $and$ls180.v:3761$239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
-    connect \B $or$ls180.v:3686$187_Y
-    connect \Y $and$ls180.v:3686$188_Y
+    connect \B $or$ls180.v:3761$238_Y
+    connect \Y $and$ls180.v:3761$239_Y
   end
-  attribute \src "ls180.v:3687.64-3687.187"
-  cell $and $and$ls180.v:3687$189
+  attribute \src "ls180.v:3762.64-3762.187"
+  cell $and $and$ls180.v:3762$240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236623,10 +237433,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
-    connect \Y $and$ls180.v:3687$189_Y
+    connect \Y $and$ls180.v:3762$240_Y
   end
-  attribute \src "ls180.v:3711.9-3711.86"
-  cell $and $and$ls180.v:3711$195
+  attribute \src "ls180.v:3786.9-3786.86"
+  cell $and $and$ls180.v:3786$246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236634,10 +237444,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_ready
     connect \B \main_sdram_bankmachine3_trascon_ready
-    connect \Y $and$ls180.v:3711$195_Y
+    connect \Y $and$ls180.v:3786$246_Y
   end
-  attribute \src "ls180.v:3723.9-3723.86"
-  cell $and $and$ls180.v:3723$196
+  attribute \src "ls180.v:3798.9-3798.86"
+  cell $and $and$ls180.v:3798$247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236645,10 +237455,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_ready
     connect \B \main_sdram_bankmachine3_trascon_ready
-    connect \Y $and$ls180.v:3723$196_Y
+    connect \Y $and$ls180.v:3798$247_Y
   end
-  attribute \src "ls180.v:3773.13-3773.87"
-  cell $and $and$ls180.v:3773$198
+  attribute \src "ls180.v:3848.13-3848.87"
+  cell $and $and$ls180.v:3848$249
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236656,10 +237466,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_ready
     connect \B \main_sdram_bankmachine3_auto_precharge
-    connect \Y $and$ls180.v:3773$198_Y
+    connect \Y $and$ls180.v:3848$249_Y
   end
-  attribute \src "ls180.v:3788.37-3788.102"
-  cell $and $and$ls180.v:3788$199
+  attribute \src "ls180.v:3863.37-3863.102"
+  cell $and $and$ls180.v:3863$250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236667,43 +237477,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3788$199_Y
+    connect \Y $and$ls180.v:3863$250_Y
   end
-  attribute \src "ls180.v:3788.108-3788.188"
-  cell $and $and$ls180.v:3788$201
+  attribute \src "ls180.v:3863.108-3863.188"
+  cell $and $and$ls180.v:3863$252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:3788$200_Y
-    connect \Y $and$ls180.v:3788$201_Y
+    connect \B $not$ls180.v:3863$251_Y
+    connect \Y $and$ls180.v:3863$252_Y
   end
-  attribute \src "ls180.v:3788.107-3788.231"
-  cell $and $and$ls180.v:3788$203
+  attribute \src "ls180.v:3863.107-3863.231"
+  cell $and $and$ls180.v:3863$254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3788$201_Y
-    connect \B $not$ls180.v:3788$202_Y
-    connect \Y $and$ls180.v:3788$203_Y
+    connect \A $and$ls180.v:3863$252_Y
+    connect \B $not$ls180.v:3863$253_Y
+    connect \Y $and$ls180.v:3863$254_Y
   end
-  attribute \src "ls180.v:3788.36-3788.232"
-  cell $and $and$ls180.v:3788$204
+  attribute \src "ls180.v:3863.36-3863.232"
+  cell $and $and$ls180.v:3863$255
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3788$199_Y
-    connect \B $and$ls180.v:3788$203_Y
-    connect \Y $and$ls180.v:3788$204_Y
+    connect \A $and$ls180.v:3863$250_Y
+    connect \B $and$ls180.v:3863$254_Y
+    connect \Y $and$ls180.v:3863$255_Y
   end
-  attribute \src "ls180.v:3789.37-3789.102"
-  cell $and $and$ls180.v:3789$205
+  attribute \src "ls180.v:3864.37-3864.102"
+  cell $and $and$ls180.v:3864$256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236711,43 +237521,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3789$205_Y
+    connect \Y $and$ls180.v:3864$256_Y
   end
-  attribute \src "ls180.v:3789.108-3789.188"
-  cell $and $and$ls180.v:3789$207
+  attribute \src "ls180.v:3864.108-3864.188"
+  cell $and $and$ls180.v:3864$258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:3789$206_Y
-    connect \Y $and$ls180.v:3789$207_Y
+    connect \B $not$ls180.v:3864$257_Y
+    connect \Y $and$ls180.v:3864$258_Y
   end
-  attribute \src "ls180.v:3789.107-3789.231"
-  cell $and $and$ls180.v:3789$209
+  attribute \src "ls180.v:3864.107-3864.231"
+  cell $and $and$ls180.v:3864$260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3789$207_Y
-    connect \B $not$ls180.v:3789$208_Y
-    connect \Y $and$ls180.v:3789$209_Y
+    connect \A $and$ls180.v:3864$258_Y
+    connect \B $not$ls180.v:3864$259_Y
+    connect \Y $and$ls180.v:3864$260_Y
   end
-  attribute \src "ls180.v:3789.36-3789.232"
-  cell $and $and$ls180.v:3789$210
+  attribute \src "ls180.v:3864.36-3864.232"
+  cell $and $and$ls180.v:3864$261
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3789$205_Y
-    connect \B $and$ls180.v:3789$209_Y
-    connect \Y $and$ls180.v:3789$210_Y
+    connect \A $and$ls180.v:3864$256_Y
+    connect \B $and$ls180.v:3864$260_Y
+    connect \Y $and$ls180.v:3864$261_Y
   end
-  attribute \src "ls180.v:3790.34-3790.85"
-  cell $and $and$ls180.v:3790$211
+  attribute \src "ls180.v:3865.34-3865.85"
+  cell $and $and$ls180.v:3865$262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236755,10 +237565,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_trrdcon_ready
     connect \B \main_sdram_tfawcon_ready
-    connect \Y $and$ls180.v:3790$211_Y
+    connect \Y $and$ls180.v:3865$262_Y
   end
-  attribute \src "ls180.v:3791.37-3791.102"
-  cell $and $and$ls180.v:3791$212
+  attribute \src "ls180.v:3866.37-3866.102"
+  cell $and $and$ls180.v:3866$263
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236766,21 +237576,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3791$212_Y
+    connect \Y $and$ls180.v:3866$263_Y
   end
-  attribute \src "ls180.v:3791.36-3791.194"
-  cell $and $and$ls180.v:3791$214
+  attribute \src "ls180.v:3866.36-3866.194"
+  cell $and $and$ls180.v:3866$265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3791$212_Y
-    connect \B $or$ls180.v:3791$213_Y
-    connect \Y $and$ls180.v:3791$214_Y
+    connect \A $and$ls180.v:3866$263_Y
+    connect \B $or$ls180.v:3866$264_Y
+    connect \Y $and$ls180.v:3866$265_Y
   end
-  attribute \src "ls180.v:3793.37-3793.102"
-  cell $and $and$ls180.v:3793$215
+  attribute \src "ls180.v:3868.37-3868.102"
+  cell $and $and$ls180.v:3868$266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236788,21 +237598,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3793$215_Y
+    connect \Y $and$ls180.v:3868$266_Y
   end
-  attribute \src "ls180.v:3793.36-3793.148"
-  cell $and $and$ls180.v:3793$216
+  attribute \src "ls180.v:3868.36-3868.148"
+  cell $and $and$ls180.v:3868$267
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3793$215_Y
+    connect \A $and$ls180.v:3868$266_Y
     connect \B \main_sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:3793$216_Y
+    connect \Y $and$ls180.v:3868$267_Y
   end
-  attribute \src "ls180.v:3794.40-3794.119"
-  cell $and $and$ls180.v:3794$217
+  attribute \src "ls180.v:3869.40-3869.119"
+  cell $and $and$ls180.v:3869$268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236810,10 +237620,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
     connect \B \main_sdram_bankmachine0_cmd_payload_is_read
-    connect \Y $and$ls180.v:3794$217_Y
+    connect \Y $and$ls180.v:3869$268_Y
   end
-  attribute \src "ls180.v:3794.124-3794.203"
-  cell $and $and$ls180.v:3794$218
+  attribute \src "ls180.v:3869.124-3869.203"
+  cell $and $and$ls180.v:3869$269
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236821,10 +237631,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
     connect \B \main_sdram_bankmachine1_cmd_payload_is_read
-    connect \Y $and$ls180.v:3794$218_Y
+    connect \Y $and$ls180.v:3869$269_Y
   end
-  attribute \src "ls180.v:3794.209-3794.288"
-  cell $and $and$ls180.v:3794$220
+  attribute \src "ls180.v:3869.209-3869.288"
+  cell $and $and$ls180.v:3869$271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236832,10 +237642,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
     connect \B \main_sdram_bankmachine2_cmd_payload_is_read
-    connect \Y $and$ls180.v:3794$220_Y
+    connect \Y $and$ls180.v:3869$271_Y
   end
-  attribute \src "ls180.v:3794.294-3794.373"
-  cell $and $and$ls180.v:3794$222
+  attribute \src "ls180.v:3869.294-3869.373"
+  cell $and $and$ls180.v:3869$273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236843,10 +237653,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
     connect \B \main_sdram_bankmachine3_cmd_payload_is_read
-    connect \Y $and$ls180.v:3794$222_Y
+    connect \Y $and$ls180.v:3869$273_Y
   end
-  attribute \src "ls180.v:3795.41-3795.121"
-  cell $and $and$ls180.v:3795$224
+  attribute \src "ls180.v:3870.41-3870.121"
+  cell $and $and$ls180.v:3870$275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236854,10 +237664,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
     connect \B \main_sdram_bankmachine0_cmd_payload_is_write
-    connect \Y $and$ls180.v:3795$224_Y
+    connect \Y $and$ls180.v:3870$275_Y
   end
-  attribute \src "ls180.v:3795.126-3795.206"
-  cell $and $and$ls180.v:3795$225
+  attribute \src "ls180.v:3870.126-3870.206"
+  cell $and $and$ls180.v:3870$276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236865,10 +237675,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
     connect \B \main_sdram_bankmachine1_cmd_payload_is_write
-    connect \Y $and$ls180.v:3795$225_Y
+    connect \Y $and$ls180.v:3870$276_Y
   end
-  attribute \src "ls180.v:3795.212-3795.292"
-  cell $and $and$ls180.v:3795$227
+  attribute \src "ls180.v:3870.212-3870.292"
+  cell $and $and$ls180.v:3870$278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236876,10 +237686,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
     connect \B \main_sdram_bankmachine2_cmd_payload_is_write
-    connect \Y $and$ls180.v:3795$227_Y
+    connect \Y $and$ls180.v:3870$278_Y
   end
-  attribute \src "ls180.v:3795.298-3795.378"
-  cell $and $and$ls180.v:3795$229
+  attribute \src "ls180.v:3870.298-3870.378"
+  cell $and $and$ls180.v:3870$280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236887,10 +237697,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
     connect \B \main_sdram_bankmachine3_cmd_payload_is_write
-    connect \Y $and$ls180.v:3795$229_Y
+    connect \Y $and$ls180.v:3870$280_Y
   end
-  attribute \src "ls180.v:3802.38-3802.111"
-  cell $and $and$ls180.v:3802$233
+  attribute \src "ls180.v:3877.38-3877.111"
+  cell $and $and$ls180.v:3877$284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236898,32 +237708,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_refresh_gnt
     connect \B \main_sdram_bankmachine1_refresh_gnt
-    connect \Y $and$ls180.v:3802$233_Y
+    connect \Y $and$ls180.v:3877$284_Y
   end
-  attribute \src "ls180.v:3802.37-3802.150"
-  cell $and $and$ls180.v:3802$234
+  attribute \src "ls180.v:3877.37-3877.150"
+  cell $and $and$ls180.v:3877$285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3802$233_Y
+    connect \A $and$ls180.v:3877$284_Y
     connect \B \main_sdram_bankmachine2_refresh_gnt
-    connect \Y $and$ls180.v:3802$234_Y
+    connect \Y $and$ls180.v:3877$285_Y
   end
-  attribute \src "ls180.v:3802.36-3802.189"
-  cell $and $and$ls180.v:3802$235
+  attribute \src "ls180.v:3877.36-3877.189"
+  cell $and $and$ls180.v:3877$286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3802$234_Y
+    connect \A $and$ls180.v:3877$285_Y
     connect \B \main_sdram_bankmachine3_refresh_gnt
-    connect \Y $and$ls180.v:3802$235_Y
+    connect \Y $and$ls180.v:3877$286_Y
   end
-  attribute \src "ls180.v:3808.77-3808.153"
-  cell $and $and$ls180.v:3808$238
+  attribute \src "ls180.v:3883.77-3883.153"
+  cell $and $and$ls180.v:3883$289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236931,65 +237741,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
     connect \B \main_sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:3808$238_Y
+    connect \Y $and$ls180.v:3883$289_Y
   end
-  attribute \src "ls180.v:3808.162-3808.246"
-  cell $and $and$ls180.v:3808$240
+  attribute \src "ls180.v:3883.162-3883.246"
+  cell $and $and$ls180.v:3883$291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_ras
-    connect \B $not$ls180.v:3808$239_Y
-    connect \Y $and$ls180.v:3808$240_Y
+    connect \B $not$ls180.v:3883$290_Y
+    connect \Y $and$ls180.v:3883$291_Y
   end
-  attribute \src "ls180.v:3808.161-3808.291"
-  cell $and $and$ls180.v:3808$242
+  attribute \src "ls180.v:3883.161-3883.291"
+  cell $and $and$ls180.v:3883$293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3808$240_Y
-    connect \B $not$ls180.v:3808$241_Y
-    connect \Y $and$ls180.v:3808$242_Y
+    connect \A $and$ls180.v:3883$291_Y
+    connect \B $not$ls180.v:3883$292_Y
+    connect \Y $and$ls180.v:3883$293_Y
   end
-  attribute \src "ls180.v:3808.76-3808.333"
-  cell $and $and$ls180.v:3808$245
+  attribute \src "ls180.v:3883.76-3883.333"
+  cell $and $and$ls180.v:3883$296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3808$238_Y
-    connect \B $or$ls180.v:3808$244_Y
-    connect \Y $and$ls180.v:3808$245_Y
+    connect \A $and$ls180.v:3883$289_Y
+    connect \B $or$ls180.v:3883$295_Y
+    connect \Y $and$ls180.v:3883$296_Y
   end
-  attribute \src "ls180.v:3808.338-3808.505"
-  cell $and $and$ls180.v:3808$248
+  attribute \src "ls180.v:3883.338-3883.505"
+  cell $and $and$ls180.v:3883$299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3808$246_Y
-    connect \B $eq$ls180.v:3808$247_Y
-    connect \Y $and$ls180.v:3808$248_Y
+    connect \A $eq$ls180.v:3883$297_Y
+    connect \B $eq$ls180.v:3883$298_Y
+    connect \Y $and$ls180.v:3883$299_Y
   end
-  attribute \src "ls180.v:3808.38-3808.507"
-  cell $and $and$ls180.v:3808$250
+  attribute \src "ls180.v:3883.38-3883.507"
+  cell $and $and$ls180.v:3883$301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
-    connect \B $or$ls180.v:3808$249_Y
-    connect \Y $and$ls180.v:3808$250_Y
+    connect \B $or$ls180.v:3883$300_Y
+    connect \Y $and$ls180.v:3883$301_Y
   end
-  attribute \src "ls180.v:3809.77-3809.153"
-  cell $and $and$ls180.v:3809$251
+  attribute \src "ls180.v:3884.77-3884.153"
+  cell $and $and$ls180.v:3884$302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -236997,65 +237807,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
     connect \B \main_sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:3809$251_Y
+    connect \Y $and$ls180.v:3884$302_Y
   end
-  attribute \src "ls180.v:3809.162-3809.246"
-  cell $and $and$ls180.v:3809$253
+  attribute \src "ls180.v:3884.162-3884.246"
+  cell $and $and$ls180.v:3884$304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_ras
-    connect \B $not$ls180.v:3809$252_Y
-    connect \Y $and$ls180.v:3809$253_Y
+    connect \B $not$ls180.v:3884$303_Y
+    connect \Y $and$ls180.v:3884$304_Y
   end
-  attribute \src "ls180.v:3809.161-3809.291"
-  cell $and $and$ls180.v:3809$255
+  attribute \src "ls180.v:3884.161-3884.291"
+  cell $and $and$ls180.v:3884$306
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3809$253_Y
-    connect \B $not$ls180.v:3809$254_Y
-    connect \Y $and$ls180.v:3809$255_Y
+    connect \A $and$ls180.v:3884$304_Y
+    connect \B $not$ls180.v:3884$305_Y
+    connect \Y $and$ls180.v:3884$306_Y
   end
-  attribute \src "ls180.v:3809.76-3809.333"
-  cell $and $and$ls180.v:3809$258
+  attribute \src "ls180.v:3884.76-3884.333"
+  cell $and $and$ls180.v:3884$309
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3809$251_Y
-    connect \B $or$ls180.v:3809$257_Y
-    connect \Y $and$ls180.v:3809$258_Y
+    connect \A $and$ls180.v:3884$302_Y
+    connect \B $or$ls180.v:3884$308_Y
+    connect \Y $and$ls180.v:3884$309_Y
   end
-  attribute \src "ls180.v:3809.338-3809.505"
-  cell $and $and$ls180.v:3809$261
+  attribute \src "ls180.v:3884.338-3884.505"
+  cell $and $and$ls180.v:3884$312
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3809$259_Y
-    connect \B $eq$ls180.v:3809$260_Y
-    connect \Y $and$ls180.v:3809$261_Y
+    connect \A $eq$ls180.v:3884$310_Y
+    connect \B $eq$ls180.v:3884$311_Y
+    connect \Y $and$ls180.v:3884$312_Y
   end
-  attribute \src "ls180.v:3809.38-3809.507"
-  cell $and $and$ls180.v:3809$263
+  attribute \src "ls180.v:3884.38-3884.507"
+  cell $and $and$ls180.v:3884$314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
-    connect \B $or$ls180.v:3809$262_Y
-    connect \Y $and$ls180.v:3809$263_Y
+    connect \B $or$ls180.v:3884$313_Y
+    connect \Y $and$ls180.v:3884$314_Y
   end
-  attribute \src "ls180.v:3810.77-3810.153"
-  cell $and $and$ls180.v:3810$264
+  attribute \src "ls180.v:3885.77-3885.153"
+  cell $and $and$ls180.v:3885$315
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237063,65 +237873,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
     connect \B \main_sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:3810$264_Y
+    connect \Y $and$ls180.v:3885$315_Y
   end
-  attribute \src "ls180.v:3810.162-3810.246"
-  cell $and $and$ls180.v:3810$266
+  attribute \src "ls180.v:3885.162-3885.246"
+  cell $and $and$ls180.v:3885$317
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_ras
-    connect \B $not$ls180.v:3810$265_Y
-    connect \Y $and$ls180.v:3810$266_Y
+    connect \B $not$ls180.v:3885$316_Y
+    connect \Y $and$ls180.v:3885$317_Y
   end
-  attribute \src "ls180.v:3810.161-3810.291"
-  cell $and $and$ls180.v:3810$268
+  attribute \src "ls180.v:3885.161-3885.291"
+  cell $and $and$ls180.v:3885$319
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3810$266_Y
-    connect \B $not$ls180.v:3810$267_Y
-    connect \Y $and$ls180.v:3810$268_Y
+    connect \A $and$ls180.v:3885$317_Y
+    connect \B $not$ls180.v:3885$318_Y
+    connect \Y $and$ls180.v:3885$319_Y
   end
-  attribute \src "ls180.v:3810.76-3810.333"
-  cell $and $and$ls180.v:3810$271
+  attribute \src "ls180.v:3885.76-3885.333"
+  cell $and $and$ls180.v:3885$322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3810$264_Y
-    connect \B $or$ls180.v:3810$270_Y
-    connect \Y $and$ls180.v:3810$271_Y
+    connect \A $and$ls180.v:3885$315_Y
+    connect \B $or$ls180.v:3885$321_Y
+    connect \Y $and$ls180.v:3885$322_Y
   end
-  attribute \src "ls180.v:3810.338-3810.505"
-  cell $and $and$ls180.v:3810$274
+  attribute \src "ls180.v:3885.338-3885.505"
+  cell $and $and$ls180.v:3885$325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3810$272_Y
-    connect \B $eq$ls180.v:3810$273_Y
-    connect \Y $and$ls180.v:3810$274_Y
+    connect \A $eq$ls180.v:3885$323_Y
+    connect \B $eq$ls180.v:3885$324_Y
+    connect \Y $and$ls180.v:3885$325_Y
   end
-  attribute \src "ls180.v:3810.38-3810.507"
-  cell $and $and$ls180.v:3810$276
+  attribute \src "ls180.v:3885.38-3885.507"
+  cell $and $and$ls180.v:3885$327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
-    connect \B $or$ls180.v:3810$275_Y
-    connect \Y $and$ls180.v:3810$276_Y
+    connect \B $or$ls180.v:3885$326_Y
+    connect \Y $and$ls180.v:3885$327_Y
   end
-  attribute \src "ls180.v:3811.77-3811.153"
-  cell $and $and$ls180.v:3811$277
+  attribute \src "ls180.v:3886.77-3886.153"
+  cell $and $and$ls180.v:3886$328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237129,65 +237939,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
     connect \B \main_sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:3811$277_Y
+    connect \Y $and$ls180.v:3886$328_Y
   end
-  attribute \src "ls180.v:3811.162-3811.246"
-  cell $and $and$ls180.v:3811$279
+  attribute \src "ls180.v:3886.162-3886.246"
+  cell $and $and$ls180.v:3886$330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_ras
-    connect \B $not$ls180.v:3811$278_Y
-    connect \Y $and$ls180.v:3811$279_Y
+    connect \B $not$ls180.v:3886$329_Y
+    connect \Y $and$ls180.v:3886$330_Y
   end
-  attribute \src "ls180.v:3811.161-3811.291"
-  cell $and $and$ls180.v:3811$281
+  attribute \src "ls180.v:3886.161-3886.291"
+  cell $and $and$ls180.v:3886$332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3811$279_Y
-    connect \B $not$ls180.v:3811$280_Y
-    connect \Y $and$ls180.v:3811$281_Y
+    connect \A $and$ls180.v:3886$330_Y
+    connect \B $not$ls180.v:3886$331_Y
+    connect \Y $and$ls180.v:3886$332_Y
   end
-  attribute \src "ls180.v:3811.76-3811.333"
-  cell $and $and$ls180.v:3811$284
+  attribute \src "ls180.v:3886.76-3886.333"
+  cell $and $and$ls180.v:3886$335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3811$277_Y
-    connect \B $or$ls180.v:3811$283_Y
-    connect \Y $and$ls180.v:3811$284_Y
+    connect \A $and$ls180.v:3886$328_Y
+    connect \B $or$ls180.v:3886$334_Y
+    connect \Y $and$ls180.v:3886$335_Y
   end
-  attribute \src "ls180.v:3811.338-3811.505"
-  cell $and $and$ls180.v:3811$287
+  attribute \src "ls180.v:3886.338-3886.505"
+  cell $and $and$ls180.v:3886$338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3811$285_Y
-    connect \B $eq$ls180.v:3811$286_Y
-    connect \Y $and$ls180.v:3811$287_Y
+    connect \A $eq$ls180.v:3886$336_Y
+    connect \B $eq$ls180.v:3886$337_Y
+    connect \Y $and$ls180.v:3886$338_Y
   end
-  attribute \src "ls180.v:3811.38-3811.507"
-  cell $and $and$ls180.v:3811$289
+  attribute \src "ls180.v:3886.38-3886.507"
+  cell $and $and$ls180.v:3886$340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
-    connect \B $or$ls180.v:3811$288_Y
-    connect \Y $and$ls180.v:3811$289_Y
+    connect \B $or$ls180.v:3886$339_Y
+    connect \Y $and$ls180.v:3886$340_Y
   end
-  attribute \src "ls180.v:3841.77-3841.153"
-  cell $and $and$ls180.v:3841$296
+  attribute \src "ls180.v:3916.77-3916.153"
+  cell $and $and$ls180.v:3916$347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237195,65 +238005,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
     connect \B \main_sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:3841$296_Y
+    connect \Y $and$ls180.v:3916$347_Y
   end
-  attribute \src "ls180.v:3841.162-3841.246"
-  cell $and $and$ls180.v:3841$298
+  attribute \src "ls180.v:3916.162-3916.246"
+  cell $and $and$ls180.v:3916$349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_ras
-    connect \B $not$ls180.v:3841$297_Y
-    connect \Y $and$ls180.v:3841$298_Y
+    connect \B $not$ls180.v:3916$348_Y
+    connect \Y $and$ls180.v:3916$349_Y
   end
-  attribute \src "ls180.v:3841.161-3841.291"
-  cell $and $and$ls180.v:3841$300
+  attribute \src "ls180.v:3916.161-3916.291"
+  cell $and $and$ls180.v:3916$351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3841$298_Y
-    connect \B $not$ls180.v:3841$299_Y
-    connect \Y $and$ls180.v:3841$300_Y
+    connect \A $and$ls180.v:3916$349_Y
+    connect \B $not$ls180.v:3916$350_Y
+    connect \Y $and$ls180.v:3916$351_Y
   end
-  attribute \src "ls180.v:3841.76-3841.333"
-  cell $and $and$ls180.v:3841$303
+  attribute \src "ls180.v:3916.76-3916.333"
+  cell $and $and$ls180.v:3916$354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3841$296_Y
-    connect \B $or$ls180.v:3841$302_Y
-    connect \Y $and$ls180.v:3841$303_Y
+    connect \A $and$ls180.v:3916$347_Y
+    connect \B $or$ls180.v:3916$353_Y
+    connect \Y $and$ls180.v:3916$354_Y
   end
-  attribute \src "ls180.v:3841.338-3841.505"
-  cell $and $and$ls180.v:3841$306
+  attribute \src "ls180.v:3916.338-3916.505"
+  cell $and $and$ls180.v:3916$357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3841$304_Y
-    connect \B $eq$ls180.v:3841$305_Y
-    connect \Y $and$ls180.v:3841$306_Y
+    connect \A $eq$ls180.v:3916$355_Y
+    connect \B $eq$ls180.v:3916$356_Y
+    connect \Y $and$ls180.v:3916$357_Y
   end
-  attribute \src "ls180.v:3841.38-3841.507"
-  cell $and $and$ls180.v:3841$308
+  attribute \src "ls180.v:3916.38-3916.507"
+  cell $and $and$ls180.v:3916$359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_valid
-    connect \B $or$ls180.v:3841$307_Y
-    connect \Y $and$ls180.v:3841$308_Y
+    connect \B $or$ls180.v:3916$358_Y
+    connect \Y $and$ls180.v:3916$359_Y
   end
-  attribute \src "ls180.v:3842.77-3842.153"
-  cell $and $and$ls180.v:3842$309
+  attribute \src "ls180.v:3917.77-3917.153"
+  cell $and $and$ls180.v:3917$360
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237261,65 +238071,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
     connect \B \main_sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:3842$309_Y
+    connect \Y $and$ls180.v:3917$360_Y
   end
-  attribute \src "ls180.v:3842.162-3842.246"
-  cell $and $and$ls180.v:3842$311
+  attribute \src "ls180.v:3917.162-3917.246"
+  cell $and $and$ls180.v:3917$362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_ras
-    connect \B $not$ls180.v:3842$310_Y
-    connect \Y $and$ls180.v:3842$311_Y
+    connect \B $not$ls180.v:3917$361_Y
+    connect \Y $and$ls180.v:3917$362_Y
   end
-  attribute \src "ls180.v:3842.161-3842.291"
-  cell $and $and$ls180.v:3842$313
+  attribute \src "ls180.v:3917.161-3917.291"
+  cell $and $and$ls180.v:3917$364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3842$311_Y
-    connect \B $not$ls180.v:3842$312_Y
-    connect \Y $and$ls180.v:3842$313_Y
+    connect \A $and$ls180.v:3917$362_Y
+    connect \B $not$ls180.v:3917$363_Y
+    connect \Y $and$ls180.v:3917$364_Y
   end
-  attribute \src "ls180.v:3842.76-3842.333"
-  cell $and $and$ls180.v:3842$316
+  attribute \src "ls180.v:3917.76-3917.333"
+  cell $and $and$ls180.v:3917$367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3842$309_Y
-    connect \B $or$ls180.v:3842$315_Y
-    connect \Y $and$ls180.v:3842$316_Y
+    connect \A $and$ls180.v:3917$360_Y
+    connect \B $or$ls180.v:3917$366_Y
+    connect \Y $and$ls180.v:3917$367_Y
   end
-  attribute \src "ls180.v:3842.338-3842.505"
-  cell $and $and$ls180.v:3842$319
+  attribute \src "ls180.v:3917.338-3917.505"
+  cell $and $and$ls180.v:3917$370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3842$317_Y
-    connect \B $eq$ls180.v:3842$318_Y
-    connect \Y $and$ls180.v:3842$319_Y
+    connect \A $eq$ls180.v:3917$368_Y
+    connect \B $eq$ls180.v:3917$369_Y
+    connect \Y $and$ls180.v:3917$370_Y
   end
-  attribute \src "ls180.v:3842.38-3842.507"
-  cell $and $and$ls180.v:3842$321
+  attribute \src "ls180.v:3917.38-3917.507"
+  cell $and $and$ls180.v:3917$372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_valid
-    connect \B $or$ls180.v:3842$320_Y
-    connect \Y $and$ls180.v:3842$321_Y
+    connect \B $or$ls180.v:3917$371_Y
+    connect \Y $and$ls180.v:3917$372_Y
   end
-  attribute \src "ls180.v:3843.77-3843.153"
-  cell $and $and$ls180.v:3843$322
+  attribute \src "ls180.v:3918.77-3918.153"
+  cell $and $and$ls180.v:3918$373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237327,65 +238137,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
     connect \B \main_sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:3843$322_Y
+    connect \Y $and$ls180.v:3918$373_Y
   end
-  attribute \src "ls180.v:3843.162-3843.246"
-  cell $and $and$ls180.v:3843$324
+  attribute \src "ls180.v:3918.162-3918.246"
+  cell $and $and$ls180.v:3918$375
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_ras
-    connect \B $not$ls180.v:3843$323_Y
-    connect \Y $and$ls180.v:3843$324_Y
+    connect \B $not$ls180.v:3918$374_Y
+    connect \Y $and$ls180.v:3918$375_Y
   end
-  attribute \src "ls180.v:3843.161-3843.291"
-  cell $and $and$ls180.v:3843$326
+  attribute \src "ls180.v:3918.161-3918.291"
+  cell $and $and$ls180.v:3918$377
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3843$324_Y
-    connect \B $not$ls180.v:3843$325_Y
-    connect \Y $and$ls180.v:3843$326_Y
+    connect \A $and$ls180.v:3918$375_Y
+    connect \B $not$ls180.v:3918$376_Y
+    connect \Y $and$ls180.v:3918$377_Y
   end
-  attribute \src "ls180.v:3843.76-3843.333"
-  cell $and $and$ls180.v:3843$329
+  attribute \src "ls180.v:3918.76-3918.333"
+  cell $and $and$ls180.v:3918$380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3843$322_Y
-    connect \B $or$ls180.v:3843$328_Y
-    connect \Y $and$ls180.v:3843$329_Y
+    connect \A $and$ls180.v:3918$373_Y
+    connect \B $or$ls180.v:3918$379_Y
+    connect \Y $and$ls180.v:3918$380_Y
   end
-  attribute \src "ls180.v:3843.338-3843.505"
-  cell $and $and$ls180.v:3843$332
+  attribute \src "ls180.v:3918.338-3918.505"
+  cell $and $and$ls180.v:3918$383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3843$330_Y
-    connect \B $eq$ls180.v:3843$331_Y
-    connect \Y $and$ls180.v:3843$332_Y
+    connect \A $eq$ls180.v:3918$381_Y
+    connect \B $eq$ls180.v:3918$382_Y
+    connect \Y $and$ls180.v:3918$383_Y
   end
-  attribute \src "ls180.v:3843.38-3843.507"
-  cell $and $and$ls180.v:3843$334
+  attribute \src "ls180.v:3918.38-3918.507"
+  cell $and $and$ls180.v:3918$385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_valid
-    connect \B $or$ls180.v:3843$333_Y
-    connect \Y $and$ls180.v:3843$334_Y
+    connect \B $or$ls180.v:3918$384_Y
+    connect \Y $and$ls180.v:3918$385_Y
   end
-  attribute \src "ls180.v:3844.77-3844.153"
-  cell $and $and$ls180.v:3844$335
+  attribute \src "ls180.v:3919.77-3919.153"
+  cell $and $and$ls180.v:3919$386
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237393,65 +238203,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
     connect \B \main_sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:3844$335_Y
+    connect \Y $and$ls180.v:3919$386_Y
   end
-  attribute \src "ls180.v:3844.162-3844.246"
-  cell $and $and$ls180.v:3844$337
+  attribute \src "ls180.v:3919.162-3919.246"
+  cell $and $and$ls180.v:3919$388
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_ras
-    connect \B $not$ls180.v:3844$336_Y
-    connect \Y $and$ls180.v:3844$337_Y
+    connect \B $not$ls180.v:3919$387_Y
+    connect \Y $and$ls180.v:3919$388_Y
   end
-  attribute \src "ls180.v:3844.161-3844.291"
-  cell $and $and$ls180.v:3844$339
+  attribute \src "ls180.v:3919.161-3919.291"
+  cell $and $and$ls180.v:3919$390
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3844$337_Y
-    connect \B $not$ls180.v:3844$338_Y
-    connect \Y $and$ls180.v:3844$339_Y
+    connect \A $and$ls180.v:3919$388_Y
+    connect \B $not$ls180.v:3919$389_Y
+    connect \Y $and$ls180.v:3919$390_Y
   end
-  attribute \src "ls180.v:3844.76-3844.333"
-  cell $and $and$ls180.v:3844$342
+  attribute \src "ls180.v:3919.76-3919.333"
+  cell $and $and$ls180.v:3919$393
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3844$335_Y
-    connect \B $or$ls180.v:3844$341_Y
-    connect \Y $and$ls180.v:3844$342_Y
+    connect \A $and$ls180.v:3919$386_Y
+    connect \B $or$ls180.v:3919$392_Y
+    connect \Y $and$ls180.v:3919$393_Y
   end
-  attribute \src "ls180.v:3844.338-3844.505"
-  cell $and $and$ls180.v:3844$345
+  attribute \src "ls180.v:3919.338-3919.505"
+  cell $and $and$ls180.v:3919$396
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3844$343_Y
-    connect \B $eq$ls180.v:3844$344_Y
-    connect \Y $and$ls180.v:3844$345_Y
+    connect \A $eq$ls180.v:3919$394_Y
+    connect \B $eq$ls180.v:3919$395_Y
+    connect \Y $and$ls180.v:3919$396_Y
   end
-  attribute \src "ls180.v:3844.38-3844.507"
-  cell $and $and$ls180.v:3844$347
+  attribute \src "ls180.v:3919.38-3919.507"
+  cell $and $and$ls180.v:3919$398
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_valid
-    connect \B $or$ls180.v:3844$346_Y
-    connect \Y $and$ls180.v:3844$347_Y
+    connect \B $or$ls180.v:3919$397_Y
+    connect \Y $and$ls180.v:3919$398_Y
   end
-  attribute \src "ls180.v:3873.8-3873.73"
-  cell $and $and$ls180.v:3873$352
+  attribute \src "ls180.v:3948.8-3948.73"
+  cell $and $and$ls180.v:3948$403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237459,21 +238269,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_valid
     connect \B \main_sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:3873$352_Y
+    connect \Y $and$ls180.v:3948$403_Y
   end
-  attribute \src "ls180.v:3873.7-3873.114"
-  cell $and $and$ls180.v:3873$354
+  attribute \src "ls180.v:3948.7-3948.114"
+  cell $and $and$ls180.v:3948$405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3873$352_Y
-    connect \B $eq$ls180.v:3873$353_Y
-    connect \Y $and$ls180.v:3873$354_Y
+    connect \A $and$ls180.v:3948$403_Y
+    connect \B $eq$ls180.v:3948$404_Y
+    connect \Y $and$ls180.v:3948$405_Y
   end
-  attribute \src "ls180.v:3876.8-3876.73"
-  cell $and $and$ls180.v:3876$355
+  attribute \src "ls180.v:3951.8-3951.73"
+  cell $and $and$ls180.v:3951$406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237481,21 +238291,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3876$355_Y
+    connect \Y $and$ls180.v:3951$406_Y
   end
-  attribute \src "ls180.v:3876.7-3876.114"
-  cell $and $and$ls180.v:3876$357
+  attribute \src "ls180.v:3951.7-3951.114"
+  cell $and $and$ls180.v:3951$408
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3876$355_Y
-    connect \B $eq$ls180.v:3876$356_Y
-    connect \Y $and$ls180.v:3876$357_Y
+    connect \A $and$ls180.v:3951$406_Y
+    connect \B $eq$ls180.v:3951$407_Y
+    connect \Y $and$ls180.v:3951$408_Y
   end
-  attribute \src "ls180.v:3882.8-3882.73"
-  cell $and $and$ls180.v:3882$359
+  attribute \src "ls180.v:3957.8-3957.73"
+  cell $and $and$ls180.v:3957$410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237503,21 +238313,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_valid
     connect \B \main_sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:3882$359_Y
+    connect \Y $and$ls180.v:3957$410_Y
   end
-  attribute \src "ls180.v:3882.7-3882.114"
-  cell $and $and$ls180.v:3882$361
+  attribute \src "ls180.v:3957.7-3957.114"
+  cell $and $and$ls180.v:3957$412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3882$359_Y
-    connect \B $eq$ls180.v:3882$360_Y
-    connect \Y $and$ls180.v:3882$361_Y
+    connect \A $and$ls180.v:3957$410_Y
+    connect \B $eq$ls180.v:3957$411_Y
+    connect \Y $and$ls180.v:3957$412_Y
   end
-  attribute \src "ls180.v:3885.8-3885.73"
-  cell $and $and$ls180.v:3885$362
+  attribute \src "ls180.v:3960.8-3960.73"
+  cell $and $and$ls180.v:3960$413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237525,21 +238335,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3885$362_Y
+    connect \Y $and$ls180.v:3960$413_Y
   end
-  attribute \src "ls180.v:3885.7-3885.114"
-  cell $and $and$ls180.v:3885$364
+  attribute \src "ls180.v:3960.7-3960.114"
+  cell $and $and$ls180.v:3960$415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3885$362_Y
-    connect \B $eq$ls180.v:3885$363_Y
-    connect \Y $and$ls180.v:3885$364_Y
+    connect \A $and$ls180.v:3960$413_Y
+    connect \B $eq$ls180.v:3960$414_Y
+    connect \Y $and$ls180.v:3960$415_Y
   end
-  attribute \src "ls180.v:3891.8-3891.73"
-  cell $and $and$ls180.v:3891$366
+  attribute \src "ls180.v:3966.8-3966.73"
+  cell $and $and$ls180.v:3966$417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237547,21 +238357,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_valid
     connect \B \main_sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:3891$366_Y
+    connect \Y $and$ls180.v:3966$417_Y
   end
-  attribute \src "ls180.v:3891.7-3891.114"
-  cell $and $and$ls180.v:3891$368
+  attribute \src "ls180.v:3966.7-3966.114"
+  cell $and $and$ls180.v:3966$419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3891$366_Y
-    connect \B $eq$ls180.v:3891$367_Y
-    connect \Y $and$ls180.v:3891$368_Y
+    connect \A $and$ls180.v:3966$417_Y
+    connect \B $eq$ls180.v:3966$418_Y
+    connect \Y $and$ls180.v:3966$419_Y
   end
-  attribute \src "ls180.v:3894.8-3894.73"
-  cell $and $and$ls180.v:3894$369
+  attribute \src "ls180.v:3969.8-3969.73"
+  cell $and $and$ls180.v:3969$420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237569,21 +238379,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3894$369_Y
+    connect \Y $and$ls180.v:3969$420_Y
   end
-  attribute \src "ls180.v:3894.7-3894.114"
-  cell $and $and$ls180.v:3894$371
+  attribute \src "ls180.v:3969.7-3969.114"
+  cell $and $and$ls180.v:3969$422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3894$369_Y
-    connect \B $eq$ls180.v:3894$370_Y
-    connect \Y $and$ls180.v:3894$371_Y
+    connect \A $and$ls180.v:3969$420_Y
+    connect \B $eq$ls180.v:3969$421_Y
+    connect \Y $and$ls180.v:3969$422_Y
   end
-  attribute \src "ls180.v:3900.8-3900.73"
-  cell $and $and$ls180.v:3900$373
+  attribute \src "ls180.v:3975.8-3975.73"
+  cell $and $and$ls180.v:3975$424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237591,21 +238401,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_valid
     connect \B \main_sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:3900$373_Y
+    connect \Y $and$ls180.v:3975$424_Y
   end
-  attribute \src "ls180.v:3900.7-3900.114"
-  cell $and $and$ls180.v:3900$375
+  attribute \src "ls180.v:3975.7-3975.114"
+  cell $and $and$ls180.v:3975$426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3900$373_Y
-    connect \B $eq$ls180.v:3900$374_Y
-    connect \Y $and$ls180.v:3900$375_Y
+    connect \A $and$ls180.v:3975$424_Y
+    connect \B $eq$ls180.v:3975$425_Y
+    connect \Y $and$ls180.v:3975$426_Y
   end
-  attribute \src "ls180.v:3903.8-3903.73"
-  cell $and $and$ls180.v:3903$376
+  attribute \src "ls180.v:3978.8-3978.73"
+  cell $and $and$ls180.v:3978$427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -237613,615 +238423,615 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:3903$376_Y
+    connect \Y $and$ls180.v:3978$427_Y
   end
-  attribute \src "ls180.v:3903.7-3903.114"
-  cell $and $and$ls180.v:3903$378
+  attribute \src "ls180.v:3978.7-3978.114"
+  cell $and $and$ls180.v:3978$429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3903$376_Y
-    connect \B $eq$ls180.v:3903$377_Y
-    connect \Y $and$ls180.v:3903$378_Y
+    connect \A $and$ls180.v:3978$427_Y
+    connect \B $eq$ls180.v:3978$428_Y
+    connect \Y $and$ls180.v:3978$429_Y
   end
-  attribute \src "ls180.v:3928.71-3928.151"
-  cell $and $and$ls180.v:3928$383
+  attribute \src "ls180.v:4003.71-4003.151"
+  cell $and $and$ls180.v:4003$434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:3928$382_Y
-    connect \Y $and$ls180.v:3928$383_Y
+    connect \B $not$ls180.v:4003$433_Y
+    connect \Y $and$ls180.v:4003$434_Y
   end
-  attribute \src "ls180.v:3928.70-3928.194"
-  cell $and $and$ls180.v:3928$385
+  attribute \src "ls180.v:4003.70-4003.194"
+  cell $and $and$ls180.v:4003$436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3928$383_Y
-    connect \B $not$ls180.v:3928$384_Y
-    connect \Y $and$ls180.v:3928$385_Y
+    connect \A $and$ls180.v:4003$434_Y
+    connect \B $not$ls180.v:4003$435_Y
+    connect \Y $and$ls180.v:4003$436_Y
   end
-  attribute \src "ls180.v:3928.41-3928.222"
-  cell $and $and$ls180.v:3928$388
+  attribute \src "ls180.v:4003.41-4003.222"
+  cell $and $and$ls180.v:4003$439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cas_allowed
-    connect \B $or$ls180.v:3928$387_Y
-    connect \Y $and$ls180.v:3928$388_Y
+    connect \B $or$ls180.v:4003$438_Y
+    connect \Y $and$ls180.v:4003$439_Y
   end
-  attribute \src "ls180.v:3966.71-3966.151"
-  cell $and $and$ls180.v:3966$392
+  attribute \src "ls180.v:4041.71-4041.151"
+  cell $and $and$ls180.v:4041$443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:3966$391_Y
-    connect \Y $and$ls180.v:3966$392_Y
+    connect \B $not$ls180.v:4041$442_Y
+    connect \Y $and$ls180.v:4041$443_Y
   end
-  attribute \src "ls180.v:3966.70-3966.194"
-  cell $and $and$ls180.v:3966$394
+  attribute \src "ls180.v:4041.70-4041.194"
+  cell $and $and$ls180.v:4041$445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3966$392_Y
-    connect \B $not$ls180.v:3966$393_Y
-    connect \Y $and$ls180.v:3966$394_Y
+    connect \A $and$ls180.v:4041$443_Y
+    connect \B $not$ls180.v:4041$444_Y
+    connect \Y $and$ls180.v:4041$445_Y
   end
-  attribute \src "ls180.v:3966.41-3966.222"
-  cell $and $and$ls180.v:3966$397
+  attribute \src "ls180.v:4041.41-4041.222"
+  cell $and $and$ls180.v:4041$448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cas_allowed
-    connect \B $or$ls180.v:3966$396_Y
-    connect \Y $and$ls180.v:3966$397_Y
+    connect \B $or$ls180.v:4041$447_Y
+    connect \Y $and$ls180.v:4041$448_Y
   end
-  attribute \src "ls180.v:3984.110-3984.179"
-  cell $and $and$ls180.v:3984$402
+  attribute \src "ls180.v:4059.110-4059.179"
+  cell $and $and$ls180.v:4059$453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3984$401_Y
-    connect \Y $and$ls180.v:3984$402_Y
+    connect \B $eq$ls180.v:4059$452_Y
+    connect \Y $and$ls180.v:4059$453_Y
   end
-  attribute \src "ls180.v:3984.185-3984.254"
-  cell $and $and$ls180.v:3984$405
+  attribute \src "ls180.v:4059.185-4059.254"
+  cell $and $and$ls180.v:4059$456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3984$404_Y
-    connect \Y $and$ls180.v:3984$405_Y
+    connect \B $eq$ls180.v:4059$455_Y
+    connect \Y $and$ls180.v:4059$456_Y
   end
-  attribute \src "ls180.v:3984.260-3984.329"
-  cell $and $and$ls180.v:3984$408
+  attribute \src "ls180.v:4059.260-4059.329"
+  cell $and $and$ls180.v:4059$459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3984$407_Y
-    connect \Y $and$ls180.v:3984$408_Y
+    connect \B $eq$ls180.v:4059$458_Y
+    connect \Y $and$ls180.v:4059$459_Y
   end
-  attribute \src "ls180.v:3984.41-3984.332"
-  cell $and $and$ls180.v:3984$411
+  attribute \src "ls180.v:4059.41-4059.332"
+  cell $and $and$ls180.v:4059$462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3984$400_Y
-    connect \B $not$ls180.v:3984$410_Y
-    connect \Y $and$ls180.v:3984$411_Y
+    connect \A $eq$ls180.v:4059$451_Y
+    connect \B $not$ls180.v:4059$461_Y
+    connect \Y $and$ls180.v:4059$462_Y
   end
-  attribute \src "ls180.v:3984.40-3984.355"
-  cell $and $and$ls180.v:3984$412
+  attribute \src "ls180.v:4059.40-4059.355"
+  cell $and $and$ls180.v:4059$463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3984$411_Y
+    connect \A $and$ls180.v:4059$462_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:3984$412_Y
+    connect \Y $and$ls180.v:4059$463_Y
   end
-  attribute \src "ls180.v:3985.34-3985.106"
-  cell $and $and$ls180.v:3985$415
+  attribute \src "ls180.v:4060.34-4060.106"
+  cell $and $and$ls180.v:4060$466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3985$413_Y
-    connect \B $not$ls180.v:3985$414_Y
-    connect \Y $and$ls180.v:3985$415_Y
+    connect \A $not$ls180.v:4060$464_Y
+    connect \B $not$ls180.v:4060$465_Y
+    connect \Y $and$ls180.v:4060$466_Y
   end
-  attribute \src "ls180.v:3989.110-3989.179"
-  cell $and $and$ls180.v:3989$418
+  attribute \src "ls180.v:4064.110-4064.179"
+  cell $and $and$ls180.v:4064$469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3989$417_Y
-    connect \Y $and$ls180.v:3989$418_Y
+    connect \B $eq$ls180.v:4064$468_Y
+    connect \Y $and$ls180.v:4064$469_Y
   end
-  attribute \src "ls180.v:3989.185-3989.254"
-  cell $and $and$ls180.v:3989$421
+  attribute \src "ls180.v:4064.185-4064.254"
+  cell $and $and$ls180.v:4064$472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3989$420_Y
-    connect \Y $and$ls180.v:3989$421_Y
+    connect \B $eq$ls180.v:4064$471_Y
+    connect \Y $and$ls180.v:4064$472_Y
   end
-  attribute \src "ls180.v:3989.260-3989.329"
-  cell $and $and$ls180.v:3989$424
+  attribute \src "ls180.v:4064.260-4064.329"
+  cell $and $and$ls180.v:4064$475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3989$423_Y
-    connect \Y $and$ls180.v:3989$424_Y
+    connect \B $eq$ls180.v:4064$474_Y
+    connect \Y $and$ls180.v:4064$475_Y
   end
-  attribute \src "ls180.v:3989.41-3989.332"
-  cell $and $and$ls180.v:3989$427
+  attribute \src "ls180.v:4064.41-4064.332"
+  cell $and $and$ls180.v:4064$478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3989$416_Y
-    connect \B $not$ls180.v:3989$426_Y
-    connect \Y $and$ls180.v:3989$427_Y
+    connect \A $eq$ls180.v:4064$467_Y
+    connect \B $not$ls180.v:4064$477_Y
+    connect \Y $and$ls180.v:4064$478_Y
   end
-  attribute \src "ls180.v:3989.40-3989.355"
-  cell $and $and$ls180.v:3989$428
+  attribute \src "ls180.v:4064.40-4064.355"
+  cell $and $and$ls180.v:4064$479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3989$427_Y
+    connect \A $and$ls180.v:4064$478_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:3989$428_Y
+    connect \Y $and$ls180.v:4064$479_Y
   end
-  attribute \src "ls180.v:3990.34-3990.106"
-  cell $and $and$ls180.v:3990$431
+  attribute \src "ls180.v:4065.34-4065.106"
+  cell $and $and$ls180.v:4065$482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3990$429_Y
-    connect \B $not$ls180.v:3990$430_Y
-    connect \Y $and$ls180.v:3990$431_Y
+    connect \A $not$ls180.v:4065$480_Y
+    connect \B $not$ls180.v:4065$481_Y
+    connect \Y $and$ls180.v:4065$482_Y
   end
-  attribute \src "ls180.v:3994.110-3994.179"
-  cell $and $and$ls180.v:3994$434
+  attribute \src "ls180.v:4069.110-4069.179"
+  cell $and $and$ls180.v:4069$485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3994$433_Y
-    connect \Y $and$ls180.v:3994$434_Y
+    connect \B $eq$ls180.v:4069$484_Y
+    connect \Y $and$ls180.v:4069$485_Y
   end
-  attribute \src "ls180.v:3994.185-3994.254"
-  cell $and $and$ls180.v:3994$437
+  attribute \src "ls180.v:4069.185-4069.254"
+  cell $and $and$ls180.v:4069$488
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3994$436_Y
-    connect \Y $and$ls180.v:3994$437_Y
+    connect \B $eq$ls180.v:4069$487_Y
+    connect \Y $and$ls180.v:4069$488_Y
   end
-  attribute \src "ls180.v:3994.260-3994.329"
-  cell $and $and$ls180.v:3994$440
+  attribute \src "ls180.v:4069.260-4069.329"
+  cell $and $and$ls180.v:4069$491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3994$439_Y
-    connect \Y $and$ls180.v:3994$440_Y
+    connect \B $eq$ls180.v:4069$490_Y
+    connect \Y $and$ls180.v:4069$491_Y
   end
-  attribute \src "ls180.v:3994.41-3994.332"
-  cell $and $and$ls180.v:3994$443
+  attribute \src "ls180.v:4069.41-4069.332"
+  cell $and $and$ls180.v:4069$494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3994$432_Y
-    connect \B $not$ls180.v:3994$442_Y
-    connect \Y $and$ls180.v:3994$443_Y
+    connect \A $eq$ls180.v:4069$483_Y
+    connect \B $not$ls180.v:4069$493_Y
+    connect \Y $and$ls180.v:4069$494_Y
   end
-  attribute \src "ls180.v:3994.40-3994.355"
-  cell $and $and$ls180.v:3994$444
+  attribute \src "ls180.v:4069.40-4069.355"
+  cell $and $and$ls180.v:4069$495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3994$443_Y
+    connect \A $and$ls180.v:4069$494_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:3994$444_Y
+    connect \Y $and$ls180.v:4069$495_Y
   end
-  attribute \src "ls180.v:3995.34-3995.106"
-  cell $and $and$ls180.v:3995$447
+  attribute \src "ls180.v:4070.34-4070.106"
+  cell $and $and$ls180.v:4070$498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3995$445_Y
-    connect \B $not$ls180.v:3995$446_Y
-    connect \Y $and$ls180.v:3995$447_Y
+    connect \A $not$ls180.v:4070$496_Y
+    connect \B $not$ls180.v:4070$497_Y
+    connect \Y $and$ls180.v:4070$498_Y
   end
-  attribute \src "ls180.v:3999.110-3999.179"
-  cell $and $and$ls180.v:3999$450
+  attribute \src "ls180.v:4074.110-4074.179"
+  cell $and $and$ls180.v:4074$501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3999$449_Y
-    connect \Y $and$ls180.v:3999$450_Y
+    connect \B $eq$ls180.v:4074$500_Y
+    connect \Y $and$ls180.v:4074$501_Y
   end
-  attribute \src "ls180.v:3999.185-3999.254"
-  cell $and $and$ls180.v:3999$453
+  attribute \src "ls180.v:4074.185-4074.254"
+  cell $and $and$ls180.v:4074$504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3999$452_Y
-    connect \Y $and$ls180.v:3999$453_Y
+    connect \B $eq$ls180.v:4074$503_Y
+    connect \Y $and$ls180.v:4074$504_Y
   end
-  attribute \src "ls180.v:3999.260-3999.329"
-  cell $and $and$ls180.v:3999$456
+  attribute \src "ls180.v:4074.260-4074.329"
+  cell $and $and$ls180.v:4074$507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3999$455_Y
-    connect \Y $and$ls180.v:3999$456_Y
+    connect \B $eq$ls180.v:4074$506_Y
+    connect \Y $and$ls180.v:4074$507_Y
   end
-  attribute \src "ls180.v:3999.41-3999.332"
-  cell $and $and$ls180.v:3999$459
+  attribute \src "ls180.v:4074.41-4074.332"
+  cell $and $and$ls180.v:4074$510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3999$448_Y
-    connect \B $not$ls180.v:3999$458_Y
-    connect \Y $and$ls180.v:3999$459_Y
+    connect \A $eq$ls180.v:4074$499_Y
+    connect \B $not$ls180.v:4074$509_Y
+    connect \Y $and$ls180.v:4074$510_Y
   end
-  attribute \src "ls180.v:3999.40-3999.355"
-  cell $and $and$ls180.v:3999$460
+  attribute \src "ls180.v:4074.40-4074.355"
+  cell $and $and$ls180.v:4074$511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3999$459_Y
+    connect \A $and$ls180.v:4074$510_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:3999$460_Y
+    connect \Y $and$ls180.v:4074$511_Y
   end
-  attribute \src "ls180.v:4000.34-4000.106"
-  cell $and $and$ls180.v:4000$463
+  attribute \src "ls180.v:4075.34-4075.106"
+  cell $and $and$ls180.v:4075$514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4000$461_Y
-    connect \B $not$ls180.v:4000$462_Y
-    connect \Y $and$ls180.v:4000$463_Y
+    connect \A $not$ls180.v:4075$512_Y
+    connect \B $not$ls180.v:4075$513_Y
+    connect \Y $and$ls180.v:4075$514_Y
   end
-  attribute \src "ls180.v:4004.151-4004.220"
-  cell $and $and$ls180.v:4004$467
+  attribute \src "ls180.v:4079.151-4079.220"
+  cell $and $and$ls180.v:4079$518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:4004$466_Y
-    connect \Y $and$ls180.v:4004$467_Y
+    connect \B $eq$ls180.v:4079$517_Y
+    connect \Y $and$ls180.v:4079$518_Y
   end
-  attribute \src "ls180.v:4004.226-4004.295"
-  cell $and $and$ls180.v:4004$470
+  attribute \src "ls180.v:4079.226-4079.295"
+  cell $and $and$ls180.v:4079$521
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:4004$469_Y
-    connect \Y $and$ls180.v:4004$470_Y
+    connect \B $eq$ls180.v:4079$520_Y
+    connect \Y $and$ls180.v:4079$521_Y
   end
-  attribute \src "ls180.v:4004.301-4004.370"
-  cell $and $and$ls180.v:4004$473
+  attribute \src "ls180.v:4079.301-4079.370"
+  cell $and $and$ls180.v:4079$524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:4004$472_Y
-    connect \Y $and$ls180.v:4004$473_Y
+    connect \B $eq$ls180.v:4079$523_Y
+    connect \Y $and$ls180.v:4079$524_Y
   end
-  attribute \src "ls180.v:4004.82-4004.373"
-  cell $and $and$ls180.v:4004$476
+  attribute \src "ls180.v:4079.82-4079.373"
+  cell $and $and$ls180.v:4079$527
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$465_Y
-    connect \B $not$ls180.v:4004$475_Y
-    connect \Y $and$ls180.v:4004$476_Y
+    connect \A $eq$ls180.v:4079$516_Y
+    connect \B $not$ls180.v:4079$526_Y
+    connect \Y $and$ls180.v:4079$527_Y
   end
-  attribute \src "ls180.v:4004.43-4004.374"
-  cell $and $and$ls180.v:4004$477
+  attribute \src "ls180.v:4079.43-4079.374"
+  cell $and $and$ls180.v:4079$528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$464_Y
-    connect \B $and$ls180.v:4004$476_Y
-    connect \Y $and$ls180.v:4004$477_Y
+    connect \A $eq$ls180.v:4079$515_Y
+    connect \B $and$ls180.v:4079$527_Y
+    connect \Y $and$ls180.v:4079$528_Y
   end
-  attribute \src "ls180.v:4004.42-4004.410"
-  cell $and $and$ls180.v:4004$478
+  attribute \src "ls180.v:4079.42-4079.410"
+  cell $and $and$ls180.v:4079$529
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4004$477_Y
+    connect \A $and$ls180.v:4079$528_Y
     connect \B \main_sdram_interface_bank0_ready
-    connect \Y $and$ls180.v:4004$478_Y
+    connect \Y $and$ls180.v:4079$529_Y
   end
-  attribute \src "ls180.v:4004.525-4004.594"
-  cell $and $and$ls180.v:4004$483
+  attribute \src "ls180.v:4079.525-4079.594"
+  cell $and $and$ls180.v:4079$534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:4004$482_Y
-    connect \Y $and$ls180.v:4004$483_Y
+    connect \B $eq$ls180.v:4079$533_Y
+    connect \Y $and$ls180.v:4079$534_Y
   end
-  attribute \src "ls180.v:4004.600-4004.669"
-  cell $and $and$ls180.v:4004$486
+  attribute \src "ls180.v:4079.600-4079.669"
+  cell $and $and$ls180.v:4079$537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:4004$485_Y
-    connect \Y $and$ls180.v:4004$486_Y
+    connect \B $eq$ls180.v:4079$536_Y
+    connect \Y $and$ls180.v:4079$537_Y
   end
-  attribute \src "ls180.v:4004.675-4004.744"
-  cell $and $and$ls180.v:4004$489
+  attribute \src "ls180.v:4079.675-4079.744"
+  cell $and $and$ls180.v:4079$540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:4004$488_Y
-    connect \Y $and$ls180.v:4004$489_Y
+    connect \B $eq$ls180.v:4079$539_Y
+    connect \Y $and$ls180.v:4079$540_Y
   end
-  attribute \src "ls180.v:4004.456-4004.747"
-  cell $and $and$ls180.v:4004$492
+  attribute \src "ls180.v:4079.456-4079.747"
+  cell $and $and$ls180.v:4079$543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$481_Y
-    connect \B $not$ls180.v:4004$491_Y
-    connect \Y $and$ls180.v:4004$492_Y
+    connect \A $eq$ls180.v:4079$532_Y
+    connect \B $not$ls180.v:4079$542_Y
+    connect \Y $and$ls180.v:4079$543_Y
   end
-  attribute \src "ls180.v:4004.417-4004.748"
-  cell $and $and$ls180.v:4004$493
+  attribute \src "ls180.v:4079.417-4079.748"
+  cell $and $and$ls180.v:4079$544
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$480_Y
-    connect \B $and$ls180.v:4004$492_Y
-    connect \Y $and$ls180.v:4004$493_Y
+    connect \A $eq$ls180.v:4079$531_Y
+    connect \B $and$ls180.v:4079$543_Y
+    connect \Y $and$ls180.v:4079$544_Y
   end
-  attribute \src "ls180.v:4004.416-4004.784"
-  cell $and $and$ls180.v:4004$494
+  attribute \src "ls180.v:4079.416-4079.784"
+  cell $and $and$ls180.v:4079$545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4004$493_Y
+    connect \A $and$ls180.v:4079$544_Y
     connect \B \main_sdram_interface_bank1_ready
-    connect \Y $and$ls180.v:4004$494_Y
+    connect \Y $and$ls180.v:4079$545_Y
   end
-  attribute \src "ls180.v:4004.899-4004.968"
-  cell $and $and$ls180.v:4004$499
+  attribute \src "ls180.v:4079.899-4079.968"
+  cell $and $and$ls180.v:4079$550
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:4004$498_Y
-    connect \Y $and$ls180.v:4004$499_Y
+    connect \B $eq$ls180.v:4079$549_Y
+    connect \Y $and$ls180.v:4079$550_Y
   end
-  attribute \src "ls180.v:4004.974-4004.1043"
-  cell $and $and$ls180.v:4004$502
+  attribute \src "ls180.v:4079.974-4079.1043"
+  cell $and $and$ls180.v:4079$553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:4004$501_Y
-    connect \Y $and$ls180.v:4004$502_Y
+    connect \B $eq$ls180.v:4079$552_Y
+    connect \Y $and$ls180.v:4079$553_Y
   end
-  attribute \src "ls180.v:4004.1049-4004.1118"
-  cell $and $and$ls180.v:4004$505
+  attribute \src "ls180.v:4079.1049-4079.1118"
+  cell $and $and$ls180.v:4079$556
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:4004$504_Y
-    connect \Y $and$ls180.v:4004$505_Y
+    connect \B $eq$ls180.v:4079$555_Y
+    connect \Y $and$ls180.v:4079$556_Y
   end
-  attribute \src "ls180.v:4004.830-4004.1121"
-  cell $and $and$ls180.v:4004$508
+  attribute \src "ls180.v:4079.830-4079.1121"
+  cell $and $and$ls180.v:4079$559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$497_Y
-    connect \B $not$ls180.v:4004$507_Y
-    connect \Y $and$ls180.v:4004$508_Y
+    connect \A $eq$ls180.v:4079$548_Y
+    connect \B $not$ls180.v:4079$558_Y
+    connect \Y $and$ls180.v:4079$559_Y
   end
-  attribute \src "ls180.v:4004.791-4004.1122"
-  cell $and $and$ls180.v:4004$509
+  attribute \src "ls180.v:4079.791-4079.1122"
+  cell $and $and$ls180.v:4079$560
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$496_Y
-    connect \B $and$ls180.v:4004$508_Y
-    connect \Y $and$ls180.v:4004$509_Y
+    connect \A $eq$ls180.v:4079$547_Y
+    connect \B $and$ls180.v:4079$559_Y
+    connect \Y $and$ls180.v:4079$560_Y
   end
-  attribute \src "ls180.v:4004.790-4004.1158"
-  cell $and $and$ls180.v:4004$510
+  attribute \src "ls180.v:4079.790-4079.1158"
+  cell $and $and$ls180.v:4079$561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4004$509_Y
+    connect \A $and$ls180.v:4079$560_Y
     connect \B \main_sdram_interface_bank2_ready
-    connect \Y $and$ls180.v:4004$510_Y
+    connect \Y $and$ls180.v:4079$561_Y
   end
-  attribute \src "ls180.v:4004.1273-4004.1342"
-  cell $and $and$ls180.v:4004$515
+  attribute \src "ls180.v:4079.1273-4079.1342"
+  cell $and $and$ls180.v:4079$566
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:4004$514_Y
-    connect \Y $and$ls180.v:4004$515_Y
+    connect \B $eq$ls180.v:4079$565_Y
+    connect \Y $and$ls180.v:4079$566_Y
   end
-  attribute \src "ls180.v:4004.1348-4004.1417"
-  cell $and $and$ls180.v:4004$518
+  attribute \src "ls180.v:4079.1348-4079.1417"
+  cell $and $and$ls180.v:4079$569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:4004$517_Y
-    connect \Y $and$ls180.v:4004$518_Y
+    connect \B $eq$ls180.v:4079$568_Y
+    connect \Y $and$ls180.v:4079$569_Y
   end
-  attribute \src "ls180.v:4004.1423-4004.1492"
-  cell $and $and$ls180.v:4004$521
+  attribute \src "ls180.v:4079.1423-4079.1492"
+  cell $and $and$ls180.v:4079$572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:4004$520_Y
-    connect \Y $and$ls180.v:4004$521_Y
+    connect \B $eq$ls180.v:4079$571_Y
+    connect \Y $and$ls180.v:4079$572_Y
   end
-  attribute \src "ls180.v:4004.1204-4004.1495"
-  cell $and $and$ls180.v:4004$524
+  attribute \src "ls180.v:4079.1204-4079.1495"
+  cell $and $and$ls180.v:4079$575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$513_Y
-    connect \B $not$ls180.v:4004$523_Y
-    connect \Y $and$ls180.v:4004$524_Y
+    connect \A $eq$ls180.v:4079$564_Y
+    connect \B $not$ls180.v:4079$574_Y
+    connect \Y $and$ls180.v:4079$575_Y
   end
-  attribute \src "ls180.v:4004.1165-4004.1496"
-  cell $and $and$ls180.v:4004$525
+  attribute \src "ls180.v:4079.1165-4079.1496"
+  cell $and $and$ls180.v:4079$576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4004$512_Y
-    connect \B $and$ls180.v:4004$524_Y
-    connect \Y $and$ls180.v:4004$525_Y
+    connect \A $eq$ls180.v:4079$563_Y
+    connect \B $and$ls180.v:4079$575_Y
+    connect \Y $and$ls180.v:4079$576_Y
   end
-  attribute \src "ls180.v:4004.1164-4004.1532"
-  cell $and $and$ls180.v:4004$526
+  attribute \src "ls180.v:4079.1164-4079.1532"
+  cell $and $and$ls180.v:4079$577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4004$525_Y
+    connect \A $and$ls180.v:4079$576_Y
     connect \B \main_sdram_interface_bank3_ready
-    connect \Y $and$ls180.v:4004$526_Y
+    connect \Y $and$ls180.v:4079$577_Y
   end
-  attribute \src "ls180.v:4062.9-4062.46"
-  cell $and $and$ls180.v:4062$532
+  attribute \src "ls180.v:4137.9-4137.46"
+  cell $and $and$ls180.v:4137$583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238229,10 +239039,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_wb_sdram_stb
     connect \B \main_wb_sdram_cyc
-    connect \Y $and$ls180.v:4062$532_Y
+    connect \Y $and$ls180.v:4137$583_Y
   end
-  attribute \src "ls180.v:4080.9-4080.46"
-  cell $and $and$ls180.v:4080$539
+  attribute \src "ls180.v:4155.9-4155.46"
+  cell $and $and$ls180.v:4155$590
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238240,10 +239050,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_wb_sdram_stb
     connect \B \main_wb_sdram_cyc
-    connect \Y $and$ls180.v:4080$539_Y
+    connect \Y $and$ls180.v:4155$590_Y
   end
-  attribute \src "ls180.v:4093.32-4093.75"
-  cell $and $and$ls180.v:4093$543
+  attribute \src "ls180.v:4168.32-4168.75"
+  cell $and $and$ls180.v:4168$594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238251,54 +239061,54 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_cyc
     connect \B \main_litedram_wb_stb
-    connect \Y $and$ls180.v:4093$543_Y
+    connect \Y $and$ls180.v:4168$594_Y
   end
-  attribute \src "ls180.v:4093.31-4093.99"
-  cell $and $and$ls180.v:4093$545
+  attribute \src "ls180.v:4168.31-4168.99"
+  cell $and $and$ls180.v:4168$596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4093$543_Y
-    connect \B $not$ls180.v:4093$544_Y
-    connect \Y $and$ls180.v:4093$545_Y
+    connect \A $and$ls180.v:4168$594_Y
+    connect \B $not$ls180.v:4168$595_Y
+    connect \Y $and$ls180.v:4168$596_Y
   end
-  attribute \src "ls180.v:4094.34-4094.102"
-  cell $and $and$ls180.v:4094$547
+  attribute \src "ls180.v:4169.34-4169.102"
+  cell $and $and$ls180.v:4169$598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4094$546_Y
+    connect \A $or$ls180.v:4169$597_Y
     connect \B \main_port_cmd_payload_we
-    connect \Y $and$ls180.v:4094$547_Y
+    connect \Y $and$ls180.v:4169$598_Y
   end
-  attribute \src "ls180.v:4094.33-4094.128"
-  cell $and $and$ls180.v:4094$549
+  attribute \src "ls180.v:4169.33-4169.128"
+  cell $and $and$ls180.v:4169$600
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4094$547_Y
-    connect \B $not$ls180.v:4094$548_Y
-    connect \Y $and$ls180.v:4094$549_Y
+    connect \A $and$ls180.v:4169$598_Y
+    connect \B $not$ls180.v:4169$599_Y
+    connect \Y $and$ls180.v:4169$600_Y
   end
-  attribute \src "ls180.v:4095.33-4095.104"
-  cell $and $and$ls180.v:4095$552
+  attribute \src "ls180.v:4170.33-4170.104"
+  cell $and $and$ls180.v:4170$603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4095$550_Y
-    connect \B $not$ls180.v:4095$551_Y
-    connect \Y $and$ls180.v:4095$552_Y
+    connect \A $or$ls180.v:4170$601_Y
+    connect \B $not$ls180.v:4170$602_Y
+    connect \Y $and$ls180.v:4170$603_Y
   end
-  attribute \src "ls180.v:4096.49-4096.85"
-  cell $and $and$ls180.v:4096$553
+  attribute \src "ls180.v:4171.49-4171.85"
+  cell $and $and$ls180.v:4171$604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238306,32 +239116,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_we
     connect \B \main_ack_wdata
-    connect \Y $and$ls180.v:4096$553_Y
+    connect \Y $and$ls180.v:4171$604_Y
   end
-  attribute \src "ls180.v:4096.90-4096.129"
-  cell $and $and$ls180.v:4096$555
+  attribute \src "ls180.v:4171.90-4171.129"
+  cell $and $and$ls180.v:4171$606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4096$554_Y
+    connect \A $not$ls180.v:4171$605_Y
     connect \B \main_ack_rdata
-    connect \Y $and$ls180.v:4096$555_Y
+    connect \Y $and$ls180.v:4171$606_Y
   end
-  attribute \src "ls180.v:4096.32-4096.131"
-  cell $and $and$ls180.v:4096$557
+  attribute \src "ls180.v:4171.32-4171.131"
+  cell $and $and$ls180.v:4171$608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_ack_cmd
-    connect \B $or$ls180.v:4096$556_Y
-    connect \Y $and$ls180.v:4096$557_Y
+    connect \B $or$ls180.v:4171$607_Y
+    connect \Y $and$ls180.v:4171$608_Y
   end
-  attribute \src "ls180.v:4097.25-4097.66"
-  cell $and $and$ls180.v:4097$558
+  attribute \src "ls180.v:4172.25-4172.66"
+  cell $and $and$ls180.v:4172$609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238339,10 +239149,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_valid
     connect \B \main_port_cmd_ready
-    connect \Y $and$ls180.v:4097$558_Y
+    connect \Y $and$ls180.v:4172$609_Y
   end
-  attribute \src "ls180.v:4098.27-4098.72"
-  cell $and $and$ls180.v:4098$560
+  attribute \src "ls180.v:4173.27-4173.72"
+  cell $and $and$ls180.v:4173$611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238350,10 +239160,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_wdata_valid
     connect \B \main_port_wdata_ready
-    connect \Y $and$ls180.v:4098$560_Y
+    connect \Y $and$ls180.v:4173$611_Y
   end
-  attribute \src "ls180.v:4099.26-4099.71"
-  cell $and $and$ls180.v:4099$562
+  attribute \src "ls180.v:4174.26-4174.71"
+  cell $and $and$ls180.v:4174$613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238361,10 +239171,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_rdata_valid
     connect \B \main_port_rdata_ready
-    connect \Y $and$ls180.v:4099$562_Y
+    connect \Y $and$ls180.v:4174$613_Y
   end
-  attribute \src "ls180.v:4128.64-4128.88"
-  cell $and $and$ls180.v:4128$568
+  attribute \src "ls180.v:4203.64-4203.88"
+  cell $and $and$ls180.v:4203$619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238372,10 +239182,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A 1'0
     connect \B \main_uart_rxtx_we
-    connect \Y $and$ls180.v:4128$568_Y
+    connect \Y $and$ls180.v:4203$619_Y
   end
-  attribute \src "ls180.v:4132.7-4132.78"
-  cell $and $and$ls180.v:4132$572
+  attribute \src "ls180.v:4207.7-4207.78"
+  cell $and $and$ls180.v:4207$623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238383,10 +239193,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_eventmanager_pending_re
     connect \B \main_uart_eventmanager_pending_r [0]
-    connect \Y $and$ls180.v:4132$572_Y
+    connect \Y $and$ls180.v:4207$623_Y
   end
-  attribute \src "ls180.v:4143.7-4143.78"
-  cell $and $and$ls180.v:4143$575
+  attribute \src "ls180.v:4218.7-4218.78"
+  cell $and $and$ls180.v:4218$626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238394,10 +239204,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_eventmanager_pending_re
     connect \B \main_uart_eventmanager_pending_r [1]
-    connect \Y $and$ls180.v:4143$575_Y
+    connect \Y $and$ls180.v:4218$626_Y
   end
-  attribute \src "ls180.v:4152.26-4152.97"
-  cell $and $and$ls180.v:4152$577
+  attribute \src "ls180.v:4227.26-4227.97"
+  cell $and $and$ls180.v:4227$628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238405,10 +239215,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_eventmanager_pending_w [0]
     connect \B \main_uart_eventmanager_storage [0]
-    connect \Y $and$ls180.v:4152$577_Y
+    connect \Y $and$ls180.v:4227$628_Y
   end
-  attribute \src "ls180.v:4152.102-4152.173"
-  cell $and $and$ls180.v:4152$578
+  attribute \src "ls180.v:4227.102-4227.173"
+  cell $and $and$ls180.v:4227$629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238416,32 +239226,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_eventmanager_pending_w [1]
     connect \B \main_uart_eventmanager_storage [1]
-    connect \Y $and$ls180.v:4152$578_Y
+    connect \Y $and$ls180.v:4227$629_Y
   end
-  attribute \src "ls180.v:4167.41-4167.133"
-  cell $and $and$ls180.v:4167$582
+  attribute \src "ls180.v:4242.41-4242.133"
+  cell $and $and$ls180.v:4242$633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_readable
-    connect \B $or$ls180.v:4167$581_Y
-    connect \Y $and$ls180.v:4167$582_Y
+    connect \B $or$ls180.v:4242$632_Y
+    connect \Y $and$ls180.v:4242$633_Y
   end
-  attribute \src "ls180.v:4178.39-4178.136"
-  cell $and $and$ls180.v:4178$587
+  attribute \src "ls180.v:4253.39-4253.136"
+  cell $and $and$ls180.v:4253$638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_we
-    connect \B $or$ls180.v:4178$586_Y
-    connect \Y $and$ls180.v:4178$587_Y
+    connect \B $or$ls180.v:4253$637_Y
+    connect \Y $and$ls180.v:4253$638_Y
   end
-  attribute \src "ls180.v:4179.37-4179.104"
-  cell $and $and$ls180.v:4179$588
+  attribute \src "ls180.v:4254.37-4254.104"
+  cell $and $and$ls180.v:4254$639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238449,32 +239259,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_readable
     connect \B \main_uart_tx_fifo_syncfifo_re
-    connect \Y $and$ls180.v:4179$588_Y
+    connect \Y $and$ls180.v:4254$639_Y
   end
-  attribute \src "ls180.v:4197.41-4197.133"
-  cell $and $and$ls180.v:4197$593
+  attribute \src "ls180.v:4272.41-4272.133"
+  cell $and $and$ls180.v:4272$644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_readable
-    connect \B $or$ls180.v:4197$592_Y
-    connect \Y $and$ls180.v:4197$593_Y
+    connect \B $or$ls180.v:4272$643_Y
+    connect \Y $and$ls180.v:4272$644_Y
   end
-  attribute \src "ls180.v:4208.39-4208.136"
-  cell $and $and$ls180.v:4208$598
+  attribute \src "ls180.v:4283.39-4283.136"
+  cell $and $and$ls180.v:4283$649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_we
-    connect \B $or$ls180.v:4208$597_Y
-    connect \Y $and$ls180.v:4208$598_Y
+    connect \B $or$ls180.v:4283$648_Y
+    connect \Y $and$ls180.v:4283$649_Y
   end
-  attribute \src "ls180.v:4209.37-4209.104"
-  cell $and $and$ls180.v:4209$599
+  attribute \src "ls180.v:4284.37-4284.104"
+  cell $and $and$ls180.v:4284$650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238482,21 +239292,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_readable
     connect \B \main_uart_rx_fifo_syncfifo_re
-    connect \Y $and$ls180.v:4209$599_Y
+    connect \Y $and$ls180.v:4284$650_Y
   end
-  attribute \src "ls180.v:4397.33-4397.86"
-  cell $and $and$ls180.v:4397$641
+  attribute \src "ls180.v:4472.33-4472.86"
+  cell $and $and$ls180.v:4472$692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_clocker_clk1
-    connect \B $not$ls180.v:4397$640_Y
-    connect \Y $and$ls180.v:4397$641_Y
+    connect \B $not$ls180.v:4472$691_Y
+    connect \Y $and$ls180.v:4472$692_Y
   end
-  attribute \src "ls180.v:4501.9-4501.68"
-  cell $and $and$ls180.v:4501$650
+  attribute \src "ls180.v:4576.9-4576.68"
+  cell $and $and$ls180.v:4576$701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238504,21 +239314,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdw_sink_valid
     connect \B \main_sdphy_cmdw_pads_out_ready
-    connect \Y $and$ls180.v:4501$650_Y
+    connect \Y $and$ls180.v:4576$701_Y
   end
-  attribute \src "ls180.v:4521.53-4521.145"
-  cell $and $and$ls180.v:4521$653
+  attribute \src "ls180.v:4596.53-4596.145"
+  cell $and $and$ls180.v:4596$704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_pads_in_valid
-    connect \B $or$ls180.v:4521$652_Y
-    connect \Y $and$ls180.v:4521$653_Y
+    connect \B $or$ls180.v:4596$703_Y
+    connect \Y $and$ls180.v:4596$704_Y
   end
-  attribute \src "ls180.v:4540.52-4540.137"
-  cell $and $and$ls180.v:4540$656
+  attribute \src "ls180.v:4615.52-4615.137"
+  cell $and $and$ls180.v:4615$707
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238526,10 +239336,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
-    connect \Y $and$ls180.v:4540$656_Y
+    connect \Y $and$ls180.v:4615$707_Y
   end
-  attribute \src "ls180.v:4581.9-4581.68"
-  cell $and $and$ls180.v:4581$664
+  attribute \src "ls180.v:4656.9-4656.68"
+  cell $and $and$ls180.v:4656$715
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238537,10 +239347,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_source_valid
     connect \B \main_sdphy_cmdr_source_ready
-    connect \Y $and$ls180.v:4581$664_Y
+    connect \Y $and$ls180.v:4656$715_Y
   end
-  attribute \src "ls180.v:4619.9-4619.68"
-  cell $and $and$ls180.v:4619$670
+  attribute \src "ls180.v:4694.9-4694.68"
+  cell $and $and$ls180.v:4694$721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238548,10 +239358,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_source_valid
     connect \B \main_sdphy_cmdr_source_ready
-    connect \Y $and$ls180.v:4619$670_Y
+    connect \Y $and$ls180.v:4694$721_Y
   end
-  attribute \src "ls180.v:4628.10-4628.69"
-  cell $and $and$ls180.v:4628$671
+  attribute \src "ls180.v:4703.10-4703.69"
+  cell $and $and$ls180.v:4703$722
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238559,21 +239369,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_sink_valid
     connect \B \main_sdphy_cmdr_pads_out_ready
-    connect \Y $and$ls180.v:4628$671_Y
+    connect \Y $and$ls180.v:4703$722_Y
   end
-  attribute \src "ls180.v:4628.9-4628.93"
-  cell $and $and$ls180.v:4628$672
+  attribute \src "ls180.v:4703.9-4703.93"
+  cell $and $and$ls180.v:4703$723
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4628$671_Y
+    connect \A $and$ls180.v:4703$722_Y
     connect \B \main_sdphy_cmdw_done
-    connect \Y $and$ls180.v:4628$672_Y
+    connect \Y $and$ls180.v:4703$723_Y
   end
-  attribute \src "ls180.v:4648.54-4648.117"
-  cell $and $and$ls180.v:4648$674
+  attribute \src "ls180.v:4723.54-4723.117"
+  cell $and $and$ls180.v:4723$725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238581,10 +239391,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_pads_in_valid
     connect \B \main_sdphy_dataw_crcr_run
-    connect \Y $and$ls180.v:4648$674_Y
+    connect \Y $and$ls180.v:4723$725_Y
   end
-  attribute \src "ls180.v:4667.53-4667.140"
-  cell $and $and$ls180.v:4667$677
+  attribute \src "ls180.v:4742.53-4742.140"
+  cell $and $and$ls180.v:4742$728
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238592,10 +239402,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
-    connect \Y $and$ls180.v:4667$677_Y
+    connect \Y $and$ls180.v:4742$728_Y
   end
-  attribute \src "ls180.v:4764.9-4764.70"
-  cell $and $and$ls180.v:4764$687
+  attribute \src "ls180.v:4839.9-4839.70"
+  cell $and $and$ls180.v:4839$738
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238603,10 +239413,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_sink_valid
     connect \B \main_sdphy_dataw_pads_out_ready
-    connect \Y $and$ls180.v:4764$687_Y
+    connect \Y $and$ls180.v:4839$738_Y
   end
-  attribute \src "ls180.v:4782.55-4782.120"
-  cell $and $and$ls180.v:4782$689
+  attribute \src "ls180.v:4857.55-4857.120"
+  cell $and $and$ls180.v:4857$740
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238614,10 +239424,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_pads_in_valid
     connect \B \main_sdphy_datar_datar_run
-    connect \Y $and$ls180.v:4782$689_Y
+    connect \Y $and$ls180.v:4857$740_Y
   end
-  attribute \src "ls180.v:4801.54-4801.143"
-  cell $and $and$ls180.v:4801$692
+  attribute \src "ls180.v:4876.54-4876.143"
+  cell $and $and$ls180.v:4876$743
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238625,10 +239435,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_valid
     connect \B \main_sdphy_datar_datar_converter_sink_ready
-    connect \Y $and$ls180.v:4801$692_Y
+    connect \Y $and$ls180.v:4876$743_Y
   end
-  attribute \src "ls180.v:4883.9-4883.70"
-  cell $and $and$ls180.v:4883$707
+  attribute \src "ls180.v:4958.9-4958.70"
+  cell $and $and$ls180.v:4958$758
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238636,10 +239446,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_source_valid
     connect \B \main_sdphy_datar_source_ready
-    connect \Y $and$ls180.v:4883$707_Y
+    connect \Y $and$ls180.v:4958$758_Y
   end
-  attribute \src "ls180.v:4890.9-4890.70"
-  cell $and $and$ls180.v:4890$708
+  attribute \src "ls180.v:4965.9-4965.70"
+  cell $and $and$ls180.v:4965$759
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238647,10 +239457,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_sink_valid
     connect \B \main_sdphy_datar_pads_out_ready
-    connect \Y $and$ls180.v:4890$708_Y
+    connect \Y $and$ls180.v:4965$759_Y
   end
-  attribute \src "ls180.v:4971.48-4971.124"
-  cell $and $and$ls180.v:4971$831
+  attribute \src "ls180.v:5046.48-5046.124"
+  cell $and $and$ls180.v:5046$882
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238658,21 +239468,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_last
     connect \B \main_sdcore_crc16_inserter_sink_valid
-    connect \Y $and$ls180.v:4971$831_Y
+    connect \Y $and$ls180.v:5046$882_Y
   end
-  attribute \src "ls180.v:4971.47-4971.165"
-  cell $and $and$ls180.v:4971$832
+  attribute \src "ls180.v:5046.47-5046.165"
+  cell $and $and$ls180.v:5046$883
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4971$831_Y
+    connect \A $and$ls180.v:5046$882_Y
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4971$832_Y
+    connect \Y $and$ls180.v:5046$883_Y
   end
-  attribute \src "ls180.v:4972.50-4972.127"
-  cell $and $and$ls180.v:4972$833
+  attribute \src "ls180.v:5047.50-5047.127"
+  cell $and $and$ls180.v:5047$884
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238680,10 +239490,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_valid
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4972$833_Y
+    connect \Y $and$ls180.v:5047$884_Y
   end
-  attribute \src "ls180.v:4974.48-4974.124"
-  cell $and $and$ls180.v:4974$834
+  attribute \src "ls180.v:5049.48-5049.124"
+  cell $and $and$ls180.v:5049$885
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238691,21 +239501,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_last
     connect \B \main_sdcore_crc16_inserter_sink_valid
-    connect \Y $and$ls180.v:4974$834_Y
+    connect \Y $and$ls180.v:5049$885_Y
   end
-  attribute \src "ls180.v:4974.47-4974.165"
-  cell $and $and$ls180.v:4974$835
+  attribute \src "ls180.v:5049.47-5049.165"
+  cell $and $and$ls180.v:5049$886
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4974$834_Y
+    connect \A $and$ls180.v:5049$885_Y
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4974$835_Y
+    connect \Y $and$ls180.v:5049$886_Y
   end
-  attribute \src "ls180.v:4975.50-4975.127"
-  cell $and $and$ls180.v:4975$836
+  attribute \src "ls180.v:5050.50-5050.127"
+  cell $and $and$ls180.v:5050$887
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238713,10 +239523,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_valid
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4975$836_Y
+    connect \Y $and$ls180.v:5050$887_Y
   end
-  attribute \src "ls180.v:4977.48-4977.124"
-  cell $and $and$ls180.v:4977$837
+  attribute \src "ls180.v:5052.48-5052.124"
+  cell $and $and$ls180.v:5052$888
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238724,21 +239534,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_last
     connect \B \main_sdcore_crc16_inserter_sink_valid
-    connect \Y $and$ls180.v:4977$837_Y
+    connect \Y $and$ls180.v:5052$888_Y
   end
-  attribute \src "ls180.v:4977.47-4977.165"
-  cell $and $and$ls180.v:4977$838
+  attribute \src "ls180.v:5052.47-5052.165"
+  cell $and $and$ls180.v:5052$889
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4977$837_Y
+    connect \A $and$ls180.v:5052$888_Y
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4977$838_Y
+    connect \Y $and$ls180.v:5052$889_Y
   end
-  attribute \src "ls180.v:4978.50-4978.127"
-  cell $and $and$ls180.v:4978$839
+  attribute \src "ls180.v:5053.50-5053.127"
+  cell $and $and$ls180.v:5053$890
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238746,10 +239556,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_valid
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4978$839_Y
+    connect \Y $and$ls180.v:5053$890_Y
   end
-  attribute \src "ls180.v:4980.48-4980.124"
-  cell $and $and$ls180.v:4980$840
+  attribute \src "ls180.v:5055.48-5055.124"
+  cell $and $and$ls180.v:5055$891
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238757,21 +239567,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_last
     connect \B \main_sdcore_crc16_inserter_sink_valid
-    connect \Y $and$ls180.v:4980$840_Y
+    connect \Y $and$ls180.v:5055$891_Y
   end
-  attribute \src "ls180.v:4980.47-4980.165"
-  cell $and $and$ls180.v:4980$841
+  attribute \src "ls180.v:5055.47-5055.165"
+  cell $and $and$ls180.v:5055$892
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4980$840_Y
+    connect \A $and$ls180.v:5055$891_Y
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4980$841_Y
+    connect \Y $and$ls180.v:5055$892_Y
   end
-  attribute \src "ls180.v:4981.50-4981.127"
-  cell $and $and$ls180.v:4981$842
+  attribute \src "ls180.v:5056.50-5056.127"
+  cell $and $and$ls180.v:5056$893
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238779,10 +239589,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_valid
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:4981$842_Y
+    connect \Y $and$ls180.v:5056$893_Y
   end
-  attribute \src "ls180.v:5094.10-5094.86"
-  cell $and $and$ls180.v:5094$891
+  attribute \src "ls180.v:5169.10-5169.86"
+  cell $and $and$ls180.v:5169$942
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238790,54 +239600,54 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_sink_valid
     connect \B \main_sdcore_crc16_inserter_sink_last
-    connect \Y $and$ls180.v:5094$891_Y
+    connect \Y $and$ls180.v:5169$942_Y
   end
-  attribute \src "ls180.v:5094.9-5094.127"
-  cell $and $and$ls180.v:5094$892
+  attribute \src "ls180.v:5169.9-5169.127"
+  cell $and $and$ls180.v:5169$943
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5094$891_Y
+    connect \A $and$ls180.v:5169$942_Y
     connect \B \main_sdcore_crc16_inserter_sink_ready
-    connect \Y $and$ls180.v:5094$892_Y
+    connect \Y $and$ls180.v:5169$943_Y
   end
-  attribute \src "ls180.v:5104.9-5104.152"
-  cell $and $and$ls180.v:5104$896
+  attribute \src "ls180.v:5179.9-5179.152"
+  cell $and $and$ls180.v:5179$947
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:5104$894_Y
-    connect \B $eq$ls180.v:5104$895_Y
-    connect \Y $and$ls180.v:5104$896_Y
+    connect \A $eq$ls180.v:5179$945_Y
+    connect \B $eq$ls180.v:5179$946_Y
+    connect \Y $and$ls180.v:5179$947_Y
   end
-  attribute \src "ls180.v:5104.8-5104.226"
-  cell $and $and$ls180.v:5104$898
+  attribute \src "ls180.v:5179.8-5179.226"
+  cell $and $and$ls180.v:5179$949
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5104$896_Y
-    connect \B $eq$ls180.v:5104$897_Y
-    connect \Y $and$ls180.v:5104$898_Y
+    connect \A $and$ls180.v:5179$947_Y
+    connect \B $eq$ls180.v:5179$948_Y
+    connect \Y $and$ls180.v:5179$949_Y
   end
-  attribute \src "ls180.v:5104.7-5104.300"
-  cell $and $and$ls180.v:5104$900
+  attribute \src "ls180.v:5179.7-5179.300"
+  cell $and $and$ls180.v:5179$951
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5104$898_Y
-    connect \B $eq$ls180.v:5104$899_Y
-    connect \Y $and$ls180.v:5104$900_Y
+    connect \A $and$ls180.v:5179$949_Y
+    connect \B $eq$ls180.v:5179$950_Y
+    connect \Y $and$ls180.v:5179$951_Y
   end
-  attribute \src "ls180.v:5109.49-5109.124"
-  cell $and $and$ls180.v:5109$901
+  attribute \src "ls180.v:5184.49-5184.124"
+  cell $and $and$ls180.v:5184$952
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238845,10 +239655,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:5109$901_Y
+    connect \Y $and$ls180.v:5184$952_Y
   end
-  attribute \src "ls180.v:5119.49-5119.124"
-  cell $and $and$ls180.v:5119$904
+  attribute \src "ls180.v:5194.49-5194.124"
+  cell $and $and$ls180.v:5194$955
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238856,10 +239666,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:5119$904_Y
+    connect \Y $and$ls180.v:5194$955_Y
   end
-  attribute \src "ls180.v:5129.49-5129.124"
-  cell $and $and$ls180.v:5129$907
+  attribute \src "ls180.v:5204.49-5204.124"
+  cell $and $and$ls180.v:5204$958
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238867,10 +239677,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:5129$907_Y
+    connect \Y $and$ls180.v:5204$958_Y
   end
-  attribute \src "ls180.v:5139.49-5139.124"
-  cell $and $and$ls180.v:5139$910
+  attribute \src "ls180.v:5214.49-5214.124"
+  cell $and $and$ls180.v:5214$961
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238878,21 +239688,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:5139$910_Y
+    connect \Y $and$ls180.v:5214$961_Y
   end
-  attribute \src "ls180.v:5151.7-5151.84"
-  cell $and $and$ls180.v:5151$915
+  attribute \src "ls180.v:5226.7-5226.84"
+  cell $and $and$ls180.v:5226$966
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
-    connect \B $gt$ls180.v:5151$914_Y
-    connect \Y $and$ls180.v:5151$915_Y
+    connect \B $gt$ls180.v:5226$965_Y
+    connect \Y $and$ls180.v:5226$966_Y
   end
-  attribute \src "ls180.v:5269.9-5269.64"
-  cell $and $and$ls180.v:5269$964
+  attribute \src "ls180.v:5344.9-5344.64"
+  cell $and $and$ls180.v:5344$1015
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238900,10 +239710,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdw_sink_valid
     connect \B \main_sdphy_cmdw_sink_ready
-    connect \Y $and$ls180.v:5269$964_Y
+    connect \Y $and$ls180.v:5344$1015_Y
   end
-  attribute \src "ls180.v:5321.10-5321.66"
-  cell $and $and$ls180.v:5321$973
+  attribute \src "ls180.v:5396.10-5396.66"
+  cell $and $and$ls180.v:5396$1024
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238911,21 +239721,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_sink_valid
     connect \B \main_sdphy_dataw_sink_last
-    connect \Y $and$ls180.v:5321$973_Y
+    connect \Y $and$ls180.v:5396$1024_Y
   end
-  attribute \src "ls180.v:5321.9-5321.97"
-  cell $and $and$ls180.v:5321$974
+  attribute \src "ls180.v:5396.9-5396.97"
+  cell $and $and$ls180.v:5396$1025
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5321$973_Y
+    connect \A $and$ls180.v:5396$1024_Y
     connect \B \main_sdphy_dataw_sink_ready
-    connect \Y $and$ls180.v:5321$974_Y
+    connect \Y $and$ls180.v:5396$1025_Y
   end
-  attribute \src "ls180.v:5347.11-5347.71"
-  cell $and $and$ls180.v:5347$982
+  attribute \src "ls180.v:5422.11-5422.71"
+  cell $and $and$ls180.v:5422$1033
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238933,21 +239743,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_source_last
     connect \B \main_sdphy_datar_source_ready
-    connect \Y $and$ls180.v:5347$982_Y
+    connect \Y $and$ls180.v:5422$1033_Y
   end
-  attribute \src "ls180.v:5431.43-5431.152"
-  cell $and $and$ls180.v:5431$990
+  attribute \src "ls180.v:5506.43-5506.152"
+  cell $and $and$ls180.v:5506$1041
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_we
-    connect \B $or$ls180.v:5431$989_Y
-    connect \Y $and$ls180.v:5431$990_Y
+    connect \B $or$ls180.v:5506$1040_Y
+    connect \Y $and$ls180.v:5506$1041_Y
   end
-  attribute \src "ls180.v:5432.41-5432.116"
-  cell $and $and$ls180.v:5432$991
+  attribute \src "ls180.v:5507.41-5507.116"
+  cell $and $and$ls180.v:5507$1042
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238955,10 +239765,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_readable
     connect \B \main_sdblock2mem_fifo_syncfifo_re
-    connect \Y $and$ls180.v:5432$991_Y
+    connect \Y $and$ls180.v:5507$1042_Y
   end
-  attribute \src "ls180.v:5444.48-5444.125"
-  cell $and $and$ls180.v:5444$996
+  attribute \src "ls180.v:5519.48-5519.125"
+  cell $and $and$ls180.v:5519$1047
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238966,10 +239776,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_valid
     connect \B \main_sdblock2mem_converter_sink_ready
-    connect \Y $and$ls180.v:5444$996_Y
+    connect \Y $and$ls180.v:5519$1047_Y
   end
-  attribute \src "ls180.v:5471.9-5471.102"
-  cell $and $and$ls180.v:5471$1000
+  attribute \src "ls180.v:5546.9-5546.102"
+  cell $and $and$ls180.v:5546$1051
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238977,10 +239787,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid
     connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready
-    connect \Y $and$ls180.v:5471$1000_Y
+    connect \Y $and$ls180.v:5546$1051_Y
   end
-  attribute \src "ls180.v:5544.9-5544.58"
-  cell $and $and$ls180.v:5544$1006
+  attribute \src "ls180.v:5619.9-5619.58"
+  cell $and $and$ls180.v:5619$1057
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238988,10 +239798,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_interface1_bus_stb
     connect \B \main_interface1_bus_ack
-    connect \Y $and$ls180.v:5544$1006_Y
+    connect \Y $and$ls180.v:5619$1057_Y
   end
-  attribute \src "ls180.v:5597.51-5597.123"
-  cell $and $and$ls180.v:5597$1014
+  attribute \src "ls180.v:5672.51-5672.123"
+  cell $and $and$ls180.v:5672$1065
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -238999,10 +239809,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_sink_first
     connect \B \main_sdmem2block_converter_first
-    connect \Y $and$ls180.v:5597$1014_Y
+    connect \Y $and$ls180.v:5672$1065_Y
   end
-  attribute \src "ls180.v:5598.50-5598.120"
-  cell $and $and$ls180.v:5598$1015
+  attribute \src "ls180.v:5673.50-5673.120"
+  cell $and $and$ls180.v:5673$1066
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239010,10 +239820,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_sink_last
     connect \B \main_sdmem2block_converter_last
-    connect \Y $and$ls180.v:5598$1015_Y
+    connect \Y $and$ls180.v:5673$1066_Y
   end
-  attribute \src "ls180.v:5599.49-5599.122"
-  cell $and $and$ls180.v:5599$1016
+  attribute \src "ls180.v:5674.49-5674.122"
+  cell $and $and$ls180.v:5674$1067
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239021,21 +239831,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_last
     connect \B \main_sdmem2block_converter_source_ready
-    connect \Y $and$ls180.v:5599$1016_Y
+    connect \Y $and$ls180.v:5674$1067_Y
   end
-  attribute \src "ls180.v:5639.43-5639.152"
-  cell $and $and$ls180.v:5639$1021
+  attribute \src "ls180.v:5714.43-5714.152"
+  cell $and $and$ls180.v:5714$1072
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_we
-    connect \B $or$ls180.v:5639$1020_Y
-    connect \Y $and$ls180.v:5639$1021_Y
+    connect \B $or$ls180.v:5714$1071_Y
+    connect \Y $and$ls180.v:5714$1072_Y
   end
-  attribute \src "ls180.v:5640.41-5640.116"
-  cell $and $and$ls180.v:5640$1022
+  attribute \src "ls180.v:5715.41-5715.116"
+  cell $and $and$ls180.v:5715$1073
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239043,10 +239853,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_readable
     connect \B \main_sdmem2block_fifo_syncfifo_re
-    connect \Y $and$ls180.v:5640$1022_Y
+    connect \Y $and$ls180.v:5715$1073_Y
   end
-  attribute \src "ls180.v:5672.9-5672.76"
-  cell $and $and$ls180.v:5672$1026
+  attribute \src "ls180.v:5747.9-5747.76"
+  cell $and $and$ls180.v:5747$1077
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239054,131 +239864,131 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_libresocsim_wishbone_cyc
     connect \B \builder_libresocsim_wishbone_stb
-    connect \Y $and$ls180.v:5672$1026_Y
+    connect \Y $and$ls180.v:5747$1077_Y
   end
-  attribute \src "ls180.v:5675.44-5675.120"
-  cell $and $and$ls180.v:5675$1028
+  attribute \src "ls180.v:5750.44-5750.120"
+  cell $and $and$ls180.v:5750$1079
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_libresocsim_wishbone_we
-    connect \B $ne$ls180.v:5675$1027_Y
-    connect \Y $and$ls180.v:5675$1028_Y
+    connect \B $ne$ls180.v:5750$1078_Y
+    connect \Y $and$ls180.v:5750$1079_Y
   end
-  attribute \src "ls180.v:5695.63-5695.107"
-  cell $and $and$ls180.v:5695$1030
+  attribute \src "ls180.v:5770.63-5770.107"
+  cell $and $and$ls180.v:5770$1081
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \B $eq$ls180.v:5695$1029_Y
-    connect \Y $and$ls180.v:5695$1030_Y
+    connect \B $eq$ls180.v:5770$1080_Y
+    connect \Y $and$ls180.v:5770$1081_Y
   end
-  attribute \src "ls180.v:5696.63-5696.107"
-  cell $and $and$ls180.v:5696$1032
+  attribute \src "ls180.v:5771.63-5771.107"
+  cell $and $and$ls180.v:5771$1083
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \B $eq$ls180.v:5696$1031_Y
-    connect \Y $and$ls180.v:5696$1032_Y
+    connect \B $eq$ls180.v:5771$1082_Y
+    connect \Y $and$ls180.v:5771$1083_Y
   end
-  attribute \src "ls180.v:5697.63-5697.107"
-  cell $and $and$ls180.v:5697$1034
+  attribute \src "ls180.v:5772.63-5772.107"
+  cell $and $and$ls180.v:5772$1085
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \B $eq$ls180.v:5697$1033_Y
-    connect \Y $and$ls180.v:5697$1034_Y
+    connect \B $eq$ls180.v:5772$1084_Y
+    connect \Y $and$ls180.v:5772$1085_Y
   end
-  attribute \src "ls180.v:5698.35-5698.79"
-  cell $and $and$ls180.v:5698$1036
+  attribute \src "ls180.v:5773.35-5773.79"
+  cell $and $and$ls180.v:5773$1087
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \B $eq$ls180.v:5698$1035_Y
-    connect \Y $and$ls180.v:5698$1036_Y
+    connect \B $eq$ls180.v:5773$1086_Y
+    connect \Y $and$ls180.v:5773$1087_Y
   end
-  attribute \src "ls180.v:5699.35-5699.79"
-  cell $and $and$ls180.v:5699$1038
+  attribute \src "ls180.v:5774.35-5774.79"
+  cell $and $and$ls180.v:5774$1089
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \B $eq$ls180.v:5699$1037_Y
-    connect \Y $and$ls180.v:5699$1038_Y
+    connect \B $eq$ls180.v:5774$1088_Y
+    connect \Y $and$ls180.v:5774$1089_Y
   end
-  attribute \src "ls180.v:5700.63-5700.107"
-  cell $and $and$ls180.v:5700$1040
+  attribute \src "ls180.v:5775.63-5775.107"
+  cell $and $and$ls180.v:5775$1091
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_err
-    connect \B $eq$ls180.v:5700$1039_Y
-    connect \Y $and$ls180.v:5700$1040_Y
+    connect \B $eq$ls180.v:5775$1090_Y
+    connect \Y $and$ls180.v:5775$1091_Y
   end
-  attribute \src "ls180.v:5701.63-5701.107"
-  cell $and $and$ls180.v:5701$1042
+  attribute \src "ls180.v:5776.63-5776.107"
+  cell $and $and$ls180.v:5776$1093
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_err
-    connect \B $eq$ls180.v:5701$1041_Y
-    connect \Y $and$ls180.v:5701$1042_Y
+    connect \B $eq$ls180.v:5776$1092_Y
+    connect \Y $and$ls180.v:5776$1093_Y
   end
-  attribute \src "ls180.v:5702.63-5702.107"
-  cell $and $and$ls180.v:5702$1044
+  attribute \src "ls180.v:5777.63-5777.107"
+  cell $and $and$ls180.v:5777$1095
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_err
-    connect \B $eq$ls180.v:5702$1043_Y
-    connect \Y $and$ls180.v:5702$1044_Y
+    connect \B $eq$ls180.v:5777$1094_Y
+    connect \Y $and$ls180.v:5777$1095_Y
   end
-  attribute \src "ls180.v:5703.35-5703.79"
-  cell $and $and$ls180.v:5703$1046
+  attribute \src "ls180.v:5778.35-5778.79"
+  cell $and $and$ls180.v:5778$1097
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_err
-    connect \B $eq$ls180.v:5703$1045_Y
-    connect \Y $and$ls180.v:5703$1046_Y
+    connect \B $eq$ls180.v:5778$1096_Y
+    connect \Y $and$ls180.v:5778$1097_Y
   end
-  attribute \src "ls180.v:5704.35-5704.79"
-  cell $and $and$ls180.v:5704$1048
+  attribute \src "ls180.v:5779.35-5779.79"
+  cell $and $and$ls180.v:5779$1099
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_err
-    connect \B $eq$ls180.v:5704$1047_Y
-    connect \Y $and$ls180.v:5704$1048_Y
+    connect \B $eq$ls180.v:5779$1098_Y
+    connect \Y $and$ls180.v:5779$1099_Y
   end
-  attribute \src "ls180.v:5749.40-5749.81"
-  cell $and $and$ls180.v:5749$1055
+  attribute \src "ls180.v:5848.40-5848.81"
+  cell $and $and$ls180.v:5848$1109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239186,10 +239996,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_cyc
     connect \B \builder_slave_sel [0]
-    connect \Y $and$ls180.v:5749$1055_Y
+    connect \Y $and$ls180.v:5848$1109_Y
   end
-  attribute \src "ls180.v:5750.50-5750.91"
-  cell $and $and$ls180.v:5750$1056
+  attribute \src "ls180.v:5849.39-5849.80"
+  cell $and $and$ls180.v:5849$1110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239197,10 +240007,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_cyc
     connect \B \builder_slave_sel [1]
-    connect \Y $and$ls180.v:5750$1056_Y
+    connect \Y $and$ls180.v:5849$1110_Y
   end
-  attribute \src "ls180.v:5751.50-5751.91"
-  cell $and $and$ls180.v:5751$1057
+  attribute \src "ls180.v:5850.39-5850.80"
+  cell $and $and$ls180.v:5850$1111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239208,10 +240018,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_cyc
     connect \B \builder_slave_sel [2]
-    connect \Y $and$ls180.v:5751$1057_Y
+    connect \Y $and$ls180.v:5850$1111_Y
   end
-  attribute \src "ls180.v:5752.29-5752.70"
-  cell $and $and$ls180.v:5752$1058
+  attribute \src "ls180.v:5851.39-5851.80"
+  cell $and $and$ls180.v:5851$1112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239219,10 +240029,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_cyc
     connect \B \builder_slave_sel [3]
-    connect \Y $and$ls180.v:5752$1058_Y
+    connect \Y $and$ls180.v:5851$1112_Y
   end
-  attribute \src "ls180.v:5753.44-5753.85"
-  cell $and $and$ls180.v:5753$1059
+  attribute \src "ls180.v:5852.50-5852.91"
+  cell $and $and$ls180.v:5852$1113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239230,10 +240040,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_cyc
     connect \B \builder_slave_sel [4]
-    connect \Y $and$ls180.v:5753$1059_Y
+    connect \Y $and$ls180.v:5852$1113_Y
+  end
+  attribute \src "ls180.v:5853.50-5853.91"
+  cell $and $and$ls180.v:5853$1114
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_cyc
+    connect \B \builder_slave_sel [5]
+    connect \Y $and$ls180.v:5853$1114_Y
+  end
+  attribute \src "ls180.v:5854.29-5854.70"
+  cell $and $and$ls180.v:5854$1115
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_cyc
+    connect \B \builder_slave_sel [6]
+    connect \Y $and$ls180.v:5854$1115_Y
+  end
+  attribute \src "ls180.v:5855.44-5855.85"
+  cell $and $and$ls180.v:5855$1116
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_cyc
+    connect \B \builder_slave_sel [7]
+    connect \Y $and$ls180.v:5855$1116_Y
   end
-  attribute \src "ls180.v:5755.25-5755.64"
-  cell $and $and$ls180.v:5755$1064
+  attribute \src "ls180.v:5857.25-5857.64"
+  cell $and $and$ls180.v:5857$1124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239241,21 +240084,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_stb
     connect \B \builder_shared_cyc
-    connect \Y $and$ls180.v:5755$1064_Y
+    connect \Y $and$ls180.v:5857$1124_Y
   end
-  attribute \src "ls180.v:5755.24-5755.89"
-  cell $and $and$ls180.v:5755$1066
+  attribute \src "ls180.v:5857.24-5857.89"
+  cell $and $and$ls180.v:5857$1126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5755$1064_Y
-    connect \B $not$ls180.v:5755$1065_Y
-    connect \Y $and$ls180.v:5755$1066_Y
+    connect \A $and$ls180.v:5857$1124_Y
+    connect \B $not$ls180.v:5857$1125_Y
+    connect \Y $and$ls180.v:5857$1126_Y
   end
-  attribute \src "ls180.v:5761.31-5761.92"
-  cell $and $and$ls180.v:5761$1072
+  attribute \src "ls180.v:5863.34-5863.95"
+  cell $and $and$ls180.v:5863$1135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -239263,54 +240106,87 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] }
     connect \B \main_libresocsim_ram_bus_dat_r
-    connect \Y $and$ls180.v:5761$1072_Y
+    connect \Y $and$ls180.v:5863$1135_Y
   end
-  attribute \src "ls180.v:5761.97-5761.168"
-  cell $and $and$ls180.v:5761$1073
+  attribute \src "ls180.v:5863.100-5863.160"
+  cell $and $and$ls180.v:5863$1136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
     connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] }
-    connect \B \main_libresocsim_libresoc_xics_icp_dat_r
-    connect \Y $and$ls180.v:5761$1073_Y
+    connect \B \main_interface0_ram_bus_dat_r
+    connect \Y $and$ls180.v:5863$1136_Y
   end
-  attribute \src "ls180.v:5761.174-5761.245"
-  cell $and $and$ls180.v:5761$1075
+  attribute \src "ls180.v:5863.166-5863.226"
+  cell $and $and$ls180.v:5863$1138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
     connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] }
-    connect \B \main_libresocsim_libresoc_xics_ics_dat_r
-    connect \Y $and$ls180.v:5761$1075_Y
+    connect \B \main_interface1_ram_bus_dat_r
+    connect \Y $and$ls180.v:5863$1138_Y
   end
-  attribute \src "ls180.v:5761.251-5761.301"
-  cell $and $and$ls180.v:5761$1077
+  attribute \src "ls180.v:5863.232-5863.292"
+  cell $and $and$ls180.v:5863$1140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
     connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] }
-    connect \B \main_wb_sdram_dat_r
-    connect \Y $and$ls180.v:5761$1077_Y
+    connect \B \main_interface2_ram_bus_dat_r
+    connect \Y $and$ls180.v:5863$1140_Y
   end
-  attribute \src "ls180.v:5761.307-5761.372"
-  cell $and $and$ls180.v:5761$1079
+  attribute \src "ls180.v:5863.298-5863.369"
+  cell $and $and$ls180.v:5863$1142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
     connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] }
+    connect \B \main_libresocsim_libresoc_xics_icp_dat_r
+    connect \Y $and$ls180.v:5863$1142_Y
+  end
+  attribute \src "ls180.v:5863.375-5863.446"
+  cell $and $and$ls180.v:5863$1144
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] }
+    connect \B \main_libresocsim_libresoc_xics_ics_dat_r
+    connect \Y $and$ls180.v:5863$1144_Y
+  end
+  attribute \src "ls180.v:5863.452-5863.502"
+  cell $and $and$ls180.v:5863$1146
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] }
+    connect \B \main_wb_sdram_dat_r
+    connect \Y $and$ls180.v:5863$1146_Y
+  end
+  attribute \src "ls180.v:5863.508-5863.573"
+  cell $and $and$ls180.v:5863$1148
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] }
     connect \B \builder_libresocsim_wishbone_dat_r
-    connect \Y $and$ls180.v:5761$1079_Y
+    connect \Y $and$ls180.v:5863$1148_Y
   end
-  attribute \src "ls180.v:5771.39-5771.92"
-  cell $and $and$ls180.v:5771$1083
+  attribute \src "ls180.v:5873.39-5873.92"
+  cell $and $and$ls180.v:5873$1152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239318,43 +240194,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5771$1083_Y
+    connect \Y $and$ls180.v:5873$1152_Y
   end
-  attribute \src "ls180.v:5771.38-5771.142"
-  cell $and $and$ls180.v:5771$1085
+  attribute \src "ls180.v:5873.38-5873.142"
+  cell $and $and$ls180.v:5873$1154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5771$1083_Y
-    connect \B $eq$ls180.v:5771$1084_Y
-    connect \Y $and$ls180.v:5771$1085_Y
+    connect \A $and$ls180.v:5873$1152_Y
+    connect \B $eq$ls180.v:5873$1153_Y
+    connect \Y $and$ls180.v:5873$1154_Y
   end
-  attribute \src "ls180.v:5772.39-5772.95"
-  cell $and $and$ls180.v:5772$1087
+  attribute \src "ls180.v:5874.39-5874.95"
+  cell $and $and$ls180.v:5874$1156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5772$1086_Y
-    connect \Y $and$ls180.v:5772$1087_Y
+    connect \B $not$ls180.v:5874$1155_Y
+    connect \Y $and$ls180.v:5874$1156_Y
   end
-  attribute \src "ls180.v:5772.38-5772.145"
-  cell $and $and$ls180.v:5772$1089
+  attribute \src "ls180.v:5874.38-5874.145"
+  cell $and $and$ls180.v:5874$1158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5772$1087_Y
-    connect \B $eq$ls180.v:5772$1088_Y
-    connect \Y $and$ls180.v:5772$1089_Y
+    connect \A $and$ls180.v:5874$1156_Y
+    connect \B $eq$ls180.v:5874$1157_Y
+    connect \Y $and$ls180.v:5874$1158_Y
   end
-  attribute \src "ls180.v:5774.41-5774.94"
-  cell $and $and$ls180.v:5774$1090
+  attribute \src "ls180.v:5876.41-5876.94"
+  cell $and $and$ls180.v:5876$1159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239362,43 +240238,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5774$1090_Y
+    connect \Y $and$ls180.v:5876$1159_Y
   end
-  attribute \src "ls180.v:5774.40-5774.144"
-  cell $and $and$ls180.v:5774$1092
+  attribute \src "ls180.v:5876.40-5876.144"
+  cell $and $and$ls180.v:5876$1161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5774$1090_Y
-    connect \B $eq$ls180.v:5774$1091_Y
-    connect \Y $and$ls180.v:5774$1092_Y
+    connect \A $and$ls180.v:5876$1159_Y
+    connect \B $eq$ls180.v:5876$1160_Y
+    connect \Y $and$ls180.v:5876$1161_Y
   end
-  attribute \src "ls180.v:5775.41-5775.97"
-  cell $and $and$ls180.v:5775$1094
+  attribute \src "ls180.v:5877.41-5877.97"
+  cell $and $and$ls180.v:5877$1163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5775$1093_Y
-    connect \Y $and$ls180.v:5775$1094_Y
+    connect \B $not$ls180.v:5877$1162_Y
+    connect \Y $and$ls180.v:5877$1163_Y
   end
-  attribute \src "ls180.v:5775.40-5775.147"
-  cell $and $and$ls180.v:5775$1096
+  attribute \src "ls180.v:5877.40-5877.147"
+  cell $and $and$ls180.v:5877$1165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5775$1094_Y
-    connect \B $eq$ls180.v:5775$1095_Y
-    connect \Y $and$ls180.v:5775$1096_Y
+    connect \A $and$ls180.v:5877$1163_Y
+    connect \B $eq$ls180.v:5877$1164_Y
+    connect \Y $and$ls180.v:5877$1165_Y
   end
-  attribute \src "ls180.v:5777.41-5777.94"
-  cell $and $and$ls180.v:5777$1097
+  attribute \src "ls180.v:5879.41-5879.94"
+  cell $and $and$ls180.v:5879$1166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239406,43 +240282,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5777$1097_Y
+    connect \Y $and$ls180.v:5879$1166_Y
   end
-  attribute \src "ls180.v:5777.40-5777.144"
-  cell $and $and$ls180.v:5777$1099
+  attribute \src "ls180.v:5879.40-5879.144"
+  cell $and $and$ls180.v:5879$1168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5777$1097_Y
-    connect \B $eq$ls180.v:5777$1098_Y
-    connect \Y $and$ls180.v:5777$1099_Y
+    connect \A $and$ls180.v:5879$1166_Y
+    connect \B $eq$ls180.v:5879$1167_Y
+    connect \Y $and$ls180.v:5879$1168_Y
   end
-  attribute \src "ls180.v:5778.41-5778.97"
-  cell $and $and$ls180.v:5778$1101
+  attribute \src "ls180.v:5880.41-5880.97"
+  cell $and $and$ls180.v:5880$1170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5778$1100_Y
-    connect \Y $and$ls180.v:5778$1101_Y
+    connect \B $not$ls180.v:5880$1169_Y
+    connect \Y $and$ls180.v:5880$1170_Y
   end
-  attribute \src "ls180.v:5778.40-5778.147"
-  cell $and $and$ls180.v:5778$1103
+  attribute \src "ls180.v:5880.40-5880.147"
+  cell $and $and$ls180.v:5880$1172
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5778$1101_Y
-    connect \B $eq$ls180.v:5778$1102_Y
-    connect \Y $and$ls180.v:5778$1103_Y
+    connect \A $and$ls180.v:5880$1170_Y
+    connect \B $eq$ls180.v:5880$1171_Y
+    connect \Y $and$ls180.v:5880$1172_Y
   end
-  attribute \src "ls180.v:5780.41-5780.94"
-  cell $and $and$ls180.v:5780$1104
+  attribute \src "ls180.v:5882.41-5882.94"
+  cell $and $and$ls180.v:5882$1173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239450,43 +240326,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5780$1104_Y
+    connect \Y $and$ls180.v:5882$1173_Y
   end
-  attribute \src "ls180.v:5780.40-5780.144"
-  cell $and $and$ls180.v:5780$1106
+  attribute \src "ls180.v:5882.40-5882.144"
+  cell $and $and$ls180.v:5882$1175
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5780$1104_Y
-    connect \B $eq$ls180.v:5780$1105_Y
-    connect \Y $and$ls180.v:5780$1106_Y
+    connect \A $and$ls180.v:5882$1173_Y
+    connect \B $eq$ls180.v:5882$1174_Y
+    connect \Y $and$ls180.v:5882$1175_Y
   end
-  attribute \src "ls180.v:5781.41-5781.97"
-  cell $and $and$ls180.v:5781$1108
+  attribute \src "ls180.v:5883.41-5883.97"
+  cell $and $and$ls180.v:5883$1177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5781$1107_Y
-    connect \Y $and$ls180.v:5781$1108_Y
+    connect \B $not$ls180.v:5883$1176_Y
+    connect \Y $and$ls180.v:5883$1177_Y
   end
-  attribute \src "ls180.v:5781.40-5781.147"
-  cell $and $and$ls180.v:5781$1110
+  attribute \src "ls180.v:5883.40-5883.147"
+  cell $and $and$ls180.v:5883$1179
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5781$1108_Y
-    connect \B $eq$ls180.v:5781$1109_Y
-    connect \Y $and$ls180.v:5781$1110_Y
+    connect \A $and$ls180.v:5883$1177_Y
+    connect \B $eq$ls180.v:5883$1178_Y
+    connect \Y $and$ls180.v:5883$1179_Y
   end
-  attribute \src "ls180.v:5783.41-5783.94"
-  cell $and $and$ls180.v:5783$1111
+  attribute \src "ls180.v:5885.41-5885.94"
+  cell $and $and$ls180.v:5885$1180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239494,43 +240370,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5783$1111_Y
+    connect \Y $and$ls180.v:5885$1180_Y
   end
-  attribute \src "ls180.v:5783.40-5783.144"
-  cell $and $and$ls180.v:5783$1113
+  attribute \src "ls180.v:5885.40-5885.144"
+  cell $and $and$ls180.v:5885$1182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5783$1111_Y
-    connect \B $eq$ls180.v:5783$1112_Y
-    connect \Y $and$ls180.v:5783$1113_Y
+    connect \A $and$ls180.v:5885$1180_Y
+    connect \B $eq$ls180.v:5885$1181_Y
+    connect \Y $and$ls180.v:5885$1182_Y
   end
-  attribute \src "ls180.v:5784.41-5784.97"
-  cell $and $and$ls180.v:5784$1115
+  attribute \src "ls180.v:5886.41-5886.97"
+  cell $and $and$ls180.v:5886$1184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5784$1114_Y
-    connect \Y $and$ls180.v:5784$1115_Y
+    connect \B $not$ls180.v:5886$1183_Y
+    connect \Y $and$ls180.v:5886$1184_Y
   end
-  attribute \src "ls180.v:5784.40-5784.147"
-  cell $and $and$ls180.v:5784$1117
+  attribute \src "ls180.v:5886.40-5886.147"
+  cell $and $and$ls180.v:5886$1186
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5784$1115_Y
-    connect \B $eq$ls180.v:5784$1116_Y
-    connect \Y $and$ls180.v:5784$1117_Y
+    connect \A $and$ls180.v:5886$1184_Y
+    connect \B $eq$ls180.v:5886$1185_Y
+    connect \Y $and$ls180.v:5886$1186_Y
   end
-  attribute \src "ls180.v:5786.44-5786.97"
-  cell $and $and$ls180.v:5786$1118
+  attribute \src "ls180.v:5888.44-5888.97"
+  cell $and $and$ls180.v:5888$1187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239538,43 +240414,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5786$1118_Y
+    connect \Y $and$ls180.v:5888$1187_Y
   end
-  attribute \src "ls180.v:5786.43-5786.147"
-  cell $and $and$ls180.v:5786$1120
+  attribute \src "ls180.v:5888.43-5888.147"
+  cell $and $and$ls180.v:5888$1189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5786$1118_Y
-    connect \B $eq$ls180.v:5786$1119_Y
-    connect \Y $and$ls180.v:5786$1120_Y
+    connect \A $and$ls180.v:5888$1187_Y
+    connect \B $eq$ls180.v:5888$1188_Y
+    connect \Y $and$ls180.v:5888$1189_Y
   end
-  attribute \src "ls180.v:5787.44-5787.100"
-  cell $and $and$ls180.v:5787$1122
+  attribute \src "ls180.v:5889.44-5889.100"
+  cell $and $and$ls180.v:5889$1191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5787$1121_Y
-    connect \Y $and$ls180.v:5787$1122_Y
+    connect \B $not$ls180.v:5889$1190_Y
+    connect \Y $and$ls180.v:5889$1191_Y
   end
-  attribute \src "ls180.v:5787.43-5787.150"
-  cell $and $and$ls180.v:5787$1124
+  attribute \src "ls180.v:5889.43-5889.150"
+  cell $and $and$ls180.v:5889$1193
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5787$1122_Y
-    connect \B $eq$ls180.v:5787$1123_Y
-    connect \Y $and$ls180.v:5787$1124_Y
+    connect \A $and$ls180.v:5889$1191_Y
+    connect \B $eq$ls180.v:5889$1192_Y
+    connect \Y $and$ls180.v:5889$1193_Y
   end
-  attribute \src "ls180.v:5789.44-5789.97"
-  cell $and $and$ls180.v:5789$1125
+  attribute \src "ls180.v:5891.44-5891.97"
+  cell $and $and$ls180.v:5891$1194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239582,43 +240458,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5789$1125_Y
+    connect \Y $and$ls180.v:5891$1194_Y
   end
-  attribute \src "ls180.v:5789.43-5789.147"
-  cell $and $and$ls180.v:5789$1127
+  attribute \src "ls180.v:5891.43-5891.147"
+  cell $and $and$ls180.v:5891$1196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5789$1125_Y
-    connect \B $eq$ls180.v:5789$1126_Y
-    connect \Y $and$ls180.v:5789$1127_Y
+    connect \A $and$ls180.v:5891$1194_Y
+    connect \B $eq$ls180.v:5891$1195_Y
+    connect \Y $and$ls180.v:5891$1196_Y
   end
-  attribute \src "ls180.v:5790.44-5790.100"
-  cell $and $and$ls180.v:5790$1129
+  attribute \src "ls180.v:5892.44-5892.100"
+  cell $and $and$ls180.v:5892$1198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5790$1128_Y
-    connect \Y $and$ls180.v:5790$1129_Y
+    connect \B $not$ls180.v:5892$1197_Y
+    connect \Y $and$ls180.v:5892$1198_Y
   end
-  attribute \src "ls180.v:5790.43-5790.150"
-  cell $and $and$ls180.v:5790$1131
+  attribute \src "ls180.v:5892.43-5892.150"
+  cell $and $and$ls180.v:5892$1200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5790$1129_Y
-    connect \B $eq$ls180.v:5790$1130_Y
-    connect \Y $and$ls180.v:5790$1131_Y
+    connect \A $and$ls180.v:5892$1198_Y
+    connect \B $eq$ls180.v:5892$1199_Y
+    connect \Y $and$ls180.v:5892$1200_Y
   end
-  attribute \src "ls180.v:5792.44-5792.97"
-  cell $and $and$ls180.v:5792$1132
+  attribute \src "ls180.v:5894.44-5894.97"
+  cell $and $and$ls180.v:5894$1201
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239626,43 +240502,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5792$1132_Y
+    connect \Y $and$ls180.v:5894$1201_Y
   end
-  attribute \src "ls180.v:5792.43-5792.147"
-  cell $and $and$ls180.v:5792$1134
+  attribute \src "ls180.v:5894.43-5894.147"
+  cell $and $and$ls180.v:5894$1203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5792$1132_Y
-    connect \B $eq$ls180.v:5792$1133_Y
-    connect \Y $and$ls180.v:5792$1134_Y
+    connect \A $and$ls180.v:5894$1201_Y
+    connect \B $eq$ls180.v:5894$1202_Y
+    connect \Y $and$ls180.v:5894$1203_Y
   end
-  attribute \src "ls180.v:5793.44-5793.100"
-  cell $and $and$ls180.v:5793$1136
+  attribute \src "ls180.v:5895.44-5895.100"
+  cell $and $and$ls180.v:5895$1205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5793$1135_Y
-    connect \Y $and$ls180.v:5793$1136_Y
+    connect \B $not$ls180.v:5895$1204_Y
+    connect \Y $and$ls180.v:5895$1205_Y
   end
-  attribute \src "ls180.v:5793.43-5793.150"
-  cell $and $and$ls180.v:5793$1138
+  attribute \src "ls180.v:5895.43-5895.150"
+  cell $and $and$ls180.v:5895$1207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5793$1136_Y
-    connect \B $eq$ls180.v:5793$1137_Y
-    connect \Y $and$ls180.v:5793$1138_Y
+    connect \A $and$ls180.v:5895$1205_Y
+    connect \B $eq$ls180.v:5895$1206_Y
+    connect \Y $and$ls180.v:5895$1207_Y
   end
-  attribute \src "ls180.v:5795.44-5795.97"
-  cell $and $and$ls180.v:5795$1139
+  attribute \src "ls180.v:5897.44-5897.97"
+  cell $and $and$ls180.v:5897$1208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239670,43 +240546,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
     connect \B \builder_interface0_bank_bus_we
-    connect \Y $and$ls180.v:5795$1139_Y
+    connect \Y $and$ls180.v:5897$1208_Y
   end
-  attribute \src "ls180.v:5795.43-5795.147"
-  cell $and $and$ls180.v:5795$1141
+  attribute \src "ls180.v:5897.43-5897.147"
+  cell $and $and$ls180.v:5897$1210
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5795$1139_Y
-    connect \B $eq$ls180.v:5795$1140_Y
-    connect \Y $and$ls180.v:5795$1141_Y
+    connect \A $and$ls180.v:5897$1208_Y
+    connect \B $eq$ls180.v:5897$1209_Y
+    connect \Y $and$ls180.v:5897$1210_Y
   end
-  attribute \src "ls180.v:5796.44-5796.100"
-  cell $and $and$ls180.v:5796$1143
+  attribute \src "ls180.v:5898.44-5898.100"
+  cell $and $and$ls180.v:5898$1212
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank0_sel
-    connect \B $not$ls180.v:5796$1142_Y
-    connect \Y $and$ls180.v:5796$1143_Y
+    connect \B $not$ls180.v:5898$1211_Y
+    connect \Y $and$ls180.v:5898$1212_Y
   end
-  attribute \src "ls180.v:5796.43-5796.150"
-  cell $and $and$ls180.v:5796$1145
+  attribute \src "ls180.v:5898.43-5898.150"
+  cell $and $and$ls180.v:5898$1214
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5796$1143_Y
-    connect \B $eq$ls180.v:5796$1144_Y
-    connect \Y $and$ls180.v:5796$1145_Y
+    connect \A $and$ls180.v:5898$1212_Y
+    connect \B $eq$ls180.v:5898$1213_Y
+    connect \Y $and$ls180.v:5898$1214_Y
   end
-  attribute \src "ls180.v:5809.36-5809.89"
-  cell $and $and$ls180.v:5809$1147
+  attribute \src "ls180.v:5911.36-5911.89"
+  cell $and $and$ls180.v:5911$1216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239714,43 +240590,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5809$1147_Y
+    connect \Y $and$ls180.v:5911$1216_Y
   end
-  attribute \src "ls180.v:5809.35-5809.139"
-  cell $and $and$ls180.v:5809$1149
+  attribute \src "ls180.v:5911.35-5911.139"
+  cell $and $and$ls180.v:5911$1218
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5809$1147_Y
-    connect \B $eq$ls180.v:5809$1148_Y
-    connect \Y $and$ls180.v:5809$1149_Y
+    connect \A $and$ls180.v:5911$1216_Y
+    connect \B $eq$ls180.v:5911$1217_Y
+    connect \Y $and$ls180.v:5911$1218_Y
   end
-  attribute \src "ls180.v:5810.36-5810.92"
-  cell $and $and$ls180.v:5810$1151
+  attribute \src "ls180.v:5912.36-5912.92"
+  cell $and $and$ls180.v:5912$1220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5810$1150_Y
-    connect \Y $and$ls180.v:5810$1151_Y
+    connect \B $not$ls180.v:5912$1219_Y
+    connect \Y $and$ls180.v:5912$1220_Y
   end
-  attribute \src "ls180.v:5810.35-5810.142"
-  cell $and $and$ls180.v:5810$1153
+  attribute \src "ls180.v:5912.35-5912.142"
+  cell $and $and$ls180.v:5912$1222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5810$1151_Y
-    connect \B $eq$ls180.v:5810$1152_Y
-    connect \Y $and$ls180.v:5810$1153_Y
+    connect \A $and$ls180.v:5912$1220_Y
+    connect \B $eq$ls180.v:5912$1221_Y
+    connect \Y $and$ls180.v:5912$1222_Y
   end
-  attribute \src "ls180.v:5812.36-5812.89"
-  cell $and $and$ls180.v:5812$1154
+  attribute \src "ls180.v:5914.36-5914.89"
+  cell $and $and$ls180.v:5914$1223
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239758,43 +240634,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5812$1154_Y
+    connect \Y $and$ls180.v:5914$1223_Y
   end
-  attribute \src "ls180.v:5812.35-5812.139"
-  cell $and $and$ls180.v:5812$1156
+  attribute \src "ls180.v:5914.35-5914.139"
+  cell $and $and$ls180.v:5914$1225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5812$1154_Y
-    connect \B $eq$ls180.v:5812$1155_Y
-    connect \Y $and$ls180.v:5812$1156_Y
+    connect \A $and$ls180.v:5914$1223_Y
+    connect \B $eq$ls180.v:5914$1224_Y
+    connect \Y $and$ls180.v:5914$1225_Y
   end
-  attribute \src "ls180.v:5813.36-5813.92"
-  cell $and $and$ls180.v:5813$1158
+  attribute \src "ls180.v:5915.36-5915.92"
+  cell $and $and$ls180.v:5915$1227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5813$1157_Y
-    connect \Y $and$ls180.v:5813$1158_Y
+    connect \B $not$ls180.v:5915$1226_Y
+    connect \Y $and$ls180.v:5915$1227_Y
   end
-  attribute \src "ls180.v:5813.35-5813.142"
-  cell $and $and$ls180.v:5813$1160
+  attribute \src "ls180.v:5915.35-5915.142"
+  cell $and $and$ls180.v:5915$1229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5813$1158_Y
-    connect \B $eq$ls180.v:5813$1159_Y
-    connect \Y $and$ls180.v:5813$1160_Y
+    connect \A $and$ls180.v:5915$1227_Y
+    connect \B $eq$ls180.v:5915$1228_Y
+    connect \Y $and$ls180.v:5915$1229_Y
   end
-  attribute \src "ls180.v:5815.36-5815.89"
-  cell $and $and$ls180.v:5815$1161
+  attribute \src "ls180.v:5917.36-5917.89"
+  cell $and $and$ls180.v:5917$1230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239802,43 +240678,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5815$1161_Y
+    connect \Y $and$ls180.v:5917$1230_Y
   end
-  attribute \src "ls180.v:5815.35-5815.139"
-  cell $and $and$ls180.v:5815$1163
+  attribute \src "ls180.v:5917.35-5917.139"
+  cell $and $and$ls180.v:5917$1232
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5815$1161_Y
-    connect \B $eq$ls180.v:5815$1162_Y
-    connect \Y $and$ls180.v:5815$1163_Y
+    connect \A $and$ls180.v:5917$1230_Y
+    connect \B $eq$ls180.v:5917$1231_Y
+    connect \Y $and$ls180.v:5917$1232_Y
   end
-  attribute \src "ls180.v:5816.36-5816.92"
-  cell $and $and$ls180.v:5816$1165
+  attribute \src "ls180.v:5918.36-5918.92"
+  cell $and $and$ls180.v:5918$1234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5816$1164_Y
-    connect \Y $and$ls180.v:5816$1165_Y
+    connect \B $not$ls180.v:5918$1233_Y
+    connect \Y $and$ls180.v:5918$1234_Y
   end
-  attribute \src "ls180.v:5816.35-5816.142"
-  cell $and $and$ls180.v:5816$1167
+  attribute \src "ls180.v:5918.35-5918.142"
+  cell $and $and$ls180.v:5918$1236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5816$1165_Y
-    connect \B $eq$ls180.v:5816$1166_Y
-    connect \Y $and$ls180.v:5816$1167_Y
+    connect \A $and$ls180.v:5918$1234_Y
+    connect \B $eq$ls180.v:5918$1235_Y
+    connect \Y $and$ls180.v:5918$1236_Y
   end
-  attribute \src "ls180.v:5818.36-5818.89"
-  cell $and $and$ls180.v:5818$1168
+  attribute \src "ls180.v:5920.36-5920.89"
+  cell $and $and$ls180.v:5920$1237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239846,43 +240722,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5818$1168_Y
+    connect \Y $and$ls180.v:5920$1237_Y
   end
-  attribute \src "ls180.v:5818.35-5818.139"
-  cell $and $and$ls180.v:5818$1170
+  attribute \src "ls180.v:5920.35-5920.139"
+  cell $and $and$ls180.v:5920$1239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5818$1168_Y
-    connect \B $eq$ls180.v:5818$1169_Y
-    connect \Y $and$ls180.v:5818$1170_Y
+    connect \A $and$ls180.v:5920$1237_Y
+    connect \B $eq$ls180.v:5920$1238_Y
+    connect \Y $and$ls180.v:5920$1239_Y
   end
-  attribute \src "ls180.v:5819.36-5819.92"
-  cell $and $and$ls180.v:5819$1172
+  attribute \src "ls180.v:5921.36-5921.92"
+  cell $and $and$ls180.v:5921$1241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5819$1171_Y
-    connect \Y $and$ls180.v:5819$1172_Y
+    connect \B $not$ls180.v:5921$1240_Y
+    connect \Y $and$ls180.v:5921$1241_Y
   end
-  attribute \src "ls180.v:5819.35-5819.142"
-  cell $and $and$ls180.v:5819$1174
+  attribute \src "ls180.v:5921.35-5921.142"
+  cell $and $and$ls180.v:5921$1243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5819$1172_Y
-    connect \B $eq$ls180.v:5819$1173_Y
-    connect \Y $and$ls180.v:5819$1174_Y
+    connect \A $and$ls180.v:5921$1241_Y
+    connect \B $eq$ls180.v:5921$1242_Y
+    connect \Y $and$ls180.v:5921$1243_Y
   end
-  attribute \src "ls180.v:5821.37-5821.90"
-  cell $and $and$ls180.v:5821$1175
+  attribute \src "ls180.v:5923.37-5923.90"
+  cell $and $and$ls180.v:5923$1244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239890,43 +240766,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5821$1175_Y
+    connect \Y $and$ls180.v:5923$1244_Y
   end
-  attribute \src "ls180.v:5821.36-5821.140"
-  cell $and $and$ls180.v:5821$1177
+  attribute \src "ls180.v:5923.36-5923.140"
+  cell $and $and$ls180.v:5923$1246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5821$1175_Y
-    connect \B $eq$ls180.v:5821$1176_Y
-    connect \Y $and$ls180.v:5821$1177_Y
+    connect \A $and$ls180.v:5923$1244_Y
+    connect \B $eq$ls180.v:5923$1245_Y
+    connect \Y $and$ls180.v:5923$1246_Y
   end
-  attribute \src "ls180.v:5822.37-5822.93"
-  cell $and $and$ls180.v:5822$1179
+  attribute \src "ls180.v:5924.37-5924.93"
+  cell $and $and$ls180.v:5924$1248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5822$1178_Y
-    connect \Y $and$ls180.v:5822$1179_Y
+    connect \B $not$ls180.v:5924$1247_Y
+    connect \Y $and$ls180.v:5924$1248_Y
   end
-  attribute \src "ls180.v:5822.36-5822.143"
-  cell $and $and$ls180.v:5822$1181
+  attribute \src "ls180.v:5924.36-5924.143"
+  cell $and $and$ls180.v:5924$1250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5822$1179_Y
-    connect \B $eq$ls180.v:5822$1180_Y
-    connect \Y $and$ls180.v:5822$1181_Y
+    connect \A $and$ls180.v:5924$1248_Y
+    connect \B $eq$ls180.v:5924$1249_Y
+    connect \Y $and$ls180.v:5924$1250_Y
   end
-  attribute \src "ls180.v:5824.37-5824.90"
-  cell $and $and$ls180.v:5824$1182
+  attribute \src "ls180.v:5926.37-5926.90"
+  cell $and $and$ls180.v:5926$1251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239934,43 +240810,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
     connect \B \builder_interface1_bank_bus_we
-    connect \Y $and$ls180.v:5824$1182_Y
+    connect \Y $and$ls180.v:5926$1251_Y
   end
-  attribute \src "ls180.v:5824.36-5824.140"
-  cell $and $and$ls180.v:5824$1184
+  attribute \src "ls180.v:5926.36-5926.140"
+  cell $and $and$ls180.v:5926$1253
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5824$1182_Y
-    connect \B $eq$ls180.v:5824$1183_Y
-    connect \Y $and$ls180.v:5824$1184_Y
+    connect \A $and$ls180.v:5926$1251_Y
+    connect \B $eq$ls180.v:5926$1252_Y
+    connect \Y $and$ls180.v:5926$1253_Y
   end
-  attribute \src "ls180.v:5825.37-5825.93"
-  cell $and $and$ls180.v:5825$1186
+  attribute \src "ls180.v:5927.37-5927.93"
+  cell $and $and$ls180.v:5927$1255
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank1_sel
-    connect \B $not$ls180.v:5825$1185_Y
-    connect \Y $and$ls180.v:5825$1186_Y
+    connect \B $not$ls180.v:5927$1254_Y
+    connect \Y $and$ls180.v:5927$1255_Y
   end
-  attribute \src "ls180.v:5825.36-5825.143"
-  cell $and $and$ls180.v:5825$1188
+  attribute \src "ls180.v:5927.36-5927.143"
+  cell $and $and$ls180.v:5927$1257
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5825$1186_Y
-    connect \B $eq$ls180.v:5825$1187_Y
-    connect \Y $and$ls180.v:5825$1188_Y
+    connect \A $and$ls180.v:5927$1255_Y
+    connect \B $eq$ls180.v:5927$1256_Y
+    connect \Y $and$ls180.v:5927$1257_Y
   end
-  attribute \src "ls180.v:5835.35-5835.88"
-  cell $and $and$ls180.v:5835$1190
+  attribute \src "ls180.v:5937.35-5937.88"
+  cell $and $and$ls180.v:5937$1259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -239978,43 +240854,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank2_sel
     connect \B \builder_interface2_bank_bus_we
-    connect \Y $and$ls180.v:5835$1190_Y
+    connect \Y $and$ls180.v:5937$1259_Y
   end
-  attribute \src "ls180.v:5835.34-5835.136"
-  cell $and $and$ls180.v:5835$1192
+  attribute \src "ls180.v:5937.34-5937.136"
+  cell $and $and$ls180.v:5937$1261
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5835$1190_Y
-    connect \B $eq$ls180.v:5835$1191_Y
-    connect \Y $and$ls180.v:5835$1192_Y
+    connect \A $and$ls180.v:5937$1259_Y
+    connect \B $eq$ls180.v:5937$1260_Y
+    connect \Y $and$ls180.v:5937$1261_Y
   end
-  attribute \src "ls180.v:5836.35-5836.91"
-  cell $and $and$ls180.v:5836$1194
+  attribute \src "ls180.v:5938.35-5938.91"
+  cell $and $and$ls180.v:5938$1263
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank2_sel
-    connect \B $not$ls180.v:5836$1193_Y
-    connect \Y $and$ls180.v:5836$1194_Y
+    connect \B $not$ls180.v:5938$1262_Y
+    connect \Y $and$ls180.v:5938$1263_Y
   end
-  attribute \src "ls180.v:5836.34-5836.139"
-  cell $and $and$ls180.v:5836$1196
+  attribute \src "ls180.v:5938.34-5938.139"
+  cell $and $and$ls180.v:5938$1265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5836$1194_Y
-    connect \B $eq$ls180.v:5836$1195_Y
-    connect \Y $and$ls180.v:5836$1196_Y
+    connect \A $and$ls180.v:5938$1263_Y
+    connect \B $eq$ls180.v:5938$1264_Y
+    connect \Y $and$ls180.v:5938$1265_Y
   end
-  attribute \src "ls180.v:5838.34-5838.87"
-  cell $and $and$ls180.v:5838$1197
+  attribute \src "ls180.v:5940.34-5940.87"
+  cell $and $and$ls180.v:5940$1266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240022,43 +240898,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank2_sel
     connect \B \builder_interface2_bank_bus_we
-    connect \Y $and$ls180.v:5838$1197_Y
+    connect \Y $and$ls180.v:5940$1266_Y
   end
-  attribute \src "ls180.v:5838.33-5838.135"
-  cell $and $and$ls180.v:5838$1199
+  attribute \src "ls180.v:5940.33-5940.135"
+  cell $and $and$ls180.v:5940$1268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5838$1197_Y
-    connect \B $eq$ls180.v:5838$1198_Y
-    connect \Y $and$ls180.v:5838$1199_Y
+    connect \A $and$ls180.v:5940$1266_Y
+    connect \B $eq$ls180.v:5940$1267_Y
+    connect \Y $and$ls180.v:5940$1268_Y
   end
-  attribute \src "ls180.v:5839.34-5839.90"
-  cell $and $and$ls180.v:5839$1201
+  attribute \src "ls180.v:5941.34-5941.90"
+  cell $and $and$ls180.v:5941$1270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank2_sel
-    connect \B $not$ls180.v:5839$1200_Y
-    connect \Y $and$ls180.v:5839$1201_Y
+    connect \B $not$ls180.v:5941$1269_Y
+    connect \Y $and$ls180.v:5941$1270_Y
   end
-  attribute \src "ls180.v:5839.33-5839.138"
-  cell $and $and$ls180.v:5839$1203
+  attribute \src "ls180.v:5941.33-5941.138"
+  cell $and $and$ls180.v:5941$1272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5839$1201_Y
-    connect \B $eq$ls180.v:5839$1202_Y
-    connect \Y $and$ls180.v:5839$1203_Y
+    connect \A $and$ls180.v:5941$1270_Y
+    connect \B $eq$ls180.v:5941$1271_Y
+    connect \Y $and$ls180.v:5941$1272_Y
   end
-  attribute \src "ls180.v:5849.40-5849.93"
-  cell $and $and$ls180.v:5849$1205
+  attribute \src "ls180.v:5951.40-5951.93"
+  cell $and $and$ls180.v:5951$1274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240066,43 +240942,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5849$1205_Y
+    connect \Y $and$ls180.v:5951$1274_Y
   end
-  attribute \src "ls180.v:5849.39-5849.143"
-  cell $and $and$ls180.v:5849$1207
+  attribute \src "ls180.v:5951.39-5951.143"
+  cell $and $and$ls180.v:5951$1276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5849$1205_Y
-    connect \B $eq$ls180.v:5849$1206_Y
-    connect \Y $and$ls180.v:5849$1207_Y
+    connect \A $and$ls180.v:5951$1274_Y
+    connect \B $eq$ls180.v:5951$1275_Y
+    connect \Y $and$ls180.v:5951$1276_Y
   end
-  attribute \src "ls180.v:5850.40-5850.96"
-  cell $and $and$ls180.v:5850$1209
+  attribute \src "ls180.v:5952.40-5952.96"
+  cell $and $and$ls180.v:5952$1278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5850$1208_Y
-    connect \Y $and$ls180.v:5850$1209_Y
+    connect \B $not$ls180.v:5952$1277_Y
+    connect \Y $and$ls180.v:5952$1278_Y
   end
-  attribute \src "ls180.v:5850.39-5850.146"
-  cell $and $and$ls180.v:5850$1211
+  attribute \src "ls180.v:5952.39-5952.146"
+  cell $and $and$ls180.v:5952$1280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5850$1209_Y
-    connect \B $eq$ls180.v:5850$1210_Y
-    connect \Y $and$ls180.v:5850$1211_Y
+    connect \A $and$ls180.v:5952$1278_Y
+    connect \B $eq$ls180.v:5952$1279_Y
+    connect \Y $and$ls180.v:5952$1280_Y
   end
-  attribute \src "ls180.v:5852.39-5852.92"
-  cell $and $and$ls180.v:5852$1212
+  attribute \src "ls180.v:5954.39-5954.92"
+  cell $and $and$ls180.v:5954$1281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240110,43 +240986,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5852$1212_Y
+    connect \Y $and$ls180.v:5954$1281_Y
   end
-  attribute \src "ls180.v:5852.38-5852.142"
-  cell $and $and$ls180.v:5852$1214
+  attribute \src "ls180.v:5954.38-5954.142"
+  cell $and $and$ls180.v:5954$1283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5852$1212_Y
-    connect \B $eq$ls180.v:5852$1213_Y
-    connect \Y $and$ls180.v:5852$1214_Y
+    connect \A $and$ls180.v:5954$1281_Y
+    connect \B $eq$ls180.v:5954$1282_Y
+    connect \Y $and$ls180.v:5954$1283_Y
   end
-  attribute \src "ls180.v:5853.39-5853.95"
-  cell $and $and$ls180.v:5853$1216
+  attribute \src "ls180.v:5955.39-5955.95"
+  cell $and $and$ls180.v:5955$1285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5853$1215_Y
-    connect \Y $and$ls180.v:5853$1216_Y
+    connect \B $not$ls180.v:5955$1284_Y
+    connect \Y $and$ls180.v:5955$1285_Y
   end
-  attribute \src "ls180.v:5853.38-5853.145"
-  cell $and $and$ls180.v:5853$1218
+  attribute \src "ls180.v:5955.38-5955.145"
+  cell $and $and$ls180.v:5955$1287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5853$1216_Y
-    connect \B $eq$ls180.v:5853$1217_Y
-    connect \Y $and$ls180.v:5853$1218_Y
+    connect \A $and$ls180.v:5955$1285_Y
+    connect \B $eq$ls180.v:5955$1286_Y
+    connect \Y $and$ls180.v:5955$1287_Y
   end
-  attribute \src "ls180.v:5855.39-5855.92"
-  cell $and $and$ls180.v:5855$1219
+  attribute \src "ls180.v:5957.39-5957.92"
+  cell $and $and$ls180.v:5957$1288
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240154,43 +241030,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5855$1219_Y
+    connect \Y $and$ls180.v:5957$1288_Y
   end
-  attribute \src "ls180.v:5855.38-5855.142"
-  cell $and $and$ls180.v:5855$1221
+  attribute \src "ls180.v:5957.38-5957.142"
+  cell $and $and$ls180.v:5957$1290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5855$1219_Y
-    connect \B $eq$ls180.v:5855$1220_Y
-    connect \Y $and$ls180.v:5855$1221_Y
+    connect \A $and$ls180.v:5957$1288_Y
+    connect \B $eq$ls180.v:5957$1289_Y
+    connect \Y $and$ls180.v:5957$1290_Y
   end
-  attribute \src "ls180.v:5856.39-5856.95"
-  cell $and $and$ls180.v:5856$1223
+  attribute \src "ls180.v:5958.39-5958.95"
+  cell $and $and$ls180.v:5958$1292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5856$1222_Y
-    connect \Y $and$ls180.v:5856$1223_Y
+    connect \B $not$ls180.v:5958$1291_Y
+    connect \Y $and$ls180.v:5958$1292_Y
   end
-  attribute \src "ls180.v:5856.38-5856.145"
-  cell $and $and$ls180.v:5856$1225
+  attribute \src "ls180.v:5958.38-5958.145"
+  cell $and $and$ls180.v:5958$1294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5856$1223_Y
-    connect \B $eq$ls180.v:5856$1224_Y
-    connect \Y $and$ls180.v:5856$1225_Y
+    connect \A $and$ls180.v:5958$1292_Y
+    connect \B $eq$ls180.v:5958$1293_Y
+    connect \Y $and$ls180.v:5958$1294_Y
   end
-  attribute \src "ls180.v:5858.39-5858.92"
-  cell $and $and$ls180.v:5858$1226
+  attribute \src "ls180.v:5960.39-5960.92"
+  cell $and $and$ls180.v:5960$1295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240198,43 +241074,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5858$1226_Y
+    connect \Y $and$ls180.v:5960$1295_Y
   end
-  attribute \src "ls180.v:5858.38-5858.142"
-  cell $and $and$ls180.v:5858$1228
+  attribute \src "ls180.v:5960.38-5960.142"
+  cell $and $and$ls180.v:5960$1297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5858$1226_Y
-    connect \B $eq$ls180.v:5858$1227_Y
-    connect \Y $and$ls180.v:5858$1228_Y
+    connect \A $and$ls180.v:5960$1295_Y
+    connect \B $eq$ls180.v:5960$1296_Y
+    connect \Y $and$ls180.v:5960$1297_Y
   end
-  attribute \src "ls180.v:5859.39-5859.95"
-  cell $and $and$ls180.v:5859$1230
+  attribute \src "ls180.v:5961.39-5961.95"
+  cell $and $and$ls180.v:5961$1299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5859$1229_Y
-    connect \Y $and$ls180.v:5859$1230_Y
+    connect \B $not$ls180.v:5961$1298_Y
+    connect \Y $and$ls180.v:5961$1299_Y
   end
-  attribute \src "ls180.v:5859.38-5859.145"
-  cell $and $and$ls180.v:5859$1232
+  attribute \src "ls180.v:5961.38-5961.145"
+  cell $and $and$ls180.v:5961$1301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5859$1230_Y
-    connect \B $eq$ls180.v:5859$1231_Y
-    connect \Y $and$ls180.v:5859$1232_Y
+    connect \A $and$ls180.v:5961$1299_Y
+    connect \B $eq$ls180.v:5961$1300_Y
+    connect \Y $and$ls180.v:5961$1301_Y
   end
-  attribute \src "ls180.v:5861.39-5861.92"
-  cell $and $and$ls180.v:5861$1233
+  attribute \src "ls180.v:5963.39-5963.92"
+  cell $and $and$ls180.v:5963$1302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240242,43 +241118,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5861$1233_Y
+    connect \Y $and$ls180.v:5963$1302_Y
   end
-  attribute \src "ls180.v:5861.38-5861.142"
-  cell $and $and$ls180.v:5861$1235
+  attribute \src "ls180.v:5963.38-5963.142"
+  cell $and $and$ls180.v:5963$1304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5861$1233_Y
-    connect \B $eq$ls180.v:5861$1234_Y
-    connect \Y $and$ls180.v:5861$1235_Y
+    connect \A $and$ls180.v:5963$1302_Y
+    connect \B $eq$ls180.v:5963$1303_Y
+    connect \Y $and$ls180.v:5963$1304_Y
   end
-  attribute \src "ls180.v:5862.39-5862.95"
-  cell $and $and$ls180.v:5862$1237
+  attribute \src "ls180.v:5964.39-5964.95"
+  cell $and $and$ls180.v:5964$1306
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5862$1236_Y
-    connect \Y $and$ls180.v:5862$1237_Y
+    connect \B $not$ls180.v:5964$1305_Y
+    connect \Y $and$ls180.v:5964$1306_Y
   end
-  attribute \src "ls180.v:5862.38-5862.145"
-  cell $and $and$ls180.v:5862$1239
+  attribute \src "ls180.v:5964.38-5964.145"
+  cell $and $and$ls180.v:5964$1308
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5862$1237_Y
-    connect \B $eq$ls180.v:5862$1238_Y
-    connect \Y $and$ls180.v:5862$1239_Y
+    connect \A $and$ls180.v:5964$1306_Y
+    connect \B $eq$ls180.v:5964$1307_Y
+    connect \Y $and$ls180.v:5964$1308_Y
   end
-  attribute \src "ls180.v:5864.40-5864.93"
-  cell $and $and$ls180.v:5864$1240
+  attribute \src "ls180.v:5966.40-5966.93"
+  cell $and $and$ls180.v:5966$1309
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240286,43 +241162,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5864$1240_Y
+    connect \Y $and$ls180.v:5966$1309_Y
   end
-  attribute \src "ls180.v:5864.39-5864.143"
-  cell $and $and$ls180.v:5864$1242
+  attribute \src "ls180.v:5966.39-5966.143"
+  cell $and $and$ls180.v:5966$1311
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5864$1240_Y
-    connect \B $eq$ls180.v:5864$1241_Y
-    connect \Y $and$ls180.v:5864$1242_Y
+    connect \A $and$ls180.v:5966$1309_Y
+    connect \B $eq$ls180.v:5966$1310_Y
+    connect \Y $and$ls180.v:5966$1311_Y
   end
-  attribute \src "ls180.v:5865.40-5865.96"
-  cell $and $and$ls180.v:5865$1244
+  attribute \src "ls180.v:5967.40-5967.96"
+  cell $and $and$ls180.v:5967$1313
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5865$1243_Y
-    connect \Y $and$ls180.v:5865$1244_Y
+    connect \B $not$ls180.v:5967$1312_Y
+    connect \Y $and$ls180.v:5967$1313_Y
   end
-  attribute \src "ls180.v:5865.39-5865.146"
-  cell $and $and$ls180.v:5865$1246
+  attribute \src "ls180.v:5967.39-5967.146"
+  cell $and $and$ls180.v:5967$1315
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5865$1244_Y
-    connect \B $eq$ls180.v:5865$1245_Y
-    connect \Y $and$ls180.v:5865$1246_Y
+    connect \A $and$ls180.v:5967$1313_Y
+    connect \B $eq$ls180.v:5967$1314_Y
+    connect \Y $and$ls180.v:5967$1315_Y
   end
-  attribute \src "ls180.v:5867.40-5867.93"
-  cell $and $and$ls180.v:5867$1247
+  attribute \src "ls180.v:5969.40-5969.93"
+  cell $and $and$ls180.v:5969$1316
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240330,43 +241206,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5867$1247_Y
+    connect \Y $and$ls180.v:5969$1316_Y
   end
-  attribute \src "ls180.v:5867.39-5867.143"
-  cell $and $and$ls180.v:5867$1249
+  attribute \src "ls180.v:5969.39-5969.143"
+  cell $and $and$ls180.v:5969$1318
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5867$1247_Y
-    connect \B $eq$ls180.v:5867$1248_Y
-    connect \Y $and$ls180.v:5867$1249_Y
+    connect \A $and$ls180.v:5969$1316_Y
+    connect \B $eq$ls180.v:5969$1317_Y
+    connect \Y $and$ls180.v:5969$1318_Y
   end
-  attribute \src "ls180.v:5868.40-5868.96"
-  cell $and $and$ls180.v:5868$1251
+  attribute \src "ls180.v:5970.40-5970.96"
+  cell $and $and$ls180.v:5970$1320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5868$1250_Y
-    connect \Y $and$ls180.v:5868$1251_Y
+    connect \B $not$ls180.v:5970$1319_Y
+    connect \Y $and$ls180.v:5970$1320_Y
   end
-  attribute \src "ls180.v:5868.39-5868.146"
-  cell $and $and$ls180.v:5868$1253
+  attribute \src "ls180.v:5970.39-5970.146"
+  cell $and $and$ls180.v:5970$1322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5868$1251_Y
-    connect \B $eq$ls180.v:5868$1252_Y
-    connect \Y $and$ls180.v:5868$1253_Y
+    connect \A $and$ls180.v:5970$1320_Y
+    connect \B $eq$ls180.v:5970$1321_Y
+    connect \Y $and$ls180.v:5970$1322_Y
   end
-  attribute \src "ls180.v:5870.40-5870.93"
-  cell $and $and$ls180.v:5870$1254
+  attribute \src "ls180.v:5972.40-5972.93"
+  cell $and $and$ls180.v:5972$1323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240374,43 +241250,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5870$1254_Y
+    connect \Y $and$ls180.v:5972$1323_Y
   end
-  attribute \src "ls180.v:5870.39-5870.143"
-  cell $and $and$ls180.v:5870$1256
+  attribute \src "ls180.v:5972.39-5972.143"
+  cell $and $and$ls180.v:5972$1325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5870$1254_Y
-    connect \B $eq$ls180.v:5870$1255_Y
-    connect \Y $and$ls180.v:5870$1256_Y
+    connect \A $and$ls180.v:5972$1323_Y
+    connect \B $eq$ls180.v:5972$1324_Y
+    connect \Y $and$ls180.v:5972$1325_Y
   end
-  attribute \src "ls180.v:5871.40-5871.96"
-  cell $and $and$ls180.v:5871$1258
+  attribute \src "ls180.v:5973.40-5973.96"
+  cell $and $and$ls180.v:5973$1327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5871$1257_Y
-    connect \Y $and$ls180.v:5871$1258_Y
+    connect \B $not$ls180.v:5973$1326_Y
+    connect \Y $and$ls180.v:5973$1327_Y
   end
-  attribute \src "ls180.v:5871.39-5871.146"
-  cell $and $and$ls180.v:5871$1260
+  attribute \src "ls180.v:5973.39-5973.146"
+  cell $and $and$ls180.v:5973$1329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5871$1258_Y
-    connect \B $eq$ls180.v:5871$1259_Y
-    connect \Y $and$ls180.v:5871$1260_Y
+    connect \A $and$ls180.v:5973$1327_Y
+    connect \B $eq$ls180.v:5973$1328_Y
+    connect \Y $and$ls180.v:5973$1329_Y
   end
-  attribute \src "ls180.v:5873.40-5873.93"
-  cell $and $and$ls180.v:5873$1261
+  attribute \src "ls180.v:5975.40-5975.93"
+  cell $and $and$ls180.v:5975$1330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240418,43 +241294,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
     connect \B \builder_interface3_bank_bus_we
-    connect \Y $and$ls180.v:5873$1261_Y
+    connect \Y $and$ls180.v:5975$1330_Y
   end
-  attribute \src "ls180.v:5873.39-5873.143"
-  cell $and $and$ls180.v:5873$1263
+  attribute \src "ls180.v:5975.39-5975.143"
+  cell $and $and$ls180.v:5975$1332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5873$1261_Y
-    connect \B $eq$ls180.v:5873$1262_Y
-    connect \Y $and$ls180.v:5873$1263_Y
+    connect \A $and$ls180.v:5975$1330_Y
+    connect \B $eq$ls180.v:5975$1331_Y
+    connect \Y $and$ls180.v:5975$1332_Y
   end
-  attribute \src "ls180.v:5874.40-5874.96"
-  cell $and $and$ls180.v:5874$1265
+  attribute \src "ls180.v:5976.40-5976.96"
+  cell $and $and$ls180.v:5976$1334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank3_sel
-    connect \B $not$ls180.v:5874$1264_Y
-    connect \Y $and$ls180.v:5874$1265_Y
+    connect \B $not$ls180.v:5976$1333_Y
+    connect \Y $and$ls180.v:5976$1334_Y
   end
-  attribute \src "ls180.v:5874.39-5874.146"
-  cell $and $and$ls180.v:5874$1267
+  attribute \src "ls180.v:5976.39-5976.146"
+  cell $and $and$ls180.v:5976$1336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5874$1265_Y
-    connect \B $eq$ls180.v:5874$1266_Y
-    connect \Y $and$ls180.v:5874$1267_Y
+    connect \A $and$ls180.v:5976$1334_Y
+    connect \B $eq$ls180.v:5976$1335_Y
+    connect \Y $and$ls180.v:5976$1336_Y
   end
-  attribute \src "ls180.v:5886.40-5886.93"
-  cell $and $and$ls180.v:5886$1269
+  attribute \src "ls180.v:5988.40-5988.93"
+  cell $and $and$ls180.v:5988$1338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240462,43 +241338,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5886$1269_Y
+    connect \Y $and$ls180.v:5988$1338_Y
   end
-  attribute \src "ls180.v:5886.39-5886.143"
-  cell $and $and$ls180.v:5886$1271
+  attribute \src "ls180.v:5988.39-5988.143"
+  cell $and $and$ls180.v:5988$1340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5886$1269_Y
-    connect \B $eq$ls180.v:5886$1270_Y
-    connect \Y $and$ls180.v:5886$1271_Y
+    connect \A $and$ls180.v:5988$1338_Y
+    connect \B $eq$ls180.v:5988$1339_Y
+    connect \Y $and$ls180.v:5988$1340_Y
   end
-  attribute \src "ls180.v:5887.40-5887.96"
-  cell $and $and$ls180.v:5887$1273
+  attribute \src "ls180.v:5989.40-5989.96"
+  cell $and $and$ls180.v:5989$1342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5887$1272_Y
-    connect \Y $and$ls180.v:5887$1273_Y
+    connect \B $not$ls180.v:5989$1341_Y
+    connect \Y $and$ls180.v:5989$1342_Y
   end
-  attribute \src "ls180.v:5887.39-5887.146"
-  cell $and $and$ls180.v:5887$1275
+  attribute \src "ls180.v:5989.39-5989.146"
+  cell $and $and$ls180.v:5989$1344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5887$1273_Y
-    connect \B $eq$ls180.v:5887$1274_Y
-    connect \Y $and$ls180.v:5887$1275_Y
+    connect \A $and$ls180.v:5989$1342_Y
+    connect \B $eq$ls180.v:5989$1343_Y
+    connect \Y $and$ls180.v:5989$1344_Y
   end
-  attribute \src "ls180.v:5889.39-5889.92"
-  cell $and $and$ls180.v:5889$1276
+  attribute \src "ls180.v:5991.39-5991.92"
+  cell $and $and$ls180.v:5991$1345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240506,43 +241382,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5889$1276_Y
+    connect \Y $and$ls180.v:5991$1345_Y
   end
-  attribute \src "ls180.v:5889.38-5889.142"
-  cell $and $and$ls180.v:5889$1278
+  attribute \src "ls180.v:5991.38-5991.142"
+  cell $and $and$ls180.v:5991$1347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5889$1276_Y
-    connect \B $eq$ls180.v:5889$1277_Y
-    connect \Y $and$ls180.v:5889$1278_Y
+    connect \A $and$ls180.v:5991$1345_Y
+    connect \B $eq$ls180.v:5991$1346_Y
+    connect \Y $and$ls180.v:5991$1347_Y
   end
-  attribute \src "ls180.v:5890.39-5890.95"
-  cell $and $and$ls180.v:5890$1280
+  attribute \src "ls180.v:5992.39-5992.95"
+  cell $and $and$ls180.v:5992$1349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5890$1279_Y
-    connect \Y $and$ls180.v:5890$1280_Y
+    connect \B $not$ls180.v:5992$1348_Y
+    connect \Y $and$ls180.v:5992$1349_Y
   end
-  attribute \src "ls180.v:5890.38-5890.145"
-  cell $and $and$ls180.v:5890$1282
+  attribute \src "ls180.v:5992.38-5992.145"
+  cell $and $and$ls180.v:5992$1351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5890$1280_Y
-    connect \B $eq$ls180.v:5890$1281_Y
-    connect \Y $and$ls180.v:5890$1282_Y
+    connect \A $and$ls180.v:5992$1349_Y
+    connect \B $eq$ls180.v:5992$1350_Y
+    connect \Y $and$ls180.v:5992$1351_Y
   end
-  attribute \src "ls180.v:5892.39-5892.92"
-  cell $and $and$ls180.v:5892$1283
+  attribute \src "ls180.v:5994.39-5994.92"
+  cell $and $and$ls180.v:5994$1352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240550,43 +241426,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5892$1283_Y
+    connect \Y $and$ls180.v:5994$1352_Y
   end
-  attribute \src "ls180.v:5892.38-5892.142"
-  cell $and $and$ls180.v:5892$1285
+  attribute \src "ls180.v:5994.38-5994.142"
+  cell $and $and$ls180.v:5994$1354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5892$1283_Y
-    connect \B $eq$ls180.v:5892$1284_Y
-    connect \Y $and$ls180.v:5892$1285_Y
+    connect \A $and$ls180.v:5994$1352_Y
+    connect \B $eq$ls180.v:5994$1353_Y
+    connect \Y $and$ls180.v:5994$1354_Y
   end
-  attribute \src "ls180.v:5893.39-5893.95"
-  cell $and $and$ls180.v:5893$1287
+  attribute \src "ls180.v:5995.39-5995.95"
+  cell $and $and$ls180.v:5995$1356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5893$1286_Y
-    connect \Y $and$ls180.v:5893$1287_Y
+    connect \B $not$ls180.v:5995$1355_Y
+    connect \Y $and$ls180.v:5995$1356_Y
   end
-  attribute \src "ls180.v:5893.38-5893.145"
-  cell $and $and$ls180.v:5893$1289
+  attribute \src "ls180.v:5995.38-5995.145"
+  cell $and $and$ls180.v:5995$1358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5893$1287_Y
-    connect \B $eq$ls180.v:5893$1288_Y
-    connect \Y $and$ls180.v:5893$1289_Y
+    connect \A $and$ls180.v:5995$1356_Y
+    connect \B $eq$ls180.v:5995$1357_Y
+    connect \Y $and$ls180.v:5995$1358_Y
   end
-  attribute \src "ls180.v:5895.39-5895.92"
-  cell $and $and$ls180.v:5895$1290
+  attribute \src "ls180.v:5997.39-5997.92"
+  cell $and $and$ls180.v:5997$1359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240594,43 +241470,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5895$1290_Y
+    connect \Y $and$ls180.v:5997$1359_Y
   end
-  attribute \src "ls180.v:5895.38-5895.142"
-  cell $and $and$ls180.v:5895$1292
+  attribute \src "ls180.v:5997.38-5997.142"
+  cell $and $and$ls180.v:5997$1361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5895$1290_Y
-    connect \B $eq$ls180.v:5895$1291_Y
-    connect \Y $and$ls180.v:5895$1292_Y
+    connect \A $and$ls180.v:5997$1359_Y
+    connect \B $eq$ls180.v:5997$1360_Y
+    connect \Y $and$ls180.v:5997$1361_Y
   end
-  attribute \src "ls180.v:5896.39-5896.95"
-  cell $and $and$ls180.v:5896$1294
+  attribute \src "ls180.v:5998.39-5998.95"
+  cell $and $and$ls180.v:5998$1363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5896$1293_Y
-    connect \Y $and$ls180.v:5896$1294_Y
+    connect \B $not$ls180.v:5998$1362_Y
+    connect \Y $and$ls180.v:5998$1363_Y
   end
-  attribute \src "ls180.v:5896.38-5896.145"
-  cell $and $and$ls180.v:5896$1296
+  attribute \src "ls180.v:5998.38-5998.145"
+  cell $and $and$ls180.v:5998$1365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5896$1294_Y
-    connect \B $eq$ls180.v:5896$1295_Y
-    connect \Y $and$ls180.v:5896$1296_Y
+    connect \A $and$ls180.v:5998$1363_Y
+    connect \B $eq$ls180.v:5998$1364_Y
+    connect \Y $and$ls180.v:5998$1365_Y
   end
-  attribute \src "ls180.v:5898.39-5898.92"
-  cell $and $and$ls180.v:5898$1297
+  attribute \src "ls180.v:6000.39-6000.92"
+  cell $and $and$ls180.v:6000$1366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240638,43 +241514,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5898$1297_Y
+    connect \Y $and$ls180.v:6000$1366_Y
   end
-  attribute \src "ls180.v:5898.38-5898.142"
-  cell $and $and$ls180.v:5898$1299
+  attribute \src "ls180.v:6000.38-6000.142"
+  cell $and $and$ls180.v:6000$1368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5898$1297_Y
-    connect \B $eq$ls180.v:5898$1298_Y
-    connect \Y $and$ls180.v:5898$1299_Y
+    connect \A $and$ls180.v:6000$1366_Y
+    connect \B $eq$ls180.v:6000$1367_Y
+    connect \Y $and$ls180.v:6000$1368_Y
   end
-  attribute \src "ls180.v:5899.39-5899.95"
-  cell $and $and$ls180.v:5899$1301
+  attribute \src "ls180.v:6001.39-6001.95"
+  cell $and $and$ls180.v:6001$1370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5899$1300_Y
-    connect \Y $and$ls180.v:5899$1301_Y
+    connect \B $not$ls180.v:6001$1369_Y
+    connect \Y $and$ls180.v:6001$1370_Y
   end
-  attribute \src "ls180.v:5899.38-5899.145"
-  cell $and $and$ls180.v:5899$1303
+  attribute \src "ls180.v:6001.38-6001.145"
+  cell $and $and$ls180.v:6001$1372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5899$1301_Y
-    connect \B $eq$ls180.v:5899$1302_Y
-    connect \Y $and$ls180.v:5899$1303_Y
+    connect \A $and$ls180.v:6001$1370_Y
+    connect \B $eq$ls180.v:6001$1371_Y
+    connect \Y $and$ls180.v:6001$1372_Y
   end
-  attribute \src "ls180.v:5901.40-5901.93"
-  cell $and $and$ls180.v:5901$1304
+  attribute \src "ls180.v:6003.40-6003.93"
+  cell $and $and$ls180.v:6003$1373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240682,43 +241558,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5901$1304_Y
+    connect \Y $and$ls180.v:6003$1373_Y
   end
-  attribute \src "ls180.v:5901.39-5901.143"
-  cell $and $and$ls180.v:5901$1306
+  attribute \src "ls180.v:6003.39-6003.143"
+  cell $and $and$ls180.v:6003$1375
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5901$1304_Y
-    connect \B $eq$ls180.v:5901$1305_Y
-    connect \Y $and$ls180.v:5901$1306_Y
+    connect \A $and$ls180.v:6003$1373_Y
+    connect \B $eq$ls180.v:6003$1374_Y
+    connect \Y $and$ls180.v:6003$1375_Y
   end
-  attribute \src "ls180.v:5902.40-5902.96"
-  cell $and $and$ls180.v:5902$1308
+  attribute \src "ls180.v:6004.40-6004.96"
+  cell $and $and$ls180.v:6004$1377
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5902$1307_Y
-    connect \Y $and$ls180.v:5902$1308_Y
+    connect \B $not$ls180.v:6004$1376_Y
+    connect \Y $and$ls180.v:6004$1377_Y
   end
-  attribute \src "ls180.v:5902.39-5902.146"
-  cell $and $and$ls180.v:5902$1310
+  attribute \src "ls180.v:6004.39-6004.146"
+  cell $and $and$ls180.v:6004$1379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5902$1308_Y
-    connect \B $eq$ls180.v:5902$1309_Y
-    connect \Y $and$ls180.v:5902$1310_Y
+    connect \A $and$ls180.v:6004$1377_Y
+    connect \B $eq$ls180.v:6004$1378_Y
+    connect \Y $and$ls180.v:6004$1379_Y
   end
-  attribute \src "ls180.v:5904.40-5904.93"
-  cell $and $and$ls180.v:5904$1311
+  attribute \src "ls180.v:6006.40-6006.93"
+  cell $and $and$ls180.v:6006$1380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240726,43 +241602,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5904$1311_Y
+    connect \Y $and$ls180.v:6006$1380_Y
   end
-  attribute \src "ls180.v:5904.39-5904.143"
-  cell $and $and$ls180.v:5904$1313
+  attribute \src "ls180.v:6006.39-6006.143"
+  cell $and $and$ls180.v:6006$1382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5904$1311_Y
-    connect \B $eq$ls180.v:5904$1312_Y
-    connect \Y $and$ls180.v:5904$1313_Y
+    connect \A $and$ls180.v:6006$1380_Y
+    connect \B $eq$ls180.v:6006$1381_Y
+    connect \Y $and$ls180.v:6006$1382_Y
   end
-  attribute \src "ls180.v:5905.40-5905.96"
-  cell $and $and$ls180.v:5905$1315
+  attribute \src "ls180.v:6007.40-6007.96"
+  cell $and $and$ls180.v:6007$1384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5905$1314_Y
-    connect \Y $and$ls180.v:5905$1315_Y
+    connect \B $not$ls180.v:6007$1383_Y
+    connect \Y $and$ls180.v:6007$1384_Y
   end
-  attribute \src "ls180.v:5905.39-5905.146"
-  cell $and $and$ls180.v:5905$1317
+  attribute \src "ls180.v:6007.39-6007.146"
+  cell $and $and$ls180.v:6007$1386
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5905$1315_Y
-    connect \B $eq$ls180.v:5905$1316_Y
-    connect \Y $and$ls180.v:5905$1317_Y
+    connect \A $and$ls180.v:6007$1384_Y
+    connect \B $eq$ls180.v:6007$1385_Y
+    connect \Y $and$ls180.v:6007$1386_Y
   end
-  attribute \src "ls180.v:5907.40-5907.93"
-  cell $and $and$ls180.v:5907$1318
+  attribute \src "ls180.v:6009.40-6009.93"
+  cell $and $and$ls180.v:6009$1387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240770,43 +241646,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5907$1318_Y
+    connect \Y $and$ls180.v:6009$1387_Y
   end
-  attribute \src "ls180.v:5907.39-5907.143"
-  cell $and $and$ls180.v:5907$1320
+  attribute \src "ls180.v:6009.39-6009.143"
+  cell $and $and$ls180.v:6009$1389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5907$1318_Y
-    connect \B $eq$ls180.v:5907$1319_Y
-    connect \Y $and$ls180.v:5907$1320_Y
+    connect \A $and$ls180.v:6009$1387_Y
+    connect \B $eq$ls180.v:6009$1388_Y
+    connect \Y $and$ls180.v:6009$1389_Y
   end
-  attribute \src "ls180.v:5908.40-5908.96"
-  cell $and $and$ls180.v:5908$1322
+  attribute \src "ls180.v:6010.40-6010.96"
+  cell $and $and$ls180.v:6010$1391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5908$1321_Y
-    connect \Y $and$ls180.v:5908$1322_Y
+    connect \B $not$ls180.v:6010$1390_Y
+    connect \Y $and$ls180.v:6010$1391_Y
   end
-  attribute \src "ls180.v:5908.39-5908.146"
-  cell $and $and$ls180.v:5908$1324
+  attribute \src "ls180.v:6010.39-6010.146"
+  cell $and $and$ls180.v:6010$1393
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5908$1322_Y
-    connect \B $eq$ls180.v:5908$1323_Y
-    connect \Y $and$ls180.v:5908$1324_Y
+    connect \A $and$ls180.v:6010$1391_Y
+    connect \B $eq$ls180.v:6010$1392_Y
+    connect \Y $and$ls180.v:6010$1393_Y
   end
-  attribute \src "ls180.v:5910.40-5910.93"
-  cell $and $and$ls180.v:5910$1325
+  attribute \src "ls180.v:6012.40-6012.93"
+  cell $and $and$ls180.v:6012$1394
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240814,43 +241690,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
     connect \B \builder_interface4_bank_bus_we
-    connect \Y $and$ls180.v:5910$1325_Y
+    connect \Y $and$ls180.v:6012$1394_Y
   end
-  attribute \src "ls180.v:5910.39-5910.143"
-  cell $and $and$ls180.v:5910$1327
+  attribute \src "ls180.v:6012.39-6012.143"
+  cell $and $and$ls180.v:6012$1396
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5910$1325_Y
-    connect \B $eq$ls180.v:5910$1326_Y
-    connect \Y $and$ls180.v:5910$1327_Y
+    connect \A $and$ls180.v:6012$1394_Y
+    connect \B $eq$ls180.v:6012$1395_Y
+    connect \Y $and$ls180.v:6012$1396_Y
   end
-  attribute \src "ls180.v:5911.40-5911.96"
-  cell $and $and$ls180.v:5911$1329
+  attribute \src "ls180.v:6013.40-6013.96"
+  cell $and $and$ls180.v:6013$1398
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank4_sel
-    connect \B $not$ls180.v:5911$1328_Y
-    connect \Y $and$ls180.v:5911$1329_Y
+    connect \B $not$ls180.v:6013$1397_Y
+    connect \Y $and$ls180.v:6013$1398_Y
   end
-  attribute \src "ls180.v:5911.39-5911.146"
-  cell $and $and$ls180.v:5911$1331
+  attribute \src "ls180.v:6013.39-6013.146"
+  cell $and $and$ls180.v:6013$1400
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5911$1329_Y
-    connect \B $eq$ls180.v:5911$1330_Y
-    connect \Y $and$ls180.v:5911$1331_Y
+    connect \A $and$ls180.v:6013$1398_Y
+    connect \B $eq$ls180.v:6013$1399_Y
+    connect \Y $and$ls180.v:6013$1400_Y
   end
-  attribute \src "ls180.v:5923.42-5923.95"
-  cell $and $and$ls180.v:5923$1333
+  attribute \src "ls180.v:6025.42-6025.95"
+  cell $and $and$ls180.v:6025$1402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240858,43 +241734,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5923$1333_Y
+    connect \Y $and$ls180.v:6025$1402_Y
   end
-  attribute \src "ls180.v:5923.41-5923.145"
-  cell $and $and$ls180.v:5923$1335
+  attribute \src "ls180.v:6025.41-6025.145"
+  cell $and $and$ls180.v:6025$1404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5923$1333_Y
-    connect \B $eq$ls180.v:5923$1334_Y
-    connect \Y $and$ls180.v:5923$1335_Y
+    connect \A $and$ls180.v:6025$1402_Y
+    connect \B $eq$ls180.v:6025$1403_Y
+    connect \Y $and$ls180.v:6025$1404_Y
   end
-  attribute \src "ls180.v:5924.42-5924.98"
-  cell $and $and$ls180.v:5924$1337
+  attribute \src "ls180.v:6026.42-6026.98"
+  cell $and $and$ls180.v:6026$1406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5924$1336_Y
-    connect \Y $and$ls180.v:5924$1337_Y
+    connect \B $not$ls180.v:6026$1405_Y
+    connect \Y $and$ls180.v:6026$1406_Y
   end
-  attribute \src "ls180.v:5924.41-5924.148"
-  cell $and $and$ls180.v:5924$1339
+  attribute \src "ls180.v:6026.41-6026.148"
+  cell $and $and$ls180.v:6026$1408
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5924$1337_Y
-    connect \B $eq$ls180.v:5924$1338_Y
-    connect \Y $and$ls180.v:5924$1339_Y
+    connect \A $and$ls180.v:6026$1406_Y
+    connect \B $eq$ls180.v:6026$1407_Y
+    connect \Y $and$ls180.v:6026$1408_Y
   end
-  attribute \src "ls180.v:5926.42-5926.95"
-  cell $and $and$ls180.v:5926$1340
+  attribute \src "ls180.v:6028.42-6028.95"
+  cell $and $and$ls180.v:6028$1409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240902,43 +241778,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5926$1340_Y
+    connect \Y $and$ls180.v:6028$1409_Y
   end
-  attribute \src "ls180.v:5926.41-5926.145"
-  cell $and $and$ls180.v:5926$1342
+  attribute \src "ls180.v:6028.41-6028.145"
+  cell $and $and$ls180.v:6028$1411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5926$1340_Y
-    connect \B $eq$ls180.v:5926$1341_Y
-    connect \Y $and$ls180.v:5926$1342_Y
+    connect \A $and$ls180.v:6028$1409_Y
+    connect \B $eq$ls180.v:6028$1410_Y
+    connect \Y $and$ls180.v:6028$1411_Y
   end
-  attribute \src "ls180.v:5927.42-5927.98"
-  cell $and $and$ls180.v:5927$1344
+  attribute \src "ls180.v:6029.42-6029.98"
+  cell $and $and$ls180.v:6029$1413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5927$1343_Y
-    connect \Y $and$ls180.v:5927$1344_Y
+    connect \B $not$ls180.v:6029$1412_Y
+    connect \Y $and$ls180.v:6029$1413_Y
   end
-  attribute \src "ls180.v:5927.41-5927.148"
-  cell $and $and$ls180.v:5927$1346
+  attribute \src "ls180.v:6029.41-6029.148"
+  cell $and $and$ls180.v:6029$1415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5927$1344_Y
-    connect \B $eq$ls180.v:5927$1345_Y
-    connect \Y $and$ls180.v:5927$1346_Y
+    connect \A $and$ls180.v:6029$1413_Y
+    connect \B $eq$ls180.v:6029$1414_Y
+    connect \Y $and$ls180.v:6029$1415_Y
   end
-  attribute \src "ls180.v:5929.42-5929.95"
-  cell $and $and$ls180.v:5929$1347
+  attribute \src "ls180.v:6031.42-6031.95"
+  cell $and $and$ls180.v:6031$1416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240946,43 +241822,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5929$1347_Y
+    connect \Y $and$ls180.v:6031$1416_Y
   end
-  attribute \src "ls180.v:5929.41-5929.145"
-  cell $and $and$ls180.v:5929$1349
+  attribute \src "ls180.v:6031.41-6031.145"
+  cell $and $and$ls180.v:6031$1418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5929$1347_Y
-    connect \B $eq$ls180.v:5929$1348_Y
-    connect \Y $and$ls180.v:5929$1349_Y
+    connect \A $and$ls180.v:6031$1416_Y
+    connect \B $eq$ls180.v:6031$1417_Y
+    connect \Y $and$ls180.v:6031$1418_Y
   end
-  attribute \src "ls180.v:5930.42-5930.98"
-  cell $and $and$ls180.v:5930$1351
+  attribute \src "ls180.v:6032.42-6032.98"
+  cell $and $and$ls180.v:6032$1420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5930$1350_Y
-    connect \Y $and$ls180.v:5930$1351_Y
+    connect \B $not$ls180.v:6032$1419_Y
+    connect \Y $and$ls180.v:6032$1420_Y
   end
-  attribute \src "ls180.v:5930.41-5930.148"
-  cell $and $and$ls180.v:5930$1353
+  attribute \src "ls180.v:6032.41-6032.148"
+  cell $and $and$ls180.v:6032$1422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5930$1351_Y
-    connect \B $eq$ls180.v:5930$1352_Y
-    connect \Y $and$ls180.v:5930$1353_Y
+    connect \A $and$ls180.v:6032$1420_Y
+    connect \B $eq$ls180.v:6032$1421_Y
+    connect \Y $and$ls180.v:6032$1422_Y
   end
-  attribute \src "ls180.v:5932.42-5932.95"
-  cell $and $and$ls180.v:5932$1354
+  attribute \src "ls180.v:6034.42-6034.95"
+  cell $and $and$ls180.v:6034$1423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -240990,43 +241866,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5932$1354_Y
+    connect \Y $and$ls180.v:6034$1423_Y
   end
-  attribute \src "ls180.v:5932.41-5932.145"
-  cell $and $and$ls180.v:5932$1356
+  attribute \src "ls180.v:6034.41-6034.145"
+  cell $and $and$ls180.v:6034$1425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5932$1354_Y
-    connect \B $eq$ls180.v:5932$1355_Y
-    connect \Y $and$ls180.v:5932$1356_Y
+    connect \A $and$ls180.v:6034$1423_Y
+    connect \B $eq$ls180.v:6034$1424_Y
+    connect \Y $and$ls180.v:6034$1425_Y
   end
-  attribute \src "ls180.v:5933.42-5933.98"
-  cell $and $and$ls180.v:5933$1358
+  attribute \src "ls180.v:6035.42-6035.98"
+  cell $and $and$ls180.v:6035$1427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5933$1357_Y
-    connect \Y $and$ls180.v:5933$1358_Y
+    connect \B $not$ls180.v:6035$1426_Y
+    connect \Y $and$ls180.v:6035$1427_Y
   end
-  attribute \src "ls180.v:5933.41-5933.148"
-  cell $and $and$ls180.v:5933$1360
+  attribute \src "ls180.v:6035.41-6035.148"
+  cell $and $and$ls180.v:6035$1429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5933$1358_Y
-    connect \B $eq$ls180.v:5933$1359_Y
-    connect \Y $and$ls180.v:5933$1360_Y
+    connect \A $and$ls180.v:6035$1427_Y
+    connect \B $eq$ls180.v:6035$1428_Y
+    connect \Y $and$ls180.v:6035$1429_Y
   end
-  attribute \src "ls180.v:5935.42-5935.95"
-  cell $and $and$ls180.v:5935$1361
+  attribute \src "ls180.v:6037.42-6037.95"
+  cell $and $and$ls180.v:6037$1430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241034,43 +241910,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5935$1361_Y
+    connect \Y $and$ls180.v:6037$1430_Y
   end
-  attribute \src "ls180.v:5935.41-5935.145"
-  cell $and $and$ls180.v:5935$1363
+  attribute \src "ls180.v:6037.41-6037.145"
+  cell $and $and$ls180.v:6037$1432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5935$1361_Y
-    connect \B $eq$ls180.v:5935$1362_Y
-    connect \Y $and$ls180.v:5935$1363_Y
+    connect \A $and$ls180.v:6037$1430_Y
+    connect \B $eq$ls180.v:6037$1431_Y
+    connect \Y $and$ls180.v:6037$1432_Y
   end
-  attribute \src "ls180.v:5936.42-5936.98"
-  cell $and $and$ls180.v:5936$1365
+  attribute \src "ls180.v:6038.42-6038.98"
+  cell $and $and$ls180.v:6038$1434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5936$1364_Y
-    connect \Y $and$ls180.v:5936$1365_Y
+    connect \B $not$ls180.v:6038$1433_Y
+    connect \Y $and$ls180.v:6038$1434_Y
   end
-  attribute \src "ls180.v:5936.41-5936.148"
-  cell $and $and$ls180.v:5936$1367
+  attribute \src "ls180.v:6038.41-6038.148"
+  cell $and $and$ls180.v:6038$1436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5936$1365_Y
-    connect \B $eq$ls180.v:5936$1366_Y
-    connect \Y $and$ls180.v:5936$1367_Y
+    connect \A $and$ls180.v:6038$1434_Y
+    connect \B $eq$ls180.v:6038$1435_Y
+    connect \Y $and$ls180.v:6038$1436_Y
   end
-  attribute \src "ls180.v:5938.42-5938.95"
-  cell $and $and$ls180.v:5938$1368
+  attribute \src "ls180.v:6040.42-6040.95"
+  cell $and $and$ls180.v:6040$1437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241078,43 +241954,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5938$1368_Y
+    connect \Y $and$ls180.v:6040$1437_Y
   end
-  attribute \src "ls180.v:5938.41-5938.145"
-  cell $and $and$ls180.v:5938$1370
+  attribute \src "ls180.v:6040.41-6040.145"
+  cell $and $and$ls180.v:6040$1439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5938$1368_Y
-    connect \B $eq$ls180.v:5938$1369_Y
-    connect \Y $and$ls180.v:5938$1370_Y
+    connect \A $and$ls180.v:6040$1437_Y
+    connect \B $eq$ls180.v:6040$1438_Y
+    connect \Y $and$ls180.v:6040$1439_Y
   end
-  attribute \src "ls180.v:5939.42-5939.98"
-  cell $and $and$ls180.v:5939$1372
+  attribute \src "ls180.v:6041.42-6041.98"
+  cell $and $and$ls180.v:6041$1441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5939$1371_Y
-    connect \Y $and$ls180.v:5939$1372_Y
+    connect \B $not$ls180.v:6041$1440_Y
+    connect \Y $and$ls180.v:6041$1441_Y
   end
-  attribute \src "ls180.v:5939.41-5939.148"
-  cell $and $and$ls180.v:5939$1374
+  attribute \src "ls180.v:6041.41-6041.148"
+  cell $and $and$ls180.v:6041$1443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5939$1372_Y
-    connect \B $eq$ls180.v:5939$1373_Y
-    connect \Y $and$ls180.v:5939$1374_Y
+    connect \A $and$ls180.v:6041$1441_Y
+    connect \B $eq$ls180.v:6041$1442_Y
+    connect \Y $and$ls180.v:6041$1443_Y
   end
-  attribute \src "ls180.v:5941.42-5941.95"
-  cell $and $and$ls180.v:5941$1375
+  attribute \src "ls180.v:6043.42-6043.95"
+  cell $and $and$ls180.v:6043$1444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241122,43 +241998,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5941$1375_Y
+    connect \Y $and$ls180.v:6043$1444_Y
   end
-  attribute \src "ls180.v:5941.41-5941.145"
-  cell $and $and$ls180.v:5941$1377
+  attribute \src "ls180.v:6043.41-6043.145"
+  cell $and $and$ls180.v:6043$1446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5941$1375_Y
-    connect \B $eq$ls180.v:5941$1376_Y
-    connect \Y $and$ls180.v:5941$1377_Y
+    connect \A $and$ls180.v:6043$1444_Y
+    connect \B $eq$ls180.v:6043$1445_Y
+    connect \Y $and$ls180.v:6043$1446_Y
   end
-  attribute \src "ls180.v:5942.42-5942.98"
-  cell $and $and$ls180.v:5942$1379
+  attribute \src "ls180.v:6044.42-6044.98"
+  cell $and $and$ls180.v:6044$1448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5942$1378_Y
-    connect \Y $and$ls180.v:5942$1379_Y
+    connect \B $not$ls180.v:6044$1447_Y
+    connect \Y $and$ls180.v:6044$1448_Y
   end
-  attribute \src "ls180.v:5942.41-5942.148"
-  cell $and $and$ls180.v:5942$1381
+  attribute \src "ls180.v:6044.41-6044.148"
+  cell $and $and$ls180.v:6044$1450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5942$1379_Y
-    connect \B $eq$ls180.v:5942$1380_Y
-    connect \Y $and$ls180.v:5942$1381_Y
+    connect \A $and$ls180.v:6044$1448_Y
+    connect \B $eq$ls180.v:6044$1449_Y
+    connect \Y $and$ls180.v:6044$1450_Y
   end
-  attribute \src "ls180.v:5944.42-5944.95"
-  cell $and $and$ls180.v:5944$1382
+  attribute \src "ls180.v:6046.42-6046.95"
+  cell $and $and$ls180.v:6046$1451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241166,43 +242042,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5944$1382_Y
+    connect \Y $and$ls180.v:6046$1451_Y
   end
-  attribute \src "ls180.v:5944.41-5944.145"
-  cell $and $and$ls180.v:5944$1384
+  attribute \src "ls180.v:6046.41-6046.145"
+  cell $and $and$ls180.v:6046$1453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5944$1382_Y
-    connect \B $eq$ls180.v:5944$1383_Y
-    connect \Y $and$ls180.v:5944$1384_Y
+    connect \A $and$ls180.v:6046$1451_Y
+    connect \B $eq$ls180.v:6046$1452_Y
+    connect \Y $and$ls180.v:6046$1453_Y
   end
-  attribute \src "ls180.v:5945.42-5945.98"
-  cell $and $and$ls180.v:5945$1386
+  attribute \src "ls180.v:6047.42-6047.98"
+  cell $and $and$ls180.v:6047$1455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5945$1385_Y
-    connect \Y $and$ls180.v:5945$1386_Y
+    connect \B $not$ls180.v:6047$1454_Y
+    connect \Y $and$ls180.v:6047$1455_Y
   end
-  attribute \src "ls180.v:5945.41-5945.148"
-  cell $and $and$ls180.v:5945$1388
+  attribute \src "ls180.v:6047.41-6047.148"
+  cell $and $and$ls180.v:6047$1457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5945$1386_Y
-    connect \B $eq$ls180.v:5945$1387_Y
-    connect \Y $and$ls180.v:5945$1388_Y
+    connect \A $and$ls180.v:6047$1455_Y
+    connect \B $eq$ls180.v:6047$1456_Y
+    connect \Y $and$ls180.v:6047$1457_Y
   end
-  attribute \src "ls180.v:5947.44-5947.97"
-  cell $and $and$ls180.v:5947$1389
+  attribute \src "ls180.v:6049.44-6049.97"
+  cell $and $and$ls180.v:6049$1458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241210,43 +242086,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5947$1389_Y
+    connect \Y $and$ls180.v:6049$1458_Y
   end
-  attribute \src "ls180.v:5947.43-5947.147"
-  cell $and $and$ls180.v:5947$1391
+  attribute \src "ls180.v:6049.43-6049.147"
+  cell $and $and$ls180.v:6049$1460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5947$1389_Y
-    connect \B $eq$ls180.v:5947$1390_Y
-    connect \Y $and$ls180.v:5947$1391_Y
+    connect \A $and$ls180.v:6049$1458_Y
+    connect \B $eq$ls180.v:6049$1459_Y
+    connect \Y $and$ls180.v:6049$1460_Y
   end
-  attribute \src "ls180.v:5948.44-5948.100"
-  cell $and $and$ls180.v:5948$1393
+  attribute \src "ls180.v:6050.44-6050.100"
+  cell $and $and$ls180.v:6050$1462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5948$1392_Y
-    connect \Y $and$ls180.v:5948$1393_Y
+    connect \B $not$ls180.v:6050$1461_Y
+    connect \Y $and$ls180.v:6050$1462_Y
   end
-  attribute \src "ls180.v:5948.43-5948.150"
-  cell $and $and$ls180.v:5948$1395
+  attribute \src "ls180.v:6050.43-6050.150"
+  cell $and $and$ls180.v:6050$1464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5948$1393_Y
-    connect \B $eq$ls180.v:5948$1394_Y
-    connect \Y $and$ls180.v:5948$1395_Y
+    connect \A $and$ls180.v:6050$1462_Y
+    connect \B $eq$ls180.v:6050$1463_Y
+    connect \Y $and$ls180.v:6050$1464_Y
   end
-  attribute \src "ls180.v:5950.44-5950.97"
-  cell $and $and$ls180.v:5950$1396
+  attribute \src "ls180.v:6052.44-6052.97"
+  cell $and $and$ls180.v:6052$1465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241254,43 +242130,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5950$1396_Y
+    connect \Y $and$ls180.v:6052$1465_Y
   end
-  attribute \src "ls180.v:5950.43-5950.147"
-  cell $and $and$ls180.v:5950$1398
+  attribute \src "ls180.v:6052.43-6052.147"
+  cell $and $and$ls180.v:6052$1467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5950$1396_Y
-    connect \B $eq$ls180.v:5950$1397_Y
-    connect \Y $and$ls180.v:5950$1398_Y
+    connect \A $and$ls180.v:6052$1465_Y
+    connect \B $eq$ls180.v:6052$1466_Y
+    connect \Y $and$ls180.v:6052$1467_Y
   end
-  attribute \src "ls180.v:5951.44-5951.100"
-  cell $and $and$ls180.v:5951$1400
+  attribute \src "ls180.v:6053.44-6053.100"
+  cell $and $and$ls180.v:6053$1469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5951$1399_Y
-    connect \Y $and$ls180.v:5951$1400_Y
+    connect \B $not$ls180.v:6053$1468_Y
+    connect \Y $and$ls180.v:6053$1469_Y
   end
-  attribute \src "ls180.v:5951.43-5951.150"
-  cell $and $and$ls180.v:5951$1402
+  attribute \src "ls180.v:6053.43-6053.150"
+  cell $and $and$ls180.v:6053$1471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5951$1400_Y
-    connect \B $eq$ls180.v:5951$1401_Y
-    connect \Y $and$ls180.v:5951$1402_Y
+    connect \A $and$ls180.v:6053$1469_Y
+    connect \B $eq$ls180.v:6053$1470_Y
+    connect \Y $and$ls180.v:6053$1471_Y
   end
-  attribute \src "ls180.v:5953.44-5953.97"
-  cell $and $and$ls180.v:5953$1403
+  attribute \src "ls180.v:6055.44-6055.97"
+  cell $and $and$ls180.v:6055$1472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241298,43 +242174,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5953$1403_Y
+    connect \Y $and$ls180.v:6055$1472_Y
   end
-  attribute \src "ls180.v:5953.43-5953.148"
-  cell $and $and$ls180.v:5953$1405
+  attribute \src "ls180.v:6055.43-6055.148"
+  cell $and $and$ls180.v:6055$1474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5953$1403_Y
-    connect \B $eq$ls180.v:5953$1404_Y
-    connect \Y $and$ls180.v:5953$1405_Y
+    connect \A $and$ls180.v:6055$1472_Y
+    connect \B $eq$ls180.v:6055$1473_Y
+    connect \Y $and$ls180.v:6055$1474_Y
   end
-  attribute \src "ls180.v:5954.44-5954.100"
-  cell $and $and$ls180.v:5954$1407
+  attribute \src "ls180.v:6056.44-6056.100"
+  cell $and $and$ls180.v:6056$1476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5954$1406_Y
-    connect \Y $and$ls180.v:5954$1407_Y
+    connect \B $not$ls180.v:6056$1475_Y
+    connect \Y $and$ls180.v:6056$1476_Y
   end
-  attribute \src "ls180.v:5954.43-5954.151"
-  cell $and $and$ls180.v:5954$1409
+  attribute \src "ls180.v:6056.43-6056.151"
+  cell $and $and$ls180.v:6056$1478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5954$1407_Y
-    connect \B $eq$ls180.v:5954$1408_Y
-    connect \Y $and$ls180.v:5954$1409_Y
+    connect \A $and$ls180.v:6056$1476_Y
+    connect \B $eq$ls180.v:6056$1477_Y
+    connect \Y $and$ls180.v:6056$1478_Y
   end
-  attribute \src "ls180.v:5956.44-5956.97"
-  cell $and $and$ls180.v:5956$1410
+  attribute \src "ls180.v:6058.44-6058.97"
+  cell $and $and$ls180.v:6058$1479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241342,43 +242218,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5956$1410_Y
+    connect \Y $and$ls180.v:6058$1479_Y
   end
-  attribute \src "ls180.v:5956.43-5956.148"
-  cell $and $and$ls180.v:5956$1412
+  attribute \src "ls180.v:6058.43-6058.148"
+  cell $and $and$ls180.v:6058$1481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5956$1410_Y
-    connect \B $eq$ls180.v:5956$1411_Y
-    connect \Y $and$ls180.v:5956$1412_Y
+    connect \A $and$ls180.v:6058$1479_Y
+    connect \B $eq$ls180.v:6058$1480_Y
+    connect \Y $and$ls180.v:6058$1481_Y
   end
-  attribute \src "ls180.v:5957.44-5957.100"
-  cell $and $and$ls180.v:5957$1414
+  attribute \src "ls180.v:6059.44-6059.100"
+  cell $and $and$ls180.v:6059$1483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5957$1413_Y
-    connect \Y $and$ls180.v:5957$1414_Y
+    connect \B $not$ls180.v:6059$1482_Y
+    connect \Y $and$ls180.v:6059$1483_Y
   end
-  attribute \src "ls180.v:5957.43-5957.151"
-  cell $and $and$ls180.v:5957$1416
+  attribute \src "ls180.v:6059.43-6059.151"
+  cell $and $and$ls180.v:6059$1485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5957$1414_Y
-    connect \B $eq$ls180.v:5957$1415_Y
-    connect \Y $and$ls180.v:5957$1416_Y
+    connect \A $and$ls180.v:6059$1483_Y
+    connect \B $eq$ls180.v:6059$1484_Y
+    connect \Y $and$ls180.v:6059$1485_Y
   end
-  attribute \src "ls180.v:5959.44-5959.97"
-  cell $and $and$ls180.v:5959$1417
+  attribute \src "ls180.v:6061.44-6061.97"
+  cell $and $and$ls180.v:6061$1486
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241386,43 +242262,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5959$1417_Y
+    connect \Y $and$ls180.v:6061$1486_Y
   end
-  attribute \src "ls180.v:5959.43-5959.148"
-  cell $and $and$ls180.v:5959$1419
+  attribute \src "ls180.v:6061.43-6061.148"
+  cell $and $and$ls180.v:6061$1488
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5959$1417_Y
-    connect \B $eq$ls180.v:5959$1418_Y
-    connect \Y $and$ls180.v:5959$1419_Y
+    connect \A $and$ls180.v:6061$1486_Y
+    connect \B $eq$ls180.v:6061$1487_Y
+    connect \Y $and$ls180.v:6061$1488_Y
   end
-  attribute \src "ls180.v:5960.44-5960.100"
-  cell $and $and$ls180.v:5960$1421
+  attribute \src "ls180.v:6062.44-6062.100"
+  cell $and $and$ls180.v:6062$1490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5960$1420_Y
-    connect \Y $and$ls180.v:5960$1421_Y
+    connect \B $not$ls180.v:6062$1489_Y
+    connect \Y $and$ls180.v:6062$1490_Y
   end
-  attribute \src "ls180.v:5960.43-5960.151"
-  cell $and $and$ls180.v:5960$1423
+  attribute \src "ls180.v:6062.43-6062.151"
+  cell $and $and$ls180.v:6062$1492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5960$1421_Y
-    connect \B $eq$ls180.v:5960$1422_Y
-    connect \Y $and$ls180.v:5960$1423_Y
+    connect \A $and$ls180.v:6062$1490_Y
+    connect \B $eq$ls180.v:6062$1491_Y
+    connect \Y $and$ls180.v:6062$1492_Y
   end
-  attribute \src "ls180.v:5962.41-5962.94"
-  cell $and $and$ls180.v:5962$1424
+  attribute \src "ls180.v:6064.41-6064.94"
+  cell $and $and$ls180.v:6064$1493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241430,43 +242306,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5962$1424_Y
+    connect \Y $and$ls180.v:6064$1493_Y
   end
-  attribute \src "ls180.v:5962.40-5962.145"
-  cell $and $and$ls180.v:5962$1426
+  attribute \src "ls180.v:6064.40-6064.145"
+  cell $and $and$ls180.v:6064$1495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5962$1424_Y
-    connect \B $eq$ls180.v:5962$1425_Y
-    connect \Y $and$ls180.v:5962$1426_Y
+    connect \A $and$ls180.v:6064$1493_Y
+    connect \B $eq$ls180.v:6064$1494_Y
+    connect \Y $and$ls180.v:6064$1495_Y
   end
-  attribute \src "ls180.v:5963.41-5963.97"
-  cell $and $and$ls180.v:5963$1428
+  attribute \src "ls180.v:6065.41-6065.97"
+  cell $and $and$ls180.v:6065$1497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5963$1427_Y
-    connect \Y $and$ls180.v:5963$1428_Y
+    connect \B $not$ls180.v:6065$1496_Y
+    connect \Y $and$ls180.v:6065$1497_Y
   end
-  attribute \src "ls180.v:5963.40-5963.148"
-  cell $and $and$ls180.v:5963$1430
+  attribute \src "ls180.v:6065.40-6065.148"
+  cell $and $and$ls180.v:6065$1499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5963$1428_Y
-    connect \B $eq$ls180.v:5963$1429_Y
-    connect \Y $and$ls180.v:5963$1430_Y
+    connect \A $and$ls180.v:6065$1497_Y
+    connect \B $eq$ls180.v:6065$1498_Y
+    connect \Y $and$ls180.v:6065$1499_Y
   end
-  attribute \src "ls180.v:5965.42-5965.95"
-  cell $and $and$ls180.v:5965$1431
+  attribute \src "ls180.v:6067.42-6067.95"
+  cell $and $and$ls180.v:6067$1500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241474,43 +242350,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
     connect \B \builder_interface5_bank_bus_we
-    connect \Y $and$ls180.v:5965$1431_Y
+    connect \Y $and$ls180.v:6067$1500_Y
   end
-  attribute \src "ls180.v:5965.41-5965.146"
-  cell $and $and$ls180.v:5965$1433
+  attribute \src "ls180.v:6067.41-6067.146"
+  cell $and $and$ls180.v:6067$1502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5965$1431_Y
-    connect \B $eq$ls180.v:5965$1432_Y
-    connect \Y $and$ls180.v:5965$1433_Y
+    connect \A $and$ls180.v:6067$1500_Y
+    connect \B $eq$ls180.v:6067$1501_Y
+    connect \Y $and$ls180.v:6067$1502_Y
   end
-  attribute \src "ls180.v:5966.42-5966.98"
-  cell $and $and$ls180.v:5966$1435
+  attribute \src "ls180.v:6068.42-6068.98"
+  cell $and $and$ls180.v:6068$1504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank5_sel
-    connect \B $not$ls180.v:5966$1434_Y
-    connect \Y $and$ls180.v:5966$1435_Y
+    connect \B $not$ls180.v:6068$1503_Y
+    connect \Y $and$ls180.v:6068$1504_Y
   end
-  attribute \src "ls180.v:5966.41-5966.149"
-  cell $and $and$ls180.v:5966$1437
+  attribute \src "ls180.v:6068.41-6068.149"
+  cell $and $and$ls180.v:6068$1506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5966$1435_Y
-    connect \B $eq$ls180.v:5966$1436_Y
-    connect \Y $and$ls180.v:5966$1437_Y
+    connect \A $and$ls180.v:6068$1504_Y
+    connect \B $eq$ls180.v:6068$1505_Y
+    connect \Y $and$ls180.v:6068$1506_Y
   end
-  attribute \src "ls180.v:5985.46-5985.99"
-  cell $and $and$ls180.v:5985$1439
+  attribute \src "ls180.v:6087.46-6087.99"
+  cell $and $and$ls180.v:6087$1508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241518,43 +242394,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:5985$1439_Y
+    connect \Y $and$ls180.v:6087$1508_Y
   end
-  attribute \src "ls180.v:5985.45-5985.149"
-  cell $and $and$ls180.v:5985$1441
+  attribute \src "ls180.v:6087.45-6087.149"
+  cell $and $and$ls180.v:6087$1510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5985$1439_Y
-    connect \B $eq$ls180.v:5985$1440_Y
-    connect \Y $and$ls180.v:5985$1441_Y
+    connect \A $and$ls180.v:6087$1508_Y
+    connect \B $eq$ls180.v:6087$1509_Y
+    connect \Y $and$ls180.v:6087$1510_Y
   end
-  attribute \src "ls180.v:5986.46-5986.102"
-  cell $and $and$ls180.v:5986$1443
+  attribute \src "ls180.v:6088.46-6088.102"
+  cell $and $and$ls180.v:6088$1512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:5986$1442_Y
-    connect \Y $and$ls180.v:5986$1443_Y
+    connect \B $not$ls180.v:6088$1511_Y
+    connect \Y $and$ls180.v:6088$1512_Y
   end
-  attribute \src "ls180.v:5986.45-5986.152"
-  cell $and $and$ls180.v:5986$1445
+  attribute \src "ls180.v:6088.45-6088.152"
+  cell $and $and$ls180.v:6088$1514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5986$1443_Y
-    connect \B $eq$ls180.v:5986$1444_Y
-    connect \Y $and$ls180.v:5986$1445_Y
+    connect \A $and$ls180.v:6088$1512_Y
+    connect \B $eq$ls180.v:6088$1513_Y
+    connect \Y $and$ls180.v:6088$1514_Y
   end
-  attribute \src "ls180.v:5988.46-5988.99"
-  cell $and $and$ls180.v:5988$1446
+  attribute \src "ls180.v:6090.46-6090.99"
+  cell $and $and$ls180.v:6090$1515
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241562,43 +242438,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:5988$1446_Y
+    connect \Y $and$ls180.v:6090$1515_Y
   end
-  attribute \src "ls180.v:5988.45-5988.149"
-  cell $and $and$ls180.v:5988$1448
+  attribute \src "ls180.v:6090.45-6090.149"
+  cell $and $and$ls180.v:6090$1517
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5988$1446_Y
-    connect \B $eq$ls180.v:5988$1447_Y
-    connect \Y $and$ls180.v:5988$1448_Y
+    connect \A $and$ls180.v:6090$1515_Y
+    connect \B $eq$ls180.v:6090$1516_Y
+    connect \Y $and$ls180.v:6090$1517_Y
   end
-  attribute \src "ls180.v:5989.46-5989.102"
-  cell $and $and$ls180.v:5989$1450
+  attribute \src "ls180.v:6091.46-6091.102"
+  cell $and $and$ls180.v:6091$1519
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:5989$1449_Y
-    connect \Y $and$ls180.v:5989$1450_Y
+    connect \B $not$ls180.v:6091$1518_Y
+    connect \Y $and$ls180.v:6091$1519_Y
   end
-  attribute \src "ls180.v:5989.45-5989.152"
-  cell $and $and$ls180.v:5989$1452
+  attribute \src "ls180.v:6091.45-6091.152"
+  cell $and $and$ls180.v:6091$1521
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5989$1450_Y
-    connect \B $eq$ls180.v:5989$1451_Y
-    connect \Y $and$ls180.v:5989$1452_Y
+    connect \A $and$ls180.v:6091$1519_Y
+    connect \B $eq$ls180.v:6091$1520_Y
+    connect \Y $and$ls180.v:6091$1521_Y
   end
-  attribute \src "ls180.v:5991.46-5991.99"
-  cell $and $and$ls180.v:5991$1453
+  attribute \src "ls180.v:6093.46-6093.99"
+  cell $and $and$ls180.v:6093$1522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241606,43 +242482,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:5991$1453_Y
+    connect \Y $and$ls180.v:6093$1522_Y
   end
-  attribute \src "ls180.v:5991.45-5991.149"
-  cell $and $and$ls180.v:5991$1455
+  attribute \src "ls180.v:6093.45-6093.149"
+  cell $and $and$ls180.v:6093$1524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5991$1453_Y
-    connect \B $eq$ls180.v:5991$1454_Y
-    connect \Y $and$ls180.v:5991$1455_Y
+    connect \A $and$ls180.v:6093$1522_Y
+    connect \B $eq$ls180.v:6093$1523_Y
+    connect \Y $and$ls180.v:6093$1524_Y
   end
-  attribute \src "ls180.v:5992.46-5992.102"
-  cell $and $and$ls180.v:5992$1457
+  attribute \src "ls180.v:6094.46-6094.102"
+  cell $and $and$ls180.v:6094$1526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:5992$1456_Y
-    connect \Y $and$ls180.v:5992$1457_Y
+    connect \B $not$ls180.v:6094$1525_Y
+    connect \Y $and$ls180.v:6094$1526_Y
   end
-  attribute \src "ls180.v:5992.45-5992.152"
-  cell $and $and$ls180.v:5992$1459
+  attribute \src "ls180.v:6094.45-6094.152"
+  cell $and $and$ls180.v:6094$1528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5992$1457_Y
-    connect \B $eq$ls180.v:5992$1458_Y
-    connect \Y $and$ls180.v:5992$1459_Y
+    connect \A $and$ls180.v:6094$1526_Y
+    connect \B $eq$ls180.v:6094$1527_Y
+    connect \Y $and$ls180.v:6094$1528_Y
   end
-  attribute \src "ls180.v:5994.46-5994.99"
-  cell $and $and$ls180.v:5994$1460
+  attribute \src "ls180.v:6096.46-6096.99"
+  cell $and $and$ls180.v:6096$1529
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241650,43 +242526,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:5994$1460_Y
+    connect \Y $and$ls180.v:6096$1529_Y
   end
-  attribute \src "ls180.v:5994.45-5994.149"
-  cell $and $and$ls180.v:5994$1462
+  attribute \src "ls180.v:6096.45-6096.149"
+  cell $and $and$ls180.v:6096$1531
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5994$1460_Y
-    connect \B $eq$ls180.v:5994$1461_Y
-    connect \Y $and$ls180.v:5994$1462_Y
+    connect \A $and$ls180.v:6096$1529_Y
+    connect \B $eq$ls180.v:6096$1530_Y
+    connect \Y $and$ls180.v:6096$1531_Y
   end
-  attribute \src "ls180.v:5995.46-5995.102"
-  cell $and $and$ls180.v:5995$1464
+  attribute \src "ls180.v:6097.46-6097.102"
+  cell $and $and$ls180.v:6097$1533
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:5995$1463_Y
-    connect \Y $and$ls180.v:5995$1464_Y
+    connect \B $not$ls180.v:6097$1532_Y
+    connect \Y $and$ls180.v:6097$1533_Y
   end
-  attribute \src "ls180.v:5995.45-5995.152"
-  cell $and $and$ls180.v:5995$1466
+  attribute \src "ls180.v:6097.45-6097.152"
+  cell $and $and$ls180.v:6097$1535
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5995$1464_Y
-    connect \B $eq$ls180.v:5995$1465_Y
-    connect \Y $and$ls180.v:5995$1466_Y
+    connect \A $and$ls180.v:6097$1533_Y
+    connect \B $eq$ls180.v:6097$1534_Y
+    connect \Y $and$ls180.v:6097$1535_Y
   end
-  attribute \src "ls180.v:5997.45-5997.98"
-  cell $and $and$ls180.v:5997$1467
+  attribute \src "ls180.v:6099.45-6099.98"
+  cell $and $and$ls180.v:6099$1536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241694,43 +242570,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:5997$1467_Y
+    connect \Y $and$ls180.v:6099$1536_Y
   end
-  attribute \src "ls180.v:5997.44-5997.148"
-  cell $and $and$ls180.v:5997$1469
+  attribute \src "ls180.v:6099.44-6099.148"
+  cell $and $and$ls180.v:6099$1538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5997$1467_Y
-    connect \B $eq$ls180.v:5997$1468_Y
-    connect \Y $and$ls180.v:5997$1469_Y
+    connect \A $and$ls180.v:6099$1536_Y
+    connect \B $eq$ls180.v:6099$1537_Y
+    connect \Y $and$ls180.v:6099$1538_Y
   end
-  attribute \src "ls180.v:5998.45-5998.101"
-  cell $and $and$ls180.v:5998$1471
+  attribute \src "ls180.v:6100.45-6100.101"
+  cell $and $and$ls180.v:6100$1540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:5998$1470_Y
-    connect \Y $and$ls180.v:5998$1471_Y
+    connect \B $not$ls180.v:6100$1539_Y
+    connect \Y $and$ls180.v:6100$1540_Y
   end
-  attribute \src "ls180.v:5998.44-5998.151"
-  cell $and $and$ls180.v:5998$1473
+  attribute \src "ls180.v:6100.44-6100.151"
+  cell $and $and$ls180.v:6100$1542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:5998$1471_Y
-    connect \B $eq$ls180.v:5998$1472_Y
-    connect \Y $and$ls180.v:5998$1473_Y
+    connect \A $and$ls180.v:6100$1540_Y
+    connect \B $eq$ls180.v:6100$1541_Y
+    connect \Y $and$ls180.v:6100$1542_Y
   end
-  attribute \src "ls180.v:6000.45-6000.98"
-  cell $and $and$ls180.v:6000$1474
+  attribute \src "ls180.v:6102.45-6102.98"
+  cell $and $and$ls180.v:6102$1543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241738,43 +242614,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6000$1474_Y
+    connect \Y $and$ls180.v:6102$1543_Y
   end
-  attribute \src "ls180.v:6000.44-6000.148"
-  cell $and $and$ls180.v:6000$1476
+  attribute \src "ls180.v:6102.44-6102.148"
+  cell $and $and$ls180.v:6102$1545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6000$1474_Y
-    connect \B $eq$ls180.v:6000$1475_Y
-    connect \Y $and$ls180.v:6000$1476_Y
+    connect \A $and$ls180.v:6102$1543_Y
+    connect \B $eq$ls180.v:6102$1544_Y
+    connect \Y $and$ls180.v:6102$1545_Y
   end
-  attribute \src "ls180.v:6001.45-6001.101"
-  cell $and $and$ls180.v:6001$1478
+  attribute \src "ls180.v:6103.45-6103.101"
+  cell $and $and$ls180.v:6103$1547
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6001$1477_Y
-    connect \Y $and$ls180.v:6001$1478_Y
+    connect \B $not$ls180.v:6103$1546_Y
+    connect \Y $and$ls180.v:6103$1547_Y
   end
-  attribute \src "ls180.v:6001.44-6001.151"
-  cell $and $and$ls180.v:6001$1480
+  attribute \src "ls180.v:6103.44-6103.151"
+  cell $and $and$ls180.v:6103$1549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6001$1478_Y
-    connect \B $eq$ls180.v:6001$1479_Y
-    connect \Y $and$ls180.v:6001$1480_Y
+    connect \A $and$ls180.v:6103$1547_Y
+    connect \B $eq$ls180.v:6103$1548_Y
+    connect \Y $and$ls180.v:6103$1549_Y
   end
-  attribute \src "ls180.v:6003.45-6003.98"
-  cell $and $and$ls180.v:6003$1481
+  attribute \src "ls180.v:6105.45-6105.98"
+  cell $and $and$ls180.v:6105$1550
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241782,43 +242658,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6003$1481_Y
+    connect \Y $and$ls180.v:6105$1550_Y
   end
-  attribute \src "ls180.v:6003.44-6003.148"
-  cell $and $and$ls180.v:6003$1483
+  attribute \src "ls180.v:6105.44-6105.148"
+  cell $and $and$ls180.v:6105$1552
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6003$1481_Y
-    connect \B $eq$ls180.v:6003$1482_Y
-    connect \Y $and$ls180.v:6003$1483_Y
+    connect \A $and$ls180.v:6105$1550_Y
+    connect \B $eq$ls180.v:6105$1551_Y
+    connect \Y $and$ls180.v:6105$1552_Y
   end
-  attribute \src "ls180.v:6004.45-6004.101"
-  cell $and $and$ls180.v:6004$1485
+  attribute \src "ls180.v:6106.45-6106.101"
+  cell $and $and$ls180.v:6106$1554
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6004$1484_Y
-    connect \Y $and$ls180.v:6004$1485_Y
+    connect \B $not$ls180.v:6106$1553_Y
+    connect \Y $and$ls180.v:6106$1554_Y
   end
-  attribute \src "ls180.v:6004.44-6004.151"
-  cell $and $and$ls180.v:6004$1487
+  attribute \src "ls180.v:6106.44-6106.151"
+  cell $and $and$ls180.v:6106$1556
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6004$1485_Y
-    connect \B $eq$ls180.v:6004$1486_Y
-    connect \Y $and$ls180.v:6004$1487_Y
+    connect \A $and$ls180.v:6106$1554_Y
+    connect \B $eq$ls180.v:6106$1555_Y
+    connect \Y $and$ls180.v:6106$1556_Y
   end
-  attribute \src "ls180.v:6006.45-6006.98"
-  cell $and $and$ls180.v:6006$1488
+  attribute \src "ls180.v:6108.45-6108.98"
+  cell $and $and$ls180.v:6108$1557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241826,43 +242702,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6006$1488_Y
+    connect \Y $and$ls180.v:6108$1557_Y
   end
-  attribute \src "ls180.v:6006.44-6006.148"
-  cell $and $and$ls180.v:6006$1490
+  attribute \src "ls180.v:6108.44-6108.148"
+  cell $and $and$ls180.v:6108$1559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6006$1488_Y
-    connect \B $eq$ls180.v:6006$1489_Y
-    connect \Y $and$ls180.v:6006$1490_Y
+    connect \A $and$ls180.v:6108$1557_Y
+    connect \B $eq$ls180.v:6108$1558_Y
+    connect \Y $and$ls180.v:6108$1559_Y
   end
-  attribute \src "ls180.v:6007.45-6007.101"
-  cell $and $and$ls180.v:6007$1492
+  attribute \src "ls180.v:6109.45-6109.101"
+  cell $and $and$ls180.v:6109$1561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6007$1491_Y
-    connect \Y $and$ls180.v:6007$1492_Y
+    connect \B $not$ls180.v:6109$1560_Y
+    connect \Y $and$ls180.v:6109$1561_Y
   end
-  attribute \src "ls180.v:6007.44-6007.151"
-  cell $and $and$ls180.v:6007$1494
+  attribute \src "ls180.v:6109.44-6109.151"
+  cell $and $and$ls180.v:6109$1563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6007$1492_Y
-    connect \B $eq$ls180.v:6007$1493_Y
-    connect \Y $and$ls180.v:6007$1494_Y
+    connect \A $and$ls180.v:6109$1561_Y
+    connect \B $eq$ls180.v:6109$1562_Y
+    connect \Y $and$ls180.v:6109$1563_Y
   end
-  attribute \src "ls180.v:6009.36-6009.89"
-  cell $and $and$ls180.v:6009$1495
+  attribute \src "ls180.v:6111.36-6111.89"
+  cell $and $and$ls180.v:6111$1564
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241870,43 +242746,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6009$1495_Y
+    connect \Y $and$ls180.v:6111$1564_Y
   end
-  attribute \src "ls180.v:6009.35-6009.139"
-  cell $and $and$ls180.v:6009$1497
+  attribute \src "ls180.v:6111.35-6111.139"
+  cell $and $and$ls180.v:6111$1566
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6009$1495_Y
-    connect \B $eq$ls180.v:6009$1496_Y
-    connect \Y $and$ls180.v:6009$1497_Y
+    connect \A $and$ls180.v:6111$1564_Y
+    connect \B $eq$ls180.v:6111$1565_Y
+    connect \Y $and$ls180.v:6111$1566_Y
   end
-  attribute \src "ls180.v:6010.36-6010.92"
-  cell $and $and$ls180.v:6010$1499
+  attribute \src "ls180.v:6112.36-6112.92"
+  cell $and $and$ls180.v:6112$1568
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6010$1498_Y
-    connect \Y $and$ls180.v:6010$1499_Y
+    connect \B $not$ls180.v:6112$1567_Y
+    connect \Y $and$ls180.v:6112$1568_Y
   end
-  attribute \src "ls180.v:6010.35-6010.142"
-  cell $and $and$ls180.v:6010$1501
+  attribute \src "ls180.v:6112.35-6112.142"
+  cell $and $and$ls180.v:6112$1570
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6010$1499_Y
-    connect \B $eq$ls180.v:6010$1500_Y
-    connect \Y $and$ls180.v:6010$1501_Y
+    connect \A $and$ls180.v:6112$1568_Y
+    connect \B $eq$ls180.v:6112$1569_Y
+    connect \Y $and$ls180.v:6112$1570_Y
   end
-  attribute \src "ls180.v:6012.47-6012.100"
-  cell $and $and$ls180.v:6012$1502
+  attribute \src "ls180.v:6114.47-6114.100"
+  cell $and $and$ls180.v:6114$1571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241914,43 +242790,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6012$1502_Y
+    connect \Y $and$ls180.v:6114$1571_Y
   end
-  attribute \src "ls180.v:6012.46-6012.150"
-  cell $and $and$ls180.v:6012$1504
+  attribute \src "ls180.v:6114.46-6114.150"
+  cell $and $and$ls180.v:6114$1573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6012$1502_Y
-    connect \B $eq$ls180.v:6012$1503_Y
-    connect \Y $and$ls180.v:6012$1504_Y
+    connect \A $and$ls180.v:6114$1571_Y
+    connect \B $eq$ls180.v:6114$1572_Y
+    connect \Y $and$ls180.v:6114$1573_Y
   end
-  attribute \src "ls180.v:6013.47-6013.103"
-  cell $and $and$ls180.v:6013$1506
+  attribute \src "ls180.v:6115.47-6115.103"
+  cell $and $and$ls180.v:6115$1575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6013$1505_Y
-    connect \Y $and$ls180.v:6013$1506_Y
+    connect \B $not$ls180.v:6115$1574_Y
+    connect \Y $and$ls180.v:6115$1575_Y
   end
-  attribute \src "ls180.v:6013.46-6013.153"
-  cell $and $and$ls180.v:6013$1508
+  attribute \src "ls180.v:6115.46-6115.153"
+  cell $and $and$ls180.v:6115$1577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6013$1506_Y
-    connect \B $eq$ls180.v:6013$1507_Y
-    connect \Y $and$ls180.v:6013$1508_Y
+    connect \A $and$ls180.v:6115$1575_Y
+    connect \B $eq$ls180.v:6115$1576_Y
+    connect \Y $and$ls180.v:6115$1577_Y
   end
-  attribute \src "ls180.v:6015.47-6015.100"
-  cell $and $and$ls180.v:6015$1509
+  attribute \src "ls180.v:6117.47-6117.100"
+  cell $and $and$ls180.v:6117$1578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -241958,43 +242834,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6015$1509_Y
+    connect \Y $and$ls180.v:6117$1578_Y
   end
-  attribute \src "ls180.v:6015.46-6015.151"
-  cell $and $and$ls180.v:6015$1511
+  attribute \src "ls180.v:6117.46-6117.151"
+  cell $and $and$ls180.v:6117$1580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6015$1509_Y
-    connect \B $eq$ls180.v:6015$1510_Y
-    connect \Y $and$ls180.v:6015$1511_Y
+    connect \A $and$ls180.v:6117$1578_Y
+    connect \B $eq$ls180.v:6117$1579_Y
+    connect \Y $and$ls180.v:6117$1580_Y
   end
-  attribute \src "ls180.v:6016.47-6016.103"
-  cell $and $and$ls180.v:6016$1513
+  attribute \src "ls180.v:6118.47-6118.103"
+  cell $and $and$ls180.v:6118$1582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6016$1512_Y
-    connect \Y $and$ls180.v:6016$1513_Y
+    connect \B $not$ls180.v:6118$1581_Y
+    connect \Y $and$ls180.v:6118$1582_Y
   end
-  attribute \src "ls180.v:6016.46-6016.154"
-  cell $and $and$ls180.v:6016$1515
+  attribute \src "ls180.v:6118.46-6118.154"
+  cell $and $and$ls180.v:6118$1584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6016$1513_Y
-    connect \B $eq$ls180.v:6016$1514_Y
-    connect \Y $and$ls180.v:6016$1515_Y
+    connect \A $and$ls180.v:6118$1582_Y
+    connect \B $eq$ls180.v:6118$1583_Y
+    connect \Y $and$ls180.v:6118$1584_Y
   end
-  attribute \src "ls180.v:6018.47-6018.100"
-  cell $and $and$ls180.v:6018$1516
+  attribute \src "ls180.v:6120.47-6120.100"
+  cell $and $and$ls180.v:6120$1585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242002,43 +242878,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6018$1516_Y
+    connect \Y $and$ls180.v:6120$1585_Y
   end
-  attribute \src "ls180.v:6018.46-6018.151"
-  cell $and $and$ls180.v:6018$1518
+  attribute \src "ls180.v:6120.46-6120.151"
+  cell $and $and$ls180.v:6120$1587
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6018$1516_Y
-    connect \B $eq$ls180.v:6018$1517_Y
-    connect \Y $and$ls180.v:6018$1518_Y
+    connect \A $and$ls180.v:6120$1585_Y
+    connect \B $eq$ls180.v:6120$1586_Y
+    connect \Y $and$ls180.v:6120$1587_Y
   end
-  attribute \src "ls180.v:6019.47-6019.103"
-  cell $and $and$ls180.v:6019$1520
+  attribute \src "ls180.v:6121.47-6121.103"
+  cell $and $and$ls180.v:6121$1589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6019$1519_Y
-    connect \Y $and$ls180.v:6019$1520_Y
+    connect \B $not$ls180.v:6121$1588_Y
+    connect \Y $and$ls180.v:6121$1589_Y
   end
-  attribute \src "ls180.v:6019.46-6019.154"
-  cell $and $and$ls180.v:6019$1522
+  attribute \src "ls180.v:6121.46-6121.154"
+  cell $and $and$ls180.v:6121$1591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6019$1520_Y
-    connect \B $eq$ls180.v:6019$1521_Y
-    connect \Y $and$ls180.v:6019$1522_Y
+    connect \A $and$ls180.v:6121$1589_Y
+    connect \B $eq$ls180.v:6121$1590_Y
+    connect \Y $and$ls180.v:6121$1591_Y
   end
-  attribute \src "ls180.v:6021.47-6021.100"
-  cell $and $and$ls180.v:6021$1523
+  attribute \src "ls180.v:6123.47-6123.100"
+  cell $and $and$ls180.v:6123$1592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242046,43 +242922,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6021$1523_Y
+    connect \Y $and$ls180.v:6123$1592_Y
   end
-  attribute \src "ls180.v:6021.46-6021.151"
-  cell $and $and$ls180.v:6021$1525
+  attribute \src "ls180.v:6123.46-6123.151"
+  cell $and $and$ls180.v:6123$1594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6021$1523_Y
-    connect \B $eq$ls180.v:6021$1524_Y
-    connect \Y $and$ls180.v:6021$1525_Y
+    connect \A $and$ls180.v:6123$1592_Y
+    connect \B $eq$ls180.v:6123$1593_Y
+    connect \Y $and$ls180.v:6123$1594_Y
   end
-  attribute \src "ls180.v:6022.47-6022.103"
-  cell $and $and$ls180.v:6022$1527
+  attribute \src "ls180.v:6124.47-6124.103"
+  cell $and $and$ls180.v:6124$1596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6022$1526_Y
-    connect \Y $and$ls180.v:6022$1527_Y
+    connect \B $not$ls180.v:6124$1595_Y
+    connect \Y $and$ls180.v:6124$1596_Y
   end
-  attribute \src "ls180.v:6022.46-6022.154"
-  cell $and $and$ls180.v:6022$1529
+  attribute \src "ls180.v:6124.46-6124.154"
+  cell $and $and$ls180.v:6124$1598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6022$1527_Y
-    connect \B $eq$ls180.v:6022$1528_Y
-    connect \Y $and$ls180.v:6022$1529_Y
+    connect \A $and$ls180.v:6124$1596_Y
+    connect \B $eq$ls180.v:6124$1597_Y
+    connect \Y $and$ls180.v:6124$1598_Y
   end
-  attribute \src "ls180.v:6024.47-6024.100"
-  cell $and $and$ls180.v:6024$1530
+  attribute \src "ls180.v:6126.47-6126.100"
+  cell $and $and$ls180.v:6126$1599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242090,43 +242966,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6024$1530_Y
+    connect \Y $and$ls180.v:6126$1599_Y
   end
-  attribute \src "ls180.v:6024.46-6024.151"
-  cell $and $and$ls180.v:6024$1532
+  attribute \src "ls180.v:6126.46-6126.151"
+  cell $and $and$ls180.v:6126$1601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6024$1530_Y
-    connect \B $eq$ls180.v:6024$1531_Y
-    connect \Y $and$ls180.v:6024$1532_Y
+    connect \A $and$ls180.v:6126$1599_Y
+    connect \B $eq$ls180.v:6126$1600_Y
+    connect \Y $and$ls180.v:6126$1601_Y
   end
-  attribute \src "ls180.v:6025.47-6025.103"
-  cell $and $and$ls180.v:6025$1534
+  attribute \src "ls180.v:6127.47-6127.103"
+  cell $and $and$ls180.v:6127$1603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6025$1533_Y
-    connect \Y $and$ls180.v:6025$1534_Y
+    connect \B $not$ls180.v:6127$1602_Y
+    connect \Y $and$ls180.v:6127$1603_Y
   end
-  attribute \src "ls180.v:6025.46-6025.154"
-  cell $and $and$ls180.v:6025$1536
+  attribute \src "ls180.v:6127.46-6127.154"
+  cell $and $and$ls180.v:6127$1605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6025$1534_Y
-    connect \B $eq$ls180.v:6025$1535_Y
-    connect \Y $and$ls180.v:6025$1536_Y
+    connect \A $and$ls180.v:6127$1603_Y
+    connect \B $eq$ls180.v:6127$1604_Y
+    connect \Y $and$ls180.v:6127$1605_Y
   end
-  attribute \src "ls180.v:6027.47-6027.100"
-  cell $and $and$ls180.v:6027$1537
+  attribute \src "ls180.v:6129.47-6129.100"
+  cell $and $and$ls180.v:6129$1606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242134,43 +243010,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6027$1537_Y
+    connect \Y $and$ls180.v:6129$1606_Y
   end
-  attribute \src "ls180.v:6027.46-6027.151"
-  cell $and $and$ls180.v:6027$1539
+  attribute \src "ls180.v:6129.46-6129.151"
+  cell $and $and$ls180.v:6129$1608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6027$1537_Y
-    connect \B $eq$ls180.v:6027$1538_Y
-    connect \Y $and$ls180.v:6027$1539_Y
+    connect \A $and$ls180.v:6129$1606_Y
+    connect \B $eq$ls180.v:6129$1607_Y
+    connect \Y $and$ls180.v:6129$1608_Y
   end
-  attribute \src "ls180.v:6028.47-6028.103"
-  cell $and $and$ls180.v:6028$1541
+  attribute \src "ls180.v:6130.47-6130.103"
+  cell $and $and$ls180.v:6130$1610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6028$1540_Y
-    connect \Y $and$ls180.v:6028$1541_Y
+    connect \B $not$ls180.v:6130$1609_Y
+    connect \Y $and$ls180.v:6130$1610_Y
   end
-  attribute \src "ls180.v:6028.46-6028.154"
-  cell $and $and$ls180.v:6028$1543
+  attribute \src "ls180.v:6130.46-6130.154"
+  cell $and $and$ls180.v:6130$1612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6028$1541_Y
-    connect \B $eq$ls180.v:6028$1542_Y
-    connect \Y $and$ls180.v:6028$1543_Y
+    connect \A $and$ls180.v:6130$1610_Y
+    connect \B $eq$ls180.v:6130$1611_Y
+    connect \Y $and$ls180.v:6130$1612_Y
   end
-  attribute \src "ls180.v:6030.46-6030.99"
-  cell $and $and$ls180.v:6030$1544
+  attribute \src "ls180.v:6132.46-6132.99"
+  cell $and $and$ls180.v:6132$1613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242178,43 +243054,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6030$1544_Y
+    connect \Y $and$ls180.v:6132$1613_Y
   end
-  attribute \src "ls180.v:6030.45-6030.150"
-  cell $and $and$ls180.v:6030$1546
+  attribute \src "ls180.v:6132.45-6132.150"
+  cell $and $and$ls180.v:6132$1615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6030$1544_Y
-    connect \B $eq$ls180.v:6030$1545_Y
-    connect \Y $and$ls180.v:6030$1546_Y
+    connect \A $and$ls180.v:6132$1613_Y
+    connect \B $eq$ls180.v:6132$1614_Y
+    connect \Y $and$ls180.v:6132$1615_Y
   end
-  attribute \src "ls180.v:6031.46-6031.102"
-  cell $and $and$ls180.v:6031$1548
+  attribute \src "ls180.v:6133.46-6133.102"
+  cell $and $and$ls180.v:6133$1617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6031$1547_Y
-    connect \Y $and$ls180.v:6031$1548_Y
+    connect \B $not$ls180.v:6133$1616_Y
+    connect \Y $and$ls180.v:6133$1617_Y
   end
-  attribute \src "ls180.v:6031.45-6031.153"
-  cell $and $and$ls180.v:6031$1550
+  attribute \src "ls180.v:6133.45-6133.153"
+  cell $and $and$ls180.v:6133$1619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6031$1548_Y
-    connect \B $eq$ls180.v:6031$1549_Y
-    connect \Y $and$ls180.v:6031$1550_Y
+    connect \A $and$ls180.v:6133$1617_Y
+    connect \B $eq$ls180.v:6133$1618_Y
+    connect \Y $and$ls180.v:6133$1619_Y
   end
-  attribute \src "ls180.v:6033.46-6033.99"
-  cell $and $and$ls180.v:6033$1551
+  attribute \src "ls180.v:6135.46-6135.99"
+  cell $and $and$ls180.v:6135$1620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242222,43 +243098,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6033$1551_Y
+    connect \Y $and$ls180.v:6135$1620_Y
   end
-  attribute \src "ls180.v:6033.45-6033.150"
-  cell $and $and$ls180.v:6033$1553
+  attribute \src "ls180.v:6135.45-6135.150"
+  cell $and $and$ls180.v:6135$1622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6033$1551_Y
-    connect \B $eq$ls180.v:6033$1552_Y
-    connect \Y $and$ls180.v:6033$1553_Y
+    connect \A $and$ls180.v:6135$1620_Y
+    connect \B $eq$ls180.v:6135$1621_Y
+    connect \Y $and$ls180.v:6135$1622_Y
   end
-  attribute \src "ls180.v:6034.46-6034.102"
-  cell $and $and$ls180.v:6034$1555
+  attribute \src "ls180.v:6136.46-6136.102"
+  cell $and $and$ls180.v:6136$1624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6034$1554_Y
-    connect \Y $and$ls180.v:6034$1555_Y
+    connect \B $not$ls180.v:6136$1623_Y
+    connect \Y $and$ls180.v:6136$1624_Y
   end
-  attribute \src "ls180.v:6034.45-6034.153"
-  cell $and $and$ls180.v:6034$1557
+  attribute \src "ls180.v:6136.45-6136.153"
+  cell $and $and$ls180.v:6136$1626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6034$1555_Y
-    connect \B $eq$ls180.v:6034$1556_Y
-    connect \Y $and$ls180.v:6034$1557_Y
+    connect \A $and$ls180.v:6136$1624_Y
+    connect \B $eq$ls180.v:6136$1625_Y
+    connect \Y $and$ls180.v:6136$1626_Y
   end
-  attribute \src "ls180.v:6036.46-6036.99"
-  cell $and $and$ls180.v:6036$1558
+  attribute \src "ls180.v:6138.46-6138.99"
+  cell $and $and$ls180.v:6138$1627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242266,43 +243142,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6036$1558_Y
+    connect \Y $and$ls180.v:6138$1627_Y
   end
-  attribute \src "ls180.v:6036.45-6036.150"
-  cell $and $and$ls180.v:6036$1560
+  attribute \src "ls180.v:6138.45-6138.150"
+  cell $and $and$ls180.v:6138$1629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6036$1558_Y
-    connect \B $eq$ls180.v:6036$1559_Y
-    connect \Y $and$ls180.v:6036$1560_Y
+    connect \A $and$ls180.v:6138$1627_Y
+    connect \B $eq$ls180.v:6138$1628_Y
+    connect \Y $and$ls180.v:6138$1629_Y
   end
-  attribute \src "ls180.v:6037.46-6037.102"
-  cell $and $and$ls180.v:6037$1562
+  attribute \src "ls180.v:6139.46-6139.102"
+  cell $and $and$ls180.v:6139$1631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6037$1561_Y
-    connect \Y $and$ls180.v:6037$1562_Y
+    connect \B $not$ls180.v:6139$1630_Y
+    connect \Y $and$ls180.v:6139$1631_Y
   end
-  attribute \src "ls180.v:6037.45-6037.153"
-  cell $and $and$ls180.v:6037$1564
+  attribute \src "ls180.v:6139.45-6139.153"
+  cell $and $and$ls180.v:6139$1633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6037$1562_Y
-    connect \B $eq$ls180.v:6037$1563_Y
-    connect \Y $and$ls180.v:6037$1564_Y
+    connect \A $and$ls180.v:6139$1631_Y
+    connect \B $eq$ls180.v:6139$1632_Y
+    connect \Y $and$ls180.v:6139$1633_Y
   end
-  attribute \src "ls180.v:6039.46-6039.99"
-  cell $and $and$ls180.v:6039$1565
+  attribute \src "ls180.v:6141.46-6141.99"
+  cell $and $and$ls180.v:6141$1634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242310,43 +243186,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6039$1565_Y
+    connect \Y $and$ls180.v:6141$1634_Y
   end
-  attribute \src "ls180.v:6039.45-6039.150"
-  cell $and $and$ls180.v:6039$1567
+  attribute \src "ls180.v:6141.45-6141.150"
+  cell $and $and$ls180.v:6141$1636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6039$1565_Y
-    connect \B $eq$ls180.v:6039$1566_Y
-    connect \Y $and$ls180.v:6039$1567_Y
+    connect \A $and$ls180.v:6141$1634_Y
+    connect \B $eq$ls180.v:6141$1635_Y
+    connect \Y $and$ls180.v:6141$1636_Y
   end
-  attribute \src "ls180.v:6040.46-6040.102"
-  cell $and $and$ls180.v:6040$1569
+  attribute \src "ls180.v:6142.46-6142.102"
+  cell $and $and$ls180.v:6142$1638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6040$1568_Y
-    connect \Y $and$ls180.v:6040$1569_Y
+    connect \B $not$ls180.v:6142$1637_Y
+    connect \Y $and$ls180.v:6142$1638_Y
   end
-  attribute \src "ls180.v:6040.45-6040.153"
-  cell $and $and$ls180.v:6040$1571
+  attribute \src "ls180.v:6142.45-6142.153"
+  cell $and $and$ls180.v:6142$1640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6040$1569_Y
-    connect \B $eq$ls180.v:6040$1570_Y
-    connect \Y $and$ls180.v:6040$1571_Y
+    connect \A $and$ls180.v:6142$1638_Y
+    connect \B $eq$ls180.v:6142$1639_Y
+    connect \Y $and$ls180.v:6142$1640_Y
   end
-  attribute \src "ls180.v:6042.46-6042.99"
-  cell $and $and$ls180.v:6042$1572
+  attribute \src "ls180.v:6144.46-6144.99"
+  cell $and $and$ls180.v:6144$1641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242354,43 +243230,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6042$1572_Y
+    connect \Y $and$ls180.v:6144$1641_Y
   end
-  attribute \src "ls180.v:6042.45-6042.150"
-  cell $and $and$ls180.v:6042$1574
+  attribute \src "ls180.v:6144.45-6144.150"
+  cell $and $and$ls180.v:6144$1643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6042$1572_Y
-    connect \B $eq$ls180.v:6042$1573_Y
-    connect \Y $and$ls180.v:6042$1574_Y
+    connect \A $and$ls180.v:6144$1641_Y
+    connect \B $eq$ls180.v:6144$1642_Y
+    connect \Y $and$ls180.v:6144$1643_Y
   end
-  attribute \src "ls180.v:6043.46-6043.102"
-  cell $and $and$ls180.v:6043$1576
+  attribute \src "ls180.v:6145.46-6145.102"
+  cell $and $and$ls180.v:6145$1645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6043$1575_Y
-    connect \Y $and$ls180.v:6043$1576_Y
+    connect \B $not$ls180.v:6145$1644_Y
+    connect \Y $and$ls180.v:6145$1645_Y
   end
-  attribute \src "ls180.v:6043.45-6043.153"
-  cell $and $and$ls180.v:6043$1578
+  attribute \src "ls180.v:6145.45-6145.153"
+  cell $and $and$ls180.v:6145$1647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6043$1576_Y
-    connect \B $eq$ls180.v:6043$1577_Y
-    connect \Y $and$ls180.v:6043$1578_Y
+    connect \A $and$ls180.v:6145$1645_Y
+    connect \B $eq$ls180.v:6145$1646_Y
+    connect \Y $and$ls180.v:6145$1647_Y
   end
-  attribute \src "ls180.v:6045.46-6045.99"
-  cell $and $and$ls180.v:6045$1579
+  attribute \src "ls180.v:6147.46-6147.99"
+  cell $and $and$ls180.v:6147$1648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242398,43 +243274,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6045$1579_Y
+    connect \Y $and$ls180.v:6147$1648_Y
   end
-  attribute \src "ls180.v:6045.45-6045.150"
-  cell $and $and$ls180.v:6045$1581
+  attribute \src "ls180.v:6147.45-6147.150"
+  cell $and $and$ls180.v:6147$1650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6045$1579_Y
-    connect \B $eq$ls180.v:6045$1580_Y
-    connect \Y $and$ls180.v:6045$1581_Y
+    connect \A $and$ls180.v:6147$1648_Y
+    connect \B $eq$ls180.v:6147$1649_Y
+    connect \Y $and$ls180.v:6147$1650_Y
   end
-  attribute \src "ls180.v:6046.46-6046.102"
-  cell $and $and$ls180.v:6046$1583
+  attribute \src "ls180.v:6148.46-6148.102"
+  cell $and $and$ls180.v:6148$1652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6046$1582_Y
-    connect \Y $and$ls180.v:6046$1583_Y
+    connect \B $not$ls180.v:6148$1651_Y
+    connect \Y $and$ls180.v:6148$1652_Y
   end
-  attribute \src "ls180.v:6046.45-6046.153"
-  cell $and $and$ls180.v:6046$1585
+  attribute \src "ls180.v:6148.45-6148.153"
+  cell $and $and$ls180.v:6148$1654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6046$1583_Y
-    connect \B $eq$ls180.v:6046$1584_Y
-    connect \Y $and$ls180.v:6046$1585_Y
+    connect \A $and$ls180.v:6148$1652_Y
+    connect \B $eq$ls180.v:6148$1653_Y
+    connect \Y $and$ls180.v:6148$1654_Y
   end
-  attribute \src "ls180.v:6048.46-6048.99"
-  cell $and $and$ls180.v:6048$1586
+  attribute \src "ls180.v:6150.46-6150.99"
+  cell $and $and$ls180.v:6150$1655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242442,43 +243318,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6048$1586_Y
+    connect \Y $and$ls180.v:6150$1655_Y
   end
-  attribute \src "ls180.v:6048.45-6048.150"
-  cell $and $and$ls180.v:6048$1588
+  attribute \src "ls180.v:6150.45-6150.150"
+  cell $and $and$ls180.v:6150$1657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6048$1586_Y
-    connect \B $eq$ls180.v:6048$1587_Y
-    connect \Y $and$ls180.v:6048$1588_Y
+    connect \A $and$ls180.v:6150$1655_Y
+    connect \B $eq$ls180.v:6150$1656_Y
+    connect \Y $and$ls180.v:6150$1657_Y
   end
-  attribute \src "ls180.v:6049.46-6049.102"
-  cell $and $and$ls180.v:6049$1590
+  attribute \src "ls180.v:6151.46-6151.102"
+  cell $and $and$ls180.v:6151$1659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6049$1589_Y
-    connect \Y $and$ls180.v:6049$1590_Y
+    connect \B $not$ls180.v:6151$1658_Y
+    connect \Y $and$ls180.v:6151$1659_Y
   end
-  attribute \src "ls180.v:6049.45-6049.153"
-  cell $and $and$ls180.v:6049$1592
+  attribute \src "ls180.v:6151.45-6151.153"
+  cell $and $and$ls180.v:6151$1661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6049$1590_Y
-    connect \B $eq$ls180.v:6049$1591_Y
-    connect \Y $and$ls180.v:6049$1592_Y
+    connect \A $and$ls180.v:6151$1659_Y
+    connect \B $eq$ls180.v:6151$1660_Y
+    connect \Y $and$ls180.v:6151$1661_Y
   end
-  attribute \src "ls180.v:6051.46-6051.99"
-  cell $and $and$ls180.v:6051$1593
+  attribute \src "ls180.v:6153.46-6153.99"
+  cell $and $and$ls180.v:6153$1662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242486,43 +243362,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6051$1593_Y
+    connect \Y $and$ls180.v:6153$1662_Y
   end
-  attribute \src "ls180.v:6051.45-6051.150"
-  cell $and $and$ls180.v:6051$1595
+  attribute \src "ls180.v:6153.45-6153.150"
+  cell $and $and$ls180.v:6153$1664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6051$1593_Y
-    connect \B $eq$ls180.v:6051$1594_Y
-    connect \Y $and$ls180.v:6051$1595_Y
+    connect \A $and$ls180.v:6153$1662_Y
+    connect \B $eq$ls180.v:6153$1663_Y
+    connect \Y $and$ls180.v:6153$1664_Y
   end
-  attribute \src "ls180.v:6052.46-6052.102"
-  cell $and $and$ls180.v:6052$1597
+  attribute \src "ls180.v:6154.46-6154.102"
+  cell $and $and$ls180.v:6154$1666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6052$1596_Y
-    connect \Y $and$ls180.v:6052$1597_Y
+    connect \B $not$ls180.v:6154$1665_Y
+    connect \Y $and$ls180.v:6154$1666_Y
   end
-  attribute \src "ls180.v:6052.45-6052.153"
-  cell $and $and$ls180.v:6052$1599
+  attribute \src "ls180.v:6154.45-6154.153"
+  cell $and $and$ls180.v:6154$1668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6052$1597_Y
-    connect \B $eq$ls180.v:6052$1598_Y
-    connect \Y $and$ls180.v:6052$1599_Y
+    connect \A $and$ls180.v:6154$1666_Y
+    connect \B $eq$ls180.v:6154$1667_Y
+    connect \Y $and$ls180.v:6154$1668_Y
   end
-  attribute \src "ls180.v:6054.46-6054.99"
-  cell $and $and$ls180.v:6054$1600
+  attribute \src "ls180.v:6156.46-6156.99"
+  cell $and $and$ls180.v:6156$1669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242530,43 +243406,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6054$1600_Y
+    connect \Y $and$ls180.v:6156$1669_Y
   end
-  attribute \src "ls180.v:6054.45-6054.150"
-  cell $and $and$ls180.v:6054$1602
+  attribute \src "ls180.v:6156.45-6156.150"
+  cell $and $and$ls180.v:6156$1671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6054$1600_Y
-    connect \B $eq$ls180.v:6054$1601_Y
-    connect \Y $and$ls180.v:6054$1602_Y
+    connect \A $and$ls180.v:6156$1669_Y
+    connect \B $eq$ls180.v:6156$1670_Y
+    connect \Y $and$ls180.v:6156$1671_Y
   end
-  attribute \src "ls180.v:6055.46-6055.102"
-  cell $and $and$ls180.v:6055$1604
+  attribute \src "ls180.v:6157.46-6157.102"
+  cell $and $and$ls180.v:6157$1673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6055$1603_Y
-    connect \Y $and$ls180.v:6055$1604_Y
+    connect \B $not$ls180.v:6157$1672_Y
+    connect \Y $and$ls180.v:6157$1673_Y
   end
-  attribute \src "ls180.v:6055.45-6055.153"
-  cell $and $and$ls180.v:6055$1606
+  attribute \src "ls180.v:6157.45-6157.153"
+  cell $and $and$ls180.v:6157$1675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6055$1604_Y
-    connect \B $eq$ls180.v:6055$1605_Y
-    connect \Y $and$ls180.v:6055$1606_Y
+    connect \A $and$ls180.v:6157$1673_Y
+    connect \B $eq$ls180.v:6157$1674_Y
+    connect \Y $and$ls180.v:6157$1675_Y
   end
-  attribute \src "ls180.v:6057.46-6057.99"
-  cell $and $and$ls180.v:6057$1607
+  attribute \src "ls180.v:6159.46-6159.99"
+  cell $and $and$ls180.v:6159$1676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242574,43 +243450,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6057$1607_Y
+    connect \Y $and$ls180.v:6159$1676_Y
   end
-  attribute \src "ls180.v:6057.45-6057.150"
-  cell $and $and$ls180.v:6057$1609
+  attribute \src "ls180.v:6159.45-6159.150"
+  cell $and $and$ls180.v:6159$1678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6057$1607_Y
-    connect \B $eq$ls180.v:6057$1608_Y
-    connect \Y $and$ls180.v:6057$1609_Y
+    connect \A $and$ls180.v:6159$1676_Y
+    connect \B $eq$ls180.v:6159$1677_Y
+    connect \Y $and$ls180.v:6159$1678_Y
   end
-  attribute \src "ls180.v:6058.46-6058.102"
-  cell $and $and$ls180.v:6058$1611
+  attribute \src "ls180.v:6160.46-6160.102"
+  cell $and $and$ls180.v:6160$1680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6058$1610_Y
-    connect \Y $and$ls180.v:6058$1611_Y
+    connect \B $not$ls180.v:6160$1679_Y
+    connect \Y $and$ls180.v:6160$1680_Y
   end
-  attribute \src "ls180.v:6058.45-6058.153"
-  cell $and $and$ls180.v:6058$1613
+  attribute \src "ls180.v:6160.45-6160.153"
+  cell $and $and$ls180.v:6160$1682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6058$1611_Y
-    connect \B $eq$ls180.v:6058$1612_Y
-    connect \Y $and$ls180.v:6058$1613_Y
+    connect \A $and$ls180.v:6160$1680_Y
+    connect \B $eq$ls180.v:6160$1681_Y
+    connect \Y $and$ls180.v:6160$1682_Y
   end
-  attribute \src "ls180.v:6060.42-6060.95"
-  cell $and $and$ls180.v:6060$1614
+  attribute \src "ls180.v:6162.42-6162.95"
+  cell $and $and$ls180.v:6162$1683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242618,43 +243494,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6060$1614_Y
+    connect \Y $and$ls180.v:6162$1683_Y
   end
-  attribute \src "ls180.v:6060.41-6060.146"
-  cell $and $and$ls180.v:6060$1616
+  attribute \src "ls180.v:6162.41-6162.146"
+  cell $and $and$ls180.v:6162$1685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6060$1614_Y
-    connect \B $eq$ls180.v:6060$1615_Y
-    connect \Y $and$ls180.v:6060$1616_Y
+    connect \A $and$ls180.v:6162$1683_Y
+    connect \B $eq$ls180.v:6162$1684_Y
+    connect \Y $and$ls180.v:6162$1685_Y
   end
-  attribute \src "ls180.v:6061.42-6061.98"
-  cell $and $and$ls180.v:6061$1618
+  attribute \src "ls180.v:6163.42-6163.98"
+  cell $and $and$ls180.v:6163$1687
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6061$1617_Y
-    connect \Y $and$ls180.v:6061$1618_Y
+    connect \B $not$ls180.v:6163$1686_Y
+    connect \Y $and$ls180.v:6163$1687_Y
   end
-  attribute \src "ls180.v:6061.41-6061.149"
-  cell $and $and$ls180.v:6061$1620
+  attribute \src "ls180.v:6163.41-6163.149"
+  cell $and $and$ls180.v:6163$1689
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6061$1618_Y
-    connect \B $eq$ls180.v:6061$1619_Y
-    connect \Y $and$ls180.v:6061$1620_Y
+    connect \A $and$ls180.v:6163$1687_Y
+    connect \B $eq$ls180.v:6163$1688_Y
+    connect \Y $and$ls180.v:6163$1689_Y
   end
-  attribute \src "ls180.v:6063.43-6063.96"
-  cell $and $and$ls180.v:6063$1621
+  attribute \src "ls180.v:6165.43-6165.96"
+  cell $and $and$ls180.v:6165$1690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242662,43 +243538,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6063$1621_Y
+    connect \Y $and$ls180.v:6165$1690_Y
   end
-  attribute \src "ls180.v:6063.42-6063.147"
-  cell $and $and$ls180.v:6063$1623
+  attribute \src "ls180.v:6165.42-6165.147"
+  cell $and $and$ls180.v:6165$1692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6063$1621_Y
-    connect \B $eq$ls180.v:6063$1622_Y
-    connect \Y $and$ls180.v:6063$1623_Y
+    connect \A $and$ls180.v:6165$1690_Y
+    connect \B $eq$ls180.v:6165$1691_Y
+    connect \Y $and$ls180.v:6165$1692_Y
   end
-  attribute \src "ls180.v:6064.43-6064.99"
-  cell $and $and$ls180.v:6064$1625
+  attribute \src "ls180.v:6166.43-6166.99"
+  cell $and $and$ls180.v:6166$1694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6064$1624_Y
-    connect \Y $and$ls180.v:6064$1625_Y
+    connect \B $not$ls180.v:6166$1693_Y
+    connect \Y $and$ls180.v:6166$1694_Y
   end
-  attribute \src "ls180.v:6064.42-6064.150"
-  cell $and $and$ls180.v:6064$1627
+  attribute \src "ls180.v:6166.42-6166.150"
+  cell $and $and$ls180.v:6166$1696
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6064$1625_Y
-    connect \B $eq$ls180.v:6064$1626_Y
-    connect \Y $and$ls180.v:6064$1627_Y
+    connect \A $and$ls180.v:6166$1694_Y
+    connect \B $eq$ls180.v:6166$1695_Y
+    connect \Y $and$ls180.v:6166$1696_Y
   end
-  attribute \src "ls180.v:6066.46-6066.99"
-  cell $and $and$ls180.v:6066$1628
+  attribute \src "ls180.v:6168.46-6168.99"
+  cell $and $and$ls180.v:6168$1697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242706,43 +243582,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6066$1628_Y
+    connect \Y $and$ls180.v:6168$1697_Y
   end
-  attribute \src "ls180.v:6066.45-6066.150"
-  cell $and $and$ls180.v:6066$1630
+  attribute \src "ls180.v:6168.45-6168.150"
+  cell $and $and$ls180.v:6168$1699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6066$1628_Y
-    connect \B $eq$ls180.v:6066$1629_Y
-    connect \Y $and$ls180.v:6066$1630_Y
+    connect \A $and$ls180.v:6168$1697_Y
+    connect \B $eq$ls180.v:6168$1698_Y
+    connect \Y $and$ls180.v:6168$1699_Y
   end
-  attribute \src "ls180.v:6067.46-6067.102"
-  cell $and $and$ls180.v:6067$1632
+  attribute \src "ls180.v:6169.46-6169.102"
+  cell $and $and$ls180.v:6169$1701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6067$1631_Y
-    connect \Y $and$ls180.v:6067$1632_Y
+    connect \B $not$ls180.v:6169$1700_Y
+    connect \Y $and$ls180.v:6169$1701_Y
   end
-  attribute \src "ls180.v:6067.45-6067.153"
-  cell $and $and$ls180.v:6067$1634
+  attribute \src "ls180.v:6169.45-6169.153"
+  cell $and $and$ls180.v:6169$1703
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6067$1632_Y
-    connect \B $eq$ls180.v:6067$1633_Y
-    connect \Y $and$ls180.v:6067$1634_Y
+    connect \A $and$ls180.v:6169$1701_Y
+    connect \B $eq$ls180.v:6169$1702_Y
+    connect \Y $and$ls180.v:6169$1703_Y
   end
-  attribute \src "ls180.v:6069.46-6069.99"
-  cell $and $and$ls180.v:6069$1635
+  attribute \src "ls180.v:6171.46-6171.99"
+  cell $and $and$ls180.v:6171$1704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242750,43 +243626,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6069$1635_Y
+    connect \Y $and$ls180.v:6171$1704_Y
   end
-  attribute \src "ls180.v:6069.45-6069.150"
-  cell $and $and$ls180.v:6069$1637
+  attribute \src "ls180.v:6171.45-6171.150"
+  cell $and $and$ls180.v:6171$1706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6069$1635_Y
-    connect \B $eq$ls180.v:6069$1636_Y
-    connect \Y $and$ls180.v:6069$1637_Y
+    connect \A $and$ls180.v:6171$1704_Y
+    connect \B $eq$ls180.v:6171$1705_Y
+    connect \Y $and$ls180.v:6171$1706_Y
   end
-  attribute \src "ls180.v:6070.46-6070.102"
-  cell $and $and$ls180.v:6070$1639
+  attribute \src "ls180.v:6172.46-6172.102"
+  cell $and $and$ls180.v:6172$1708
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6070$1638_Y
-    connect \Y $and$ls180.v:6070$1639_Y
+    connect \B $not$ls180.v:6172$1707_Y
+    connect \Y $and$ls180.v:6172$1708_Y
   end
-  attribute \src "ls180.v:6070.45-6070.153"
-  cell $and $and$ls180.v:6070$1641
+  attribute \src "ls180.v:6172.45-6172.153"
+  cell $and $and$ls180.v:6172$1710
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6070$1639_Y
-    connect \B $eq$ls180.v:6070$1640_Y
-    connect \Y $and$ls180.v:6070$1641_Y
+    connect \A $and$ls180.v:6172$1708_Y
+    connect \B $eq$ls180.v:6172$1709_Y
+    connect \Y $and$ls180.v:6172$1710_Y
   end
-  attribute \src "ls180.v:6072.45-6072.98"
-  cell $and $and$ls180.v:6072$1642
+  attribute \src "ls180.v:6174.45-6174.98"
+  cell $and $and$ls180.v:6174$1711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242794,43 +243670,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6072$1642_Y
+    connect \Y $and$ls180.v:6174$1711_Y
   end
-  attribute \src "ls180.v:6072.44-6072.149"
-  cell $and $and$ls180.v:6072$1644
+  attribute \src "ls180.v:6174.44-6174.149"
+  cell $and $and$ls180.v:6174$1713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6072$1642_Y
-    connect \B $eq$ls180.v:6072$1643_Y
-    connect \Y $and$ls180.v:6072$1644_Y
+    connect \A $and$ls180.v:6174$1711_Y
+    connect \B $eq$ls180.v:6174$1712_Y
+    connect \Y $and$ls180.v:6174$1713_Y
   end
-  attribute \src "ls180.v:6073.45-6073.101"
-  cell $and $and$ls180.v:6073$1646
+  attribute \src "ls180.v:6175.45-6175.101"
+  cell $and $and$ls180.v:6175$1715
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6073$1645_Y
-    connect \Y $and$ls180.v:6073$1646_Y
+    connect \B $not$ls180.v:6175$1714_Y
+    connect \Y $and$ls180.v:6175$1715_Y
   end
-  attribute \src "ls180.v:6073.44-6073.152"
-  cell $and $and$ls180.v:6073$1648
+  attribute \src "ls180.v:6175.44-6175.152"
+  cell $and $and$ls180.v:6175$1717
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6073$1646_Y
-    connect \B $eq$ls180.v:6073$1647_Y
-    connect \Y $and$ls180.v:6073$1648_Y
+    connect \A $and$ls180.v:6175$1715_Y
+    connect \B $eq$ls180.v:6175$1716_Y
+    connect \Y $and$ls180.v:6175$1717_Y
   end
-  attribute \src "ls180.v:6075.45-6075.98"
-  cell $and $and$ls180.v:6075$1649
+  attribute \src "ls180.v:6177.45-6177.98"
+  cell $and $and$ls180.v:6177$1718
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242838,43 +243714,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6075$1649_Y
+    connect \Y $and$ls180.v:6177$1718_Y
   end
-  attribute \src "ls180.v:6075.44-6075.149"
-  cell $and $and$ls180.v:6075$1651
+  attribute \src "ls180.v:6177.44-6177.149"
+  cell $and $and$ls180.v:6177$1720
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6075$1649_Y
-    connect \B $eq$ls180.v:6075$1650_Y
-    connect \Y $and$ls180.v:6075$1651_Y
+    connect \A $and$ls180.v:6177$1718_Y
+    connect \B $eq$ls180.v:6177$1719_Y
+    connect \Y $and$ls180.v:6177$1720_Y
   end
-  attribute \src "ls180.v:6076.45-6076.101"
-  cell $and $and$ls180.v:6076$1653
+  attribute \src "ls180.v:6178.45-6178.101"
+  cell $and $and$ls180.v:6178$1722
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6076$1652_Y
-    connect \Y $and$ls180.v:6076$1653_Y
+    connect \B $not$ls180.v:6178$1721_Y
+    connect \Y $and$ls180.v:6178$1722_Y
   end
-  attribute \src "ls180.v:6076.44-6076.152"
-  cell $and $and$ls180.v:6076$1655
+  attribute \src "ls180.v:6178.44-6178.152"
+  cell $and $and$ls180.v:6178$1724
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6076$1653_Y
-    connect \B $eq$ls180.v:6076$1654_Y
-    connect \Y $and$ls180.v:6076$1655_Y
+    connect \A $and$ls180.v:6178$1722_Y
+    connect \B $eq$ls180.v:6178$1723_Y
+    connect \Y $and$ls180.v:6178$1724_Y
   end
-  attribute \src "ls180.v:6078.45-6078.98"
-  cell $and $and$ls180.v:6078$1656
+  attribute \src "ls180.v:6180.45-6180.98"
+  cell $and $and$ls180.v:6180$1725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242882,43 +243758,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6078$1656_Y
+    connect \Y $and$ls180.v:6180$1725_Y
   end
-  attribute \src "ls180.v:6078.44-6078.149"
-  cell $and $and$ls180.v:6078$1658
+  attribute \src "ls180.v:6180.44-6180.149"
+  cell $and $and$ls180.v:6180$1727
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6078$1656_Y
-    connect \B $eq$ls180.v:6078$1657_Y
-    connect \Y $and$ls180.v:6078$1658_Y
+    connect \A $and$ls180.v:6180$1725_Y
+    connect \B $eq$ls180.v:6180$1726_Y
+    connect \Y $and$ls180.v:6180$1727_Y
   end
-  attribute \src "ls180.v:6079.45-6079.101"
-  cell $and $and$ls180.v:6079$1660
+  attribute \src "ls180.v:6181.45-6181.101"
+  cell $and $and$ls180.v:6181$1729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6079$1659_Y
-    connect \Y $and$ls180.v:6079$1660_Y
+    connect \B $not$ls180.v:6181$1728_Y
+    connect \Y $and$ls180.v:6181$1729_Y
   end
-  attribute \src "ls180.v:6079.44-6079.152"
-  cell $and $and$ls180.v:6079$1662
+  attribute \src "ls180.v:6181.44-6181.152"
+  cell $and $and$ls180.v:6181$1731
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6079$1660_Y
-    connect \B $eq$ls180.v:6079$1661_Y
-    connect \Y $and$ls180.v:6079$1662_Y
+    connect \A $and$ls180.v:6181$1729_Y
+    connect \B $eq$ls180.v:6181$1730_Y
+    connect \Y $and$ls180.v:6181$1731_Y
   end
-  attribute \src "ls180.v:6081.45-6081.98"
-  cell $and $and$ls180.v:6081$1663
+  attribute \src "ls180.v:6183.45-6183.98"
+  cell $and $and$ls180.v:6183$1732
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242926,43 +243802,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
     connect \B \builder_interface6_bank_bus_we
-    connect \Y $and$ls180.v:6081$1663_Y
+    connect \Y $and$ls180.v:6183$1732_Y
   end
-  attribute \src "ls180.v:6081.44-6081.149"
-  cell $and $and$ls180.v:6081$1665
+  attribute \src "ls180.v:6183.44-6183.149"
+  cell $and $and$ls180.v:6183$1734
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6081$1663_Y
-    connect \B $eq$ls180.v:6081$1664_Y
-    connect \Y $and$ls180.v:6081$1665_Y
+    connect \A $and$ls180.v:6183$1732_Y
+    connect \B $eq$ls180.v:6183$1733_Y
+    connect \Y $and$ls180.v:6183$1734_Y
   end
-  attribute \src "ls180.v:6082.45-6082.101"
-  cell $and $and$ls180.v:6082$1667
+  attribute \src "ls180.v:6184.45-6184.101"
+  cell $and $and$ls180.v:6184$1736
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank6_sel
-    connect \B $not$ls180.v:6082$1666_Y
-    connect \Y $and$ls180.v:6082$1667_Y
+    connect \B $not$ls180.v:6184$1735_Y
+    connect \Y $and$ls180.v:6184$1736_Y
   end
-  attribute \src "ls180.v:6082.44-6082.152"
-  cell $and $and$ls180.v:6082$1669
+  attribute \src "ls180.v:6184.44-6184.152"
+  cell $and $and$ls180.v:6184$1738
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6082$1667_Y
-    connect \B $eq$ls180.v:6082$1668_Y
-    connect \Y $and$ls180.v:6082$1669_Y
+    connect \A $and$ls180.v:6184$1736_Y
+    connect \B $eq$ls180.v:6184$1737_Y
+    connect \Y $and$ls180.v:6184$1738_Y
   end
-  attribute \src "ls180.v:6120.42-6120.95"
-  cell $and $and$ls180.v:6120$1671
+  attribute \src "ls180.v:6222.42-6222.95"
+  cell $and $and$ls180.v:6222$1740
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -242970,43 +243846,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6120$1671_Y
+    connect \Y $and$ls180.v:6222$1740_Y
   end
-  attribute \src "ls180.v:6120.41-6120.145"
-  cell $and $and$ls180.v:6120$1673
+  attribute \src "ls180.v:6222.41-6222.145"
+  cell $and $and$ls180.v:6222$1742
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6120$1671_Y
-    connect \B $eq$ls180.v:6120$1672_Y
-    connect \Y $and$ls180.v:6120$1673_Y
+    connect \A $and$ls180.v:6222$1740_Y
+    connect \B $eq$ls180.v:6222$1741_Y
+    connect \Y $and$ls180.v:6222$1742_Y
   end
-  attribute \src "ls180.v:6121.42-6121.98"
-  cell $and $and$ls180.v:6121$1675
+  attribute \src "ls180.v:6223.42-6223.98"
+  cell $and $and$ls180.v:6223$1744
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6121$1674_Y
-    connect \Y $and$ls180.v:6121$1675_Y
+    connect \B $not$ls180.v:6223$1743_Y
+    connect \Y $and$ls180.v:6223$1744_Y
   end
-  attribute \src "ls180.v:6121.41-6121.148"
-  cell $and $and$ls180.v:6121$1677
+  attribute \src "ls180.v:6223.41-6223.148"
+  cell $and $and$ls180.v:6223$1746
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6121$1675_Y
-    connect \B $eq$ls180.v:6121$1676_Y
-    connect \Y $and$ls180.v:6121$1677_Y
+    connect \A $and$ls180.v:6223$1744_Y
+    connect \B $eq$ls180.v:6223$1745_Y
+    connect \Y $and$ls180.v:6223$1746_Y
   end
-  attribute \src "ls180.v:6123.42-6123.95"
-  cell $and $and$ls180.v:6123$1678
+  attribute \src "ls180.v:6225.42-6225.95"
+  cell $and $and$ls180.v:6225$1747
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243014,43 +243890,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6123$1678_Y
+    connect \Y $and$ls180.v:6225$1747_Y
   end
-  attribute \src "ls180.v:6123.41-6123.145"
-  cell $and $and$ls180.v:6123$1680
+  attribute \src "ls180.v:6225.41-6225.145"
+  cell $and $and$ls180.v:6225$1749
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6123$1678_Y
-    connect \B $eq$ls180.v:6123$1679_Y
-    connect \Y $and$ls180.v:6123$1680_Y
+    connect \A $and$ls180.v:6225$1747_Y
+    connect \B $eq$ls180.v:6225$1748_Y
+    connect \Y $and$ls180.v:6225$1749_Y
   end
-  attribute \src "ls180.v:6124.42-6124.98"
-  cell $and $and$ls180.v:6124$1682
+  attribute \src "ls180.v:6226.42-6226.98"
+  cell $and $and$ls180.v:6226$1751
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6124$1681_Y
-    connect \Y $and$ls180.v:6124$1682_Y
+    connect \B $not$ls180.v:6226$1750_Y
+    connect \Y $and$ls180.v:6226$1751_Y
   end
-  attribute \src "ls180.v:6124.41-6124.148"
-  cell $and $and$ls180.v:6124$1684
+  attribute \src "ls180.v:6226.41-6226.148"
+  cell $and $and$ls180.v:6226$1753
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6124$1682_Y
-    connect \B $eq$ls180.v:6124$1683_Y
-    connect \Y $and$ls180.v:6124$1684_Y
+    connect \A $and$ls180.v:6226$1751_Y
+    connect \B $eq$ls180.v:6226$1752_Y
+    connect \Y $and$ls180.v:6226$1753_Y
   end
-  attribute \src "ls180.v:6126.42-6126.95"
-  cell $and $and$ls180.v:6126$1685
+  attribute \src "ls180.v:6228.42-6228.95"
+  cell $and $and$ls180.v:6228$1754
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243058,43 +243934,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6126$1685_Y
+    connect \Y $and$ls180.v:6228$1754_Y
   end
-  attribute \src "ls180.v:6126.41-6126.145"
-  cell $and $and$ls180.v:6126$1687
+  attribute \src "ls180.v:6228.41-6228.145"
+  cell $and $and$ls180.v:6228$1756
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6126$1685_Y
-    connect \B $eq$ls180.v:6126$1686_Y
-    connect \Y $and$ls180.v:6126$1687_Y
+    connect \A $and$ls180.v:6228$1754_Y
+    connect \B $eq$ls180.v:6228$1755_Y
+    connect \Y $and$ls180.v:6228$1756_Y
   end
-  attribute \src "ls180.v:6127.42-6127.98"
-  cell $and $and$ls180.v:6127$1689
+  attribute \src "ls180.v:6229.42-6229.98"
+  cell $and $and$ls180.v:6229$1758
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6127$1688_Y
-    connect \Y $and$ls180.v:6127$1689_Y
+    connect \B $not$ls180.v:6229$1757_Y
+    connect \Y $and$ls180.v:6229$1758_Y
   end
-  attribute \src "ls180.v:6127.41-6127.148"
-  cell $and $and$ls180.v:6127$1691
+  attribute \src "ls180.v:6229.41-6229.148"
+  cell $and $and$ls180.v:6229$1760
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6127$1689_Y
-    connect \B $eq$ls180.v:6127$1690_Y
-    connect \Y $and$ls180.v:6127$1691_Y
+    connect \A $and$ls180.v:6229$1758_Y
+    connect \B $eq$ls180.v:6229$1759_Y
+    connect \Y $and$ls180.v:6229$1760_Y
   end
-  attribute \src "ls180.v:6129.42-6129.95"
-  cell $and $and$ls180.v:6129$1692
+  attribute \src "ls180.v:6231.42-6231.95"
+  cell $and $and$ls180.v:6231$1761
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243102,43 +243978,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6129$1692_Y
+    connect \Y $and$ls180.v:6231$1761_Y
   end
-  attribute \src "ls180.v:6129.41-6129.145"
-  cell $and $and$ls180.v:6129$1694
+  attribute \src "ls180.v:6231.41-6231.145"
+  cell $and $and$ls180.v:6231$1763
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6129$1692_Y
-    connect \B $eq$ls180.v:6129$1693_Y
-    connect \Y $and$ls180.v:6129$1694_Y
+    connect \A $and$ls180.v:6231$1761_Y
+    connect \B $eq$ls180.v:6231$1762_Y
+    connect \Y $and$ls180.v:6231$1763_Y
   end
-  attribute \src "ls180.v:6130.42-6130.98"
-  cell $and $and$ls180.v:6130$1696
+  attribute \src "ls180.v:6232.42-6232.98"
+  cell $and $and$ls180.v:6232$1765
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6130$1695_Y
-    connect \Y $and$ls180.v:6130$1696_Y
+    connect \B $not$ls180.v:6232$1764_Y
+    connect \Y $and$ls180.v:6232$1765_Y
   end
-  attribute \src "ls180.v:6130.41-6130.148"
-  cell $and $and$ls180.v:6130$1698
+  attribute \src "ls180.v:6232.41-6232.148"
+  cell $and $and$ls180.v:6232$1767
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6130$1696_Y
-    connect \B $eq$ls180.v:6130$1697_Y
-    connect \Y $and$ls180.v:6130$1698_Y
+    connect \A $and$ls180.v:6232$1765_Y
+    connect \B $eq$ls180.v:6232$1766_Y
+    connect \Y $and$ls180.v:6232$1767_Y
   end
-  attribute \src "ls180.v:6132.42-6132.95"
-  cell $and $and$ls180.v:6132$1699
+  attribute \src "ls180.v:6234.42-6234.95"
+  cell $and $and$ls180.v:6234$1768
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243146,43 +244022,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6132$1699_Y
+    connect \Y $and$ls180.v:6234$1768_Y
   end
-  attribute \src "ls180.v:6132.41-6132.145"
-  cell $and $and$ls180.v:6132$1701
+  attribute \src "ls180.v:6234.41-6234.145"
+  cell $and $and$ls180.v:6234$1770
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6132$1699_Y
-    connect \B $eq$ls180.v:6132$1700_Y
-    connect \Y $and$ls180.v:6132$1701_Y
+    connect \A $and$ls180.v:6234$1768_Y
+    connect \B $eq$ls180.v:6234$1769_Y
+    connect \Y $and$ls180.v:6234$1770_Y
   end
-  attribute \src "ls180.v:6133.42-6133.98"
-  cell $and $and$ls180.v:6133$1703
+  attribute \src "ls180.v:6235.42-6235.98"
+  cell $and $and$ls180.v:6235$1772
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6133$1702_Y
-    connect \Y $and$ls180.v:6133$1703_Y
+    connect \B $not$ls180.v:6235$1771_Y
+    connect \Y $and$ls180.v:6235$1772_Y
   end
-  attribute \src "ls180.v:6133.41-6133.148"
-  cell $and $and$ls180.v:6133$1705
+  attribute \src "ls180.v:6235.41-6235.148"
+  cell $and $and$ls180.v:6235$1774
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6133$1703_Y
-    connect \B $eq$ls180.v:6133$1704_Y
-    connect \Y $and$ls180.v:6133$1705_Y
+    connect \A $and$ls180.v:6235$1772_Y
+    connect \B $eq$ls180.v:6235$1773_Y
+    connect \Y $and$ls180.v:6235$1774_Y
   end
-  attribute \src "ls180.v:6135.42-6135.95"
-  cell $and $and$ls180.v:6135$1706
+  attribute \src "ls180.v:6237.42-6237.95"
+  cell $and $and$ls180.v:6237$1775
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243190,43 +244066,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6135$1706_Y
+    connect \Y $and$ls180.v:6237$1775_Y
   end
-  attribute \src "ls180.v:6135.41-6135.145"
-  cell $and $and$ls180.v:6135$1708
+  attribute \src "ls180.v:6237.41-6237.145"
+  cell $and $and$ls180.v:6237$1777
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6135$1706_Y
-    connect \B $eq$ls180.v:6135$1707_Y
-    connect \Y $and$ls180.v:6135$1708_Y
+    connect \A $and$ls180.v:6237$1775_Y
+    connect \B $eq$ls180.v:6237$1776_Y
+    connect \Y $and$ls180.v:6237$1777_Y
   end
-  attribute \src "ls180.v:6136.42-6136.98"
-  cell $and $and$ls180.v:6136$1710
+  attribute \src "ls180.v:6238.42-6238.98"
+  cell $and $and$ls180.v:6238$1779
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6136$1709_Y
-    connect \Y $and$ls180.v:6136$1710_Y
+    connect \B $not$ls180.v:6238$1778_Y
+    connect \Y $and$ls180.v:6238$1779_Y
   end
-  attribute \src "ls180.v:6136.41-6136.148"
-  cell $and $and$ls180.v:6136$1712
+  attribute \src "ls180.v:6238.41-6238.148"
+  cell $and $and$ls180.v:6238$1781
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6136$1710_Y
-    connect \B $eq$ls180.v:6136$1711_Y
-    connect \Y $and$ls180.v:6136$1712_Y
+    connect \A $and$ls180.v:6238$1779_Y
+    connect \B $eq$ls180.v:6238$1780_Y
+    connect \Y $and$ls180.v:6238$1781_Y
   end
-  attribute \src "ls180.v:6138.42-6138.95"
-  cell $and $and$ls180.v:6138$1713
+  attribute \src "ls180.v:6240.42-6240.95"
+  cell $and $and$ls180.v:6240$1782
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243234,43 +244110,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6138$1713_Y
+    connect \Y $and$ls180.v:6240$1782_Y
   end
-  attribute \src "ls180.v:6138.41-6138.145"
-  cell $and $and$ls180.v:6138$1715
+  attribute \src "ls180.v:6240.41-6240.145"
+  cell $and $and$ls180.v:6240$1784
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6138$1713_Y
-    connect \B $eq$ls180.v:6138$1714_Y
-    connect \Y $and$ls180.v:6138$1715_Y
+    connect \A $and$ls180.v:6240$1782_Y
+    connect \B $eq$ls180.v:6240$1783_Y
+    connect \Y $and$ls180.v:6240$1784_Y
   end
-  attribute \src "ls180.v:6139.42-6139.98"
-  cell $and $and$ls180.v:6139$1717
+  attribute \src "ls180.v:6241.42-6241.98"
+  cell $and $and$ls180.v:6241$1786
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6139$1716_Y
-    connect \Y $and$ls180.v:6139$1717_Y
+    connect \B $not$ls180.v:6241$1785_Y
+    connect \Y $and$ls180.v:6241$1786_Y
   end
-  attribute \src "ls180.v:6139.41-6139.148"
-  cell $and $and$ls180.v:6139$1719
+  attribute \src "ls180.v:6241.41-6241.148"
+  cell $and $and$ls180.v:6241$1788
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6139$1717_Y
-    connect \B $eq$ls180.v:6139$1718_Y
-    connect \Y $and$ls180.v:6139$1719_Y
+    connect \A $and$ls180.v:6241$1786_Y
+    connect \B $eq$ls180.v:6241$1787_Y
+    connect \Y $and$ls180.v:6241$1788_Y
   end
-  attribute \src "ls180.v:6141.42-6141.95"
-  cell $and $and$ls180.v:6141$1720
+  attribute \src "ls180.v:6243.42-6243.95"
+  cell $and $and$ls180.v:6243$1789
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243278,43 +244154,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6141$1720_Y
+    connect \Y $and$ls180.v:6243$1789_Y
   end
-  attribute \src "ls180.v:6141.41-6141.145"
-  cell $and $and$ls180.v:6141$1722
+  attribute \src "ls180.v:6243.41-6243.145"
+  cell $and $and$ls180.v:6243$1791
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6141$1720_Y
-    connect \B $eq$ls180.v:6141$1721_Y
-    connect \Y $and$ls180.v:6141$1722_Y
+    connect \A $and$ls180.v:6243$1789_Y
+    connect \B $eq$ls180.v:6243$1790_Y
+    connect \Y $and$ls180.v:6243$1791_Y
   end
-  attribute \src "ls180.v:6142.42-6142.98"
-  cell $and $and$ls180.v:6142$1724
+  attribute \src "ls180.v:6244.42-6244.98"
+  cell $and $and$ls180.v:6244$1793
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6142$1723_Y
-    connect \Y $and$ls180.v:6142$1724_Y
+    connect \B $not$ls180.v:6244$1792_Y
+    connect \Y $and$ls180.v:6244$1793_Y
   end
-  attribute \src "ls180.v:6142.41-6142.148"
-  cell $and $and$ls180.v:6142$1726
+  attribute \src "ls180.v:6244.41-6244.148"
+  cell $and $and$ls180.v:6244$1795
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6142$1724_Y
-    connect \B $eq$ls180.v:6142$1725_Y
-    connect \Y $and$ls180.v:6142$1726_Y
+    connect \A $and$ls180.v:6244$1793_Y
+    connect \B $eq$ls180.v:6244$1794_Y
+    connect \Y $and$ls180.v:6244$1795_Y
   end
-  attribute \src "ls180.v:6144.44-6144.97"
-  cell $and $and$ls180.v:6144$1727
+  attribute \src "ls180.v:6246.44-6246.97"
+  cell $and $and$ls180.v:6246$1796
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243322,43 +244198,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6144$1727_Y
+    connect \Y $and$ls180.v:6246$1796_Y
   end
-  attribute \src "ls180.v:6144.43-6144.147"
-  cell $and $and$ls180.v:6144$1729
+  attribute \src "ls180.v:6246.43-6246.147"
+  cell $and $and$ls180.v:6246$1798
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6144$1727_Y
-    connect \B $eq$ls180.v:6144$1728_Y
-    connect \Y $and$ls180.v:6144$1729_Y
+    connect \A $and$ls180.v:6246$1796_Y
+    connect \B $eq$ls180.v:6246$1797_Y
+    connect \Y $and$ls180.v:6246$1798_Y
   end
-  attribute \src "ls180.v:6145.44-6145.100"
-  cell $and $and$ls180.v:6145$1731
+  attribute \src "ls180.v:6247.44-6247.100"
+  cell $and $and$ls180.v:6247$1800
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6145$1730_Y
-    connect \Y $and$ls180.v:6145$1731_Y
+    connect \B $not$ls180.v:6247$1799_Y
+    connect \Y $and$ls180.v:6247$1800_Y
   end
-  attribute \src "ls180.v:6145.43-6145.150"
-  cell $and $and$ls180.v:6145$1733
+  attribute \src "ls180.v:6247.43-6247.150"
+  cell $and $and$ls180.v:6247$1802
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6145$1731_Y
-    connect \B $eq$ls180.v:6145$1732_Y
-    connect \Y $and$ls180.v:6145$1733_Y
+    connect \A $and$ls180.v:6247$1800_Y
+    connect \B $eq$ls180.v:6247$1801_Y
+    connect \Y $and$ls180.v:6247$1802_Y
   end
-  attribute \src "ls180.v:6147.44-6147.97"
-  cell $and $and$ls180.v:6147$1734
+  attribute \src "ls180.v:6249.44-6249.97"
+  cell $and $and$ls180.v:6249$1803
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243366,43 +244242,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6147$1734_Y
+    connect \Y $and$ls180.v:6249$1803_Y
   end
-  attribute \src "ls180.v:6147.43-6147.147"
-  cell $and $and$ls180.v:6147$1736
+  attribute \src "ls180.v:6249.43-6249.147"
+  cell $and $and$ls180.v:6249$1805
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6147$1734_Y
-    connect \B $eq$ls180.v:6147$1735_Y
-    connect \Y $and$ls180.v:6147$1736_Y
+    connect \A $and$ls180.v:6249$1803_Y
+    connect \B $eq$ls180.v:6249$1804_Y
+    connect \Y $and$ls180.v:6249$1805_Y
   end
-  attribute \src "ls180.v:6148.44-6148.100"
-  cell $and $and$ls180.v:6148$1738
+  attribute \src "ls180.v:6250.44-6250.100"
+  cell $and $and$ls180.v:6250$1807
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6148$1737_Y
-    connect \Y $and$ls180.v:6148$1738_Y
+    connect \B $not$ls180.v:6250$1806_Y
+    connect \Y $and$ls180.v:6250$1807_Y
   end
-  attribute \src "ls180.v:6148.43-6148.150"
-  cell $and $and$ls180.v:6148$1740
+  attribute \src "ls180.v:6250.43-6250.150"
+  cell $and $and$ls180.v:6250$1809
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6148$1738_Y
-    connect \B $eq$ls180.v:6148$1739_Y
-    connect \Y $and$ls180.v:6148$1740_Y
+    connect \A $and$ls180.v:6250$1807_Y
+    connect \B $eq$ls180.v:6250$1808_Y
+    connect \Y $and$ls180.v:6250$1809_Y
   end
-  attribute \src "ls180.v:6150.44-6150.97"
-  cell $and $and$ls180.v:6150$1741
+  attribute \src "ls180.v:6252.44-6252.97"
+  cell $and $and$ls180.v:6252$1810
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243410,43 +244286,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6150$1741_Y
+    connect \Y $and$ls180.v:6252$1810_Y
   end
-  attribute \src "ls180.v:6150.43-6150.148"
-  cell $and $and$ls180.v:6150$1743
+  attribute \src "ls180.v:6252.43-6252.148"
+  cell $and $and$ls180.v:6252$1812
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6150$1741_Y
-    connect \B $eq$ls180.v:6150$1742_Y
-    connect \Y $and$ls180.v:6150$1743_Y
+    connect \A $and$ls180.v:6252$1810_Y
+    connect \B $eq$ls180.v:6252$1811_Y
+    connect \Y $and$ls180.v:6252$1812_Y
   end
-  attribute \src "ls180.v:6151.44-6151.100"
-  cell $and $and$ls180.v:6151$1745
+  attribute \src "ls180.v:6253.44-6253.100"
+  cell $and $and$ls180.v:6253$1814
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6151$1744_Y
-    connect \Y $and$ls180.v:6151$1745_Y
+    connect \B $not$ls180.v:6253$1813_Y
+    connect \Y $and$ls180.v:6253$1814_Y
   end
-  attribute \src "ls180.v:6151.43-6151.151"
-  cell $and $and$ls180.v:6151$1747
+  attribute \src "ls180.v:6253.43-6253.151"
+  cell $and $and$ls180.v:6253$1816
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6151$1745_Y
-    connect \B $eq$ls180.v:6151$1746_Y
-    connect \Y $and$ls180.v:6151$1747_Y
+    connect \A $and$ls180.v:6253$1814_Y
+    connect \B $eq$ls180.v:6253$1815_Y
+    connect \Y $and$ls180.v:6253$1816_Y
   end
-  attribute \src "ls180.v:6153.44-6153.97"
-  cell $and $and$ls180.v:6153$1748
+  attribute \src "ls180.v:6255.44-6255.97"
+  cell $and $and$ls180.v:6255$1817
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243454,43 +244330,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6153$1748_Y
+    connect \Y $and$ls180.v:6255$1817_Y
   end
-  attribute \src "ls180.v:6153.43-6153.148"
-  cell $and $and$ls180.v:6153$1750
+  attribute \src "ls180.v:6255.43-6255.148"
+  cell $and $and$ls180.v:6255$1819
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6153$1748_Y
-    connect \B $eq$ls180.v:6153$1749_Y
-    connect \Y $and$ls180.v:6153$1750_Y
+    connect \A $and$ls180.v:6255$1817_Y
+    connect \B $eq$ls180.v:6255$1818_Y
+    connect \Y $and$ls180.v:6255$1819_Y
   end
-  attribute \src "ls180.v:6154.44-6154.100"
-  cell $and $and$ls180.v:6154$1752
+  attribute \src "ls180.v:6256.44-6256.100"
+  cell $and $and$ls180.v:6256$1821
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6154$1751_Y
-    connect \Y $and$ls180.v:6154$1752_Y
+    connect \B $not$ls180.v:6256$1820_Y
+    connect \Y $and$ls180.v:6256$1821_Y
   end
-  attribute \src "ls180.v:6154.43-6154.151"
-  cell $and $and$ls180.v:6154$1754
+  attribute \src "ls180.v:6256.43-6256.151"
+  cell $and $and$ls180.v:6256$1823
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6154$1752_Y
-    connect \B $eq$ls180.v:6154$1753_Y
-    connect \Y $and$ls180.v:6154$1754_Y
+    connect \A $and$ls180.v:6256$1821_Y
+    connect \B $eq$ls180.v:6256$1822_Y
+    connect \Y $and$ls180.v:6256$1823_Y
   end
-  attribute \src "ls180.v:6156.44-6156.97"
-  cell $and $and$ls180.v:6156$1755
+  attribute \src "ls180.v:6258.44-6258.97"
+  cell $and $and$ls180.v:6258$1824
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243498,43 +244374,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6156$1755_Y
+    connect \Y $and$ls180.v:6258$1824_Y
   end
-  attribute \src "ls180.v:6156.43-6156.148"
-  cell $and $and$ls180.v:6156$1757
+  attribute \src "ls180.v:6258.43-6258.148"
+  cell $and $and$ls180.v:6258$1826
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6156$1755_Y
-    connect \B $eq$ls180.v:6156$1756_Y
-    connect \Y $and$ls180.v:6156$1757_Y
+    connect \A $and$ls180.v:6258$1824_Y
+    connect \B $eq$ls180.v:6258$1825_Y
+    connect \Y $and$ls180.v:6258$1826_Y
   end
-  attribute \src "ls180.v:6157.44-6157.100"
-  cell $and $and$ls180.v:6157$1759
+  attribute \src "ls180.v:6259.44-6259.100"
+  cell $and $and$ls180.v:6259$1828
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6157$1758_Y
-    connect \Y $and$ls180.v:6157$1759_Y
+    connect \B $not$ls180.v:6259$1827_Y
+    connect \Y $and$ls180.v:6259$1828_Y
   end
-  attribute \src "ls180.v:6157.43-6157.151"
-  cell $and $and$ls180.v:6157$1761
+  attribute \src "ls180.v:6259.43-6259.151"
+  cell $and $and$ls180.v:6259$1830
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6157$1759_Y
-    connect \B $eq$ls180.v:6157$1760_Y
-    connect \Y $and$ls180.v:6157$1761_Y
+    connect \A $and$ls180.v:6259$1828_Y
+    connect \B $eq$ls180.v:6259$1829_Y
+    connect \Y $and$ls180.v:6259$1830_Y
   end
-  attribute \src "ls180.v:6159.41-6159.94"
-  cell $and $and$ls180.v:6159$1762
+  attribute \src "ls180.v:6261.41-6261.94"
+  cell $and $and$ls180.v:6261$1831
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243542,43 +244418,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6159$1762_Y
+    connect \Y $and$ls180.v:6261$1831_Y
   end
-  attribute \src "ls180.v:6159.40-6159.145"
-  cell $and $and$ls180.v:6159$1764
+  attribute \src "ls180.v:6261.40-6261.145"
+  cell $and $and$ls180.v:6261$1833
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6159$1762_Y
-    connect \B $eq$ls180.v:6159$1763_Y
-    connect \Y $and$ls180.v:6159$1764_Y
+    connect \A $and$ls180.v:6261$1831_Y
+    connect \B $eq$ls180.v:6261$1832_Y
+    connect \Y $and$ls180.v:6261$1833_Y
   end
-  attribute \src "ls180.v:6160.41-6160.97"
-  cell $and $and$ls180.v:6160$1766
+  attribute \src "ls180.v:6262.41-6262.97"
+  cell $and $and$ls180.v:6262$1835
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6160$1765_Y
-    connect \Y $and$ls180.v:6160$1766_Y
+    connect \B $not$ls180.v:6262$1834_Y
+    connect \Y $and$ls180.v:6262$1835_Y
   end
-  attribute \src "ls180.v:6160.40-6160.148"
-  cell $and $and$ls180.v:6160$1768
+  attribute \src "ls180.v:6262.40-6262.148"
+  cell $and $and$ls180.v:6262$1837
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6160$1766_Y
-    connect \B $eq$ls180.v:6160$1767_Y
-    connect \Y $and$ls180.v:6160$1768_Y
+    connect \A $and$ls180.v:6262$1835_Y
+    connect \B $eq$ls180.v:6262$1836_Y
+    connect \Y $and$ls180.v:6262$1837_Y
   end
-  attribute \src "ls180.v:6162.42-6162.95"
-  cell $and $and$ls180.v:6162$1769
+  attribute \src "ls180.v:6264.42-6264.95"
+  cell $and $and$ls180.v:6264$1838
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243586,43 +244462,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6162$1769_Y
+    connect \Y $and$ls180.v:6264$1838_Y
   end
-  attribute \src "ls180.v:6162.41-6162.146"
-  cell $and $and$ls180.v:6162$1771
+  attribute \src "ls180.v:6264.41-6264.146"
+  cell $and $and$ls180.v:6264$1840
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6162$1769_Y
-    connect \B $eq$ls180.v:6162$1770_Y
-    connect \Y $and$ls180.v:6162$1771_Y
+    connect \A $and$ls180.v:6264$1838_Y
+    connect \B $eq$ls180.v:6264$1839_Y
+    connect \Y $and$ls180.v:6264$1840_Y
   end
-  attribute \src "ls180.v:6163.42-6163.98"
-  cell $and $and$ls180.v:6163$1773
+  attribute \src "ls180.v:6265.42-6265.98"
+  cell $and $and$ls180.v:6265$1842
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6163$1772_Y
-    connect \Y $and$ls180.v:6163$1773_Y
+    connect \B $not$ls180.v:6265$1841_Y
+    connect \Y $and$ls180.v:6265$1842_Y
   end
-  attribute \src "ls180.v:6163.41-6163.149"
-  cell $and $and$ls180.v:6163$1775
+  attribute \src "ls180.v:6265.41-6265.149"
+  cell $and $and$ls180.v:6265$1844
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6163$1773_Y
-    connect \B $eq$ls180.v:6163$1774_Y
-    connect \Y $and$ls180.v:6163$1775_Y
+    connect \A $and$ls180.v:6265$1842_Y
+    connect \B $eq$ls180.v:6265$1843_Y
+    connect \Y $and$ls180.v:6265$1844_Y
   end
-  attribute \src "ls180.v:6165.44-6165.97"
-  cell $and $and$ls180.v:6165$1776
+  attribute \src "ls180.v:6267.44-6267.97"
+  cell $and $and$ls180.v:6267$1845
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243630,43 +244506,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6165$1776_Y
+    connect \Y $and$ls180.v:6267$1845_Y
   end
-  attribute \src "ls180.v:6165.43-6165.148"
-  cell $and $and$ls180.v:6165$1778
+  attribute \src "ls180.v:6267.43-6267.148"
+  cell $and $and$ls180.v:6267$1847
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6165$1776_Y
-    connect \B $eq$ls180.v:6165$1777_Y
-    connect \Y $and$ls180.v:6165$1778_Y
+    connect \A $and$ls180.v:6267$1845_Y
+    connect \B $eq$ls180.v:6267$1846_Y
+    connect \Y $and$ls180.v:6267$1847_Y
   end
-  attribute \src "ls180.v:6166.44-6166.100"
-  cell $and $and$ls180.v:6166$1780
+  attribute \src "ls180.v:6268.44-6268.100"
+  cell $and $and$ls180.v:6268$1849
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6166$1779_Y
-    connect \Y $and$ls180.v:6166$1780_Y
+    connect \B $not$ls180.v:6268$1848_Y
+    connect \Y $and$ls180.v:6268$1849_Y
   end
-  attribute \src "ls180.v:6166.43-6166.151"
-  cell $and $and$ls180.v:6166$1782
+  attribute \src "ls180.v:6268.43-6268.151"
+  cell $and $and$ls180.v:6268$1851
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6166$1780_Y
-    connect \B $eq$ls180.v:6166$1781_Y
-    connect \Y $and$ls180.v:6166$1782_Y
+    connect \A $and$ls180.v:6268$1849_Y
+    connect \B $eq$ls180.v:6268$1850_Y
+    connect \Y $and$ls180.v:6268$1851_Y
   end
-  attribute \src "ls180.v:6168.44-6168.97"
-  cell $and $and$ls180.v:6168$1783
+  attribute \src "ls180.v:6270.44-6270.97"
+  cell $and $and$ls180.v:6270$1852
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243674,43 +244550,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6168$1783_Y
+    connect \Y $and$ls180.v:6270$1852_Y
   end
-  attribute \src "ls180.v:6168.43-6168.148"
-  cell $and $and$ls180.v:6168$1785
+  attribute \src "ls180.v:6270.43-6270.148"
+  cell $and $and$ls180.v:6270$1854
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6168$1783_Y
-    connect \B $eq$ls180.v:6168$1784_Y
-    connect \Y $and$ls180.v:6168$1785_Y
+    connect \A $and$ls180.v:6270$1852_Y
+    connect \B $eq$ls180.v:6270$1853_Y
+    connect \Y $and$ls180.v:6270$1854_Y
   end
-  attribute \src "ls180.v:6169.44-6169.100"
-  cell $and $and$ls180.v:6169$1787
+  attribute \src "ls180.v:6271.44-6271.100"
+  cell $and $and$ls180.v:6271$1856
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6169$1786_Y
-    connect \Y $and$ls180.v:6169$1787_Y
+    connect \B $not$ls180.v:6271$1855_Y
+    connect \Y $and$ls180.v:6271$1856_Y
   end
-  attribute \src "ls180.v:6169.43-6169.151"
-  cell $and $and$ls180.v:6169$1789
+  attribute \src "ls180.v:6271.43-6271.151"
+  cell $and $and$ls180.v:6271$1858
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6169$1787_Y
-    connect \B $eq$ls180.v:6169$1788_Y
-    connect \Y $and$ls180.v:6169$1789_Y
+    connect \A $and$ls180.v:6271$1856_Y
+    connect \B $eq$ls180.v:6271$1857_Y
+    connect \Y $and$ls180.v:6271$1858_Y
   end
-  attribute \src "ls180.v:6171.44-6171.97"
-  cell $and $and$ls180.v:6171$1790
+  attribute \src "ls180.v:6273.44-6273.97"
+  cell $and $and$ls180.v:6273$1859
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243718,43 +244594,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6171$1790_Y
+    connect \Y $and$ls180.v:6273$1859_Y
   end
-  attribute \src "ls180.v:6171.43-6171.148"
-  cell $and $and$ls180.v:6171$1792
+  attribute \src "ls180.v:6273.43-6273.148"
+  cell $and $and$ls180.v:6273$1861
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6171$1790_Y
-    connect \B $eq$ls180.v:6171$1791_Y
-    connect \Y $and$ls180.v:6171$1792_Y
+    connect \A $and$ls180.v:6273$1859_Y
+    connect \B $eq$ls180.v:6273$1860_Y
+    connect \Y $and$ls180.v:6273$1861_Y
   end
-  attribute \src "ls180.v:6172.44-6172.100"
-  cell $and $and$ls180.v:6172$1794
+  attribute \src "ls180.v:6274.44-6274.100"
+  cell $and $and$ls180.v:6274$1863
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6172$1793_Y
-    connect \Y $and$ls180.v:6172$1794_Y
+    connect \B $not$ls180.v:6274$1862_Y
+    connect \Y $and$ls180.v:6274$1863_Y
   end
-  attribute \src "ls180.v:6172.43-6172.151"
-  cell $and $and$ls180.v:6172$1796
+  attribute \src "ls180.v:6274.43-6274.151"
+  cell $and $and$ls180.v:6274$1865
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6172$1794_Y
-    connect \B $eq$ls180.v:6172$1795_Y
-    connect \Y $and$ls180.v:6172$1796_Y
+    connect \A $and$ls180.v:6274$1863_Y
+    connect \B $eq$ls180.v:6274$1864_Y
+    connect \Y $and$ls180.v:6274$1865_Y
   end
-  attribute \src "ls180.v:6174.44-6174.97"
-  cell $and $and$ls180.v:6174$1797
+  attribute \src "ls180.v:6276.44-6276.97"
+  cell $and $and$ls180.v:6276$1866
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243762,43 +244638,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
     connect \B \builder_interface7_bank_bus_we
-    connect \Y $and$ls180.v:6174$1797_Y
+    connect \Y $and$ls180.v:6276$1866_Y
   end
-  attribute \src "ls180.v:6174.43-6174.148"
-  cell $and $and$ls180.v:6174$1799
+  attribute \src "ls180.v:6276.43-6276.148"
+  cell $and $and$ls180.v:6276$1868
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6174$1797_Y
-    connect \B $eq$ls180.v:6174$1798_Y
-    connect \Y $and$ls180.v:6174$1799_Y
+    connect \A $and$ls180.v:6276$1866_Y
+    connect \B $eq$ls180.v:6276$1867_Y
+    connect \Y $and$ls180.v:6276$1868_Y
   end
-  attribute \src "ls180.v:6175.44-6175.100"
-  cell $and $and$ls180.v:6175$1801
+  attribute \src "ls180.v:6277.44-6277.100"
+  cell $and $and$ls180.v:6277$1870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank7_sel
-    connect \B $not$ls180.v:6175$1800_Y
-    connect \Y $and$ls180.v:6175$1801_Y
+    connect \B $not$ls180.v:6277$1869_Y
+    connect \Y $and$ls180.v:6277$1870_Y
   end
-  attribute \src "ls180.v:6175.43-6175.151"
-  cell $and $and$ls180.v:6175$1803
+  attribute \src "ls180.v:6277.43-6277.151"
+  cell $and $and$ls180.v:6277$1872
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6175$1801_Y
-    connect \B $eq$ls180.v:6175$1802_Y
-    connect \Y $and$ls180.v:6175$1803_Y
+    connect \A $and$ls180.v:6277$1870_Y
+    connect \B $eq$ls180.v:6277$1871_Y
+    connect \Y $and$ls180.v:6277$1872_Y
   end
-  attribute \src "ls180.v:6199.44-6199.97"
-  cell $and $and$ls180.v:6199$1805
+  attribute \src "ls180.v:6301.44-6301.97"
+  cell $and $and$ls180.v:6301$1874
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243806,43 +244682,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
     connect \B \builder_interface8_bank_bus_we
-    connect \Y $and$ls180.v:6199$1805_Y
+    connect \Y $and$ls180.v:6301$1874_Y
   end
-  attribute \src "ls180.v:6199.43-6199.147"
-  cell $and $and$ls180.v:6199$1807
+  attribute \src "ls180.v:6301.43-6301.147"
+  cell $and $and$ls180.v:6301$1876
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6199$1805_Y
-    connect \B $eq$ls180.v:6199$1806_Y
-    connect \Y $and$ls180.v:6199$1807_Y
+    connect \A $and$ls180.v:6301$1874_Y
+    connect \B $eq$ls180.v:6301$1875_Y
+    connect \Y $and$ls180.v:6301$1876_Y
   end
-  attribute \src "ls180.v:6200.44-6200.100"
-  cell $and $and$ls180.v:6200$1809
+  attribute \src "ls180.v:6302.44-6302.100"
+  cell $and $and$ls180.v:6302$1878
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
-    connect \B $not$ls180.v:6200$1808_Y
-    connect \Y $and$ls180.v:6200$1809_Y
+    connect \B $not$ls180.v:6302$1877_Y
+    connect \Y $and$ls180.v:6302$1878_Y
   end
-  attribute \src "ls180.v:6200.43-6200.150"
-  cell $and $and$ls180.v:6200$1811
+  attribute \src "ls180.v:6302.43-6302.150"
+  cell $and $and$ls180.v:6302$1880
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6200$1809_Y
-    connect \B $eq$ls180.v:6200$1810_Y
-    connect \Y $and$ls180.v:6200$1811_Y
+    connect \A $and$ls180.v:6302$1878_Y
+    connect \B $eq$ls180.v:6302$1879_Y
+    connect \Y $and$ls180.v:6302$1880_Y
   end
-  attribute \src "ls180.v:6202.49-6202.102"
-  cell $and $and$ls180.v:6202$1812
+  attribute \src "ls180.v:6304.49-6304.102"
+  cell $and $and$ls180.v:6304$1881
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243850,43 +244726,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
     connect \B \builder_interface8_bank_bus_we
-    connect \Y $and$ls180.v:6202$1812_Y
+    connect \Y $and$ls180.v:6304$1881_Y
   end
-  attribute \src "ls180.v:6202.48-6202.152"
-  cell $and $and$ls180.v:6202$1814
+  attribute \src "ls180.v:6304.48-6304.152"
+  cell $and $and$ls180.v:6304$1883
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6202$1812_Y
-    connect \B $eq$ls180.v:6202$1813_Y
-    connect \Y $and$ls180.v:6202$1814_Y
+    connect \A $and$ls180.v:6304$1881_Y
+    connect \B $eq$ls180.v:6304$1882_Y
+    connect \Y $and$ls180.v:6304$1883_Y
   end
-  attribute \src "ls180.v:6203.49-6203.105"
-  cell $and $and$ls180.v:6203$1816
+  attribute \src "ls180.v:6305.49-6305.105"
+  cell $and $and$ls180.v:6305$1885
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
-    connect \B $not$ls180.v:6203$1815_Y
-    connect \Y $and$ls180.v:6203$1816_Y
+    connect \B $not$ls180.v:6305$1884_Y
+    connect \Y $and$ls180.v:6305$1885_Y
   end
-  attribute \src "ls180.v:6203.48-6203.155"
-  cell $and $and$ls180.v:6203$1818
+  attribute \src "ls180.v:6305.48-6305.155"
+  cell $and $and$ls180.v:6305$1887
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6203$1816_Y
-    connect \B $eq$ls180.v:6203$1817_Y
-    connect \Y $and$ls180.v:6203$1818_Y
+    connect \A $and$ls180.v:6305$1885_Y
+    connect \B $eq$ls180.v:6305$1886_Y
+    connect \Y $and$ls180.v:6305$1887_Y
   end
-  attribute \src "ls180.v:6205.49-6205.102"
-  cell $and $and$ls180.v:6205$1819
+  attribute \src "ls180.v:6307.49-6307.102"
+  cell $and $and$ls180.v:6307$1888
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243894,43 +244770,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
     connect \B \builder_interface8_bank_bus_we
-    connect \Y $and$ls180.v:6205$1819_Y
+    connect \Y $and$ls180.v:6307$1888_Y
   end
-  attribute \src "ls180.v:6205.48-6205.152"
-  cell $and $and$ls180.v:6205$1821
+  attribute \src "ls180.v:6307.48-6307.152"
+  cell $and $and$ls180.v:6307$1890
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6205$1819_Y
-    connect \B $eq$ls180.v:6205$1820_Y
-    connect \Y $and$ls180.v:6205$1821_Y
+    connect \A $and$ls180.v:6307$1888_Y
+    connect \B $eq$ls180.v:6307$1889_Y
+    connect \Y $and$ls180.v:6307$1890_Y
   end
-  attribute \src "ls180.v:6206.49-6206.105"
-  cell $and $and$ls180.v:6206$1823
+  attribute \src "ls180.v:6308.49-6308.105"
+  cell $and $and$ls180.v:6308$1892
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
-    connect \B $not$ls180.v:6206$1822_Y
-    connect \Y $and$ls180.v:6206$1823_Y
+    connect \B $not$ls180.v:6308$1891_Y
+    connect \Y $and$ls180.v:6308$1892_Y
   end
-  attribute \src "ls180.v:6206.48-6206.155"
-  cell $and $and$ls180.v:6206$1825
+  attribute \src "ls180.v:6308.48-6308.155"
+  cell $and $and$ls180.v:6308$1894
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6206$1823_Y
-    connect \B $eq$ls180.v:6206$1824_Y
-    connect \Y $and$ls180.v:6206$1825_Y
+    connect \A $and$ls180.v:6308$1892_Y
+    connect \B $eq$ls180.v:6308$1893_Y
+    connect \Y $and$ls180.v:6308$1894_Y
   end
-  attribute \src "ls180.v:6208.42-6208.95"
-  cell $and $and$ls180.v:6208$1826
+  attribute \src "ls180.v:6310.42-6310.95"
+  cell $and $and$ls180.v:6310$1895
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243938,43 +244814,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
     connect \B \builder_interface8_bank_bus_we
-    connect \Y $and$ls180.v:6208$1826_Y
+    connect \Y $and$ls180.v:6310$1895_Y
   end
-  attribute \src "ls180.v:6208.41-6208.145"
-  cell $and $and$ls180.v:6208$1828
+  attribute \src "ls180.v:6310.41-6310.145"
+  cell $and $and$ls180.v:6310$1897
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6208$1826_Y
-    connect \B $eq$ls180.v:6208$1827_Y
-    connect \Y $and$ls180.v:6208$1828_Y
+    connect \A $and$ls180.v:6310$1895_Y
+    connect \B $eq$ls180.v:6310$1896_Y
+    connect \Y $and$ls180.v:6310$1897_Y
   end
-  attribute \src "ls180.v:6209.42-6209.98"
-  cell $and $and$ls180.v:6209$1830
+  attribute \src "ls180.v:6311.42-6311.98"
+  cell $and $and$ls180.v:6311$1899
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank8_sel
-    connect \B $not$ls180.v:6209$1829_Y
-    connect \Y $and$ls180.v:6209$1830_Y
+    connect \B $not$ls180.v:6311$1898_Y
+    connect \Y $and$ls180.v:6311$1899_Y
   end
-  attribute \src "ls180.v:6209.41-6209.148"
-  cell $and $and$ls180.v:6209$1832
+  attribute \src "ls180.v:6311.41-6311.148"
+  cell $and $and$ls180.v:6311$1901
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6209$1830_Y
-    connect \B $eq$ls180.v:6209$1831_Y
-    connect \Y $and$ls180.v:6209$1832_Y
+    connect \A $and$ls180.v:6311$1899_Y
+    connect \B $eq$ls180.v:6311$1900_Y
+    connect \Y $and$ls180.v:6311$1901_Y
   end
-  attribute \src "ls180.v:6216.46-6216.99"
-  cell $and $and$ls180.v:6216$1834
+  attribute \src "ls180.v:6318.46-6318.99"
+  cell $and $and$ls180.v:6318$1903
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -243982,43 +244858,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6216$1834_Y
+    connect \Y $and$ls180.v:6318$1903_Y
   end
-  attribute \src "ls180.v:6216.45-6216.149"
-  cell $and $and$ls180.v:6216$1836
+  attribute \src "ls180.v:6318.45-6318.149"
+  cell $and $and$ls180.v:6318$1905
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6216$1834_Y
-    connect \B $eq$ls180.v:6216$1835_Y
-    connect \Y $and$ls180.v:6216$1836_Y
+    connect \A $and$ls180.v:6318$1903_Y
+    connect \B $eq$ls180.v:6318$1904_Y
+    connect \Y $and$ls180.v:6318$1905_Y
   end
-  attribute \src "ls180.v:6217.46-6217.102"
-  cell $and $and$ls180.v:6217$1838
+  attribute \src "ls180.v:6319.46-6319.102"
+  cell $and $and$ls180.v:6319$1907
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6217$1837_Y
-    connect \Y $and$ls180.v:6217$1838_Y
+    connect \B $not$ls180.v:6319$1906_Y
+    connect \Y $and$ls180.v:6319$1907_Y
   end
-  attribute \src "ls180.v:6217.45-6217.152"
-  cell $and $and$ls180.v:6217$1840
+  attribute \src "ls180.v:6319.45-6319.152"
+  cell $and $and$ls180.v:6319$1909
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6217$1838_Y
-    connect \B $eq$ls180.v:6217$1839_Y
-    connect \Y $and$ls180.v:6217$1840_Y
+    connect \A $and$ls180.v:6319$1907_Y
+    connect \B $eq$ls180.v:6319$1908_Y
+    connect \Y $and$ls180.v:6319$1909_Y
   end
-  attribute \src "ls180.v:6219.50-6219.103"
-  cell $and $and$ls180.v:6219$1841
+  attribute \src "ls180.v:6321.50-6321.103"
+  cell $and $and$ls180.v:6321$1910
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244026,43 +244902,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6219$1841_Y
+    connect \Y $and$ls180.v:6321$1910_Y
   end
-  attribute \src "ls180.v:6219.49-6219.153"
-  cell $and $and$ls180.v:6219$1843
+  attribute \src "ls180.v:6321.49-6321.153"
+  cell $and $and$ls180.v:6321$1912
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6219$1841_Y
-    connect \B $eq$ls180.v:6219$1842_Y
-    connect \Y $and$ls180.v:6219$1843_Y
+    connect \A $and$ls180.v:6321$1910_Y
+    connect \B $eq$ls180.v:6321$1911_Y
+    connect \Y $and$ls180.v:6321$1912_Y
   end
-  attribute \src "ls180.v:6220.50-6220.106"
-  cell $and $and$ls180.v:6220$1845
+  attribute \src "ls180.v:6322.50-6322.106"
+  cell $and $and$ls180.v:6322$1914
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6220$1844_Y
-    connect \Y $and$ls180.v:6220$1845_Y
+    connect \B $not$ls180.v:6322$1913_Y
+    connect \Y $and$ls180.v:6322$1914_Y
   end
-  attribute \src "ls180.v:6220.49-6220.156"
-  cell $and $and$ls180.v:6220$1847
+  attribute \src "ls180.v:6322.49-6322.156"
+  cell $and $and$ls180.v:6322$1916
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6220$1845_Y
-    connect \B $eq$ls180.v:6220$1846_Y
-    connect \Y $and$ls180.v:6220$1847_Y
+    connect \A $and$ls180.v:6322$1914_Y
+    connect \B $eq$ls180.v:6322$1915_Y
+    connect \Y $and$ls180.v:6322$1916_Y
   end
-  attribute \src "ls180.v:6222.40-6222.93"
-  cell $and $and$ls180.v:6222$1848
+  attribute \src "ls180.v:6324.40-6324.93"
+  cell $and $and$ls180.v:6324$1917
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244070,43 +244946,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6222$1848_Y
+    connect \Y $and$ls180.v:6324$1917_Y
   end
-  attribute \src "ls180.v:6222.39-6222.143"
-  cell $and $and$ls180.v:6222$1850
+  attribute \src "ls180.v:6324.39-6324.143"
+  cell $and $and$ls180.v:6324$1919
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6222$1848_Y
-    connect \B $eq$ls180.v:6222$1849_Y
-    connect \Y $and$ls180.v:6222$1850_Y
+    connect \A $and$ls180.v:6324$1917_Y
+    connect \B $eq$ls180.v:6324$1918_Y
+    connect \Y $and$ls180.v:6324$1919_Y
   end
-  attribute \src "ls180.v:6223.40-6223.96"
-  cell $and $and$ls180.v:6223$1852
+  attribute \src "ls180.v:6325.40-6325.96"
+  cell $and $and$ls180.v:6325$1921
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6223$1851_Y
-    connect \Y $and$ls180.v:6223$1852_Y
+    connect \B $not$ls180.v:6325$1920_Y
+    connect \Y $and$ls180.v:6325$1921_Y
   end
-  attribute \src "ls180.v:6223.39-6223.146"
-  cell $and $and$ls180.v:6223$1854
+  attribute \src "ls180.v:6325.39-6325.146"
+  cell $and $and$ls180.v:6325$1923
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6223$1852_Y
-    connect \B $eq$ls180.v:6223$1853_Y
-    connect \Y $and$ls180.v:6223$1854_Y
+    connect \A $and$ls180.v:6325$1921_Y
+    connect \B $eq$ls180.v:6325$1922_Y
+    connect \Y $and$ls180.v:6325$1923_Y
   end
-  attribute \src "ls180.v:6225.50-6225.103"
-  cell $and $and$ls180.v:6225$1855
+  attribute \src "ls180.v:6327.50-6327.103"
+  cell $and $and$ls180.v:6327$1924
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244114,43 +244990,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6225$1855_Y
+    connect \Y $and$ls180.v:6327$1924_Y
   end
-  attribute \src "ls180.v:6225.49-6225.153"
-  cell $and $and$ls180.v:6225$1857
+  attribute \src "ls180.v:6327.49-6327.153"
+  cell $and $and$ls180.v:6327$1926
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6225$1855_Y
-    connect \B $eq$ls180.v:6225$1856_Y
-    connect \Y $and$ls180.v:6225$1857_Y
+    connect \A $and$ls180.v:6327$1924_Y
+    connect \B $eq$ls180.v:6327$1925_Y
+    connect \Y $and$ls180.v:6327$1926_Y
   end
-  attribute \src "ls180.v:6226.50-6226.106"
-  cell $and $and$ls180.v:6226$1859
+  attribute \src "ls180.v:6328.50-6328.106"
+  cell $and $and$ls180.v:6328$1928
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6226$1858_Y
-    connect \Y $and$ls180.v:6226$1859_Y
+    connect \B $not$ls180.v:6328$1927_Y
+    connect \Y $and$ls180.v:6328$1928_Y
   end
-  attribute \src "ls180.v:6226.49-6226.156"
-  cell $and $and$ls180.v:6226$1861
+  attribute \src "ls180.v:6328.49-6328.156"
+  cell $and $and$ls180.v:6328$1930
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6226$1859_Y
-    connect \B $eq$ls180.v:6226$1860_Y
-    connect \Y $and$ls180.v:6226$1861_Y
+    connect \A $and$ls180.v:6328$1928_Y
+    connect \B $eq$ls180.v:6328$1929_Y
+    connect \Y $and$ls180.v:6328$1930_Y
   end
-  attribute \src "ls180.v:6228.50-6228.103"
-  cell $and $and$ls180.v:6228$1862
+  attribute \src "ls180.v:6330.50-6330.103"
+  cell $and $and$ls180.v:6330$1931
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244158,43 +245034,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6228$1862_Y
+    connect \Y $and$ls180.v:6330$1931_Y
   end
-  attribute \src "ls180.v:6228.49-6228.153"
-  cell $and $and$ls180.v:6228$1864
+  attribute \src "ls180.v:6330.49-6330.153"
+  cell $and $and$ls180.v:6330$1933
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6228$1862_Y
-    connect \B $eq$ls180.v:6228$1863_Y
-    connect \Y $and$ls180.v:6228$1864_Y
+    connect \A $and$ls180.v:6330$1931_Y
+    connect \B $eq$ls180.v:6330$1932_Y
+    connect \Y $and$ls180.v:6330$1933_Y
   end
-  attribute \src "ls180.v:6229.50-6229.106"
-  cell $and $and$ls180.v:6229$1866
+  attribute \src "ls180.v:6331.50-6331.106"
+  cell $and $and$ls180.v:6331$1935
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6229$1865_Y
-    connect \Y $and$ls180.v:6229$1866_Y
+    connect \B $not$ls180.v:6331$1934_Y
+    connect \Y $and$ls180.v:6331$1935_Y
   end
-  attribute \src "ls180.v:6229.49-6229.156"
-  cell $and $and$ls180.v:6229$1868
+  attribute \src "ls180.v:6331.49-6331.156"
+  cell $and $and$ls180.v:6331$1937
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6229$1866_Y
-    connect \B $eq$ls180.v:6229$1867_Y
-    connect \Y $and$ls180.v:6229$1868_Y
+    connect \A $and$ls180.v:6331$1935_Y
+    connect \B $eq$ls180.v:6331$1936_Y
+    connect \Y $and$ls180.v:6331$1937_Y
   end
-  attribute \src "ls180.v:6231.51-6231.104"
-  cell $and $and$ls180.v:6231$1869
+  attribute \src "ls180.v:6333.51-6333.104"
+  cell $and $and$ls180.v:6333$1938
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244202,43 +245078,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6231$1869_Y
+    connect \Y $and$ls180.v:6333$1938_Y
   end
-  attribute \src "ls180.v:6231.50-6231.154"
-  cell $and $and$ls180.v:6231$1871
+  attribute \src "ls180.v:6333.50-6333.154"
+  cell $and $and$ls180.v:6333$1940
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6231$1869_Y
-    connect \B $eq$ls180.v:6231$1870_Y
-    connect \Y $and$ls180.v:6231$1871_Y
+    connect \A $and$ls180.v:6333$1938_Y
+    connect \B $eq$ls180.v:6333$1939_Y
+    connect \Y $and$ls180.v:6333$1940_Y
   end
-  attribute \src "ls180.v:6232.51-6232.107"
-  cell $and $and$ls180.v:6232$1873
+  attribute \src "ls180.v:6334.51-6334.107"
+  cell $and $and$ls180.v:6334$1942
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6232$1872_Y
-    connect \Y $and$ls180.v:6232$1873_Y
+    connect \B $not$ls180.v:6334$1941_Y
+    connect \Y $and$ls180.v:6334$1942_Y
   end
-  attribute \src "ls180.v:6232.50-6232.157"
-  cell $and $and$ls180.v:6232$1875
+  attribute \src "ls180.v:6334.50-6334.157"
+  cell $and $and$ls180.v:6334$1944
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6232$1873_Y
-    connect \B $eq$ls180.v:6232$1874_Y
-    connect \Y $and$ls180.v:6232$1875_Y
+    connect \A $and$ls180.v:6334$1942_Y
+    connect \B $eq$ls180.v:6334$1943_Y
+    connect \Y $and$ls180.v:6334$1944_Y
   end
-  attribute \src "ls180.v:6234.49-6234.102"
-  cell $and $and$ls180.v:6234$1876
+  attribute \src "ls180.v:6336.49-6336.102"
+  cell $and $and$ls180.v:6336$1945
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244246,43 +245122,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6234$1876_Y
+    connect \Y $and$ls180.v:6336$1945_Y
   end
-  attribute \src "ls180.v:6234.48-6234.152"
-  cell $and $and$ls180.v:6234$1878
+  attribute \src "ls180.v:6336.48-6336.152"
+  cell $and $and$ls180.v:6336$1947
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6234$1876_Y
-    connect \B $eq$ls180.v:6234$1877_Y
-    connect \Y $and$ls180.v:6234$1878_Y
+    connect \A $and$ls180.v:6336$1945_Y
+    connect \B $eq$ls180.v:6336$1946_Y
+    connect \Y $and$ls180.v:6336$1947_Y
   end
-  attribute \src "ls180.v:6235.49-6235.105"
-  cell $and $and$ls180.v:6235$1880
+  attribute \src "ls180.v:6337.49-6337.105"
+  cell $and $and$ls180.v:6337$1949
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6235$1879_Y
-    connect \Y $and$ls180.v:6235$1880_Y
+    connect \B $not$ls180.v:6337$1948_Y
+    connect \Y $and$ls180.v:6337$1949_Y
   end
-  attribute \src "ls180.v:6235.48-6235.155"
-  cell $and $and$ls180.v:6235$1882
+  attribute \src "ls180.v:6337.48-6337.155"
+  cell $and $and$ls180.v:6337$1951
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6235$1880_Y
-    connect \B $eq$ls180.v:6235$1881_Y
-    connect \Y $and$ls180.v:6235$1882_Y
+    connect \A $and$ls180.v:6337$1949_Y
+    connect \B $eq$ls180.v:6337$1950_Y
+    connect \Y $and$ls180.v:6337$1951_Y
   end
-  attribute \src "ls180.v:6237.49-6237.102"
-  cell $and $and$ls180.v:6237$1883
+  attribute \src "ls180.v:6339.49-6339.102"
+  cell $and $and$ls180.v:6339$1952
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244290,43 +245166,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6237$1883_Y
+    connect \Y $and$ls180.v:6339$1952_Y
   end
-  attribute \src "ls180.v:6237.48-6237.152"
-  cell $and $and$ls180.v:6237$1885
+  attribute \src "ls180.v:6339.48-6339.152"
+  cell $and $and$ls180.v:6339$1954
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6237$1883_Y
-    connect \B $eq$ls180.v:6237$1884_Y
-    connect \Y $and$ls180.v:6237$1885_Y
+    connect \A $and$ls180.v:6339$1952_Y
+    connect \B $eq$ls180.v:6339$1953_Y
+    connect \Y $and$ls180.v:6339$1954_Y
   end
-  attribute \src "ls180.v:6238.49-6238.105"
-  cell $and $and$ls180.v:6238$1887
+  attribute \src "ls180.v:6340.49-6340.105"
+  cell $and $and$ls180.v:6340$1956
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6238$1886_Y
-    connect \Y $and$ls180.v:6238$1887_Y
+    connect \B $not$ls180.v:6340$1955_Y
+    connect \Y $and$ls180.v:6340$1956_Y
   end
-  attribute \src "ls180.v:6238.48-6238.155"
-  cell $and $and$ls180.v:6238$1889
+  attribute \src "ls180.v:6340.48-6340.155"
+  cell $and $and$ls180.v:6340$1958
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6238$1887_Y
-    connect \B $eq$ls180.v:6238$1888_Y
-    connect \Y $and$ls180.v:6238$1889_Y
+    connect \A $and$ls180.v:6340$1956_Y
+    connect \B $eq$ls180.v:6340$1957_Y
+    connect \Y $and$ls180.v:6340$1958_Y
   end
-  attribute \src "ls180.v:6240.49-6240.102"
-  cell $and $and$ls180.v:6240$1890
+  attribute \src "ls180.v:6342.49-6342.102"
+  cell $and $and$ls180.v:6342$1959
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244334,43 +245210,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6240$1890_Y
+    connect \Y $and$ls180.v:6342$1959_Y
   end
-  attribute \src "ls180.v:6240.48-6240.152"
-  cell $and $and$ls180.v:6240$1892
+  attribute \src "ls180.v:6342.48-6342.152"
+  cell $and $and$ls180.v:6342$1961
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6240$1890_Y
-    connect \B $eq$ls180.v:6240$1891_Y
-    connect \Y $and$ls180.v:6240$1892_Y
+    connect \A $and$ls180.v:6342$1959_Y
+    connect \B $eq$ls180.v:6342$1960_Y
+    connect \Y $and$ls180.v:6342$1961_Y
   end
-  attribute \src "ls180.v:6241.49-6241.105"
-  cell $and $and$ls180.v:6241$1894
+  attribute \src "ls180.v:6343.49-6343.105"
+  cell $and $and$ls180.v:6343$1963
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6241$1893_Y
-    connect \Y $and$ls180.v:6241$1894_Y
+    connect \B $not$ls180.v:6343$1962_Y
+    connect \Y $and$ls180.v:6343$1963_Y
   end
-  attribute \src "ls180.v:6241.48-6241.155"
-  cell $and $and$ls180.v:6241$1896
+  attribute \src "ls180.v:6343.48-6343.155"
+  cell $and $and$ls180.v:6343$1965
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6241$1894_Y
-    connect \B $eq$ls180.v:6241$1895_Y
-    connect \Y $and$ls180.v:6241$1896_Y
+    connect \A $and$ls180.v:6343$1963_Y
+    connect \B $eq$ls180.v:6343$1964_Y
+    connect \Y $and$ls180.v:6343$1965_Y
   end
-  attribute \src "ls180.v:6243.49-6243.102"
-  cell $and $and$ls180.v:6243$1897
+  attribute \src "ls180.v:6345.49-6345.102"
+  cell $and $and$ls180.v:6345$1966
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244378,43 +245254,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
     connect \B \builder_interface9_bank_bus_we
-    connect \Y $and$ls180.v:6243$1897_Y
+    connect \Y $and$ls180.v:6345$1966_Y
   end
-  attribute \src "ls180.v:6243.48-6243.152"
-  cell $and $and$ls180.v:6243$1899
+  attribute \src "ls180.v:6345.48-6345.152"
+  cell $and $and$ls180.v:6345$1968
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6243$1897_Y
-    connect \B $eq$ls180.v:6243$1898_Y
-    connect \Y $and$ls180.v:6243$1899_Y
+    connect \A $and$ls180.v:6345$1966_Y
+    connect \B $eq$ls180.v:6345$1967_Y
+    connect \Y $and$ls180.v:6345$1968_Y
   end
-  attribute \src "ls180.v:6244.49-6244.105"
-  cell $and $and$ls180.v:6244$1901
+  attribute \src "ls180.v:6346.49-6346.105"
+  cell $and $and$ls180.v:6346$1970
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank9_sel
-    connect \B $not$ls180.v:6244$1900_Y
-    connect \Y $and$ls180.v:6244$1901_Y
+    connect \B $not$ls180.v:6346$1969_Y
+    connect \Y $and$ls180.v:6346$1970_Y
   end
-  attribute \src "ls180.v:6244.48-6244.155"
-  cell $and $and$ls180.v:6244$1903
+  attribute \src "ls180.v:6346.48-6346.155"
+  cell $and $and$ls180.v:6346$1972
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6244$1901_Y
-    connect \B $eq$ls180.v:6244$1902_Y
-    connect \Y $and$ls180.v:6244$1903_Y
+    connect \A $and$ls180.v:6346$1970_Y
+    connect \B $eq$ls180.v:6346$1971_Y
+    connect \Y $and$ls180.v:6346$1972_Y
   end
-  attribute \src "ls180.v:6261.42-6261.97"
-  cell $and $and$ls180.v:6261$1905
+  attribute \src "ls180.v:6363.42-6363.97"
+  cell $and $and$ls180.v:6363$1974
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244422,43 +245298,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6261$1905_Y
+    connect \Y $and$ls180.v:6363$1974_Y
   end
-  attribute \src "ls180.v:6261.41-6261.148"
-  cell $and $and$ls180.v:6261$1907
+  attribute \src "ls180.v:6363.41-6363.148"
+  cell $and $and$ls180.v:6363$1976
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6261$1905_Y
-    connect \B $eq$ls180.v:6261$1906_Y
-    connect \Y $and$ls180.v:6261$1907_Y
+    connect \A $and$ls180.v:6363$1974_Y
+    connect \B $eq$ls180.v:6363$1975_Y
+    connect \Y $and$ls180.v:6363$1976_Y
   end
-  attribute \src "ls180.v:6262.42-6262.100"
-  cell $and $and$ls180.v:6262$1909
+  attribute \src "ls180.v:6364.42-6364.100"
+  cell $and $and$ls180.v:6364$1978
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6262$1908_Y
-    connect \Y $and$ls180.v:6262$1909_Y
+    connect \B $not$ls180.v:6364$1977_Y
+    connect \Y $and$ls180.v:6364$1978_Y
   end
-  attribute \src "ls180.v:6262.41-6262.151"
-  cell $and $and$ls180.v:6262$1911
+  attribute \src "ls180.v:6364.41-6364.151"
+  cell $and $and$ls180.v:6364$1980
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6262$1909_Y
-    connect \B $eq$ls180.v:6262$1910_Y
-    connect \Y $and$ls180.v:6262$1911_Y
+    connect \A $and$ls180.v:6364$1978_Y
+    connect \B $eq$ls180.v:6364$1979_Y
+    connect \Y $and$ls180.v:6364$1980_Y
   end
-  attribute \src "ls180.v:6264.42-6264.97"
-  cell $and $and$ls180.v:6264$1912
+  attribute \src "ls180.v:6366.42-6366.97"
+  cell $and $and$ls180.v:6366$1981
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244466,43 +245342,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6264$1912_Y
+    connect \Y $and$ls180.v:6366$1981_Y
   end
-  attribute \src "ls180.v:6264.41-6264.148"
-  cell $and $and$ls180.v:6264$1914
+  attribute \src "ls180.v:6366.41-6366.148"
+  cell $and $and$ls180.v:6366$1983
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6264$1912_Y
-    connect \B $eq$ls180.v:6264$1913_Y
-    connect \Y $and$ls180.v:6264$1914_Y
+    connect \A $and$ls180.v:6366$1981_Y
+    connect \B $eq$ls180.v:6366$1982_Y
+    connect \Y $and$ls180.v:6366$1983_Y
   end
-  attribute \src "ls180.v:6265.42-6265.100"
-  cell $and $and$ls180.v:6265$1916
+  attribute \src "ls180.v:6367.42-6367.100"
+  cell $and $and$ls180.v:6367$1985
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6265$1915_Y
-    connect \Y $and$ls180.v:6265$1916_Y
+    connect \B $not$ls180.v:6367$1984_Y
+    connect \Y $and$ls180.v:6367$1985_Y
   end
-  attribute \src "ls180.v:6265.41-6265.151"
-  cell $and $and$ls180.v:6265$1918
+  attribute \src "ls180.v:6367.41-6367.151"
+  cell $and $and$ls180.v:6367$1987
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6265$1916_Y
-    connect \B $eq$ls180.v:6265$1917_Y
-    connect \Y $and$ls180.v:6265$1918_Y
+    connect \A $and$ls180.v:6367$1985_Y
+    connect \B $eq$ls180.v:6367$1986_Y
+    connect \Y $and$ls180.v:6367$1987_Y
   end
-  attribute \src "ls180.v:6267.40-6267.95"
-  cell $and $and$ls180.v:6267$1919
+  attribute \src "ls180.v:6369.40-6369.95"
+  cell $and $and$ls180.v:6369$1988
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244510,43 +245386,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6267$1919_Y
+    connect \Y $and$ls180.v:6369$1988_Y
   end
-  attribute \src "ls180.v:6267.39-6267.146"
-  cell $and $and$ls180.v:6267$1921
+  attribute \src "ls180.v:6369.39-6369.146"
+  cell $and $and$ls180.v:6369$1990
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6267$1919_Y
-    connect \B $eq$ls180.v:6267$1920_Y
-    connect \Y $and$ls180.v:6267$1921_Y
+    connect \A $and$ls180.v:6369$1988_Y
+    connect \B $eq$ls180.v:6369$1989_Y
+    connect \Y $and$ls180.v:6369$1990_Y
   end
-  attribute \src "ls180.v:6268.40-6268.98"
-  cell $and $and$ls180.v:6268$1923
+  attribute \src "ls180.v:6370.40-6370.98"
+  cell $and $and$ls180.v:6370$1992
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6268$1922_Y
-    connect \Y $and$ls180.v:6268$1923_Y
+    connect \B $not$ls180.v:6370$1991_Y
+    connect \Y $and$ls180.v:6370$1992_Y
   end
-  attribute \src "ls180.v:6268.39-6268.149"
-  cell $and $and$ls180.v:6268$1925
+  attribute \src "ls180.v:6370.39-6370.149"
+  cell $and $and$ls180.v:6370$1994
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6268$1923_Y
-    connect \B $eq$ls180.v:6268$1924_Y
-    connect \Y $and$ls180.v:6268$1925_Y
+    connect \A $and$ls180.v:6370$1992_Y
+    connect \B $eq$ls180.v:6370$1993_Y
+    connect \Y $and$ls180.v:6370$1994_Y
   end
-  attribute \src "ls180.v:6270.39-6270.94"
-  cell $and $and$ls180.v:6270$1926
+  attribute \src "ls180.v:6372.39-6372.94"
+  cell $and $and$ls180.v:6372$1995
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244554,43 +245430,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6270$1926_Y
+    connect \Y $and$ls180.v:6372$1995_Y
   end
-  attribute \src "ls180.v:6270.38-6270.145"
-  cell $and $and$ls180.v:6270$1928
+  attribute \src "ls180.v:6372.38-6372.145"
+  cell $and $and$ls180.v:6372$1997
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6270$1926_Y
-    connect \B $eq$ls180.v:6270$1927_Y
-    connect \Y $and$ls180.v:6270$1928_Y
+    connect \A $and$ls180.v:6372$1995_Y
+    connect \B $eq$ls180.v:6372$1996_Y
+    connect \Y $and$ls180.v:6372$1997_Y
   end
-  attribute \src "ls180.v:6271.39-6271.97"
-  cell $and $and$ls180.v:6271$1930
+  attribute \src "ls180.v:6373.39-6373.97"
+  cell $and $and$ls180.v:6373$1999
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6271$1929_Y
-    connect \Y $and$ls180.v:6271$1930_Y
+    connect \B $not$ls180.v:6373$1998_Y
+    connect \Y $and$ls180.v:6373$1999_Y
   end
-  attribute \src "ls180.v:6271.38-6271.148"
-  cell $and $and$ls180.v:6271$1932
+  attribute \src "ls180.v:6373.38-6373.148"
+  cell $and $and$ls180.v:6373$2001
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6271$1930_Y
-    connect \B $eq$ls180.v:6271$1931_Y
-    connect \Y $and$ls180.v:6271$1932_Y
+    connect \A $and$ls180.v:6373$1999_Y
+    connect \B $eq$ls180.v:6373$2000_Y
+    connect \Y $and$ls180.v:6373$2001_Y
   end
-  attribute \src "ls180.v:6273.38-6273.93"
-  cell $and $and$ls180.v:6273$1933
+  attribute \src "ls180.v:6375.38-6375.93"
+  cell $and $and$ls180.v:6375$2002
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244598,43 +245474,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6273$1933_Y
+    connect \Y $and$ls180.v:6375$2002_Y
   end
-  attribute \src "ls180.v:6273.37-6273.144"
-  cell $and $and$ls180.v:6273$1935
+  attribute \src "ls180.v:6375.37-6375.144"
+  cell $and $and$ls180.v:6375$2004
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6273$1933_Y
-    connect \B $eq$ls180.v:6273$1934_Y
-    connect \Y $and$ls180.v:6273$1935_Y
+    connect \A $and$ls180.v:6375$2002_Y
+    connect \B $eq$ls180.v:6375$2003_Y
+    connect \Y $and$ls180.v:6375$2004_Y
   end
-  attribute \src "ls180.v:6274.38-6274.96"
-  cell $and $and$ls180.v:6274$1937
+  attribute \src "ls180.v:6376.38-6376.96"
+  cell $and $and$ls180.v:6376$2006
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6274$1936_Y
-    connect \Y $and$ls180.v:6274$1937_Y
+    connect \B $not$ls180.v:6376$2005_Y
+    connect \Y $and$ls180.v:6376$2006_Y
   end
-  attribute \src "ls180.v:6274.37-6274.147"
-  cell $and $and$ls180.v:6274$1939
+  attribute \src "ls180.v:6376.37-6376.147"
+  cell $and $and$ls180.v:6376$2008
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6274$1937_Y
-    connect \B $eq$ls180.v:6274$1938_Y
-    connect \Y $and$ls180.v:6274$1939_Y
+    connect \A $and$ls180.v:6376$2006_Y
+    connect \B $eq$ls180.v:6376$2007_Y
+    connect \Y $and$ls180.v:6376$2008_Y
   end
-  attribute \src "ls180.v:6276.37-6276.92"
-  cell $and $and$ls180.v:6276$1940
+  attribute \src "ls180.v:6378.37-6378.92"
+  cell $and $and$ls180.v:6378$2009
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244642,43 +245518,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6276$1940_Y
+    connect \Y $and$ls180.v:6378$2009_Y
   end
-  attribute \src "ls180.v:6276.36-6276.143"
-  cell $and $and$ls180.v:6276$1942
+  attribute \src "ls180.v:6378.36-6378.143"
+  cell $and $and$ls180.v:6378$2011
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6276$1940_Y
-    connect \B $eq$ls180.v:6276$1941_Y
-    connect \Y $and$ls180.v:6276$1942_Y
+    connect \A $and$ls180.v:6378$2009_Y
+    connect \B $eq$ls180.v:6378$2010_Y
+    connect \Y $and$ls180.v:6378$2011_Y
   end
-  attribute \src "ls180.v:6277.37-6277.95"
-  cell $and $and$ls180.v:6277$1944
+  attribute \src "ls180.v:6379.37-6379.95"
+  cell $and $and$ls180.v:6379$2013
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6277$1943_Y
-    connect \Y $and$ls180.v:6277$1944_Y
+    connect \B $not$ls180.v:6379$2012_Y
+    connect \Y $and$ls180.v:6379$2013_Y
   end
-  attribute \src "ls180.v:6277.36-6277.146"
-  cell $and $and$ls180.v:6277$1946
+  attribute \src "ls180.v:6379.36-6379.146"
+  cell $and $and$ls180.v:6379$2015
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6277$1944_Y
-    connect \B $eq$ls180.v:6277$1945_Y
-    connect \Y $and$ls180.v:6277$1946_Y
+    connect \A $and$ls180.v:6379$2013_Y
+    connect \B $eq$ls180.v:6379$2014_Y
+    connect \Y $and$ls180.v:6379$2015_Y
   end
-  attribute \src "ls180.v:6279.43-6279.98"
-  cell $and $and$ls180.v:6279$1947
+  attribute \src "ls180.v:6381.43-6381.98"
+  cell $and $and$ls180.v:6381$2016
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244686,43 +245562,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
     connect \B \builder_interface10_bank_bus_we
-    connect \Y $and$ls180.v:6279$1947_Y
+    connect \Y $and$ls180.v:6381$2016_Y
   end
-  attribute \src "ls180.v:6279.42-6279.149"
-  cell $and $and$ls180.v:6279$1949
+  attribute \src "ls180.v:6381.42-6381.149"
+  cell $and $and$ls180.v:6381$2018
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6279$1947_Y
-    connect \B $eq$ls180.v:6279$1948_Y
-    connect \Y $and$ls180.v:6279$1949_Y
+    connect \A $and$ls180.v:6381$2016_Y
+    connect \B $eq$ls180.v:6381$2017_Y
+    connect \Y $and$ls180.v:6381$2018_Y
   end
-  attribute \src "ls180.v:6280.43-6280.101"
-  cell $and $and$ls180.v:6280$1951
+  attribute \src "ls180.v:6382.43-6382.101"
+  cell $and $and$ls180.v:6382$2020
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank10_sel
-    connect \B $not$ls180.v:6280$1950_Y
-    connect \Y $and$ls180.v:6280$1951_Y
+    connect \B $not$ls180.v:6382$2019_Y
+    connect \Y $and$ls180.v:6382$2020_Y
   end
-  attribute \src "ls180.v:6280.42-6280.152"
-  cell $and $and$ls180.v:6280$1953
+  attribute \src "ls180.v:6382.42-6382.152"
+  cell $and $and$ls180.v:6382$2022
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6280$1951_Y
-    connect \B $eq$ls180.v:6280$1952_Y
-    connect \Y $and$ls180.v:6280$1953_Y
+    connect \A $and$ls180.v:6382$2020_Y
+    connect \B $eq$ls180.v:6382$2021_Y
+    connect \Y $and$ls180.v:6382$2022_Y
   end
-  attribute \src "ls180.v:6301.42-6301.97"
-  cell $and $and$ls180.v:6301$1956
+  attribute \src "ls180.v:6403.42-6403.97"
+  cell $and $and$ls180.v:6403$2025
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244730,43 +245606,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6301$1956_Y
+    connect \Y $and$ls180.v:6403$2025_Y
   end
-  attribute \src "ls180.v:6301.41-6301.148"
-  cell $and $and$ls180.v:6301$1958
+  attribute \src "ls180.v:6403.41-6403.148"
+  cell $and $and$ls180.v:6403$2027
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6301$1956_Y
-    connect \B $eq$ls180.v:6301$1957_Y
-    connect \Y $and$ls180.v:6301$1958_Y
+    connect \A $and$ls180.v:6403$2025_Y
+    connect \B $eq$ls180.v:6403$2026_Y
+    connect \Y $and$ls180.v:6403$2027_Y
   end
-  attribute \src "ls180.v:6302.42-6302.100"
-  cell $and $and$ls180.v:6302$1960
+  attribute \src "ls180.v:6404.42-6404.100"
+  cell $and $and$ls180.v:6404$2029
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6302$1959_Y
-    connect \Y $and$ls180.v:6302$1960_Y
+    connect \B $not$ls180.v:6404$2028_Y
+    connect \Y $and$ls180.v:6404$2029_Y
   end
-  attribute \src "ls180.v:6302.41-6302.151"
-  cell $and $and$ls180.v:6302$1962
+  attribute \src "ls180.v:6404.41-6404.151"
+  cell $and $and$ls180.v:6404$2031
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6302$1960_Y
-    connect \B $eq$ls180.v:6302$1961_Y
-    connect \Y $and$ls180.v:6302$1962_Y
+    connect \A $and$ls180.v:6404$2029_Y
+    connect \B $eq$ls180.v:6404$2030_Y
+    connect \Y $and$ls180.v:6404$2031_Y
   end
-  attribute \src "ls180.v:6304.42-6304.97"
-  cell $and $and$ls180.v:6304$1963
+  attribute \src "ls180.v:6406.42-6406.97"
+  cell $and $and$ls180.v:6406$2032
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244774,43 +245650,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6304$1963_Y
+    connect \Y $and$ls180.v:6406$2032_Y
   end
-  attribute \src "ls180.v:6304.41-6304.148"
-  cell $and $and$ls180.v:6304$1965
+  attribute \src "ls180.v:6406.41-6406.148"
+  cell $and $and$ls180.v:6406$2034
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6304$1963_Y
-    connect \B $eq$ls180.v:6304$1964_Y
-    connect \Y $and$ls180.v:6304$1965_Y
+    connect \A $and$ls180.v:6406$2032_Y
+    connect \B $eq$ls180.v:6406$2033_Y
+    connect \Y $and$ls180.v:6406$2034_Y
   end
-  attribute \src "ls180.v:6305.42-6305.100"
-  cell $and $and$ls180.v:6305$1967
+  attribute \src "ls180.v:6407.42-6407.100"
+  cell $and $and$ls180.v:6407$2036
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6305$1966_Y
-    connect \Y $and$ls180.v:6305$1967_Y
+    connect \B $not$ls180.v:6407$2035_Y
+    connect \Y $and$ls180.v:6407$2036_Y
   end
-  attribute \src "ls180.v:6305.41-6305.151"
-  cell $and $and$ls180.v:6305$1969
+  attribute \src "ls180.v:6407.41-6407.151"
+  cell $and $and$ls180.v:6407$2038
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6305$1967_Y
-    connect \B $eq$ls180.v:6305$1968_Y
-    connect \Y $and$ls180.v:6305$1969_Y
+    connect \A $and$ls180.v:6407$2036_Y
+    connect \B $eq$ls180.v:6407$2037_Y
+    connect \Y $and$ls180.v:6407$2038_Y
   end
-  attribute \src "ls180.v:6307.40-6307.95"
-  cell $and $and$ls180.v:6307$1970
+  attribute \src "ls180.v:6409.40-6409.95"
+  cell $and $and$ls180.v:6409$2039
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244818,43 +245694,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6307$1970_Y
+    connect \Y $and$ls180.v:6409$2039_Y
   end
-  attribute \src "ls180.v:6307.39-6307.146"
-  cell $and $and$ls180.v:6307$1972
+  attribute \src "ls180.v:6409.39-6409.146"
+  cell $and $and$ls180.v:6409$2041
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6307$1970_Y
-    connect \B $eq$ls180.v:6307$1971_Y
-    connect \Y $and$ls180.v:6307$1972_Y
+    connect \A $and$ls180.v:6409$2039_Y
+    connect \B $eq$ls180.v:6409$2040_Y
+    connect \Y $and$ls180.v:6409$2041_Y
   end
-  attribute \src "ls180.v:6308.40-6308.98"
-  cell $and $and$ls180.v:6308$1974
+  attribute \src "ls180.v:6410.40-6410.98"
+  cell $and $and$ls180.v:6410$2043
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6308$1973_Y
-    connect \Y $and$ls180.v:6308$1974_Y
+    connect \B $not$ls180.v:6410$2042_Y
+    connect \Y $and$ls180.v:6410$2043_Y
   end
-  attribute \src "ls180.v:6308.39-6308.149"
-  cell $and $and$ls180.v:6308$1976
+  attribute \src "ls180.v:6410.39-6410.149"
+  cell $and $and$ls180.v:6410$2045
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6308$1974_Y
-    connect \B $eq$ls180.v:6308$1975_Y
-    connect \Y $and$ls180.v:6308$1976_Y
+    connect \A $and$ls180.v:6410$2043_Y
+    connect \B $eq$ls180.v:6410$2044_Y
+    connect \Y $and$ls180.v:6410$2045_Y
   end
-  attribute \src "ls180.v:6310.39-6310.94"
-  cell $and $and$ls180.v:6310$1977
+  attribute \src "ls180.v:6412.39-6412.94"
+  cell $and $and$ls180.v:6412$2046
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244862,43 +245738,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6310$1977_Y
+    connect \Y $and$ls180.v:6412$2046_Y
   end
-  attribute \src "ls180.v:6310.38-6310.145"
-  cell $and $and$ls180.v:6310$1979
+  attribute \src "ls180.v:6412.38-6412.145"
+  cell $and $and$ls180.v:6412$2048
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6310$1977_Y
-    connect \B $eq$ls180.v:6310$1978_Y
-    connect \Y $and$ls180.v:6310$1979_Y
+    connect \A $and$ls180.v:6412$2046_Y
+    connect \B $eq$ls180.v:6412$2047_Y
+    connect \Y $and$ls180.v:6412$2048_Y
   end
-  attribute \src "ls180.v:6311.39-6311.97"
-  cell $and $and$ls180.v:6311$1981
+  attribute \src "ls180.v:6413.39-6413.97"
+  cell $and $and$ls180.v:6413$2050
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6311$1980_Y
-    connect \Y $and$ls180.v:6311$1981_Y
+    connect \B $not$ls180.v:6413$2049_Y
+    connect \Y $and$ls180.v:6413$2050_Y
   end
-  attribute \src "ls180.v:6311.38-6311.148"
-  cell $and $and$ls180.v:6311$1983
+  attribute \src "ls180.v:6413.38-6413.148"
+  cell $and $and$ls180.v:6413$2052
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6311$1981_Y
-    connect \B $eq$ls180.v:6311$1982_Y
-    connect \Y $and$ls180.v:6311$1983_Y
+    connect \A $and$ls180.v:6413$2050_Y
+    connect \B $eq$ls180.v:6413$2051_Y
+    connect \Y $and$ls180.v:6413$2052_Y
   end
-  attribute \src "ls180.v:6313.38-6313.93"
-  cell $and $and$ls180.v:6313$1984
+  attribute \src "ls180.v:6415.38-6415.93"
+  cell $and $and$ls180.v:6415$2053
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244906,43 +245782,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6313$1984_Y
+    connect \Y $and$ls180.v:6415$2053_Y
   end
-  attribute \src "ls180.v:6313.37-6313.144"
-  cell $and $and$ls180.v:6313$1986
+  attribute \src "ls180.v:6415.37-6415.144"
+  cell $and $and$ls180.v:6415$2055
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6313$1984_Y
-    connect \B $eq$ls180.v:6313$1985_Y
-    connect \Y $and$ls180.v:6313$1986_Y
+    connect \A $and$ls180.v:6415$2053_Y
+    connect \B $eq$ls180.v:6415$2054_Y
+    connect \Y $and$ls180.v:6415$2055_Y
   end
-  attribute \src "ls180.v:6314.38-6314.96"
-  cell $and $and$ls180.v:6314$1988
+  attribute \src "ls180.v:6416.38-6416.96"
+  cell $and $and$ls180.v:6416$2057
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6314$1987_Y
-    connect \Y $and$ls180.v:6314$1988_Y
+    connect \B $not$ls180.v:6416$2056_Y
+    connect \Y $and$ls180.v:6416$2057_Y
   end
-  attribute \src "ls180.v:6314.37-6314.147"
-  cell $and $and$ls180.v:6314$1990
+  attribute \src "ls180.v:6416.37-6416.147"
+  cell $and $and$ls180.v:6416$2059
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6314$1988_Y
-    connect \B $eq$ls180.v:6314$1989_Y
-    connect \Y $and$ls180.v:6314$1990_Y
+    connect \A $and$ls180.v:6416$2057_Y
+    connect \B $eq$ls180.v:6416$2058_Y
+    connect \Y $and$ls180.v:6416$2059_Y
   end
-  attribute \src "ls180.v:6316.37-6316.92"
-  cell $and $and$ls180.v:6316$1991
+  attribute \src "ls180.v:6418.37-6418.92"
+  cell $and $and$ls180.v:6418$2060
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244950,43 +245826,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6316$1991_Y
+    connect \Y $and$ls180.v:6418$2060_Y
   end
-  attribute \src "ls180.v:6316.36-6316.143"
-  cell $and $and$ls180.v:6316$1993
+  attribute \src "ls180.v:6418.36-6418.143"
+  cell $and $and$ls180.v:6418$2062
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6316$1991_Y
-    connect \B $eq$ls180.v:6316$1992_Y
-    connect \Y $and$ls180.v:6316$1993_Y
+    connect \A $and$ls180.v:6418$2060_Y
+    connect \B $eq$ls180.v:6418$2061_Y
+    connect \Y $and$ls180.v:6418$2062_Y
   end
-  attribute \src "ls180.v:6317.37-6317.95"
-  cell $and $and$ls180.v:6317$1995
+  attribute \src "ls180.v:6419.37-6419.95"
+  cell $and $and$ls180.v:6419$2064
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6317$1994_Y
-    connect \Y $and$ls180.v:6317$1995_Y
+    connect \B $not$ls180.v:6419$2063_Y
+    connect \Y $and$ls180.v:6419$2064_Y
   end
-  attribute \src "ls180.v:6317.36-6317.146"
-  cell $and $and$ls180.v:6317$1997
+  attribute \src "ls180.v:6419.36-6419.146"
+  cell $and $and$ls180.v:6419$2066
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6317$1995_Y
-    connect \B $eq$ls180.v:6317$1996_Y
-    connect \Y $and$ls180.v:6317$1997_Y
+    connect \A $and$ls180.v:6419$2064_Y
+    connect \B $eq$ls180.v:6419$2065_Y
+    connect \Y $and$ls180.v:6419$2066_Y
   end
-  attribute \src "ls180.v:6319.43-6319.98"
-  cell $and $and$ls180.v:6319$1998
+  attribute \src "ls180.v:6421.43-6421.98"
+  cell $and $and$ls180.v:6421$2067
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -244994,43 +245870,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6319$1998_Y
+    connect \Y $and$ls180.v:6421$2067_Y
   end
-  attribute \src "ls180.v:6319.42-6319.149"
-  cell $and $and$ls180.v:6319$2000
+  attribute \src "ls180.v:6421.42-6421.149"
+  cell $and $and$ls180.v:6421$2069
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6319$1998_Y
-    connect \B $eq$ls180.v:6319$1999_Y
-    connect \Y $and$ls180.v:6319$2000_Y
+    connect \A $and$ls180.v:6421$2067_Y
+    connect \B $eq$ls180.v:6421$2068_Y
+    connect \Y $and$ls180.v:6421$2069_Y
   end
-  attribute \src "ls180.v:6320.43-6320.101"
-  cell $and $and$ls180.v:6320$2002
+  attribute \src "ls180.v:6422.43-6422.101"
+  cell $and $and$ls180.v:6422$2071
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6320$2001_Y
-    connect \Y $and$ls180.v:6320$2002_Y
+    connect \B $not$ls180.v:6422$2070_Y
+    connect \Y $and$ls180.v:6422$2071_Y
   end
-  attribute \src "ls180.v:6320.42-6320.152"
-  cell $and $and$ls180.v:6320$2004
+  attribute \src "ls180.v:6422.42-6422.152"
+  cell $and $and$ls180.v:6422$2073
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6320$2002_Y
-    connect \B $eq$ls180.v:6320$2003_Y
-    connect \Y $and$ls180.v:6320$2004_Y
+    connect \A $and$ls180.v:6422$2071_Y
+    connect \B $eq$ls180.v:6422$2072_Y
+    connect \Y $and$ls180.v:6422$2073_Y
   end
-  attribute \src "ls180.v:6322.46-6322.101"
-  cell $and $and$ls180.v:6322$2005
+  attribute \src "ls180.v:6424.46-6424.101"
+  cell $and $and$ls180.v:6424$2074
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245038,43 +245914,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6322$2005_Y
+    connect \Y $and$ls180.v:6424$2074_Y
   end
-  attribute \src "ls180.v:6322.45-6322.152"
-  cell $and $and$ls180.v:6322$2007
+  attribute \src "ls180.v:6424.45-6424.152"
+  cell $and $and$ls180.v:6424$2076
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6322$2005_Y
-    connect \B $eq$ls180.v:6322$2006_Y
-    connect \Y $and$ls180.v:6322$2007_Y
+    connect \A $and$ls180.v:6424$2074_Y
+    connect \B $eq$ls180.v:6424$2075_Y
+    connect \Y $and$ls180.v:6424$2076_Y
   end
-  attribute \src "ls180.v:6323.46-6323.104"
-  cell $and $and$ls180.v:6323$2009
+  attribute \src "ls180.v:6425.46-6425.104"
+  cell $and $and$ls180.v:6425$2078
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6323$2008_Y
-    connect \Y $and$ls180.v:6323$2009_Y
+    connect \B $not$ls180.v:6425$2077_Y
+    connect \Y $and$ls180.v:6425$2078_Y
   end
-  attribute \src "ls180.v:6323.45-6323.155"
-  cell $and $and$ls180.v:6323$2011
+  attribute \src "ls180.v:6425.45-6425.155"
+  cell $and $and$ls180.v:6425$2080
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6323$2009_Y
-    connect \B $eq$ls180.v:6323$2010_Y
-    connect \Y $and$ls180.v:6323$2011_Y
+    connect \A $and$ls180.v:6425$2078_Y
+    connect \B $eq$ls180.v:6425$2079_Y
+    connect \Y $and$ls180.v:6425$2080_Y
   end
-  attribute \src "ls180.v:6325.46-6325.101"
-  cell $and $and$ls180.v:6325$2012
+  attribute \src "ls180.v:6427.46-6427.101"
+  cell $and $and$ls180.v:6427$2081
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245082,43 +245958,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
     connect \B \builder_interface11_bank_bus_we
-    connect \Y $and$ls180.v:6325$2012_Y
+    connect \Y $and$ls180.v:6427$2081_Y
   end
-  attribute \src "ls180.v:6325.45-6325.152"
-  cell $and $and$ls180.v:6325$2014
+  attribute \src "ls180.v:6427.45-6427.152"
+  cell $and $and$ls180.v:6427$2083
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6325$2012_Y
-    connect \B $eq$ls180.v:6325$2013_Y
-    connect \Y $and$ls180.v:6325$2014_Y
+    connect \A $and$ls180.v:6427$2081_Y
+    connect \B $eq$ls180.v:6427$2082_Y
+    connect \Y $and$ls180.v:6427$2083_Y
   end
-  attribute \src "ls180.v:6326.46-6326.104"
-  cell $and $and$ls180.v:6326$2016
+  attribute \src "ls180.v:6428.46-6428.104"
+  cell $and $and$ls180.v:6428$2085
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank11_sel
-    connect \B $not$ls180.v:6326$2015_Y
-    connect \Y $and$ls180.v:6326$2016_Y
+    connect \B $not$ls180.v:6428$2084_Y
+    connect \Y $and$ls180.v:6428$2085_Y
   end
-  attribute \src "ls180.v:6326.45-6326.155"
-  cell $and $and$ls180.v:6326$2018
+  attribute \src "ls180.v:6428.45-6428.155"
+  cell $and $and$ls180.v:6428$2087
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6326$2016_Y
-    connect \B $eq$ls180.v:6326$2017_Y
-    connect \Y $and$ls180.v:6326$2018_Y
+    connect \A $and$ls180.v:6428$2085_Y
+    connect \B $eq$ls180.v:6428$2086_Y
+    connect \Y $and$ls180.v:6428$2087_Y
   end
-  attribute \src "ls180.v:6349.39-6349.94"
-  cell $and $and$ls180.v:6349$2021
+  attribute \src "ls180.v:6451.39-6451.94"
+  cell $and $and$ls180.v:6451$2090
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245126,43 +246002,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6349$2021_Y
+    connect \Y $and$ls180.v:6451$2090_Y
   end
-  attribute \src "ls180.v:6349.38-6349.145"
-  cell $and $and$ls180.v:6349$2023
+  attribute \src "ls180.v:6451.38-6451.145"
+  cell $and $and$ls180.v:6451$2092
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6349$2021_Y
-    connect \B $eq$ls180.v:6349$2022_Y
-    connect \Y $and$ls180.v:6349$2023_Y
+    connect \A $and$ls180.v:6451$2090_Y
+    connect \B $eq$ls180.v:6451$2091_Y
+    connect \Y $and$ls180.v:6451$2092_Y
   end
-  attribute \src "ls180.v:6350.39-6350.97"
-  cell $and $and$ls180.v:6350$2025
+  attribute \src "ls180.v:6452.39-6452.97"
+  cell $and $and$ls180.v:6452$2094
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6350$2024_Y
-    connect \Y $and$ls180.v:6350$2025_Y
+    connect \B $not$ls180.v:6452$2093_Y
+    connect \Y $and$ls180.v:6452$2094_Y
   end
-  attribute \src "ls180.v:6350.38-6350.148"
-  cell $and $and$ls180.v:6350$2027
+  attribute \src "ls180.v:6452.38-6452.148"
+  cell $and $and$ls180.v:6452$2096
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6350$2025_Y
-    connect \B $eq$ls180.v:6350$2026_Y
-    connect \Y $and$ls180.v:6350$2027_Y
+    connect \A $and$ls180.v:6452$2094_Y
+    connect \B $eq$ls180.v:6452$2095_Y
+    connect \Y $and$ls180.v:6452$2096_Y
   end
-  attribute \src "ls180.v:6352.39-6352.94"
-  cell $and $and$ls180.v:6352$2028
+  attribute \src "ls180.v:6454.39-6454.94"
+  cell $and $and$ls180.v:6454$2097
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245170,43 +246046,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6352$2028_Y
+    connect \Y $and$ls180.v:6454$2097_Y
   end
-  attribute \src "ls180.v:6352.38-6352.145"
-  cell $and $and$ls180.v:6352$2030
+  attribute \src "ls180.v:6454.38-6454.145"
+  cell $and $and$ls180.v:6454$2099
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6352$2028_Y
-    connect \B $eq$ls180.v:6352$2029_Y
-    connect \Y $and$ls180.v:6352$2030_Y
+    connect \A $and$ls180.v:6454$2097_Y
+    connect \B $eq$ls180.v:6454$2098_Y
+    connect \Y $and$ls180.v:6454$2099_Y
   end
-  attribute \src "ls180.v:6353.39-6353.97"
-  cell $and $and$ls180.v:6353$2032
+  attribute \src "ls180.v:6455.39-6455.97"
+  cell $and $and$ls180.v:6455$2101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6353$2031_Y
-    connect \Y $and$ls180.v:6353$2032_Y
+    connect \B $not$ls180.v:6455$2100_Y
+    connect \Y $and$ls180.v:6455$2101_Y
   end
-  attribute \src "ls180.v:6353.38-6353.148"
-  cell $and $and$ls180.v:6353$2034
+  attribute \src "ls180.v:6455.38-6455.148"
+  cell $and $and$ls180.v:6455$2103
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6353$2032_Y
-    connect \B $eq$ls180.v:6353$2033_Y
-    connect \Y $and$ls180.v:6353$2034_Y
+    connect \A $and$ls180.v:6455$2101_Y
+    connect \B $eq$ls180.v:6455$2102_Y
+    connect \Y $and$ls180.v:6455$2103_Y
   end
-  attribute \src "ls180.v:6355.39-6355.94"
-  cell $and $and$ls180.v:6355$2035
+  attribute \src "ls180.v:6457.39-6457.94"
+  cell $and $and$ls180.v:6457$2104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245214,43 +246090,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6355$2035_Y
+    connect \Y $and$ls180.v:6457$2104_Y
   end
-  attribute \src "ls180.v:6355.38-6355.145"
-  cell $and $and$ls180.v:6355$2037
+  attribute \src "ls180.v:6457.38-6457.145"
+  cell $and $and$ls180.v:6457$2106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6355$2035_Y
-    connect \B $eq$ls180.v:6355$2036_Y
-    connect \Y $and$ls180.v:6355$2037_Y
+    connect \A $and$ls180.v:6457$2104_Y
+    connect \B $eq$ls180.v:6457$2105_Y
+    connect \Y $and$ls180.v:6457$2106_Y
   end
-  attribute \src "ls180.v:6356.39-6356.97"
-  cell $and $and$ls180.v:6356$2039
+  attribute \src "ls180.v:6458.39-6458.97"
+  cell $and $and$ls180.v:6458$2108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6356$2038_Y
-    connect \Y $and$ls180.v:6356$2039_Y
+    connect \B $not$ls180.v:6458$2107_Y
+    connect \Y $and$ls180.v:6458$2108_Y
   end
-  attribute \src "ls180.v:6356.38-6356.148"
-  cell $and $and$ls180.v:6356$2041
+  attribute \src "ls180.v:6458.38-6458.148"
+  cell $and $and$ls180.v:6458$2110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6356$2039_Y
-    connect \B $eq$ls180.v:6356$2040_Y
-    connect \Y $and$ls180.v:6356$2041_Y
+    connect \A $and$ls180.v:6458$2108_Y
+    connect \B $eq$ls180.v:6458$2109_Y
+    connect \Y $and$ls180.v:6458$2110_Y
   end
-  attribute \src "ls180.v:6358.39-6358.94"
-  cell $and $and$ls180.v:6358$2042
+  attribute \src "ls180.v:6460.39-6460.94"
+  cell $and $and$ls180.v:6460$2111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245258,43 +246134,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6358$2042_Y
+    connect \Y $and$ls180.v:6460$2111_Y
   end
-  attribute \src "ls180.v:6358.38-6358.145"
-  cell $and $and$ls180.v:6358$2044
+  attribute \src "ls180.v:6460.38-6460.145"
+  cell $and $and$ls180.v:6460$2113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6358$2042_Y
-    connect \B $eq$ls180.v:6358$2043_Y
-    connect \Y $and$ls180.v:6358$2044_Y
+    connect \A $and$ls180.v:6460$2111_Y
+    connect \B $eq$ls180.v:6460$2112_Y
+    connect \Y $and$ls180.v:6460$2113_Y
   end
-  attribute \src "ls180.v:6359.39-6359.97"
-  cell $and $and$ls180.v:6359$2046
+  attribute \src "ls180.v:6461.39-6461.97"
+  cell $and $and$ls180.v:6461$2115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6359$2045_Y
-    connect \Y $and$ls180.v:6359$2046_Y
+    connect \B $not$ls180.v:6461$2114_Y
+    connect \Y $and$ls180.v:6461$2115_Y
   end
-  attribute \src "ls180.v:6359.38-6359.148"
-  cell $and $and$ls180.v:6359$2048
+  attribute \src "ls180.v:6461.38-6461.148"
+  cell $and $and$ls180.v:6461$2117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6359$2046_Y
-    connect \B $eq$ls180.v:6359$2047_Y
-    connect \Y $and$ls180.v:6359$2048_Y
+    connect \A $and$ls180.v:6461$2115_Y
+    connect \B $eq$ls180.v:6461$2116_Y
+    connect \Y $and$ls180.v:6461$2117_Y
   end
-  attribute \src "ls180.v:6361.41-6361.96"
-  cell $and $and$ls180.v:6361$2049
+  attribute \src "ls180.v:6463.41-6463.96"
+  cell $and $and$ls180.v:6463$2118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245302,43 +246178,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6361$2049_Y
+    connect \Y $and$ls180.v:6463$2118_Y
   end
-  attribute \src "ls180.v:6361.40-6361.147"
-  cell $and $and$ls180.v:6361$2051
+  attribute \src "ls180.v:6463.40-6463.147"
+  cell $and $and$ls180.v:6463$2120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6361$2049_Y
-    connect \B $eq$ls180.v:6361$2050_Y
-    connect \Y $and$ls180.v:6361$2051_Y
+    connect \A $and$ls180.v:6463$2118_Y
+    connect \B $eq$ls180.v:6463$2119_Y
+    connect \Y $and$ls180.v:6463$2120_Y
   end
-  attribute \src "ls180.v:6362.41-6362.99"
-  cell $and $and$ls180.v:6362$2053
+  attribute \src "ls180.v:6464.41-6464.99"
+  cell $and $and$ls180.v:6464$2122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6362$2052_Y
-    connect \Y $and$ls180.v:6362$2053_Y
+    connect \B $not$ls180.v:6464$2121_Y
+    connect \Y $and$ls180.v:6464$2122_Y
   end
-  attribute \src "ls180.v:6362.40-6362.150"
-  cell $and $and$ls180.v:6362$2055
+  attribute \src "ls180.v:6464.40-6464.150"
+  cell $and $and$ls180.v:6464$2124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6362$2053_Y
-    connect \B $eq$ls180.v:6362$2054_Y
-    connect \Y $and$ls180.v:6362$2055_Y
+    connect \A $and$ls180.v:6464$2122_Y
+    connect \B $eq$ls180.v:6464$2123_Y
+    connect \Y $and$ls180.v:6464$2124_Y
   end
-  attribute \src "ls180.v:6364.41-6364.96"
-  cell $and $and$ls180.v:6364$2056
+  attribute \src "ls180.v:6466.41-6466.96"
+  cell $and $and$ls180.v:6466$2125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245346,43 +246222,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6364$2056_Y
+    connect \Y $and$ls180.v:6466$2125_Y
   end
-  attribute \src "ls180.v:6364.40-6364.147"
-  cell $and $and$ls180.v:6364$2058
+  attribute \src "ls180.v:6466.40-6466.147"
+  cell $and $and$ls180.v:6466$2127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6364$2056_Y
-    connect \B $eq$ls180.v:6364$2057_Y
-    connect \Y $and$ls180.v:6364$2058_Y
+    connect \A $and$ls180.v:6466$2125_Y
+    connect \B $eq$ls180.v:6466$2126_Y
+    connect \Y $and$ls180.v:6466$2127_Y
   end
-  attribute \src "ls180.v:6365.41-6365.99"
-  cell $and $and$ls180.v:6365$2060
+  attribute \src "ls180.v:6467.41-6467.99"
+  cell $and $and$ls180.v:6467$2129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6365$2059_Y
-    connect \Y $and$ls180.v:6365$2060_Y
+    connect \B $not$ls180.v:6467$2128_Y
+    connect \Y $and$ls180.v:6467$2129_Y
   end
-  attribute \src "ls180.v:6365.40-6365.150"
-  cell $and $and$ls180.v:6365$2062
+  attribute \src "ls180.v:6467.40-6467.150"
+  cell $and $and$ls180.v:6467$2131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6365$2060_Y
-    connect \B $eq$ls180.v:6365$2061_Y
-    connect \Y $and$ls180.v:6365$2062_Y
+    connect \A $and$ls180.v:6467$2129_Y
+    connect \B $eq$ls180.v:6467$2130_Y
+    connect \Y $and$ls180.v:6467$2131_Y
   end
-  attribute \src "ls180.v:6367.41-6367.96"
-  cell $and $and$ls180.v:6367$2063
+  attribute \src "ls180.v:6469.41-6469.96"
+  cell $and $and$ls180.v:6469$2132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245390,43 +246266,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6367$2063_Y
+    connect \Y $and$ls180.v:6469$2132_Y
   end
-  attribute \src "ls180.v:6367.40-6367.147"
-  cell $and $and$ls180.v:6367$2065
+  attribute \src "ls180.v:6469.40-6469.147"
+  cell $and $and$ls180.v:6469$2134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6367$2063_Y
-    connect \B $eq$ls180.v:6367$2064_Y
-    connect \Y $and$ls180.v:6367$2065_Y
+    connect \A $and$ls180.v:6469$2132_Y
+    connect \B $eq$ls180.v:6469$2133_Y
+    connect \Y $and$ls180.v:6469$2134_Y
   end
-  attribute \src "ls180.v:6368.41-6368.99"
-  cell $and $and$ls180.v:6368$2067
+  attribute \src "ls180.v:6470.41-6470.99"
+  cell $and $and$ls180.v:6470$2136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6368$2066_Y
-    connect \Y $and$ls180.v:6368$2067_Y
+    connect \B $not$ls180.v:6470$2135_Y
+    connect \Y $and$ls180.v:6470$2136_Y
   end
-  attribute \src "ls180.v:6368.40-6368.150"
-  cell $and $and$ls180.v:6368$2069
+  attribute \src "ls180.v:6470.40-6470.150"
+  cell $and $and$ls180.v:6470$2138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6368$2067_Y
-    connect \B $eq$ls180.v:6368$2068_Y
-    connect \Y $and$ls180.v:6368$2069_Y
+    connect \A $and$ls180.v:6470$2136_Y
+    connect \B $eq$ls180.v:6470$2137_Y
+    connect \Y $and$ls180.v:6470$2138_Y
   end
-  attribute \src "ls180.v:6370.41-6370.96"
-  cell $and $and$ls180.v:6370$2070
+  attribute \src "ls180.v:6472.41-6472.96"
+  cell $and $and$ls180.v:6472$2139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245434,43 +246310,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6370$2070_Y
+    connect \Y $and$ls180.v:6472$2139_Y
   end
-  attribute \src "ls180.v:6370.40-6370.147"
-  cell $and $and$ls180.v:6370$2072
+  attribute \src "ls180.v:6472.40-6472.147"
+  cell $and $and$ls180.v:6472$2141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6370$2070_Y
-    connect \B $eq$ls180.v:6370$2071_Y
-    connect \Y $and$ls180.v:6370$2072_Y
+    connect \A $and$ls180.v:6472$2139_Y
+    connect \B $eq$ls180.v:6472$2140_Y
+    connect \Y $and$ls180.v:6472$2141_Y
   end
-  attribute \src "ls180.v:6371.41-6371.99"
-  cell $and $and$ls180.v:6371$2074
+  attribute \src "ls180.v:6473.41-6473.99"
+  cell $and $and$ls180.v:6473$2143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6371$2073_Y
-    connect \Y $and$ls180.v:6371$2074_Y
+    connect \B $not$ls180.v:6473$2142_Y
+    connect \Y $and$ls180.v:6473$2143_Y
   end
-  attribute \src "ls180.v:6371.40-6371.150"
-  cell $and $and$ls180.v:6371$2076
+  attribute \src "ls180.v:6473.40-6473.150"
+  cell $and $and$ls180.v:6473$2145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6371$2074_Y
-    connect \B $eq$ls180.v:6371$2075_Y
-    connect \Y $and$ls180.v:6371$2076_Y
+    connect \A $and$ls180.v:6473$2143_Y
+    connect \B $eq$ls180.v:6473$2144_Y
+    connect \Y $and$ls180.v:6473$2145_Y
   end
-  attribute \src "ls180.v:6373.37-6373.92"
-  cell $and $and$ls180.v:6373$2077
+  attribute \src "ls180.v:6475.37-6475.92"
+  cell $and $and$ls180.v:6475$2146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245478,43 +246354,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6373$2077_Y
+    connect \Y $and$ls180.v:6475$2146_Y
   end
-  attribute \src "ls180.v:6373.36-6373.143"
-  cell $and $and$ls180.v:6373$2079
+  attribute \src "ls180.v:6475.36-6475.143"
+  cell $and $and$ls180.v:6475$2148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6373$2077_Y
-    connect \B $eq$ls180.v:6373$2078_Y
-    connect \Y $and$ls180.v:6373$2079_Y
+    connect \A $and$ls180.v:6475$2146_Y
+    connect \B $eq$ls180.v:6475$2147_Y
+    connect \Y $and$ls180.v:6475$2148_Y
   end
-  attribute \src "ls180.v:6374.37-6374.95"
-  cell $and $and$ls180.v:6374$2081
+  attribute \src "ls180.v:6476.37-6476.95"
+  cell $and $and$ls180.v:6476$2150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6374$2080_Y
-    connect \Y $and$ls180.v:6374$2081_Y
+    connect \B $not$ls180.v:6476$2149_Y
+    connect \Y $and$ls180.v:6476$2150_Y
   end
-  attribute \src "ls180.v:6374.36-6374.146"
-  cell $and $and$ls180.v:6374$2083
+  attribute \src "ls180.v:6476.36-6476.146"
+  cell $and $and$ls180.v:6476$2152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6374$2081_Y
-    connect \B $eq$ls180.v:6374$2082_Y
-    connect \Y $and$ls180.v:6374$2083_Y
+    connect \A $and$ls180.v:6476$2150_Y
+    connect \B $eq$ls180.v:6476$2151_Y
+    connect \Y $and$ls180.v:6476$2152_Y
   end
-  attribute \src "ls180.v:6376.47-6376.102"
-  cell $and $and$ls180.v:6376$2084
+  attribute \src "ls180.v:6478.47-6478.102"
+  cell $and $and$ls180.v:6478$2153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245522,43 +246398,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6376$2084_Y
+    connect \Y $and$ls180.v:6478$2153_Y
   end
-  attribute \src "ls180.v:6376.46-6376.153"
-  cell $and $and$ls180.v:6376$2086
+  attribute \src "ls180.v:6478.46-6478.153"
+  cell $and $and$ls180.v:6478$2155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6376$2084_Y
-    connect \B $eq$ls180.v:6376$2085_Y
-    connect \Y $and$ls180.v:6376$2086_Y
+    connect \A $and$ls180.v:6478$2153_Y
+    connect \B $eq$ls180.v:6478$2154_Y
+    connect \Y $and$ls180.v:6478$2155_Y
   end
-  attribute \src "ls180.v:6377.47-6377.105"
-  cell $and $and$ls180.v:6377$2088
+  attribute \src "ls180.v:6479.47-6479.105"
+  cell $and $and$ls180.v:6479$2157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6377$2087_Y
-    connect \Y $and$ls180.v:6377$2088_Y
+    connect \B $not$ls180.v:6479$2156_Y
+    connect \Y $and$ls180.v:6479$2157_Y
   end
-  attribute \src "ls180.v:6377.46-6377.156"
-  cell $and $and$ls180.v:6377$2090
+  attribute \src "ls180.v:6479.46-6479.156"
+  cell $and $and$ls180.v:6479$2159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6377$2088_Y
-    connect \B $eq$ls180.v:6377$2089_Y
-    connect \Y $and$ls180.v:6377$2090_Y
+    connect \A $and$ls180.v:6479$2157_Y
+    connect \B $eq$ls180.v:6479$2158_Y
+    connect \Y $and$ls180.v:6479$2159_Y
   end
-  attribute \src "ls180.v:6379.40-6379.95"
-  cell $and $and$ls180.v:6379$2091
+  attribute \src "ls180.v:6481.40-6481.95"
+  cell $and $and$ls180.v:6481$2160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245566,43 +246442,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6379$2091_Y
+    connect \Y $and$ls180.v:6481$2160_Y
   end
-  attribute \src "ls180.v:6379.39-6379.147"
-  cell $and $and$ls180.v:6379$2093
+  attribute \src "ls180.v:6481.39-6481.147"
+  cell $and $and$ls180.v:6481$2162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6379$2091_Y
-    connect \B $eq$ls180.v:6379$2092_Y
-    connect \Y $and$ls180.v:6379$2093_Y
+    connect \A $and$ls180.v:6481$2160_Y
+    connect \B $eq$ls180.v:6481$2161_Y
+    connect \Y $and$ls180.v:6481$2162_Y
   end
-  attribute \src "ls180.v:6380.40-6380.98"
-  cell $and $and$ls180.v:6380$2095
+  attribute \src "ls180.v:6482.40-6482.98"
+  cell $and $and$ls180.v:6482$2164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6380$2094_Y
-    connect \Y $and$ls180.v:6380$2095_Y
+    connect \B $not$ls180.v:6482$2163_Y
+    connect \Y $and$ls180.v:6482$2164_Y
   end
-  attribute \src "ls180.v:6380.39-6380.150"
-  cell $and $and$ls180.v:6380$2097
+  attribute \src "ls180.v:6482.39-6482.150"
+  cell $and $and$ls180.v:6482$2166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6380$2095_Y
-    connect \B $eq$ls180.v:6380$2096_Y
-    connect \Y $and$ls180.v:6380$2097_Y
+    connect \A $and$ls180.v:6482$2164_Y
+    connect \B $eq$ls180.v:6482$2165_Y
+    connect \Y $and$ls180.v:6482$2166_Y
   end
-  attribute \src "ls180.v:6382.40-6382.95"
-  cell $and $and$ls180.v:6382$2098
+  attribute \src "ls180.v:6484.40-6484.95"
+  cell $and $and$ls180.v:6484$2167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245610,43 +246486,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6382$2098_Y
+    connect \Y $and$ls180.v:6484$2167_Y
   end
-  attribute \src "ls180.v:6382.39-6382.147"
-  cell $and $and$ls180.v:6382$2100
+  attribute \src "ls180.v:6484.39-6484.147"
+  cell $and $and$ls180.v:6484$2169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6382$2098_Y
-    connect \B $eq$ls180.v:6382$2099_Y
-    connect \Y $and$ls180.v:6382$2100_Y
+    connect \A $and$ls180.v:6484$2167_Y
+    connect \B $eq$ls180.v:6484$2168_Y
+    connect \Y $and$ls180.v:6484$2169_Y
   end
-  attribute \src "ls180.v:6383.40-6383.98"
-  cell $and $and$ls180.v:6383$2102
+  attribute \src "ls180.v:6485.40-6485.98"
+  cell $and $and$ls180.v:6485$2171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6383$2101_Y
-    connect \Y $and$ls180.v:6383$2102_Y
+    connect \B $not$ls180.v:6485$2170_Y
+    connect \Y $and$ls180.v:6485$2171_Y
   end
-  attribute \src "ls180.v:6383.39-6383.150"
-  cell $and $and$ls180.v:6383$2104
+  attribute \src "ls180.v:6485.39-6485.150"
+  cell $and $and$ls180.v:6485$2173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6383$2102_Y
-    connect \B $eq$ls180.v:6383$2103_Y
-    connect \Y $and$ls180.v:6383$2104_Y
+    connect \A $and$ls180.v:6485$2171_Y
+    connect \B $eq$ls180.v:6485$2172_Y
+    connect \Y $and$ls180.v:6485$2173_Y
   end
-  attribute \src "ls180.v:6385.40-6385.95"
-  cell $and $and$ls180.v:6385$2105
+  attribute \src "ls180.v:6487.40-6487.95"
+  cell $and $and$ls180.v:6487$2174
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245654,43 +246530,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6385$2105_Y
+    connect \Y $and$ls180.v:6487$2174_Y
   end
-  attribute \src "ls180.v:6385.39-6385.147"
-  cell $and $and$ls180.v:6385$2107
+  attribute \src "ls180.v:6487.39-6487.147"
+  cell $and $and$ls180.v:6487$2176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6385$2105_Y
-    connect \B $eq$ls180.v:6385$2106_Y
-    connect \Y $and$ls180.v:6385$2107_Y
+    connect \A $and$ls180.v:6487$2174_Y
+    connect \B $eq$ls180.v:6487$2175_Y
+    connect \Y $and$ls180.v:6487$2176_Y
   end
-  attribute \src "ls180.v:6386.40-6386.98"
-  cell $and $and$ls180.v:6386$2109
+  attribute \src "ls180.v:6488.40-6488.98"
+  cell $and $and$ls180.v:6488$2178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6386$2108_Y
-    connect \Y $and$ls180.v:6386$2109_Y
+    connect \B $not$ls180.v:6488$2177_Y
+    connect \Y $and$ls180.v:6488$2178_Y
   end
-  attribute \src "ls180.v:6386.39-6386.150"
-  cell $and $and$ls180.v:6386$2111
+  attribute \src "ls180.v:6488.39-6488.150"
+  cell $and $and$ls180.v:6488$2180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6386$2109_Y
-    connect \B $eq$ls180.v:6386$2110_Y
-    connect \Y $and$ls180.v:6386$2111_Y
+    connect \A $and$ls180.v:6488$2178_Y
+    connect \B $eq$ls180.v:6488$2179_Y
+    connect \Y $and$ls180.v:6488$2180_Y
   end
-  attribute \src "ls180.v:6388.40-6388.95"
-  cell $and $and$ls180.v:6388$2112
+  attribute \src "ls180.v:6490.40-6490.95"
+  cell $and $and$ls180.v:6490$2181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245698,43 +246574,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6388$2112_Y
+    connect \Y $and$ls180.v:6490$2181_Y
   end
-  attribute \src "ls180.v:6388.39-6388.147"
-  cell $and $and$ls180.v:6388$2114
+  attribute \src "ls180.v:6490.39-6490.147"
+  cell $and $and$ls180.v:6490$2183
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6388$2112_Y
-    connect \B $eq$ls180.v:6388$2113_Y
-    connect \Y $and$ls180.v:6388$2114_Y
+    connect \A $and$ls180.v:6490$2181_Y
+    connect \B $eq$ls180.v:6490$2182_Y
+    connect \Y $and$ls180.v:6490$2183_Y
   end
-  attribute \src "ls180.v:6389.40-6389.98"
-  cell $and $and$ls180.v:6389$2116
+  attribute \src "ls180.v:6491.40-6491.98"
+  cell $and $and$ls180.v:6491$2185
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6389$2115_Y
-    connect \Y $and$ls180.v:6389$2116_Y
+    connect \B $not$ls180.v:6491$2184_Y
+    connect \Y $and$ls180.v:6491$2185_Y
   end
-  attribute \src "ls180.v:6389.39-6389.150"
-  cell $and $and$ls180.v:6389$2118
+  attribute \src "ls180.v:6491.39-6491.150"
+  cell $and $and$ls180.v:6491$2187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6389$2116_Y
-    connect \B $eq$ls180.v:6389$2117_Y
-    connect \Y $and$ls180.v:6389$2118_Y
+    connect \A $and$ls180.v:6491$2185_Y
+    connect \B $eq$ls180.v:6491$2186_Y
+    connect \Y $and$ls180.v:6491$2187_Y
   end
-  attribute \src "ls180.v:6391.52-6391.107"
-  cell $and $and$ls180.v:6391$2119
+  attribute \src "ls180.v:6493.52-6493.107"
+  cell $and $and$ls180.v:6493$2188
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245742,43 +246618,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6391$2119_Y
+    connect \Y $and$ls180.v:6493$2188_Y
   end
-  attribute \src "ls180.v:6391.51-6391.159"
-  cell $and $and$ls180.v:6391$2121
+  attribute \src "ls180.v:6493.51-6493.159"
+  cell $and $and$ls180.v:6493$2190
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6391$2119_Y
-    connect \B $eq$ls180.v:6391$2120_Y
-    connect \Y $and$ls180.v:6391$2121_Y
+    connect \A $and$ls180.v:6493$2188_Y
+    connect \B $eq$ls180.v:6493$2189_Y
+    connect \Y $and$ls180.v:6493$2190_Y
   end
-  attribute \src "ls180.v:6392.52-6392.110"
-  cell $and $and$ls180.v:6392$2123
+  attribute \src "ls180.v:6494.52-6494.110"
+  cell $and $and$ls180.v:6494$2192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6392$2122_Y
-    connect \Y $and$ls180.v:6392$2123_Y
+    connect \B $not$ls180.v:6494$2191_Y
+    connect \Y $and$ls180.v:6494$2192_Y
   end
-  attribute \src "ls180.v:6392.51-6392.162"
-  cell $and $and$ls180.v:6392$2125
+  attribute \src "ls180.v:6494.51-6494.162"
+  cell $and $and$ls180.v:6494$2194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6392$2123_Y
-    connect \B $eq$ls180.v:6392$2124_Y
-    connect \Y $and$ls180.v:6392$2125_Y
+    connect \A $and$ls180.v:6494$2192_Y
+    connect \B $eq$ls180.v:6494$2193_Y
+    connect \Y $and$ls180.v:6494$2194_Y
   end
-  attribute \src "ls180.v:6394.53-6394.108"
-  cell $and $and$ls180.v:6394$2126
+  attribute \src "ls180.v:6496.53-6496.108"
+  cell $and $and$ls180.v:6496$2195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245786,43 +246662,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6394$2126_Y
+    connect \Y $and$ls180.v:6496$2195_Y
   end
-  attribute \src "ls180.v:6394.52-6394.160"
-  cell $and $and$ls180.v:6394$2128
+  attribute \src "ls180.v:6496.52-6496.160"
+  cell $and $and$ls180.v:6496$2197
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6394$2126_Y
-    connect \B $eq$ls180.v:6394$2127_Y
-    connect \Y $and$ls180.v:6394$2128_Y
+    connect \A $and$ls180.v:6496$2195_Y
+    connect \B $eq$ls180.v:6496$2196_Y
+    connect \Y $and$ls180.v:6496$2197_Y
   end
-  attribute \src "ls180.v:6395.53-6395.111"
-  cell $and $and$ls180.v:6395$2130
+  attribute \src "ls180.v:6497.53-6497.111"
+  cell $and $and$ls180.v:6497$2199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6395$2129_Y
-    connect \Y $and$ls180.v:6395$2130_Y
+    connect \B $not$ls180.v:6497$2198_Y
+    connect \Y $and$ls180.v:6497$2199_Y
   end
-  attribute \src "ls180.v:6395.52-6395.163"
-  cell $and $and$ls180.v:6395$2132
+  attribute \src "ls180.v:6497.52-6497.163"
+  cell $and $and$ls180.v:6497$2201
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6395$2130_Y
-    connect \B $eq$ls180.v:6395$2131_Y
-    connect \Y $and$ls180.v:6395$2132_Y
+    connect \A $and$ls180.v:6497$2199_Y
+    connect \B $eq$ls180.v:6497$2200_Y
+    connect \Y $and$ls180.v:6497$2201_Y
   end
-  attribute \src "ls180.v:6397.44-6397.99"
-  cell $and $and$ls180.v:6397$2133
+  attribute \src "ls180.v:6499.44-6499.99"
+  cell $and $and$ls180.v:6499$2202
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245830,43 +246706,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
     connect \B \builder_interface12_bank_bus_we
-    connect \Y $and$ls180.v:6397$2133_Y
+    connect \Y $and$ls180.v:6499$2202_Y
   end
-  attribute \src "ls180.v:6397.43-6397.151"
-  cell $and $and$ls180.v:6397$2135
+  attribute \src "ls180.v:6499.43-6499.151"
+  cell $and $and$ls180.v:6499$2204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6397$2133_Y
-    connect \B $eq$ls180.v:6397$2134_Y
-    connect \Y $and$ls180.v:6397$2135_Y
+    connect \A $and$ls180.v:6499$2202_Y
+    connect \B $eq$ls180.v:6499$2203_Y
+    connect \Y $and$ls180.v:6499$2204_Y
   end
-  attribute \src "ls180.v:6398.44-6398.102"
-  cell $and $and$ls180.v:6398$2137
+  attribute \src "ls180.v:6500.44-6500.102"
+  cell $and $and$ls180.v:6500$2206
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank12_sel
-    connect \B $not$ls180.v:6398$2136_Y
-    connect \Y $and$ls180.v:6398$2137_Y
+    connect \B $not$ls180.v:6500$2205_Y
+    connect \Y $and$ls180.v:6500$2206_Y
   end
-  attribute \src "ls180.v:6398.43-6398.154"
-  cell $and $and$ls180.v:6398$2139
+  attribute \src "ls180.v:6500.43-6500.154"
+  cell $and $and$ls180.v:6500$2208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6398$2137_Y
-    connect \B $eq$ls180.v:6398$2138_Y
-    connect \Y $and$ls180.v:6398$2139_Y
+    connect \A $and$ls180.v:6500$2206_Y
+    connect \B $eq$ls180.v:6500$2207_Y
+    connect \Y $and$ls180.v:6500$2208_Y
   end
-  attribute \src "ls180.v:6417.30-6417.85"
-  cell $and $and$ls180.v:6417$2141
+  attribute \src "ls180.v:6519.30-6519.85"
+  cell $and $and$ls180.v:6519$2210
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245874,43 +246750,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6417$2141_Y
+    connect \Y $and$ls180.v:6519$2210_Y
   end
-  attribute \src "ls180.v:6417.29-6417.136"
-  cell $and $and$ls180.v:6417$2143
+  attribute \src "ls180.v:6519.29-6519.136"
+  cell $and $and$ls180.v:6519$2212
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6417$2141_Y
-    connect \B $eq$ls180.v:6417$2142_Y
-    connect \Y $and$ls180.v:6417$2143_Y
+    connect \A $and$ls180.v:6519$2210_Y
+    connect \B $eq$ls180.v:6519$2211_Y
+    connect \Y $and$ls180.v:6519$2212_Y
   end
-  attribute \src "ls180.v:6418.30-6418.88"
-  cell $and $and$ls180.v:6418$2145
+  attribute \src "ls180.v:6520.30-6520.88"
+  cell $and $and$ls180.v:6520$2214
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6418$2144_Y
-    connect \Y $and$ls180.v:6418$2145_Y
+    connect \B $not$ls180.v:6520$2213_Y
+    connect \Y $and$ls180.v:6520$2214_Y
   end
-  attribute \src "ls180.v:6418.29-6418.139"
-  cell $and $and$ls180.v:6418$2147
+  attribute \src "ls180.v:6520.29-6520.139"
+  cell $and $and$ls180.v:6520$2216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6418$2145_Y
-    connect \B $eq$ls180.v:6418$2146_Y
-    connect \Y $and$ls180.v:6418$2147_Y
+    connect \A $and$ls180.v:6520$2214_Y
+    connect \B $eq$ls180.v:6520$2215_Y
+    connect \Y $and$ls180.v:6520$2216_Y
   end
-  attribute \src "ls180.v:6420.40-6420.95"
-  cell $and $and$ls180.v:6420$2148
+  attribute \src "ls180.v:6522.40-6522.95"
+  cell $and $and$ls180.v:6522$2217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245918,43 +246794,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6420$2148_Y
+    connect \Y $and$ls180.v:6522$2217_Y
   end
-  attribute \src "ls180.v:6420.39-6420.146"
-  cell $and $and$ls180.v:6420$2150
+  attribute \src "ls180.v:6522.39-6522.146"
+  cell $and $and$ls180.v:6522$2219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6420$2148_Y
-    connect \B $eq$ls180.v:6420$2149_Y
-    connect \Y $and$ls180.v:6420$2150_Y
+    connect \A $and$ls180.v:6522$2217_Y
+    connect \B $eq$ls180.v:6522$2218_Y
+    connect \Y $and$ls180.v:6522$2219_Y
   end
-  attribute \src "ls180.v:6421.40-6421.98"
-  cell $and $and$ls180.v:6421$2152
+  attribute \src "ls180.v:6523.40-6523.98"
+  cell $and $and$ls180.v:6523$2221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6421$2151_Y
-    connect \Y $and$ls180.v:6421$2152_Y
+    connect \B $not$ls180.v:6523$2220_Y
+    connect \Y $and$ls180.v:6523$2221_Y
   end
-  attribute \src "ls180.v:6421.39-6421.149"
-  cell $and $and$ls180.v:6421$2154
+  attribute \src "ls180.v:6523.39-6523.149"
+  cell $and $and$ls180.v:6523$2223
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6421$2152_Y
-    connect \B $eq$ls180.v:6421$2153_Y
-    connect \Y $and$ls180.v:6421$2154_Y
+    connect \A $and$ls180.v:6523$2221_Y
+    connect \B $eq$ls180.v:6523$2222_Y
+    connect \Y $and$ls180.v:6523$2223_Y
   end
-  attribute \src "ls180.v:6423.41-6423.96"
-  cell $and $and$ls180.v:6423$2155
+  attribute \src "ls180.v:6525.41-6525.96"
+  cell $and $and$ls180.v:6525$2224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -245962,43 +246838,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6423$2155_Y
+    connect \Y $and$ls180.v:6525$2224_Y
   end
-  attribute \src "ls180.v:6423.40-6423.147"
-  cell $and $and$ls180.v:6423$2157
+  attribute \src "ls180.v:6525.40-6525.147"
+  cell $and $and$ls180.v:6525$2226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6423$2155_Y
-    connect \B $eq$ls180.v:6423$2156_Y
-    connect \Y $and$ls180.v:6423$2157_Y
+    connect \A $and$ls180.v:6525$2224_Y
+    connect \B $eq$ls180.v:6525$2225_Y
+    connect \Y $and$ls180.v:6525$2226_Y
   end
-  attribute \src "ls180.v:6424.41-6424.99"
-  cell $and $and$ls180.v:6424$2159
+  attribute \src "ls180.v:6526.41-6526.99"
+  cell $and $and$ls180.v:6526$2228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6424$2158_Y
-    connect \Y $and$ls180.v:6424$2159_Y
+    connect \B $not$ls180.v:6526$2227_Y
+    connect \Y $and$ls180.v:6526$2228_Y
   end
-  attribute \src "ls180.v:6424.40-6424.150"
-  cell $and $and$ls180.v:6424$2161
+  attribute \src "ls180.v:6526.40-6526.150"
+  cell $and $and$ls180.v:6526$2230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6424$2159_Y
-    connect \B $eq$ls180.v:6424$2160_Y
-    connect \Y $and$ls180.v:6424$2161_Y
+    connect \A $and$ls180.v:6526$2228_Y
+    connect \B $eq$ls180.v:6526$2229_Y
+    connect \Y $and$ls180.v:6526$2230_Y
   end
-  attribute \src "ls180.v:6426.45-6426.100"
-  cell $and $and$ls180.v:6426$2162
+  attribute \src "ls180.v:6528.45-6528.100"
+  cell $and $and$ls180.v:6528$2231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246006,43 +246882,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6426$2162_Y
+    connect \Y $and$ls180.v:6528$2231_Y
   end
-  attribute \src "ls180.v:6426.44-6426.151"
-  cell $and $and$ls180.v:6426$2164
+  attribute \src "ls180.v:6528.44-6528.151"
+  cell $and $and$ls180.v:6528$2233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6426$2162_Y
-    connect \B $eq$ls180.v:6426$2163_Y
-    connect \Y $and$ls180.v:6426$2164_Y
+    connect \A $and$ls180.v:6528$2231_Y
+    connect \B $eq$ls180.v:6528$2232_Y
+    connect \Y $and$ls180.v:6528$2233_Y
   end
-  attribute \src "ls180.v:6427.45-6427.103"
-  cell $and $and$ls180.v:6427$2166
+  attribute \src "ls180.v:6529.45-6529.103"
+  cell $and $and$ls180.v:6529$2235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6427$2165_Y
-    connect \Y $and$ls180.v:6427$2166_Y
+    connect \B $not$ls180.v:6529$2234_Y
+    connect \Y $and$ls180.v:6529$2235_Y
   end
-  attribute \src "ls180.v:6427.44-6427.154"
-  cell $and $and$ls180.v:6427$2168
+  attribute \src "ls180.v:6529.44-6529.154"
+  cell $and $and$ls180.v:6529$2237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6427$2166_Y
-    connect \B $eq$ls180.v:6427$2167_Y
-    connect \Y $and$ls180.v:6427$2168_Y
+    connect \A $and$ls180.v:6529$2235_Y
+    connect \B $eq$ls180.v:6529$2236_Y
+    connect \Y $and$ls180.v:6529$2237_Y
   end
-  attribute \src "ls180.v:6429.46-6429.101"
-  cell $and $and$ls180.v:6429$2169
+  attribute \src "ls180.v:6531.46-6531.101"
+  cell $and $and$ls180.v:6531$2238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246050,43 +246926,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6429$2169_Y
+    connect \Y $and$ls180.v:6531$2238_Y
   end
-  attribute \src "ls180.v:6429.45-6429.152"
-  cell $and $and$ls180.v:6429$2171
+  attribute \src "ls180.v:6531.45-6531.152"
+  cell $and $and$ls180.v:6531$2240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6429$2169_Y
-    connect \B $eq$ls180.v:6429$2170_Y
-    connect \Y $and$ls180.v:6429$2171_Y
+    connect \A $and$ls180.v:6531$2238_Y
+    connect \B $eq$ls180.v:6531$2239_Y
+    connect \Y $and$ls180.v:6531$2240_Y
   end
-  attribute \src "ls180.v:6430.46-6430.104"
-  cell $and $and$ls180.v:6430$2173
+  attribute \src "ls180.v:6532.46-6532.104"
+  cell $and $and$ls180.v:6532$2242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6430$2172_Y
-    connect \Y $and$ls180.v:6430$2173_Y
+    connect \B $not$ls180.v:6532$2241_Y
+    connect \Y $and$ls180.v:6532$2242_Y
   end
-  attribute \src "ls180.v:6430.45-6430.155"
-  cell $and $and$ls180.v:6430$2175
+  attribute \src "ls180.v:6532.45-6532.155"
+  cell $and $and$ls180.v:6532$2244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6430$2173_Y
-    connect \B $eq$ls180.v:6430$2174_Y
-    connect \Y $and$ls180.v:6430$2175_Y
+    connect \A $and$ls180.v:6532$2242_Y
+    connect \B $eq$ls180.v:6532$2243_Y
+    connect \Y $and$ls180.v:6532$2244_Y
   end
-  attribute \src "ls180.v:6432.44-6432.99"
-  cell $and $and$ls180.v:6432$2176
+  attribute \src "ls180.v:6534.44-6534.99"
+  cell $and $and$ls180.v:6534$2245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246094,43 +246970,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6432$2176_Y
+    connect \Y $and$ls180.v:6534$2245_Y
   end
-  attribute \src "ls180.v:6432.43-6432.150"
-  cell $and $and$ls180.v:6432$2178
+  attribute \src "ls180.v:6534.43-6534.150"
+  cell $and $and$ls180.v:6534$2247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6432$2176_Y
-    connect \B $eq$ls180.v:6432$2177_Y
-    connect \Y $and$ls180.v:6432$2178_Y
+    connect \A $and$ls180.v:6534$2245_Y
+    connect \B $eq$ls180.v:6534$2246_Y
+    connect \Y $and$ls180.v:6534$2247_Y
   end
-  attribute \src "ls180.v:6433.44-6433.102"
-  cell $and $and$ls180.v:6433$2180
+  attribute \src "ls180.v:6535.44-6535.102"
+  cell $and $and$ls180.v:6535$2249
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6433$2179_Y
-    connect \Y $and$ls180.v:6433$2180_Y
+    connect \B $not$ls180.v:6535$2248_Y
+    connect \Y $and$ls180.v:6535$2249_Y
   end
-  attribute \src "ls180.v:6433.43-6433.153"
-  cell $and $and$ls180.v:6433$2182
+  attribute \src "ls180.v:6535.43-6535.153"
+  cell $and $and$ls180.v:6535$2251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6433$2180_Y
-    connect \B $eq$ls180.v:6433$2181_Y
-    connect \Y $and$ls180.v:6433$2182_Y
+    connect \A $and$ls180.v:6535$2249_Y
+    connect \B $eq$ls180.v:6535$2250_Y
+    connect \Y $and$ls180.v:6535$2251_Y
   end
-  attribute \src "ls180.v:6435.41-6435.96"
-  cell $and $and$ls180.v:6435$2183
+  attribute \src "ls180.v:6537.41-6537.96"
+  cell $and $and$ls180.v:6537$2252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246138,43 +247014,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6435$2183_Y
+    connect \Y $and$ls180.v:6537$2252_Y
   end
-  attribute \src "ls180.v:6435.40-6435.147"
-  cell $and $and$ls180.v:6435$2185
+  attribute \src "ls180.v:6537.40-6537.147"
+  cell $and $and$ls180.v:6537$2254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6435$2183_Y
-    connect \B $eq$ls180.v:6435$2184_Y
-    connect \Y $and$ls180.v:6435$2185_Y
+    connect \A $and$ls180.v:6537$2252_Y
+    connect \B $eq$ls180.v:6537$2253_Y
+    connect \Y $and$ls180.v:6537$2254_Y
   end
-  attribute \src "ls180.v:6436.41-6436.99"
-  cell $and $and$ls180.v:6436$2187
+  attribute \src "ls180.v:6538.41-6538.99"
+  cell $and $and$ls180.v:6538$2256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6436$2186_Y
-    connect \Y $and$ls180.v:6436$2187_Y
+    connect \B $not$ls180.v:6538$2255_Y
+    connect \Y $and$ls180.v:6538$2256_Y
   end
-  attribute \src "ls180.v:6436.40-6436.150"
-  cell $and $and$ls180.v:6436$2189
+  attribute \src "ls180.v:6538.40-6538.150"
+  cell $and $and$ls180.v:6538$2258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6436$2187_Y
-    connect \B $eq$ls180.v:6436$2188_Y
-    connect \Y $and$ls180.v:6436$2189_Y
+    connect \A $and$ls180.v:6538$2256_Y
+    connect \B $eq$ls180.v:6538$2257_Y
+    connect \Y $and$ls180.v:6538$2258_Y
   end
-  attribute \src "ls180.v:6438.40-6438.95"
-  cell $and $and$ls180.v:6438$2190
+  attribute \src "ls180.v:6540.40-6540.95"
+  cell $and $and$ls180.v:6540$2259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246182,43 +247058,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
     connect \B \builder_interface13_bank_bus_we
-    connect \Y $and$ls180.v:6438$2190_Y
+    connect \Y $and$ls180.v:6540$2259_Y
   end
-  attribute \src "ls180.v:6438.39-6438.146"
-  cell $and $and$ls180.v:6438$2192
+  attribute \src "ls180.v:6540.39-6540.146"
+  cell $and $and$ls180.v:6540$2261
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6438$2190_Y
-    connect \B $eq$ls180.v:6438$2191_Y
-    connect \Y $and$ls180.v:6438$2192_Y
+    connect \A $and$ls180.v:6540$2259_Y
+    connect \B $eq$ls180.v:6540$2260_Y
+    connect \Y $and$ls180.v:6540$2261_Y
   end
-  attribute \src "ls180.v:6439.40-6439.98"
-  cell $and $and$ls180.v:6439$2194
+  attribute \src "ls180.v:6541.40-6541.98"
+  cell $and $and$ls180.v:6541$2263
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank13_sel
-    connect \B $not$ls180.v:6439$2193_Y
-    connect \Y $and$ls180.v:6439$2194_Y
+    connect \B $not$ls180.v:6541$2262_Y
+    connect \Y $and$ls180.v:6541$2263_Y
   end
-  attribute \src "ls180.v:6439.39-6439.149"
-  cell $and $and$ls180.v:6439$2196
+  attribute \src "ls180.v:6541.39-6541.149"
+  cell $and $and$ls180.v:6541$2265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6439$2194_Y
-    connect \B $eq$ls180.v:6439$2195_Y
-    connect \Y $and$ls180.v:6439$2196_Y
+    connect \A $and$ls180.v:6541$2263_Y
+    connect \B $eq$ls180.v:6541$2264_Y
+    connect \Y $and$ls180.v:6541$2265_Y
   end
-  attribute \src "ls180.v:6451.46-6451.101"
-  cell $and $and$ls180.v:6451$2198
+  attribute \src "ls180.v:6553.46-6553.101"
+  cell $and $and$ls180.v:6553$2267
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246226,43 +247102,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
     connect \B \builder_interface14_bank_bus_we
-    connect \Y $and$ls180.v:6451$2198_Y
+    connect \Y $and$ls180.v:6553$2267_Y
   end
-  attribute \src "ls180.v:6451.45-6451.152"
-  cell $and $and$ls180.v:6451$2200
+  attribute \src "ls180.v:6553.45-6553.152"
+  cell $and $and$ls180.v:6553$2269
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6451$2198_Y
-    connect \B $eq$ls180.v:6451$2199_Y
-    connect \Y $and$ls180.v:6451$2200_Y
+    connect \A $and$ls180.v:6553$2267_Y
+    connect \B $eq$ls180.v:6553$2268_Y
+    connect \Y $and$ls180.v:6553$2269_Y
   end
-  attribute \src "ls180.v:6452.46-6452.104"
-  cell $and $and$ls180.v:6452$2202
+  attribute \src "ls180.v:6554.46-6554.104"
+  cell $and $and$ls180.v:6554$2271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
-    connect \B $not$ls180.v:6452$2201_Y
-    connect \Y $and$ls180.v:6452$2202_Y
+    connect \B $not$ls180.v:6554$2270_Y
+    connect \Y $and$ls180.v:6554$2271_Y
   end
-  attribute \src "ls180.v:6452.45-6452.155"
-  cell $and $and$ls180.v:6452$2204
+  attribute \src "ls180.v:6554.45-6554.155"
+  cell $and $and$ls180.v:6554$2273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6452$2202_Y
-    connect \B $eq$ls180.v:6452$2203_Y
-    connect \Y $and$ls180.v:6452$2204_Y
+    connect \A $and$ls180.v:6554$2271_Y
+    connect \B $eq$ls180.v:6554$2272_Y
+    connect \Y $and$ls180.v:6554$2273_Y
   end
-  attribute \src "ls180.v:6454.46-6454.101"
-  cell $and $and$ls180.v:6454$2205
+  attribute \src "ls180.v:6556.46-6556.101"
+  cell $and $and$ls180.v:6556$2274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246270,43 +247146,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
     connect \B \builder_interface14_bank_bus_we
-    connect \Y $and$ls180.v:6454$2205_Y
+    connect \Y $and$ls180.v:6556$2274_Y
   end
-  attribute \src "ls180.v:6454.45-6454.152"
-  cell $and $and$ls180.v:6454$2207
+  attribute \src "ls180.v:6556.45-6556.152"
+  cell $and $and$ls180.v:6556$2276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6454$2205_Y
-    connect \B $eq$ls180.v:6454$2206_Y
-    connect \Y $and$ls180.v:6454$2207_Y
+    connect \A $and$ls180.v:6556$2274_Y
+    connect \B $eq$ls180.v:6556$2275_Y
+    connect \Y $and$ls180.v:6556$2276_Y
   end
-  attribute \src "ls180.v:6455.46-6455.104"
-  cell $and $and$ls180.v:6455$2209
+  attribute \src "ls180.v:6557.46-6557.104"
+  cell $and $and$ls180.v:6557$2278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
-    connect \B $not$ls180.v:6455$2208_Y
-    connect \Y $and$ls180.v:6455$2209_Y
+    connect \B $not$ls180.v:6557$2277_Y
+    connect \Y $and$ls180.v:6557$2278_Y
   end
-  attribute \src "ls180.v:6455.45-6455.155"
-  cell $and $and$ls180.v:6455$2211
+  attribute \src "ls180.v:6557.45-6557.155"
+  cell $and $and$ls180.v:6557$2280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6455$2209_Y
-    connect \B $eq$ls180.v:6455$2210_Y
-    connect \Y $and$ls180.v:6455$2211_Y
+    connect \A $and$ls180.v:6557$2278_Y
+    connect \B $eq$ls180.v:6557$2279_Y
+    connect \Y $and$ls180.v:6557$2280_Y
   end
-  attribute \src "ls180.v:6457.46-6457.101"
-  cell $and $and$ls180.v:6457$2212
+  attribute \src "ls180.v:6559.46-6559.101"
+  cell $and $and$ls180.v:6559$2281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246314,43 +247190,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
     connect \B \builder_interface14_bank_bus_we
-    connect \Y $and$ls180.v:6457$2212_Y
+    connect \Y $and$ls180.v:6559$2281_Y
   end
-  attribute \src "ls180.v:6457.45-6457.152"
-  cell $and $and$ls180.v:6457$2214
+  attribute \src "ls180.v:6559.45-6559.152"
+  cell $and $and$ls180.v:6559$2283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6457$2212_Y
-    connect \B $eq$ls180.v:6457$2213_Y
-    connect \Y $and$ls180.v:6457$2214_Y
+    connect \A $and$ls180.v:6559$2281_Y
+    connect \B $eq$ls180.v:6559$2282_Y
+    connect \Y $and$ls180.v:6559$2283_Y
   end
-  attribute \src "ls180.v:6458.46-6458.104"
-  cell $and $and$ls180.v:6458$2216
+  attribute \src "ls180.v:6560.46-6560.104"
+  cell $and $and$ls180.v:6560$2285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
-    connect \B $not$ls180.v:6458$2215_Y
-    connect \Y $and$ls180.v:6458$2216_Y
+    connect \B $not$ls180.v:6560$2284_Y
+    connect \Y $and$ls180.v:6560$2285_Y
   end
-  attribute \src "ls180.v:6458.45-6458.155"
-  cell $and $and$ls180.v:6458$2218
+  attribute \src "ls180.v:6560.45-6560.155"
+  cell $and $and$ls180.v:6560$2287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6458$2216_Y
-    connect \B $eq$ls180.v:6458$2217_Y
-    connect \Y $and$ls180.v:6458$2218_Y
+    connect \A $and$ls180.v:6560$2285_Y
+    connect \B $eq$ls180.v:6560$2286_Y
+    connect \Y $and$ls180.v:6560$2287_Y
   end
-  attribute \src "ls180.v:6460.46-6460.101"
-  cell $and $and$ls180.v:6460$2219
+  attribute \src "ls180.v:6562.46-6562.101"
+  cell $and $and$ls180.v:6562$2288
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246358,263 +247234,263 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
     connect \B \builder_interface14_bank_bus_we
-    connect \Y $and$ls180.v:6460$2219_Y
+    connect \Y $and$ls180.v:6562$2288_Y
   end
-  attribute \src "ls180.v:6460.45-6460.152"
-  cell $and $and$ls180.v:6460$2221
+  attribute \src "ls180.v:6562.45-6562.152"
+  cell $and $and$ls180.v:6562$2290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6460$2219_Y
-    connect \B $eq$ls180.v:6460$2220_Y
-    connect \Y $and$ls180.v:6460$2221_Y
+    connect \A $and$ls180.v:6562$2288_Y
+    connect \B $eq$ls180.v:6562$2289_Y
+    connect \Y $and$ls180.v:6562$2290_Y
   end
-  attribute \src "ls180.v:6461.46-6461.104"
-  cell $and $and$ls180.v:6461$2223
+  attribute \src "ls180.v:6563.46-6563.104"
+  cell $and $and$ls180.v:6563$2292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_csrbank14_sel
-    connect \B $not$ls180.v:6461$2222_Y
-    connect \Y $and$ls180.v:6461$2223_Y
+    connect \B $not$ls180.v:6563$2291_Y
+    connect \Y $and$ls180.v:6563$2292_Y
   end
-  attribute \src "ls180.v:6461.45-6461.155"
-  cell $and $and$ls180.v:6461$2225
+  attribute \src "ls180.v:6563.45-6563.155"
+  cell $and $and$ls180.v:6563$2294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6461$2223_Y
-    connect \B $eq$ls180.v:6461$2224_Y
-    connect \Y $and$ls180.v:6461$2225_Y
+    connect \A $and$ls180.v:6563$2292_Y
+    connect \B $eq$ls180.v:6563$2293_Y
+    connect \Y $and$ls180.v:6563$2294_Y
   end
-  attribute \src "ls180.v:6842.109-6842.178"
-  cell $and $and$ls180.v:6842$2263
+  attribute \src "ls180.v:6944.109-6944.178"
+  cell $and $and$ls180.v:6944$2332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:6842$2262_Y
-    connect \Y $and$ls180.v:6842$2263_Y
+    connect \B $eq$ls180.v:6944$2331_Y
+    connect \Y $and$ls180.v:6944$2332_Y
   end
-  attribute \src "ls180.v:6842.184-6842.253"
-  cell $and $and$ls180.v:6842$2266
+  attribute \src "ls180.v:6944.184-6944.253"
+  cell $and $and$ls180.v:6944$2335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:6842$2265_Y
-    connect \Y $and$ls180.v:6842$2266_Y
+    connect \B $eq$ls180.v:6944$2334_Y
+    connect \Y $and$ls180.v:6944$2335_Y
   end
-  attribute \src "ls180.v:6842.259-6842.328"
-  cell $and $and$ls180.v:6842$2269
+  attribute \src "ls180.v:6944.259-6944.328"
+  cell $and $and$ls180.v:6944$2338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:6842$2268_Y
-    connect \Y $and$ls180.v:6842$2269_Y
+    connect \B $eq$ls180.v:6944$2337_Y
+    connect \Y $and$ls180.v:6944$2338_Y
   end
-  attribute \src "ls180.v:6842.40-6842.331"
-  cell $and $and$ls180.v:6842$2272
+  attribute \src "ls180.v:6944.40-6944.331"
+  cell $and $and$ls180.v:6944$2341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:6842$2261_Y
-    connect \B $not$ls180.v:6842$2271_Y
-    connect \Y $and$ls180.v:6842$2272_Y
+    connect \A $eq$ls180.v:6944$2330_Y
+    connect \B $not$ls180.v:6944$2340_Y
+    connect \Y $and$ls180.v:6944$2341_Y
   end
-  attribute \src "ls180.v:6842.39-6842.354"
-  cell $and $and$ls180.v:6842$2273
+  attribute \src "ls180.v:6944.39-6944.354"
+  cell $and $and$ls180.v:6944$2342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6842$2272_Y
+    connect \A $and$ls180.v:6944$2341_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:6842$2273_Y
+    connect \Y $and$ls180.v:6944$2342_Y
   end
-  attribute \src "ls180.v:6866.109-6866.178"
-  cell $and $and$ls180.v:6866$2279
+  attribute \src "ls180.v:6968.109-6968.178"
+  cell $and $and$ls180.v:6968$2348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:6866$2278_Y
-    connect \Y $and$ls180.v:6866$2279_Y
+    connect \B $eq$ls180.v:6968$2347_Y
+    connect \Y $and$ls180.v:6968$2348_Y
   end
-  attribute \src "ls180.v:6866.184-6866.253"
-  cell $and $and$ls180.v:6866$2282
+  attribute \src "ls180.v:6968.184-6968.253"
+  cell $and $and$ls180.v:6968$2351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:6866$2281_Y
-    connect \Y $and$ls180.v:6866$2282_Y
+    connect \B $eq$ls180.v:6968$2350_Y
+    connect \Y $and$ls180.v:6968$2351_Y
   end
-  attribute \src "ls180.v:6866.259-6866.328"
-  cell $and $and$ls180.v:6866$2285
+  attribute \src "ls180.v:6968.259-6968.328"
+  cell $and $and$ls180.v:6968$2354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:6866$2284_Y
-    connect \Y $and$ls180.v:6866$2285_Y
+    connect \B $eq$ls180.v:6968$2353_Y
+    connect \Y $and$ls180.v:6968$2354_Y
   end
-  attribute \src "ls180.v:6866.40-6866.331"
-  cell $and $and$ls180.v:6866$2288
+  attribute \src "ls180.v:6968.40-6968.331"
+  cell $and $and$ls180.v:6968$2357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:6866$2277_Y
-    connect \B $not$ls180.v:6866$2287_Y
-    connect \Y $and$ls180.v:6866$2288_Y
+    connect \A $eq$ls180.v:6968$2346_Y
+    connect \B $not$ls180.v:6968$2356_Y
+    connect \Y $and$ls180.v:6968$2357_Y
   end
-  attribute \src "ls180.v:6866.39-6866.354"
-  cell $and $and$ls180.v:6866$2289
+  attribute \src "ls180.v:6968.39-6968.354"
+  cell $and $and$ls180.v:6968$2358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6866$2288_Y
+    connect \A $and$ls180.v:6968$2357_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:6866$2289_Y
+    connect \Y $and$ls180.v:6968$2358_Y
   end
-  attribute \src "ls180.v:6890.109-6890.178"
-  cell $and $and$ls180.v:6890$2295
+  attribute \src "ls180.v:6992.109-6992.178"
+  cell $and $and$ls180.v:6992$2364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:6890$2294_Y
-    connect \Y $and$ls180.v:6890$2295_Y
+    connect \B $eq$ls180.v:6992$2363_Y
+    connect \Y $and$ls180.v:6992$2364_Y
   end
-  attribute \src "ls180.v:6890.184-6890.253"
-  cell $and $and$ls180.v:6890$2298
+  attribute \src "ls180.v:6992.184-6992.253"
+  cell $and $and$ls180.v:6992$2367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:6890$2297_Y
-    connect \Y $and$ls180.v:6890$2298_Y
+    connect \B $eq$ls180.v:6992$2366_Y
+    connect \Y $and$ls180.v:6992$2367_Y
   end
-  attribute \src "ls180.v:6890.259-6890.328"
-  cell $and $and$ls180.v:6890$2301
+  attribute \src "ls180.v:6992.259-6992.328"
+  cell $and $and$ls180.v:6992$2370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:6890$2300_Y
-    connect \Y $and$ls180.v:6890$2301_Y
+    connect \B $eq$ls180.v:6992$2369_Y
+    connect \Y $and$ls180.v:6992$2370_Y
   end
-  attribute \src "ls180.v:6890.40-6890.331"
-  cell $and $and$ls180.v:6890$2304
+  attribute \src "ls180.v:6992.40-6992.331"
+  cell $and $and$ls180.v:6992$2373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:6890$2293_Y
-    connect \B $not$ls180.v:6890$2303_Y
-    connect \Y $and$ls180.v:6890$2304_Y
+    connect \A $eq$ls180.v:6992$2362_Y
+    connect \B $not$ls180.v:6992$2372_Y
+    connect \Y $and$ls180.v:6992$2373_Y
   end
-  attribute \src "ls180.v:6890.39-6890.354"
-  cell $and $and$ls180.v:6890$2305
+  attribute \src "ls180.v:6992.39-6992.354"
+  cell $and $and$ls180.v:6992$2374
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6890$2304_Y
+    connect \A $and$ls180.v:6992$2373_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:6890$2305_Y
+    connect \Y $and$ls180.v:6992$2374_Y
   end
-  attribute \src "ls180.v:6914.109-6914.178"
-  cell $and $and$ls180.v:6914$2311
+  attribute \src "ls180.v:7016.109-7016.178"
+  cell $and $and$ls180.v:7016$2380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:6914$2310_Y
-    connect \Y $and$ls180.v:6914$2311_Y
+    connect \B $eq$ls180.v:7016$2379_Y
+    connect \Y $and$ls180.v:7016$2380_Y
   end
-  attribute \src "ls180.v:6914.184-6914.253"
-  cell $and $and$ls180.v:6914$2314
+  attribute \src "ls180.v:7016.184-7016.253"
+  cell $and $and$ls180.v:7016$2383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:6914$2313_Y
-    connect \Y $and$ls180.v:6914$2314_Y
+    connect \B $eq$ls180.v:7016$2382_Y
+    connect \Y $and$ls180.v:7016$2383_Y
   end
-  attribute \src "ls180.v:6914.259-6914.328"
-  cell $and $and$ls180.v:6914$2317
+  attribute \src "ls180.v:7016.259-7016.328"
+  cell $and $and$ls180.v:7016$2386
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:6914$2316_Y
-    connect \Y $and$ls180.v:6914$2317_Y
+    connect \B $eq$ls180.v:7016$2385_Y
+    connect \Y $and$ls180.v:7016$2386_Y
   end
-  attribute \src "ls180.v:6914.40-6914.331"
-  cell $and $and$ls180.v:6914$2320
+  attribute \src "ls180.v:7016.40-7016.331"
+  cell $and $and$ls180.v:7016$2389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:6914$2309_Y
-    connect \B $not$ls180.v:6914$2319_Y
-    connect \Y $and$ls180.v:6914$2320_Y
+    connect \A $eq$ls180.v:7016$2378_Y
+    connect \B $not$ls180.v:7016$2388_Y
+    connect \Y $and$ls180.v:7016$2389_Y
   end
-  attribute \src "ls180.v:6914.39-6914.354"
-  cell $and $and$ls180.v:6914$2321
+  attribute \src "ls180.v:7016.39-7016.354"
+  cell $and $and$ls180.v:7016$2390
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:6914$2320_Y
+    connect \A $and$ls180.v:7016$2389_Y
     connect \B \main_port_cmd_valid
-    connect \Y $and$ls180.v:6914$2321_Y
+    connect \Y $and$ls180.v:7016$2390_Y
   end
-  attribute \src "ls180.v:7119.39-7119.104"
-  cell $and $and$ls180.v:7119$2333
+  attribute \src "ls180.v:7221.39-7221.104"
+  cell $and $and$ls180.v:7221$2402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246622,21 +247498,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7119$2333_Y
+    connect \Y $and$ls180.v:7221$2402_Y
   end
-  attribute \src "ls180.v:7119.38-7119.145"
-  cell $and $and$ls180.v:7119$2334
+  attribute \src "ls180.v:7221.38-7221.145"
+  cell $and $and$ls180.v:7221$2403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7119$2333_Y
+    connect \A $and$ls180.v:7221$2402_Y
     connect \B \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $and$ls180.v:7119$2334_Y
+    connect \Y $and$ls180.v:7221$2403_Y
   end
-  attribute \src "ls180.v:7122.39-7122.104"
-  cell $and $and$ls180.v:7122$2335
+  attribute \src "ls180.v:7224.39-7224.104"
+  cell $and $and$ls180.v:7224$2404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246644,21 +247520,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7122$2335_Y
+    connect \Y $and$ls180.v:7224$2404_Y
   end
-  attribute \src "ls180.v:7122.38-7122.145"
-  cell $and $and$ls180.v:7122$2336
+  attribute \src "ls180.v:7224.38-7224.145"
+  cell $and $and$ls180.v:7224$2405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7122$2335_Y
+    connect \A $and$ls180.v:7224$2404_Y
     connect \B \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $and$ls180.v:7122$2336_Y
+    connect \Y $and$ls180.v:7224$2405_Y
   end
-  attribute \src "ls180.v:7125.39-7125.82"
-  cell $and $and$ls180.v:7125$2337
+  attribute \src "ls180.v:7227.39-7227.82"
+  cell $and $and$ls180.v:7227$2406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246666,21 +247542,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cmd_valid
     connect \B \main_sdram_cmd_ready
-    connect \Y $and$ls180.v:7125$2337_Y
+    connect \Y $and$ls180.v:7227$2406_Y
   end
-  attribute \src "ls180.v:7125.38-7125.112"
-  cell $and $and$ls180.v:7125$2338
+  attribute \src "ls180.v:7227.38-7227.112"
+  cell $and $and$ls180.v:7227$2407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7125$2337_Y
+    connect \A $and$ls180.v:7227$2406_Y
     connect \B \main_sdram_cmd_payload_cas
-    connect \Y $and$ls180.v:7125$2338_Y
+    connect \Y $and$ls180.v:7227$2407_Y
   end
-  attribute \src "ls180.v:7136.39-7136.104"
-  cell $and $and$ls180.v:7136$2340
+  attribute \src "ls180.v:7238.39-7238.104"
+  cell $and $and$ls180.v:7238$2409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246688,21 +247564,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7136$2340_Y
+    connect \Y $and$ls180.v:7238$2409_Y
   end
-  attribute \src "ls180.v:7136.38-7136.145"
-  cell $and $and$ls180.v:7136$2341
+  attribute \src "ls180.v:7238.38-7238.145"
+  cell $and $and$ls180.v:7238$2410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7136$2340_Y
+    connect \A $and$ls180.v:7238$2409_Y
     connect \B \main_sdram_choose_req_cmd_payload_ras
-    connect \Y $and$ls180.v:7136$2341_Y
+    connect \Y $and$ls180.v:7238$2410_Y
   end
-  attribute \src "ls180.v:7139.39-7139.104"
-  cell $and $and$ls180.v:7139$2342
+  attribute \src "ls180.v:7241.39-7241.104"
+  cell $and $and$ls180.v:7241$2411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246710,21 +247586,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7139$2342_Y
+    connect \Y $and$ls180.v:7241$2411_Y
   end
-  attribute \src "ls180.v:7139.38-7139.145"
-  cell $and $and$ls180.v:7139$2343
+  attribute \src "ls180.v:7241.38-7241.145"
+  cell $and $and$ls180.v:7241$2412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7139$2342_Y
+    connect \A $and$ls180.v:7241$2411_Y
     connect \B \main_sdram_choose_req_cmd_payload_ras
-    connect \Y $and$ls180.v:7139$2343_Y
+    connect \Y $and$ls180.v:7241$2412_Y
   end
-  attribute \src "ls180.v:7142.39-7142.82"
-  cell $and $and$ls180.v:7142$2344
+  attribute \src "ls180.v:7244.39-7244.82"
+  cell $and $and$ls180.v:7244$2413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246732,21 +247608,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cmd_valid
     connect \B \main_sdram_cmd_ready
-    connect \Y $and$ls180.v:7142$2344_Y
+    connect \Y $and$ls180.v:7244$2413_Y
   end
-  attribute \src "ls180.v:7142.38-7142.112"
-  cell $and $and$ls180.v:7142$2345
+  attribute \src "ls180.v:7244.38-7244.112"
+  cell $and $and$ls180.v:7244$2414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7142$2344_Y
+    connect \A $and$ls180.v:7244$2413_Y
     connect \B \main_sdram_cmd_payload_ras
-    connect \Y $and$ls180.v:7142$2345_Y
+    connect \Y $and$ls180.v:7244$2414_Y
   end
-  attribute \src "ls180.v:7153.39-7153.104"
-  cell $and $and$ls180.v:7153$2347
+  attribute \src "ls180.v:7255.39-7255.104"
+  cell $and $and$ls180.v:7255$2416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246754,21 +247630,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7153$2347_Y
+    connect \Y $and$ls180.v:7255$2416_Y
   end
-  attribute \src "ls180.v:7153.38-7153.144"
-  cell $and $and$ls180.v:7153$2348
+  attribute \src "ls180.v:7255.38-7255.144"
+  cell $and $and$ls180.v:7255$2417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7153$2347_Y
+    connect \A $and$ls180.v:7255$2416_Y
     connect \B \main_sdram_choose_req_cmd_payload_we
-    connect \Y $and$ls180.v:7153$2348_Y
+    connect \Y $and$ls180.v:7255$2417_Y
   end
-  attribute \src "ls180.v:7156.39-7156.104"
-  cell $and $and$ls180.v:7156$2349
+  attribute \src "ls180.v:7258.39-7258.104"
+  cell $and $and$ls180.v:7258$2418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246776,21 +247652,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7156$2349_Y
+    connect \Y $and$ls180.v:7258$2418_Y
   end
-  attribute \src "ls180.v:7156.38-7156.144"
-  cell $and $and$ls180.v:7156$2350
+  attribute \src "ls180.v:7258.38-7258.144"
+  cell $and $and$ls180.v:7258$2419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7156$2349_Y
+    connect \A $and$ls180.v:7258$2418_Y
     connect \B \main_sdram_choose_req_cmd_payload_we
-    connect \Y $and$ls180.v:7156$2350_Y
+    connect \Y $and$ls180.v:7258$2419_Y
   end
-  attribute \src "ls180.v:7159.39-7159.82"
-  cell $and $and$ls180.v:7159$2351
+  attribute \src "ls180.v:7261.39-7261.82"
+  cell $and $and$ls180.v:7261$2420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246798,21 +247674,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cmd_valid
     connect \B \main_sdram_cmd_ready
-    connect \Y $and$ls180.v:7159$2351_Y
+    connect \Y $and$ls180.v:7261$2420_Y
   end
-  attribute \src "ls180.v:7159.38-7159.111"
-  cell $and $and$ls180.v:7159$2352
+  attribute \src "ls180.v:7261.38-7261.111"
+  cell $and $and$ls180.v:7261$2421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7159$2351_Y
+    connect \A $and$ls180.v:7261$2420_Y
     connect \B \main_sdram_cmd_payload_we
-    connect \Y $and$ls180.v:7159$2352_Y
+    connect \Y $and$ls180.v:7261$2421_Y
   end
-  attribute \src "ls180.v:7170.39-7170.104"
-  cell $and $and$ls180.v:7170$2354
+  attribute \src "ls180.v:7272.39-7272.104"
+  cell $and $and$ls180.v:7272$2423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246820,21 +247696,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7170$2354_Y
+    connect \Y $and$ls180.v:7272$2423_Y
   end
-  attribute \src "ls180.v:7170.38-7170.149"
-  cell $and $and$ls180.v:7170$2355
+  attribute \src "ls180.v:7272.38-7272.149"
+  cell $and $and$ls180.v:7272$2424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7170$2354_Y
+    connect \A $and$ls180.v:7272$2423_Y
     connect \B \main_sdram_choose_req_cmd_payload_is_read
-    connect \Y $and$ls180.v:7170$2355_Y
+    connect \Y $and$ls180.v:7272$2424_Y
   end
-  attribute \src "ls180.v:7173.39-7173.104"
-  cell $and $and$ls180.v:7173$2356
+  attribute \src "ls180.v:7275.39-7275.104"
+  cell $and $and$ls180.v:7275$2425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246842,21 +247718,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7173$2356_Y
+    connect \Y $and$ls180.v:7275$2425_Y
   end
-  attribute \src "ls180.v:7173.38-7173.149"
-  cell $and $and$ls180.v:7173$2357
+  attribute \src "ls180.v:7275.38-7275.149"
+  cell $and $and$ls180.v:7275$2426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7173$2356_Y
+    connect \A $and$ls180.v:7275$2425_Y
     connect \B \main_sdram_choose_req_cmd_payload_is_read
-    connect \Y $and$ls180.v:7173$2357_Y
+    connect \Y $and$ls180.v:7275$2426_Y
   end
-  attribute \src "ls180.v:7176.39-7176.82"
-  cell $and $and$ls180.v:7176$2358
+  attribute \src "ls180.v:7278.39-7278.82"
+  cell $and $and$ls180.v:7278$2427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246864,21 +247740,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cmd_valid
     connect \B \main_sdram_cmd_ready
-    connect \Y $and$ls180.v:7176$2358_Y
+    connect \Y $and$ls180.v:7278$2427_Y
   end
-  attribute \src "ls180.v:7176.38-7176.116"
-  cell $and $and$ls180.v:7176$2359
+  attribute \src "ls180.v:7278.38-7278.116"
+  cell $and $and$ls180.v:7278$2428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7176$2358_Y
+    connect \A $and$ls180.v:7278$2427_Y
     connect \B \main_sdram_cmd_payload_is_read
-    connect \Y $and$ls180.v:7176$2359_Y
+    connect \Y $and$ls180.v:7278$2428_Y
   end
-  attribute \src "ls180.v:7187.39-7187.104"
-  cell $and $and$ls180.v:7187$2361
+  attribute \src "ls180.v:7289.39-7289.104"
+  cell $and $and$ls180.v:7289$2430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246886,21 +247762,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7187$2361_Y
+    connect \Y $and$ls180.v:7289$2430_Y
   end
-  attribute \src "ls180.v:7187.38-7187.150"
-  cell $and $and$ls180.v:7187$2362
+  attribute \src "ls180.v:7289.38-7289.150"
+  cell $and $and$ls180.v:7289$2431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7187$2361_Y
+    connect \A $and$ls180.v:7289$2430_Y
     connect \B \main_sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:7187$2362_Y
+    connect \Y $and$ls180.v:7289$2431_Y
   end
-  attribute \src "ls180.v:7190.39-7190.104"
-  cell $and $and$ls180.v:7190$2363
+  attribute \src "ls180.v:7292.39-7292.104"
+  cell $and $and$ls180.v:7292$2432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246908,21 +247784,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
     connect \B \main_sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:7190$2363_Y
+    connect \Y $and$ls180.v:7292$2432_Y
   end
-  attribute \src "ls180.v:7190.38-7190.150"
-  cell $and $and$ls180.v:7190$2364
+  attribute \src "ls180.v:7292.38-7292.150"
+  cell $and $and$ls180.v:7292$2433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7190$2363_Y
+    connect \A $and$ls180.v:7292$2432_Y
     connect \B \main_sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:7190$2364_Y
+    connect \Y $and$ls180.v:7292$2433_Y
   end
-  attribute \src "ls180.v:7193.39-7193.82"
-  cell $and $and$ls180.v:7193$2365
+  attribute \src "ls180.v:7295.39-7295.82"
+  cell $and $and$ls180.v:7295$2434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246930,32 +247806,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_cmd_valid
     connect \B \main_sdram_cmd_ready
-    connect \Y $and$ls180.v:7193$2365_Y
+    connect \Y $and$ls180.v:7295$2434_Y
   end
-  attribute \src "ls180.v:7193.38-7193.117"
-  cell $and $and$ls180.v:7193$2366
+  attribute \src "ls180.v:7295.38-7295.117"
+  cell $and $and$ls180.v:7295$2435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7193$2365_Y
+    connect \A $and$ls180.v:7295$2434_Y
     connect \B \main_sdram_cmd_payload_is_write
-    connect \Y $and$ls180.v:7193$2366_Y
+    connect \Y $and$ls180.v:7295$2435_Y
   end
-  attribute \src "ls180.v:7412.17-7412.67"
-  cell $and $and$ls180.v:7412$2373
+  attribute \src "ls180.v:7514.17-7514.67"
+  cell $and $and$ls180.v:7514$2442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7412$2372_Y
+    connect \A $not$ls180.v:7514$2441_Y
     connect \B \main_sdphy_sdpads_clk
-    connect \Y $and$ls180.v:7412$2373_Y
+    connect \Y $and$ls180.v:7514$2442_Y
   end
-  attribute \src "ls180.v:7491.8-7491.67"
-  cell $and $and$ls180.v:7491$2404
+  attribute \src "ls180.v:7593.8-7593.67"
+  cell $and $and$ls180.v:7593$2473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246963,54 +247839,120 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:7491$2404_Y
+    connect \Y $and$ls180.v:7593$2473_Y
   end
-  attribute \src "ls180.v:7491.7-7491.102"
-  cell $and $and$ls180.v:7491$2406
+  attribute \src "ls180.v:7593.7-7593.102"
+  cell $and $and$ls180.v:7593$2475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7491$2404_Y
-    connect \B $not$ls180.v:7491$2405_Y
-    connect \Y $and$ls180.v:7491$2406_Y
+    connect \A $and$ls180.v:7593$2473_Y
+    connect \B $not$ls180.v:7593$2474_Y
+    connect \Y $and$ls180.v:7593$2475_Y
   end
-  attribute \src "ls180.v:7510.7-7510.75"
-  cell $and $and$ls180.v:7510$2410
+  attribute \src "ls180.v:7612.7-7612.75"
+  cell $and $and$ls180.v:7612$2479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7510$2409_Y
+    connect \A $not$ls180.v:7612$2478_Y
     connect \B \main_libresocsim_zero_old_trigger
-    connect \Y $and$ls180.v:7510$2410_Y
+    connect \Y $and$ls180.v:7612$2479_Y
+  end
+  attribute \src "ls180.v:7616.8-7616.65"
+  cell $and $and$ls180.v:7616$2480
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_cyc
+    connect \B \main_interface0_ram_bus_stb
+    connect \Y $and$ls180.v:7616$2480_Y
+  end
+  attribute \src "ls180.v:7616.7-7616.99"
+  cell $and $and$ls180.v:7616$2482
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:7616$2480_Y
+    connect \B $not$ls180.v:7616$2481_Y
+    connect \Y $and$ls180.v:7616$2482_Y
+  end
+  attribute \src "ls180.v:7620.8-7620.65"
+  cell $and $and$ls180.v:7620$2483
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_cyc
+    connect \B \main_interface1_ram_bus_stb
+    connect \Y $and$ls180.v:7620$2483_Y
+  end
+  attribute \src "ls180.v:7620.7-7620.99"
+  cell $and $and$ls180.v:7620$2485
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:7620$2483_Y
+    connect \B $not$ls180.v:7620$2484_Y
+    connect \Y $and$ls180.v:7620$2485_Y
+  end
+  attribute \src "ls180.v:7624.8-7624.65"
+  cell $and $and$ls180.v:7624$2486
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_cyc
+    connect \B \main_interface2_ram_bus_stb
+    connect \Y $and$ls180.v:7624$2486_Y
+  end
+  attribute \src "ls180.v:7624.7-7624.99"
+  cell $and $and$ls180.v:7624$2488
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $and$ls180.v:7624$2486_Y
+    connect \B $not$ls180.v:7624$2487_Y
+    connect \Y $and$ls180.v:7624$2488_Y
   end
-  attribute \src "ls180.v:7518.7-7518.56"
-  cell $and $and$ls180.v:7518$2412
+  attribute \src "ls180.v:7632.7-7632.56"
+  cell $and $and$ls180.v:7632$2490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_wait
-    connect \B $not$ls180.v:7518$2411_Y
-    connect \Y $and$ls180.v:7518$2412_Y
+    connect \B $not$ls180.v:7632$2489_Y
+    connect \Y $and$ls180.v:7632$2490_Y
   end
-  attribute \src "ls180.v:7546.7-7546.75"
-  cell $and $and$ls180.v:7546$2419
+  attribute \src "ls180.v:7660.7-7660.75"
+  cell $and $and$ls180.v:7660$2497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_start1
-    connect \B $eq$ls180.v:7546$2418_Y
-    connect \Y $and$ls180.v:7546$2419_Y
+    connect \B $eq$ls180.v:7660$2496_Y
+    connect \Y $and$ls180.v:7660$2497_Y
   end
-  attribute \src "ls180.v:7588.8-7588.131"
-  cell $and $and$ls180.v:7588$2425
+  attribute \src "ls180.v:7702.8-7702.131"
+  cell $and $and$ls180.v:7702$2503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247018,21 +247960,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:7588$2425_Y
+    connect \Y $and$ls180.v:7702$2503_Y
   end
-  attribute \src "ls180.v:7588.7-7588.190"
-  cell $and $and$ls180.v:7588$2427
+  attribute \src "ls180.v:7702.7-7702.190"
+  cell $and $and$ls180.v:7702$2505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7588$2425_Y
-    connect \B $not$ls180.v:7588$2426_Y
-    connect \Y $and$ls180.v:7588$2427_Y
+    connect \A $and$ls180.v:7702$2503_Y
+    connect \B $not$ls180.v:7702$2504_Y
+    connect \Y $and$ls180.v:7702$2505_Y
   end
-  attribute \src "ls180.v:7594.8-7594.131"
-  cell $and $and$ls180.v:7594$2430
+  attribute \src "ls180.v:7708.8-7708.131"
+  cell $and $and$ls180.v:7708$2508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247040,21 +247982,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:7594$2430_Y
+    connect \Y $and$ls180.v:7708$2508_Y
   end
-  attribute \src "ls180.v:7594.7-7594.190"
-  cell $and $and$ls180.v:7594$2432
+  attribute \src "ls180.v:7708.7-7708.190"
+  cell $and $and$ls180.v:7708$2510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7594$2430_Y
-    connect \B $not$ls180.v:7594$2431_Y
-    connect \Y $and$ls180.v:7594$2432_Y
+    connect \A $and$ls180.v:7708$2508_Y
+    connect \B $not$ls180.v:7708$2509_Y
+    connect \Y $and$ls180.v:7708$2510_Y
   end
-  attribute \src "ls180.v:7634.8-7634.131"
-  cell $and $and$ls180.v:7634$2441
+  attribute \src "ls180.v:7748.8-7748.131"
+  cell $and $and$ls180.v:7748$2519
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247062,21 +248004,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:7634$2441_Y
+    connect \Y $and$ls180.v:7748$2519_Y
   end
-  attribute \src "ls180.v:7634.7-7634.190"
-  cell $and $and$ls180.v:7634$2443
+  attribute \src "ls180.v:7748.7-7748.190"
+  cell $and $and$ls180.v:7748$2521
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7634$2441_Y
-    connect \B $not$ls180.v:7634$2442_Y
-    connect \Y $and$ls180.v:7634$2443_Y
+    connect \A $and$ls180.v:7748$2519_Y
+    connect \B $not$ls180.v:7748$2520_Y
+    connect \Y $and$ls180.v:7748$2521_Y
   end
-  attribute \src "ls180.v:7640.8-7640.131"
-  cell $and $and$ls180.v:7640$2446
+  attribute \src "ls180.v:7754.8-7754.131"
+  cell $and $and$ls180.v:7754$2524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247084,21 +248026,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:7640$2446_Y
+    connect \Y $and$ls180.v:7754$2524_Y
   end
-  attribute \src "ls180.v:7640.7-7640.190"
-  cell $and $and$ls180.v:7640$2448
+  attribute \src "ls180.v:7754.7-7754.190"
+  cell $and $and$ls180.v:7754$2526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7640$2446_Y
-    connect \B $not$ls180.v:7640$2447_Y
-    connect \Y $and$ls180.v:7640$2448_Y
+    connect \A $and$ls180.v:7754$2524_Y
+    connect \B $not$ls180.v:7754$2525_Y
+    connect \Y $and$ls180.v:7754$2526_Y
   end
-  attribute \src "ls180.v:7680.8-7680.131"
-  cell $and $and$ls180.v:7680$2457
+  attribute \src "ls180.v:7794.8-7794.131"
+  cell $and $and$ls180.v:7794$2535
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247106,21 +248048,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:7680$2457_Y
+    connect \Y $and$ls180.v:7794$2535_Y
   end
-  attribute \src "ls180.v:7680.7-7680.190"
-  cell $and $and$ls180.v:7680$2459
+  attribute \src "ls180.v:7794.7-7794.190"
+  cell $and $and$ls180.v:7794$2537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7680$2457_Y
-    connect \B $not$ls180.v:7680$2458_Y
-    connect \Y $and$ls180.v:7680$2459_Y
+    connect \A $and$ls180.v:7794$2535_Y
+    connect \B $not$ls180.v:7794$2536_Y
+    connect \Y $and$ls180.v:7794$2537_Y
   end
-  attribute \src "ls180.v:7686.8-7686.131"
-  cell $and $and$ls180.v:7686$2462
+  attribute \src "ls180.v:7800.8-7800.131"
+  cell $and $and$ls180.v:7800$2540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247128,21 +248070,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:7686$2462_Y
+    connect \Y $and$ls180.v:7800$2540_Y
   end
-  attribute \src "ls180.v:7686.7-7686.190"
-  cell $and $and$ls180.v:7686$2464
+  attribute \src "ls180.v:7800.7-7800.190"
+  cell $and $and$ls180.v:7800$2542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7686$2462_Y
-    connect \B $not$ls180.v:7686$2463_Y
-    connect \Y $and$ls180.v:7686$2464_Y
+    connect \A $and$ls180.v:7800$2540_Y
+    connect \B $not$ls180.v:7800$2541_Y
+    connect \Y $and$ls180.v:7800$2542_Y
   end
-  attribute \src "ls180.v:7726.8-7726.131"
-  cell $and $and$ls180.v:7726$2473
+  attribute \src "ls180.v:7840.8-7840.131"
+  cell $and $and$ls180.v:7840$2551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247150,21 +248092,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:7726$2473_Y
+    connect \Y $and$ls180.v:7840$2551_Y
   end
-  attribute \src "ls180.v:7726.7-7726.190"
-  cell $and $and$ls180.v:7726$2475
+  attribute \src "ls180.v:7840.7-7840.190"
+  cell $and $and$ls180.v:7840$2553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7726$2473_Y
-    connect \B $not$ls180.v:7726$2474_Y
-    connect \Y $and$ls180.v:7726$2475_Y
+    connect \A $and$ls180.v:7840$2551_Y
+    connect \B $not$ls180.v:7840$2552_Y
+    connect \Y $and$ls180.v:7840$2553_Y
   end
-  attribute \src "ls180.v:7732.8-7732.131"
-  cell $and $and$ls180.v:7732$2478
+  attribute \src "ls180.v:7846.8-7846.131"
+  cell $and $and$ls180.v:7846$2556
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247172,109 +248114,109 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:7732$2478_Y
+    connect \Y $and$ls180.v:7846$2556_Y
   end
-  attribute \src "ls180.v:7732.7-7732.190"
-  cell $and $and$ls180.v:7732$2480
+  attribute \src "ls180.v:7846.7-7846.190"
+  cell $and $and$ls180.v:7846$2558
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7732$2478_Y
-    connect \B $not$ls180.v:7732$2479_Y
-    connect \Y $and$ls180.v:7732$2480_Y
+    connect \A $and$ls180.v:7846$2556_Y
+    connect \B $not$ls180.v:7846$2557_Y
+    connect \Y $and$ls180.v:7846$2558_Y
   end
-  attribute \src "ls180.v:7929.48-7929.124"
-  cell $and $and$ls180.v:7929$2505
+  attribute \src "ls180.v:8043.48-8043.124"
+  cell $and $and$ls180.v:8043$2583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7929$2504_Y
+    connect \A $eq$ls180.v:8043$2582_Y
     connect \B \main_sdram_interface_bank0_wdata_ready
-    connect \Y $and$ls180.v:7929$2505_Y
+    connect \Y $and$ls180.v:8043$2583_Y
   end
-  attribute \src "ls180.v:7929.130-7929.206"
-  cell $and $and$ls180.v:7929$2508
+  attribute \src "ls180.v:8043.130-8043.206"
+  cell $and $and$ls180.v:8043$2586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7929$2507_Y
+    connect \A $eq$ls180.v:8043$2585_Y
     connect \B \main_sdram_interface_bank1_wdata_ready
-    connect \Y $and$ls180.v:7929$2508_Y
+    connect \Y $and$ls180.v:8043$2586_Y
   end
-  attribute \src "ls180.v:7929.212-7929.288"
-  cell $and $and$ls180.v:7929$2511
+  attribute \src "ls180.v:8043.212-8043.288"
+  cell $and $and$ls180.v:8043$2589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7929$2510_Y
+    connect \A $eq$ls180.v:8043$2588_Y
     connect \B \main_sdram_interface_bank2_wdata_ready
-    connect \Y $and$ls180.v:7929$2511_Y
+    connect \Y $and$ls180.v:8043$2589_Y
   end
-  attribute \src "ls180.v:7929.294-7929.370"
-  cell $and $and$ls180.v:7929$2514
+  attribute \src "ls180.v:8043.294-8043.370"
+  cell $and $and$ls180.v:8043$2592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7929$2513_Y
+    connect \A $eq$ls180.v:8043$2591_Y
     connect \B \main_sdram_interface_bank3_wdata_ready
-    connect \Y $and$ls180.v:7929$2514_Y
+    connect \Y $and$ls180.v:8043$2592_Y
   end
-  attribute \src "ls180.v:7930.49-7930.125"
-  cell $and $and$ls180.v:7930$2517
+  attribute \src "ls180.v:8044.49-8044.125"
+  cell $and $and$ls180.v:8044$2595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7930$2516_Y
+    connect \A $eq$ls180.v:8044$2594_Y
     connect \B \main_sdram_interface_bank0_rdata_valid
-    connect \Y $and$ls180.v:7930$2517_Y
+    connect \Y $and$ls180.v:8044$2595_Y
   end
-  attribute \src "ls180.v:7930.131-7930.207"
-  cell $and $and$ls180.v:7930$2520
+  attribute \src "ls180.v:8044.131-8044.207"
+  cell $and $and$ls180.v:8044$2598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7930$2519_Y
+    connect \A $eq$ls180.v:8044$2597_Y
     connect \B \main_sdram_interface_bank1_rdata_valid
-    connect \Y $and$ls180.v:7930$2520_Y
+    connect \Y $and$ls180.v:8044$2598_Y
   end
-  attribute \src "ls180.v:7930.213-7930.289"
-  cell $and $and$ls180.v:7930$2523
+  attribute \src "ls180.v:8044.213-8044.289"
+  cell $and $and$ls180.v:8044$2601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7930$2522_Y
+    connect \A $eq$ls180.v:8044$2600_Y
     connect \B \main_sdram_interface_bank2_rdata_valid
-    connect \Y $and$ls180.v:7930$2523_Y
+    connect \Y $and$ls180.v:8044$2601_Y
   end
-  attribute \src "ls180.v:7930.295-7930.371"
-  cell $and $and$ls180.v:7930$2526
+  attribute \src "ls180.v:8044.295-8044.371"
+  cell $and $and$ls180.v:8044$2604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7930$2525_Y
+    connect \A $eq$ls180.v:8044$2603_Y
     connect \B \main_sdram_interface_bank3_rdata_valid
-    connect \Y $and$ls180.v:7930$2526_Y
+    connect \Y $and$ls180.v:8044$2604_Y
   end
-  attribute \src "ls180.v:7949.8-7949.49"
-  cell $and $and$ls180.v:7949$2529
+  attribute \src "ls180.v:8063.8-8063.49"
+  cell $and $and$ls180.v:8063$2607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247282,10 +248224,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_valid
     connect \B \main_port_cmd_ready
-    connect \Y $and$ls180.v:7949$2529_Y
+    connect \Y $and$ls180.v:8063$2607_Y
   end
-  attribute \src "ls180.v:7952.8-7952.53"
-  cell $and $and$ls180.v:7952$2530
+  attribute \src "ls180.v:8066.8-8066.53"
+  cell $and $and$ls180.v:8066$2608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247293,32 +248235,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_wdata_valid
     connect \B \main_port_wdata_ready
-    connect \Y $and$ls180.v:7952$2530_Y
+    connect \Y $and$ls180.v:8066$2608_Y
   end
-  attribute \src "ls180.v:7957.8-7957.59"
-  cell $and $and$ls180.v:7957$2532
+  attribute \src "ls180.v:8071.8-8071.59"
+  cell $and $and$ls180.v:8071$2610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_sink_valid
-    connect \B $not$ls180.v:7957$2531_Y
-    connect \Y $and$ls180.v:7957$2532_Y
+    connect \B $not$ls180.v:8071$2609_Y
+    connect \Y $and$ls180.v:8071$2610_Y
   end
-  attribute \src "ls180.v:7957.7-7957.90"
-  cell $and $and$ls180.v:7957$2534
+  attribute \src "ls180.v:8071.7-8071.90"
+  cell $and $and$ls180.v:8071$2612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7957$2532_Y
-    connect \B $not$ls180.v:7957$2533_Y
-    connect \Y $and$ls180.v:7957$2534_Y
+    connect \A $and$ls180.v:8071$2610_Y
+    connect \B $not$ls180.v:8071$2611_Y
+    connect \Y $and$ls180.v:8071$2612_Y
   end
-  attribute \src "ls180.v:7963.8-7963.59"
-  cell $and $and$ls180.v:7963$2535
+  attribute \src "ls180.v:8077.8-8077.59"
+  cell $and $and$ls180.v:8077$2613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247326,43 +248268,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_uart_clk_txen
     connect \B \main_uart_phy_tx_busy
-    connect \Y $and$ls180.v:7963$2535_Y
+    connect \Y $and$ls180.v:8077$2613_Y
   end
-  attribute \src "ls180.v:7987.8-7987.48"
-  cell $and $and$ls180.v:7987$2542
+  attribute \src "ls180.v:8101.8-8101.48"
+  cell $and $and$ls180.v:8101$2620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7987$2541_Y
+    connect \A $not$ls180.v:8101$2619_Y
     connect \B \main_uart_phy_rx_r
-    connect \Y $and$ls180.v:7987$2542_Y
+    connect \Y $and$ls180.v:8101$2620_Y
   end
-  attribute \src "ls180.v:8020.7-8020.57"
-  cell $and $and$ls180.v:8020$2548
+  attribute \src "ls180.v:8134.7-8134.57"
+  cell $and $and$ls180.v:8134$2626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8020$2547_Y
+    connect \A $not$ls180.v:8134$2625_Y
     connect \B \main_uart_tx_old_trigger
-    connect \Y $and$ls180.v:8020$2548_Y
+    connect \Y $and$ls180.v:8134$2626_Y
   end
-  attribute \src "ls180.v:8027.7-8027.57"
-  cell $and $and$ls180.v:8027$2550
+  attribute \src "ls180.v:8141.7-8141.57"
+  cell $and $and$ls180.v:8141$2628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8027$2549_Y
+    connect \A $not$ls180.v:8141$2627_Y
     connect \B \main_uart_rx_old_trigger
-    connect \Y $and$ls180.v:8027$2550_Y
+    connect \Y $and$ls180.v:8141$2628_Y
   end
-  attribute \src "ls180.v:8037.8-8037.75"
-  cell $and $and$ls180.v:8037$2551
+  attribute \src "ls180.v:8151.8-8151.75"
+  cell $and $and$ls180.v:8151$2629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247370,21 +248312,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_we
     connect \B \main_uart_tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8037$2551_Y
+    connect \Y $and$ls180.v:8151$2629_Y
   end
-  attribute \src "ls180.v:8037.7-8037.107"
-  cell $and $and$ls180.v:8037$2553
+  attribute \src "ls180.v:8151.7-8151.107"
+  cell $and $and$ls180.v:8151$2631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8037$2551_Y
-    connect \B $not$ls180.v:8037$2552_Y
-    connect \Y $and$ls180.v:8037$2553_Y
+    connect \A $and$ls180.v:8151$2629_Y
+    connect \B $not$ls180.v:8151$2630_Y
+    connect \Y $and$ls180.v:8151$2631_Y
   end
-  attribute \src "ls180.v:8043.8-8043.75"
-  cell $and $and$ls180.v:8043$2556
+  attribute \src "ls180.v:8157.8-8157.75"
+  cell $and $and$ls180.v:8157$2634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247392,21 +248334,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_we
     connect \B \main_uart_tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8043$2556_Y
+    connect \Y $and$ls180.v:8157$2634_Y
   end
-  attribute \src "ls180.v:8043.7-8043.107"
-  cell $and $and$ls180.v:8043$2558
+  attribute \src "ls180.v:8157.7-8157.107"
+  cell $and $and$ls180.v:8157$2636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8043$2556_Y
-    connect \B $not$ls180.v:8043$2557_Y
-    connect \Y $and$ls180.v:8043$2558_Y
+    connect \A $and$ls180.v:8157$2634_Y
+    connect \B $not$ls180.v:8157$2635_Y
+    connect \Y $and$ls180.v:8157$2636_Y
   end
-  attribute \src "ls180.v:8059.8-8059.75"
-  cell $and $and$ls180.v:8059$2562
+  attribute \src "ls180.v:8173.8-8173.75"
+  cell $and $and$ls180.v:8173$2640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247414,21 +248356,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_we
     connect \B \main_uart_rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8059$2562_Y
+    connect \Y $and$ls180.v:8173$2640_Y
   end
-  attribute \src "ls180.v:8059.7-8059.107"
-  cell $and $and$ls180.v:8059$2564
+  attribute \src "ls180.v:8173.7-8173.107"
+  cell $and $and$ls180.v:8173$2642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8059$2562_Y
-    connect \B $not$ls180.v:8059$2563_Y
-    connect \Y $and$ls180.v:8059$2564_Y
+    connect \A $and$ls180.v:8173$2640_Y
+    connect \B $not$ls180.v:8173$2641_Y
+    connect \Y $and$ls180.v:8173$2642_Y
   end
-  attribute \src "ls180.v:8065.8-8065.75"
-  cell $and $and$ls180.v:8065$2567
+  attribute \src "ls180.v:8179.8-8179.75"
+  cell $and $and$ls180.v:8179$2645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247436,21 +248378,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_we
     connect \B \main_uart_rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8065$2567_Y
+    connect \Y $and$ls180.v:8179$2645_Y
   end
-  attribute \src "ls180.v:8065.7-8065.107"
-  cell $and $and$ls180.v:8065$2569
+  attribute \src "ls180.v:8179.7-8179.107"
+  cell $and $and$ls180.v:8179$2647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8065$2567_Y
-    connect \B $not$ls180.v:8065$2568_Y
-    connect \Y $and$ls180.v:8065$2569_Y
+    connect \A $and$ls180.v:8179$2645_Y
+    connect \B $not$ls180.v:8179$2646_Y
+    connect \Y $and$ls180.v:8179$2647_Y
   end
-  attribute \src "ls180.v:8213.7-8213.96"
-  cell $and $and$ls180.v:8213$2597
+  attribute \src "ls180.v:8327.7-8327.96"
+  cell $and $and$ls180.v:8327$2675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247458,10 +248400,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_source_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
-    connect \Y $and$ls180.v:8213$2597_Y
+    connect \Y $and$ls180.v:8327$2675_Y
   end
-  attribute \src "ls180.v:8214.8-8214.93"
-  cell $and $and$ls180.v:8214$2598
+  attribute \src "ls180.v:8328.8-8328.93"
+  cell $and $and$ls180.v:8328$2676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247469,10 +248411,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
-    connect \Y $and$ls180.v:8214$2598_Y
+    connect \Y $and$ls180.v:8328$2676_Y
   end
-  attribute \src "ls180.v:8222.8-8222.93"
-  cell $and $and$ls180.v:8222$2599
+  attribute \src "ls180.v:8336.8-8336.93"
+  cell $and $and$ls180.v:8336$2677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247480,10 +248422,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
-    connect \Y $and$ls180.v:8222$2599_Y
+    connect \Y $and$ls180.v:8336$2677_Y
   end
-  attribute \src "ls180.v:8294.7-8294.98"
-  cell $and $and$ls180.v:8294$2609
+  attribute \src "ls180.v:8408.7-8408.98"
+  cell $and $and$ls180.v:8408$2687
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247491,10 +248433,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_source_valid
     connect \B \main_sdphy_dataw_crcr_converter_source_ready
-    connect \Y $and$ls180.v:8294$2609_Y
+    connect \Y $and$ls180.v:8408$2687_Y
   end
-  attribute \src "ls180.v:8295.8-8295.95"
-  cell $and $and$ls180.v:8295$2610
+  attribute \src "ls180.v:8409.8-8409.95"
+  cell $and $and$ls180.v:8409$2688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247502,10 +248444,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
-    connect \Y $and$ls180.v:8295$2610_Y
+    connect \Y $and$ls180.v:8409$2688_Y
   end
-  attribute \src "ls180.v:8303.8-8303.95"
-  cell $and $and$ls180.v:8303$2611
+  attribute \src "ls180.v:8417.8-8417.95"
+  cell $and $and$ls180.v:8417$2689
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247513,10 +248455,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
-    connect \Y $and$ls180.v:8303$2611_Y
+    connect \Y $and$ls180.v:8417$2689_Y
   end
-  attribute \src "ls180.v:8373.7-8373.100"
-  cell $and $and$ls180.v:8373$2621
+  attribute \src "ls180.v:8487.7-8487.100"
+  cell $and $and$ls180.v:8487$2699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247524,10 +248466,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_source_valid
     connect \B \main_sdphy_datar_datar_converter_source_ready
-    connect \Y $and$ls180.v:8373$2621_Y
+    connect \Y $and$ls180.v:8487$2699_Y
   end
-  attribute \src "ls180.v:8374.8-8374.97"
-  cell $and $and$ls180.v:8374$2622
+  attribute \src "ls180.v:8488.8-8488.97"
+  cell $and $and$ls180.v:8488$2700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247535,10 +248477,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_valid
     connect \B \main_sdphy_datar_datar_converter_sink_ready
-    connect \Y $and$ls180.v:8374$2622_Y
+    connect \Y $and$ls180.v:8488$2700_Y
   end
-  attribute \src "ls180.v:8382.8-8382.97"
-  cell $and $and$ls180.v:8382$2623
+  attribute \src "ls180.v:8496.8-8496.97"
+  cell $and $and$ls180.v:8496$2701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247546,10 +248488,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_valid
     connect \B \main_sdphy_datar_datar_converter_sink_ready
-    connect \Y $and$ls180.v:8382$2623_Y
+    connect \Y $and$ls180.v:8496$2701_Y
   end
-  attribute \src "ls180.v:8473.7-8473.82"
-  cell $and $and$ls180.v:8473$2629
+  attribute \src "ls180.v:8587.7-8587.82"
+  cell $and $and$ls180.v:8587$2707
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247557,10 +248499,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8473$2629_Y
+    connect \Y $and$ls180.v:8587$2707_Y
   end
-  attribute \src "ls180.v:8476.7-8476.82"
-  cell $and $and$ls180.v:8476$2630
+  attribute \src "ls180.v:8590.7-8590.82"
+  cell $and $and$ls180.v:8590$2708
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247568,10 +248510,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8476$2630_Y
+    connect \Y $and$ls180.v:8590$2708_Y
   end
-  attribute \src "ls180.v:8479.7-8479.82"
-  cell $and $and$ls180.v:8479$2631
+  attribute \src "ls180.v:8593.7-8593.82"
+  cell $and $and$ls180.v:8593$2709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247579,10 +248521,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8479$2631_Y
+    connect \Y $and$ls180.v:8593$2709_Y
   end
-  attribute \src "ls180.v:8482.7-8482.82"
-  cell $and $and$ls180.v:8482$2632
+  attribute \src "ls180.v:8596.7-8596.82"
+  cell $and $and$ls180.v:8596$2710
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247590,10 +248532,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8482$2632_Y
+    connect \Y $and$ls180.v:8596$2710_Y
   end
-  attribute \src "ls180.v:8485.7-8485.82"
-  cell $and $and$ls180.v:8485$2633
+  attribute \src "ls180.v:8599.7-8599.82"
+  cell $and $and$ls180.v:8599$2711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247601,10 +248543,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8485$2633_Y
+    connect \Y $and$ls180.v:8599$2711_Y
   end
-  attribute \src "ls180.v:8490.7-8490.82"
-  cell $and $and$ls180.v:8490$2634
+  attribute \src "ls180.v:8604.7-8604.82"
+  cell $and $and$ls180.v:8604$2712
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247612,10 +248554,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8490$2634_Y
+    connect \Y $and$ls180.v:8604$2712_Y
   end
-  attribute \src "ls180.v:8495.7-8495.82"
-  cell $and $and$ls180.v:8495$2635
+  attribute \src "ls180.v:8609.7-8609.82"
+  cell $and $and$ls180.v:8609$2713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247623,10 +248565,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8495$2635_Y
+    connect \Y $and$ls180.v:8609$2713_Y
   end
-  attribute \src "ls180.v:8500.7-8500.82"
-  cell $and $and$ls180.v:8500$2636
+  attribute \src "ls180.v:8614.7-8614.82"
+  cell $and $and$ls180.v:8614$2714
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247634,10 +248576,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8500$2636_Y
+    connect \Y $and$ls180.v:8614$2714_Y
   end
-  attribute \src "ls180.v:8505.7-8505.82"
-  cell $and $and$ls180.v:8505$2637
+  attribute \src "ls180.v:8619.7-8619.82"
+  cell $and $and$ls180.v:8619$2715
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247645,10 +248587,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8505$2637_Y
+    connect \Y $and$ls180.v:8619$2715_Y
   end
-  attribute \src "ls180.v:8570.8-8570.83"
-  cell $and $and$ls180.v:8570$2640
+  attribute \src "ls180.v:8684.8-8684.83"
+  cell $and $and$ls180.v:8684$2718
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247656,21 +248598,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_we
     connect \B \main_sdblock2mem_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8570$2640_Y
+    connect \Y $and$ls180.v:8684$2718_Y
   end
-  attribute \src "ls180.v:8570.7-8570.119"
-  cell $and $and$ls180.v:8570$2642
+  attribute \src "ls180.v:8684.7-8684.119"
+  cell $and $and$ls180.v:8684$2720
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8570$2640_Y
-    connect \B $not$ls180.v:8570$2641_Y
-    connect \Y $and$ls180.v:8570$2642_Y
+    connect \A $and$ls180.v:8684$2718_Y
+    connect \B $not$ls180.v:8684$2719_Y
+    connect \Y $and$ls180.v:8684$2720_Y
   end
-  attribute \src "ls180.v:8576.8-8576.83"
-  cell $and $and$ls180.v:8576$2645
+  attribute \src "ls180.v:8690.8-8690.83"
+  cell $and $and$ls180.v:8690$2723
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247678,21 +248620,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_we
     connect \B \main_sdblock2mem_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8576$2645_Y
+    connect \Y $and$ls180.v:8690$2723_Y
   end
-  attribute \src "ls180.v:8576.7-8576.119"
-  cell $and $and$ls180.v:8576$2647
+  attribute \src "ls180.v:8690.7-8690.119"
+  cell $and $and$ls180.v:8690$2725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8576$2645_Y
-    connect \B $not$ls180.v:8576$2646_Y
-    connect \Y $and$ls180.v:8576$2647_Y
+    connect \A $and$ls180.v:8690$2723_Y
+    connect \B $not$ls180.v:8690$2724_Y
+    connect \Y $and$ls180.v:8690$2725_Y
   end
-  attribute \src "ls180.v:8596.7-8596.88"
-  cell $and $and$ls180.v:8596$2654
+  attribute \src "ls180.v:8710.7-8710.88"
+  cell $and $and$ls180.v:8710$2732
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247700,10 +248642,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_source_valid
     connect \B \main_sdblock2mem_converter_source_ready
-    connect \Y $and$ls180.v:8596$2654_Y
+    connect \Y $and$ls180.v:8710$2732_Y
   end
-  attribute \src "ls180.v:8597.8-8597.85"
-  cell $and $and$ls180.v:8597$2655
+  attribute \src "ls180.v:8711.8-8711.85"
+  cell $and $and$ls180.v:8711$2733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247711,10 +248653,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_valid
     connect \B \main_sdblock2mem_converter_sink_ready
-    connect \Y $and$ls180.v:8597$2655_Y
+    connect \Y $and$ls180.v:8711$2733_Y
   end
-  attribute \src "ls180.v:8605.8-8605.85"
-  cell $and $and$ls180.v:8605$2656
+  attribute \src "ls180.v:8719.8-8719.85"
+  cell $and $and$ls180.v:8719$2734
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247722,10 +248664,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_valid
     connect \B \main_sdblock2mem_converter_sink_ready
-    connect \Y $and$ls180.v:8605$2656_Y
+    connect \Y $and$ls180.v:8719$2734_Y
   end
-  attribute \src "ls180.v:8649.7-8649.88"
-  cell $and $and$ls180.v:8649$2660
+  attribute \src "ls180.v:8763.7-8763.88"
+  cell $and $and$ls180.v:8763$2738
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247733,10 +248675,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_source_valid
     connect \B \main_sdmem2block_converter_source_ready
-    connect \Y $and$ls180.v:8649$2660_Y
+    connect \Y $and$ls180.v:8763$2738_Y
   end
-  attribute \src "ls180.v:8656.8-8656.83"
-  cell $and $and$ls180.v:8656$2662
+  attribute \src "ls180.v:8770.8-8770.83"
+  cell $and $and$ls180.v:8770$2740
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247744,21 +248686,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_we
     connect \B \main_sdmem2block_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8656$2662_Y
+    connect \Y $and$ls180.v:8770$2740_Y
   end
-  attribute \src "ls180.v:8656.7-8656.119"
-  cell $and $and$ls180.v:8656$2664
+  attribute \src "ls180.v:8770.7-8770.119"
+  cell $and $and$ls180.v:8770$2742
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8656$2662_Y
-    connect \B $not$ls180.v:8656$2663_Y
-    connect \Y $and$ls180.v:8656$2664_Y
+    connect \A $and$ls180.v:8770$2740_Y
+    connect \B $not$ls180.v:8770$2741_Y
+    connect \Y $and$ls180.v:8770$2742_Y
   end
-  attribute \src "ls180.v:8662.8-8662.83"
-  cell $and $and$ls180.v:8662$2667
+  attribute \src "ls180.v:8776.8-8776.83"
+  cell $and $and$ls180.v:8776$2745
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247766,21 +248708,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_we
     connect \B \main_sdmem2block_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8662$2667_Y
+    connect \Y $and$ls180.v:8776$2745_Y
   end
-  attribute \src "ls180.v:8662.7-8662.119"
-  cell $and $and$ls180.v:8662$2669
+  attribute \src "ls180.v:8776.7-8776.119"
+  cell $and $and$ls180.v:8776$2747
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8662$2667_Y
-    connect \B $not$ls180.v:8662$2668_Y
-    connect \Y $and$ls180.v:8662$2669_Y
+    connect \A $and$ls180.v:8776$2745_Y
+    connect \B $not$ls180.v:8776$2746_Y
+    connect \Y $and$ls180.v:8776$2747_Y
   end
-  attribute \src "ls180.v:2810.42-2810.101"
-  cell $eq $eq$ls180.v:2810$18
+  attribute \src "ls180.v:2855.42-2855.101"
+  cell $eq $eq$ls180.v:2855$30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247788,10 +248730,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface0_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:2810$18_Y
+    connect \Y $eq$ls180.v:2855$30_Y
   end
-  attribute \src "ls180.v:2817.11-2817.54"
-  cell $eq $eq$ls180.v:2817$23
+  attribute \src "ls180.v:2862.11-2862.54"
+  cell $eq $eq$ls180.v:2862$35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247799,10 +248741,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter0_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:2817$23_Y
+    connect \Y $eq$ls180.v:2862$35_Y
   end
-  attribute \src "ls180.v:2870.42-2870.101"
-  cell $eq $eq$ls180.v:2870$29
+  attribute \src "ls180.v:2915.42-2915.101"
+  cell $eq $eq$ls180.v:2915$41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247810,10 +248752,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface1_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:2870$29_Y
+    connect \Y $eq$ls180.v:2915$41_Y
   end
-  attribute \src "ls180.v:2877.11-2877.54"
-  cell $eq $eq$ls180.v:2877$34
+  attribute \src "ls180.v:2922.11-2922.54"
+  cell $eq $eq$ls180.v:2922$46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247821,10 +248763,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter1_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:2877$34_Y
+    connect \Y $eq$ls180.v:2922$46_Y
   end
-  attribute \src "ls180.v:2930.42-2930.101"
-  cell $eq $eq$ls180.v:2930$40
+  attribute \src "ls180.v:2975.42-2975.101"
+  cell $eq $eq$ls180.v:2975$52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247832,10 +248774,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface2_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:2930$40_Y
+    connect \Y $eq$ls180.v:2975$52_Y
   end
-  attribute \src "ls180.v:2937.11-2937.54"
-  cell $eq $eq$ls180.v:2937$45
+  attribute \src "ls180.v:2982.11-2982.54"
+  cell $eq $eq$ls180.v:2982$57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247843,10 +248785,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter2_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:2937$45_Y
+    connect \Y $eq$ls180.v:2982$57_Y
   end
-  attribute \src "ls180.v:3123.34-3123.65"
-  cell $eq $eq$ls180.v:3123$73
+  attribute \src "ls180.v:3198.34-3198.65"
+  cell $eq $eq$ls180.v:3198$124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -247854,10 +248796,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_count1
     connect \B 1'0
-    connect \Y $eq$ls180.v:3123$73_Y
+    connect \Y $eq$ls180.v:3198$124_Y
   end
-  attribute \src "ls180.v:3127.68-3127.102"
-  cell $eq $eq$ls180.v:3127$76
+  attribute \src "ls180.v:3202.68-3202.102"
+  cell $eq $eq$ls180.v:3202$127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247865,10 +248807,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:3127$76_Y
+    connect \Y $eq$ls180.v:3202$127_Y
   end
-  attribute \src "ls180.v:3171.43-3171.134"
-  cell $eq $eq$ls180.v:3171$81
+  attribute \src "ls180.v:3246.43-3246.134"
+  cell $eq $eq$ls180.v:3246$132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -247876,10 +248818,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_row
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:3171$81_Y
+    connect \Y $eq$ls180.v:3246$132_Y
   end
-  attribute \src "ls180.v:3188.47-3188.88"
-  cell $eq $eq$ls180.v:3188$94
+  attribute \src "ls180.v:3263.47-3263.88"
+  cell $eq $eq$ls180.v:3263$145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247887,10 +248829,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:3188$94_Y
+    connect \Y $eq$ls180.v:3263$145_Y
   end
-  attribute \src "ls180.v:3328.43-3328.134"
-  cell $eq $eq$ls180.v:3328$111
+  attribute \src "ls180.v:3403.43-3403.134"
+  cell $eq $eq$ls180.v:3403$162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -247898,10 +248840,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_row
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:3328$111_Y
+    connect \Y $eq$ls180.v:3403$162_Y
   end
-  attribute \src "ls180.v:3345.47-3345.88"
-  cell $eq $eq$ls180.v:3345$124
+  attribute \src "ls180.v:3420.47-3420.88"
+  cell $eq $eq$ls180.v:3420$175
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247909,10 +248851,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:3345$124_Y
+    connect \Y $eq$ls180.v:3420$175_Y
   end
-  attribute \src "ls180.v:3485.43-3485.134"
-  cell $eq $eq$ls180.v:3485$141
+  attribute \src "ls180.v:3560.43-3560.134"
+  cell $eq $eq$ls180.v:3560$192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -247920,10 +248862,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_row
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:3485$141_Y
+    connect \Y $eq$ls180.v:3560$192_Y
   end
-  attribute \src "ls180.v:3502.47-3502.88"
-  cell $eq $eq$ls180.v:3502$154
+  attribute \src "ls180.v:3577.47-3577.88"
+  cell $eq $eq$ls180.v:3577$205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247931,10 +248873,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:3502$154_Y
+    connect \Y $eq$ls180.v:3577$205_Y
   end
-  attribute \src "ls180.v:3642.43-3642.134"
-  cell $eq $eq$ls180.v:3642$171
+  attribute \src "ls180.v:3717.43-3717.134"
+  cell $eq $eq$ls180.v:3717$222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -247942,10 +248884,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_row
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:3642$171_Y
+    connect \Y $eq$ls180.v:3717$222_Y
   end
-  attribute \src "ls180.v:3659.47-3659.88"
-  cell $eq $eq$ls180.v:3659$184
+  attribute \src "ls180.v:3734.47-3734.88"
+  cell $eq $eq$ls180.v:3734$235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247953,10 +248895,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:3659$184_Y
+    connect \Y $eq$ls180.v:3734$235_Y
   end
-  attribute \src "ls180.v:3796.32-3796.56"
-  cell $eq $eq$ls180.v:3796$231
+  attribute \src "ls180.v:3871.32-3871.56"
+  cell $eq $eq$ls180.v:3871$282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -247964,10 +248906,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_time0
     connect \B 1'0
-    connect \Y $eq$ls180.v:3796$231_Y
+    connect \Y $eq$ls180.v:3871$282_Y
   end
-  attribute \src "ls180.v:3797.32-3797.56"
-  cell $eq $eq$ls180.v:3797$232
+  attribute \src "ls180.v:3872.32-3872.56"
+  cell $eq $eq$ls180.v:3872$283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247975,10 +248917,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_time1
     connect \B 1'0
-    connect \Y $eq$ls180.v:3797$232_Y
+    connect \Y $eq$ls180.v:3872$283_Y
   end
-  attribute \src "ls180.v:3808.339-3808.418"
-  cell $eq $eq$ls180.v:3808$246
+  attribute \src "ls180.v:3883.339-3883.418"
+  cell $eq $eq$ls180.v:3883$297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247986,10 +248928,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_read
     connect \B \main_sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:3808$246_Y
+    connect \Y $eq$ls180.v:3883$297_Y
   end
-  attribute \src "ls180.v:3808.423-3808.504"
-  cell $eq $eq$ls180.v:3808$247
+  attribute \src "ls180.v:3883.423-3883.504"
+  cell $eq $eq$ls180.v:3883$298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247997,10 +248939,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_write
     connect \B \main_sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:3808$247_Y
+    connect \Y $eq$ls180.v:3883$298_Y
   end
-  attribute \src "ls180.v:3809.339-3809.418"
-  cell $eq $eq$ls180.v:3809$259
+  attribute \src "ls180.v:3884.339-3884.418"
+  cell $eq $eq$ls180.v:3884$310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248008,10 +248950,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_read
     connect \B \main_sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:3809$259_Y
+    connect \Y $eq$ls180.v:3884$310_Y
   end
-  attribute \src "ls180.v:3809.423-3809.504"
-  cell $eq $eq$ls180.v:3809$260
+  attribute \src "ls180.v:3884.423-3884.504"
+  cell $eq $eq$ls180.v:3884$311
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248019,10 +248961,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_write
     connect \B \main_sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:3809$260_Y
+    connect \Y $eq$ls180.v:3884$311_Y
   end
-  attribute \src "ls180.v:3810.339-3810.418"
-  cell $eq $eq$ls180.v:3810$272
+  attribute \src "ls180.v:3885.339-3885.418"
+  cell $eq $eq$ls180.v:3885$323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248030,10 +248972,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_read
     connect \B \main_sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:3810$272_Y
+    connect \Y $eq$ls180.v:3885$323_Y
   end
-  attribute \src "ls180.v:3810.423-3810.504"
-  cell $eq $eq$ls180.v:3810$273
+  attribute \src "ls180.v:3885.423-3885.504"
+  cell $eq $eq$ls180.v:3885$324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248041,10 +248983,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_write
     connect \B \main_sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:3810$273_Y
+    connect \Y $eq$ls180.v:3885$324_Y
   end
-  attribute \src "ls180.v:3811.339-3811.418"
-  cell $eq $eq$ls180.v:3811$285
+  attribute \src "ls180.v:3886.339-3886.418"
+  cell $eq $eq$ls180.v:3886$336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248052,10 +248994,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_read
     connect \B \main_sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:3811$285_Y
+    connect \Y $eq$ls180.v:3886$336_Y
   end
-  attribute \src "ls180.v:3811.423-3811.504"
-  cell $eq $eq$ls180.v:3811$286
+  attribute \src "ls180.v:3886.423-3886.504"
+  cell $eq $eq$ls180.v:3886$337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248063,10 +249005,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_write
     connect \B \main_sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:3811$286_Y
+    connect \Y $eq$ls180.v:3886$337_Y
   end
-  attribute \src "ls180.v:3841.339-3841.418"
-  cell $eq $eq$ls180.v:3841$304
+  attribute \src "ls180.v:3916.339-3916.418"
+  cell $eq $eq$ls180.v:3916$355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248074,10 +249016,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_read
     connect \B \main_sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:3841$304_Y
+    connect \Y $eq$ls180.v:3916$355_Y
   end
-  attribute \src "ls180.v:3841.423-3841.504"
-  cell $eq $eq$ls180.v:3841$305
+  attribute \src "ls180.v:3916.423-3916.504"
+  cell $eq $eq$ls180.v:3916$356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248085,10 +249027,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_is_write
     connect \B \main_sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:3841$305_Y
+    connect \Y $eq$ls180.v:3916$356_Y
   end
-  attribute \src "ls180.v:3842.339-3842.418"
-  cell $eq $eq$ls180.v:3842$317
+  attribute \src "ls180.v:3917.339-3917.418"
+  cell $eq $eq$ls180.v:3917$368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248096,10 +249038,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_read
     connect \B \main_sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:3842$317_Y
+    connect \Y $eq$ls180.v:3917$368_Y
   end
-  attribute \src "ls180.v:3842.423-3842.504"
-  cell $eq $eq$ls180.v:3842$318
+  attribute \src "ls180.v:3917.423-3917.504"
+  cell $eq $eq$ls180.v:3917$369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248107,10 +249049,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_is_write
     connect \B \main_sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:3842$318_Y
+    connect \Y $eq$ls180.v:3917$369_Y
   end
-  attribute \src "ls180.v:3843.339-3843.418"
-  cell $eq $eq$ls180.v:3843$330
+  attribute \src "ls180.v:3918.339-3918.418"
+  cell $eq $eq$ls180.v:3918$381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248118,10 +249060,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_read
     connect \B \main_sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:3843$330_Y
+    connect \Y $eq$ls180.v:3918$381_Y
   end
-  attribute \src "ls180.v:3843.423-3843.504"
-  cell $eq $eq$ls180.v:3843$331
+  attribute \src "ls180.v:3918.423-3918.504"
+  cell $eq $eq$ls180.v:3918$382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248129,10 +249071,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_is_write
     connect \B \main_sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:3843$331_Y
+    connect \Y $eq$ls180.v:3918$382_Y
   end
-  attribute \src "ls180.v:3844.339-3844.418"
-  cell $eq $eq$ls180.v:3844$343
+  attribute \src "ls180.v:3919.339-3919.418"
+  cell $eq $eq$ls180.v:3919$394
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248140,10 +249082,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_read
     connect \B \main_sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:3844$343_Y
+    connect \Y $eq$ls180.v:3919$394_Y
   end
-  attribute \src "ls180.v:3844.423-3844.504"
-  cell $eq $eq$ls180.v:3844$344
+  attribute \src "ls180.v:3919.423-3919.504"
+  cell $eq $eq$ls180.v:3919$395
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248151,10 +249093,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_is_write
     connect \B \main_sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:3844$344_Y
+    connect \Y $eq$ls180.v:3919$395_Y
   end
-  attribute \src "ls180.v:3873.78-3873.113"
-  cell $eq $eq$ls180.v:3873$353
+  attribute \src "ls180.v:3948.78-3948.113"
+  cell $eq $eq$ls180.v:3948$404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248162,10 +249104,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3873$353_Y
+    connect \Y $eq$ls180.v:3948$404_Y
   end
-  attribute \src "ls180.v:3876.78-3876.113"
-  cell $eq $eq$ls180.v:3876$356
+  attribute \src "ls180.v:3951.78-3951.113"
+  cell $eq $eq$ls180.v:3951$407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248173,10 +249115,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3876$356_Y
+    connect \Y $eq$ls180.v:3951$407_Y
   end
-  attribute \src "ls180.v:3882.78-3882.113"
-  cell $eq $eq$ls180.v:3882$360
+  attribute \src "ls180.v:3957.78-3957.113"
+  cell $eq $eq$ls180.v:3957$411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248184,10 +249126,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:3882$360_Y
+    connect \Y $eq$ls180.v:3957$411_Y
   end
-  attribute \src "ls180.v:3885.78-3885.113"
-  cell $eq $eq$ls180.v:3885$363
+  attribute \src "ls180.v:3960.78-3960.113"
+  cell $eq $eq$ls180.v:3960$414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248195,10 +249137,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:3885$363_Y
+    connect \Y $eq$ls180.v:3960$414_Y
   end
-  attribute \src "ls180.v:3891.78-3891.113"
-  cell $eq $eq$ls180.v:3891$367
+  attribute \src "ls180.v:3966.78-3966.113"
+  cell $eq $eq$ls180.v:3966$418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248206,10 +249148,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:3891$367_Y
+    connect \Y $eq$ls180.v:3966$418_Y
   end
-  attribute \src "ls180.v:3894.78-3894.113"
-  cell $eq $eq$ls180.v:3894$370
+  attribute \src "ls180.v:3969.78-3969.113"
+  cell $eq $eq$ls180.v:3969$421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248217,10 +249159,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:3894$370_Y
+    connect \Y $eq$ls180.v:3969$421_Y
   end
-  attribute \src "ls180.v:3900.78-3900.113"
-  cell $eq $eq$ls180.v:3900$374
+  attribute \src "ls180.v:3975.78-3975.113"
+  cell $eq $eq$ls180.v:3975$425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248228,10 +249170,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:3900$374_Y
+    connect \Y $eq$ls180.v:3975$425_Y
   end
-  attribute \src "ls180.v:3903.78-3903.113"
-  cell $eq $eq$ls180.v:3903$377
+  attribute \src "ls180.v:3978.78-3978.113"
+  cell $eq $eq$ls180.v:3978$428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248239,10 +249181,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:3903$377_Y
+    connect \Y $eq$ls180.v:3978$428_Y
   end
-  attribute \src "ls180.v:3984.42-3984.82"
-  cell $eq $eq$ls180.v:3984$400
+  attribute \src "ls180.v:4059.42-4059.82"
+  cell $eq $eq$ls180.v:4059$451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248250,10 +249192,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3984$400_Y
+    connect \Y $eq$ls180.v:4059$451_Y
   end
-  attribute \src "ls180.v:3984.145-3984.178"
-  cell $eq $eq$ls180.v:3984$401
+  attribute \src "ls180.v:4059.145-4059.178"
+  cell $eq $eq$ls180.v:4059$452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248261,10 +249203,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3984$401_Y
+    connect \Y $eq$ls180.v:4059$452_Y
   end
-  attribute \src "ls180.v:3984.220-3984.253"
-  cell $eq $eq$ls180.v:3984$404
+  attribute \src "ls180.v:4059.220-4059.253"
+  cell $eq $eq$ls180.v:4059$455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248272,10 +249214,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3984$404_Y
+    connect \Y $eq$ls180.v:4059$455_Y
   end
-  attribute \src "ls180.v:3984.295-3984.328"
-  cell $eq $eq$ls180.v:3984$407
+  attribute \src "ls180.v:4059.295-4059.328"
+  cell $eq $eq$ls180.v:4059$458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248283,10 +249225,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3984$407_Y
+    connect \Y $eq$ls180.v:4059$458_Y
   end
-  attribute \src "ls180.v:3989.42-3989.82"
-  cell $eq $eq$ls180.v:3989$416
+  attribute \src "ls180.v:4064.42-4064.82"
+  cell $eq $eq$ls180.v:4064$467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248294,10 +249236,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3989$416_Y
+    connect \Y $eq$ls180.v:4064$467_Y
   end
-  attribute \src "ls180.v:3989.145-3989.178"
-  cell $eq $eq$ls180.v:3989$417
+  attribute \src "ls180.v:4064.145-4064.178"
+  cell $eq $eq$ls180.v:4064$468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248305,10 +249247,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3989$417_Y
+    connect \Y $eq$ls180.v:4064$468_Y
   end
-  attribute \src "ls180.v:3989.220-3989.253"
-  cell $eq $eq$ls180.v:3989$420
+  attribute \src "ls180.v:4064.220-4064.253"
+  cell $eq $eq$ls180.v:4064$471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248316,10 +249258,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3989$420_Y
+    connect \Y $eq$ls180.v:4064$471_Y
   end
-  attribute \src "ls180.v:3989.295-3989.328"
-  cell $eq $eq$ls180.v:3989$423
+  attribute \src "ls180.v:4064.295-4064.328"
+  cell $eq $eq$ls180.v:4064$474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248327,10 +249269,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3989$423_Y
+    connect \Y $eq$ls180.v:4064$474_Y
   end
-  attribute \src "ls180.v:3994.42-3994.82"
-  cell $eq $eq$ls180.v:3994$432
+  attribute \src "ls180.v:4069.42-4069.82"
+  cell $eq $eq$ls180.v:4069$483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248338,10 +249280,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3994$432_Y
+    connect \Y $eq$ls180.v:4069$483_Y
   end
-  attribute \src "ls180.v:3994.145-3994.178"
-  cell $eq $eq$ls180.v:3994$433
+  attribute \src "ls180.v:4069.145-4069.178"
+  cell $eq $eq$ls180.v:4069$484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248349,10 +249291,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3994$433_Y
+    connect \Y $eq$ls180.v:4069$484_Y
   end
-  attribute \src "ls180.v:3994.220-3994.253"
-  cell $eq $eq$ls180.v:3994$436
+  attribute \src "ls180.v:4069.220-4069.253"
+  cell $eq $eq$ls180.v:4069$487
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248360,10 +249302,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3994$436_Y
+    connect \Y $eq$ls180.v:4069$487_Y
   end
-  attribute \src "ls180.v:3994.295-3994.328"
-  cell $eq $eq$ls180.v:3994$439
+  attribute \src "ls180.v:4069.295-4069.328"
+  cell $eq $eq$ls180.v:4069$490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248371,10 +249313,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3994$439_Y
+    connect \Y $eq$ls180.v:4069$490_Y
   end
-  attribute \src "ls180.v:3999.42-3999.82"
-  cell $eq $eq$ls180.v:3999$448
+  attribute \src "ls180.v:4074.42-4074.82"
+  cell $eq $eq$ls180.v:4074$499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248382,10 +249324,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3999$448_Y
+    connect \Y $eq$ls180.v:4074$499_Y
   end
-  attribute \src "ls180.v:3999.145-3999.178"
-  cell $eq $eq$ls180.v:3999$449
+  attribute \src "ls180.v:4074.145-4074.178"
+  cell $eq $eq$ls180.v:4074$500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248393,10 +249335,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3999$449_Y
+    connect \Y $eq$ls180.v:4074$500_Y
   end
-  attribute \src "ls180.v:3999.220-3999.253"
-  cell $eq $eq$ls180.v:3999$452
+  attribute \src "ls180.v:4074.220-4074.253"
+  cell $eq $eq$ls180.v:4074$503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248404,10 +249346,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3999$452_Y
+    connect \Y $eq$ls180.v:4074$503_Y
   end
-  attribute \src "ls180.v:3999.295-3999.328"
-  cell $eq $eq$ls180.v:3999$455
+  attribute \src "ls180.v:4074.295-4074.328"
+  cell $eq $eq$ls180.v:4074$506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248415,10 +249357,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3999$455_Y
+    connect \Y $eq$ls180.v:4074$506_Y
   end
-  attribute \src "ls180.v:4004.44-4004.77"
-  cell $eq $eq$ls180.v:4004$464
+  attribute \src "ls180.v:4079.44-4079.77"
+  cell $eq $eq$ls180.v:4079$515
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248426,10 +249368,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$464_Y
+    connect \Y $eq$ls180.v:4079$515_Y
   end
-  attribute \src "ls180.v:4004.83-4004.123"
-  cell $eq $eq$ls180.v:4004$465
+  attribute \src "ls180.v:4079.83-4079.123"
+  cell $eq $eq$ls180.v:4079$516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248437,10 +249379,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$465_Y
+    connect \Y $eq$ls180.v:4079$516_Y
   end
-  attribute \src "ls180.v:4004.186-4004.219"
-  cell $eq $eq$ls180.v:4004$466
+  attribute \src "ls180.v:4079.186-4079.219"
+  cell $eq $eq$ls180.v:4079$517
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248448,10 +249390,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$466_Y
+    connect \Y $eq$ls180.v:4079$517_Y
   end
-  attribute \src "ls180.v:4004.261-4004.294"
-  cell $eq $eq$ls180.v:4004$469
+  attribute \src "ls180.v:4079.261-4079.294"
+  cell $eq $eq$ls180.v:4079$520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248459,10 +249401,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$469_Y
+    connect \Y $eq$ls180.v:4079$520_Y
   end
-  attribute \src "ls180.v:4004.336-4004.369"
-  cell $eq $eq$ls180.v:4004$472
+  attribute \src "ls180.v:4079.336-4079.369"
+  cell $eq $eq$ls180.v:4079$523
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248470,10 +249412,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$472_Y
+    connect \Y $eq$ls180.v:4079$523_Y
   end
-  attribute \src "ls180.v:4004.418-4004.451"
-  cell $eq $eq$ls180.v:4004$480
+  attribute \src "ls180.v:4079.418-4079.451"
+  cell $eq $eq$ls180.v:4079$531
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248481,10 +249423,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$480_Y
+    connect \Y $eq$ls180.v:4079$531_Y
   end
-  attribute \src "ls180.v:4004.457-4004.497"
-  cell $eq $eq$ls180.v:4004$481
+  attribute \src "ls180.v:4079.457-4079.497"
+  cell $eq $eq$ls180.v:4079$532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248492,10 +249434,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:4004$481_Y
+    connect \Y $eq$ls180.v:4079$532_Y
   end
-  attribute \src "ls180.v:4004.560-4004.593"
-  cell $eq $eq$ls180.v:4004$482
+  attribute \src "ls180.v:4079.560-4079.593"
+  cell $eq $eq$ls180.v:4079$533
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248503,10 +249445,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$482_Y
+    connect \Y $eq$ls180.v:4079$533_Y
   end
-  attribute \src "ls180.v:4004.635-4004.668"
-  cell $eq $eq$ls180.v:4004$485
+  attribute \src "ls180.v:4079.635-4079.668"
+  cell $eq $eq$ls180.v:4079$536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248514,10 +249456,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$485_Y
+    connect \Y $eq$ls180.v:4079$536_Y
   end
-  attribute \src "ls180.v:4004.710-4004.743"
-  cell $eq $eq$ls180.v:4004$488
+  attribute \src "ls180.v:4079.710-4079.743"
+  cell $eq $eq$ls180.v:4079$539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248525,10 +249467,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$488_Y
+    connect \Y $eq$ls180.v:4079$539_Y
   end
-  attribute \src "ls180.v:4004.792-4004.825"
-  cell $eq $eq$ls180.v:4004$496
+  attribute \src "ls180.v:4079.792-4079.825"
+  cell $eq $eq$ls180.v:4079$547
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248536,10 +249478,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$496_Y
+    connect \Y $eq$ls180.v:4079$547_Y
   end
-  attribute \src "ls180.v:4004.831-4004.871"
-  cell $eq $eq$ls180.v:4004$497
+  attribute \src "ls180.v:4079.831-4079.871"
+  cell $eq $eq$ls180.v:4079$548
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248547,10 +249489,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:4004$497_Y
+    connect \Y $eq$ls180.v:4079$548_Y
   end
-  attribute \src "ls180.v:4004.934-4004.967"
-  cell $eq $eq$ls180.v:4004$498
+  attribute \src "ls180.v:4079.934-4079.967"
+  cell $eq $eq$ls180.v:4079$549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248558,10 +249500,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$498_Y
+    connect \Y $eq$ls180.v:4079$549_Y
   end
-  attribute \src "ls180.v:4004.1009-4004.1042"
-  cell $eq $eq$ls180.v:4004$501
+  attribute \src "ls180.v:4079.1009-4079.1042"
+  cell $eq $eq$ls180.v:4079$552
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248569,10 +249511,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$501_Y
+    connect \Y $eq$ls180.v:4079$552_Y
   end
-  attribute \src "ls180.v:4004.1084-4004.1117"
-  cell $eq $eq$ls180.v:4004$504
+  attribute \src "ls180.v:4079.1084-4079.1117"
+  cell $eq $eq$ls180.v:4079$555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248580,10 +249522,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$504_Y
+    connect \Y $eq$ls180.v:4079$555_Y
   end
-  attribute \src "ls180.v:4004.1166-4004.1199"
-  cell $eq $eq$ls180.v:4004$512
+  attribute \src "ls180.v:4079.1166-4079.1199"
+  cell $eq $eq$ls180.v:4079$563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248591,10 +249533,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$512_Y
+    connect \Y $eq$ls180.v:4079$563_Y
   end
-  attribute \src "ls180.v:4004.1205-4004.1245"
-  cell $eq $eq$ls180.v:4004$513
+  attribute \src "ls180.v:4079.1205-4079.1245"
+  cell $eq $eq$ls180.v:4079$564
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248602,10 +249544,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:4004$513_Y
+    connect \Y $eq$ls180.v:4079$564_Y
   end
-  attribute \src "ls180.v:4004.1308-4004.1341"
-  cell $eq $eq$ls180.v:4004$514
+  attribute \src "ls180.v:4079.1308-4079.1341"
+  cell $eq $eq$ls180.v:4079$565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248613,10 +249555,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$514_Y
+    connect \Y $eq$ls180.v:4079$565_Y
   end
-  attribute \src "ls180.v:4004.1383-4004.1416"
-  cell $eq $eq$ls180.v:4004$517
+  attribute \src "ls180.v:4079.1383-4079.1416"
+  cell $eq $eq$ls180.v:4079$568
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248624,10 +249566,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$517_Y
+    connect \Y $eq$ls180.v:4079$568_Y
   end
-  attribute \src "ls180.v:4004.1458-4004.1491"
-  cell $eq $eq$ls180.v:4004$520
+  attribute \src "ls180.v:4079.1458-4079.1491"
+  cell $eq $eq$ls180.v:4079$571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248635,10 +249577,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4004$520_Y
+    connect \Y $eq$ls180.v:4079$571_Y
   end
-  attribute \src "ls180.v:4063.29-4063.57"
-  cell $eq $eq$ls180.v:4063$533
+  attribute \src "ls180.v:4138.29-4138.57"
+  cell $eq $eq$ls180.v:4138$584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -248646,10 +249588,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:4063$533_Y
+    connect \Y $eq$ls180.v:4138$584_Y
   end
-  attribute \src "ls180.v:4070.11-4070.41"
-  cell $eq $eq$ls180.v:4070$538
+  attribute \src "ls180.v:4145.11-4145.41"
+  cell $eq $eq$ls180.v:4145$589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248657,76 +249599,76 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_converter_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:4070$538_Y
+    connect \Y $eq$ls180.v:4145$589_Y
   end
-  attribute \src "ls180.v:4227.37-4227.111"
-  cell $eq $eq$ls180.v:4227$603
+  attribute \src "ls180.v:4302.37-4302.111"
+  cell $eq $eq$ls180.v:4302$654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 16
     parameter \Y_WIDTH 1
     connect \A \main_spimaster30_clk_divider
-    connect \B $sub$ls180.v:4227$602_Y
-    connect \Y $eq$ls180.v:4227$603_Y
+    connect \B $sub$ls180.v:4302$653_Y
+    connect \Y $eq$ls180.v:4302$654_Y
   end
-  attribute \src "ls180.v:4228.37-4228.105"
-  cell $eq $eq$ls180.v:4228$605
+  attribute \src "ls180.v:4303.37-4303.105"
+  cell $eq $eq$ls180.v:4303$656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 16
     parameter \Y_WIDTH 1
     connect \A \main_spimaster30_clk_divider
-    connect \B $sub$ls180.v:4228$604_Y
-    connect \Y $eq$ls180.v:4228$605_Y
+    connect \B $sub$ls180.v:4303$655_Y
+    connect \Y $eq$ls180.v:4303$656_Y
   end
-  attribute \src "ls180.v:4255.10-4255.67"
-  cell $eq $eq$ls180.v:4255$609
+  attribute \src "ls180.v:4330.10-4330.67"
+  cell $eq $eq$ls180.v:4330$660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \main_spimaster27_count
-    connect \B $sub$ls180.v:4255$608_Y
-    connect \Y $eq$ls180.v:4255$609_Y
+    connect \B $sub$ls180.v:4330$659_Y
+    connect \Y $eq$ls180.v:4330$660_Y
   end
-  attribute \src "ls180.v:4285.35-4285.108"
-  cell $eq $eq$ls180.v:4285$611
+  attribute \src "ls180.v:4360.35-4360.108"
+  cell $eq $eq$ls180.v:4360$662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 16
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_clk_divider1
-    connect \B $sub$ls180.v:4285$610_Y
-    connect \Y $eq$ls180.v:4285$611_Y
+    connect \B $sub$ls180.v:4360$661_Y
+    connect \Y $eq$ls180.v:4360$662_Y
   end
-  attribute \src "ls180.v:4286.35-4286.102"
-  cell $eq $eq$ls180.v:4286$613
+  attribute \src "ls180.v:4361.35-4361.102"
+  cell $eq $eq$ls180.v:4361$664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 16
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_clk_divider1
-    connect \B $sub$ls180.v:4286$612_Y
-    connect \Y $eq$ls180.v:4286$613_Y
+    connect \B $sub$ls180.v:4361$663_Y
+    connect \Y $eq$ls180.v:4361$664_Y
   end
-  attribute \src "ls180.v:4314.10-4314.65"
-  cell $eq $eq$ls180.v:4314$617
+  attribute \src "ls180.v:4389.10-4389.65"
+  cell $eq $eq$ls180.v:4389$668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_count
-    connect \B $sub$ls180.v:4314$616_Y
-    connect \Y $eq$ls180.v:4314$617_Y
+    connect \B $sub$ls180.v:4389$667_Y
+    connect \Y $eq$ls180.v:4389$668_Y
   end
-  attribute \src "ls180.v:4418.10-4418.40"
-  cell $eq $eq$ls180.v:4418$644
+  attribute \src "ls180.v:4493.10-4493.40"
+  cell $eq $eq$ls180.v:4493$695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248734,10 +249676,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_init_count
     connect \B 7'1001111
-    connect \Y $eq$ls180.v:4418$644_Y
+    connect \Y $eq$ls180.v:4493$695_Y
   end
-  attribute \src "ls180.v:4475.10-4475.39"
-  cell $eq $eq$ls180.v:4475$647
+  attribute \src "ls180.v:4550.10-4550.39"
+  cell $eq $eq$ls180.v:4550$698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248745,10 +249687,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdw_count
     connect \B 3'111
-    connect \Y $eq$ls180.v:4475$647_Y
+    connect \Y $eq$ls180.v:4550$698_Y
   end
-  attribute \src "ls180.v:4492.10-4492.39"
-  cell $eq $eq$ls180.v:4492$649
+  attribute \src "ls180.v:4567.10-4567.39"
+  cell $eq $eq$ls180.v:4567$700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248756,10 +249698,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdw_count
     connect \B 3'111
-    connect \Y $eq$ls180.v:4492$649_Y
+    connect \Y $eq$ls180.v:4567$700_Y
   end
-  attribute \src "ls180.v:4520.38-4520.88"
-  cell $eq $eq$ls180.v:4520$651
+  attribute \src "ls180.v:4595.38-4595.88"
+  cell $eq $eq$ls180.v:4595$702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248767,10 +249709,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
     connect \B 1'0
-    connect \Y $eq$ls180.v:4520$651_Y
+    connect \Y $eq$ls180.v:4595$702_Y
   end
-  attribute \src "ls180.v:4570.9-4570.40"
-  cell $eq $eq$ls180.v:4570$661
+  attribute \src "ls180.v:4645.9-4645.40"
+  cell $eq $eq$ls180.v:4645$712
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -248778,21 +249720,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_timeout
     connect \B 1'0
-    connect \Y $eq$ls180.v:4570$661_Y
+    connect \Y $eq$ls180.v:4645$712_Y
   end
-  attribute \src "ls180.v:4579.36-4579.105"
-  cell $eq $eq$ls180.v:4579$663
+  attribute \src "ls180.v:4654.36-4654.105"
+  cell $eq $eq$ls180.v:4654$714
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_count
-    connect \B $sub$ls180.v:4579$662_Y
-    connect \Y $eq$ls180.v:4579$663_Y
+    connect \B $sub$ls180.v:4654$713_Y
+    connect \Y $eq$ls180.v:4654$714_Y
   end
-  attribute \src "ls180.v:4598.9-4598.40"
-  cell $eq $eq$ls180.v:4598$667
+  attribute \src "ls180.v:4673.9-4673.40"
+  cell $eq $eq$ls180.v:4673$718
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -248800,10 +249742,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_timeout
     connect \B 1'0
-    connect \Y $eq$ls180.v:4598$667_Y
+    connect \Y $eq$ls180.v:4673$718_Y
   end
-  attribute \src "ls180.v:4610.10-4610.39"
-  cell $eq $eq$ls180.v:4610$669
+  attribute \src "ls180.v:4685.10-4685.39"
+  cell $eq $eq$ls180.v:4685$720
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248811,10 +249753,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_count
     connect \B 3'111
-    connect \Y $eq$ls180.v:4610$669_Y
+    connect \Y $eq$ls180.v:4685$720_Y
   end
-  attribute \src "ls180.v:4647.39-4647.94"
-  cell $eq $eq$ls180.v:4647$673
+  attribute \src "ls180.v:4722.39-4722.94"
+  cell $eq $eq$ls180.v:4722$724
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248822,10 +249764,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:4647$673_Y
+    connect \Y $eq$ls180.v:4722$724_Y
   end
-  attribute \src "ls180.v:4684.32-4684.89"
-  cell $eq $eq$ls180.v:4684$682
+  attribute \src "ls180.v:4759.32-4759.89"
+  cell $eq $eq$ls180.v:4759$733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248833,10 +249775,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
     connect \B 3'101
-    connect \Y $eq$ls180.v:4684$682_Y
+    connect \Y $eq$ls180.v:4759$733_Y
   end
-  attribute \src "ls180.v:4732.10-4732.40"
-  cell $eq $eq$ls180.v:4732$686
+  attribute \src "ls180.v:4807.10-4807.40"
+  cell $eq $eq$ls180.v:4807$737
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -248844,10 +249786,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4732$686_Y
+    connect \Y $eq$ls180.v:4807$737_Y
   end
-  attribute \src "ls180.v:4781.40-4781.98"
-  cell $eq $eq$ls180.v:4781$688
+  attribute \src "ls180.v:4856.40-4856.98"
+  cell $eq $eq$ls180.v:4856$739
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -248855,10 +249797,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_pads_in_payload_data_i
     connect \B 1'0
-    connect \Y $eq$ls180.v:4781$688_Y
+    connect \Y $eq$ls180.v:4856$739_Y
   end
-  attribute \src "ls180.v:4832.9-4832.41"
-  cell $eq $eq$ls180.v:4832$698
+  attribute \src "ls180.v:4907.9-4907.41"
+  cell $eq $eq$ls180.v:4907$749
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -248866,21 +249808,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_timeout
     connect \B 1'0
-    connect \Y $eq$ls180.v:4832$698_Y
+    connect \Y $eq$ls180.v:4907$749_Y
   end
-  attribute \src "ls180.v:4841.37-4841.123"
-  cell $eq $eq$ls180.v:4841$701
+  attribute \src "ls180.v:4916.37-4916.123"
+  cell $eq $eq$ls180.v:4916$752
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 10
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_count
-    connect \B $sub$ls180.v:4841$700_Y
-    connect \Y $eq$ls180.v:4841$701_Y
+    connect \B $sub$ls180.v:4916$751_Y
+    connect \Y $eq$ls180.v:4916$752_Y
   end
-  attribute \src "ls180.v:4864.9-4864.41"
-  cell $eq $eq$ls180.v:4864$704
+  attribute \src "ls180.v:4939.9-4939.41"
+  cell $eq $eq$ls180.v:4939$755
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -248888,10 +249830,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_timeout
     connect \B 1'0
-    connect \Y $eq$ls180.v:4864$704_Y
+    connect \Y $eq$ls180.v:4939$755_Y
   end
-  attribute \src "ls180.v:4874.10-4874.41"
-  cell $eq $eq$ls180.v:4874$706
+  attribute \src "ls180.v:4949.10-4949.41"
+  cell $eq $eq$ls180.v:4949$757
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -248899,10 +249841,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_count
     connect \B 6'100111
-    connect \Y $eq$ls180.v:4874$706_Y
+    connect \Y $eq$ls180.v:4949$757_Y
   end
-  attribute \src "ls180.v:5043.9-5043.47"
-  cell $eq $eq$ls180.v:5043$888
+  attribute \src "ls180.v:5118.9-5118.47"
+  cell $eq $eq$ls180.v:5118$939
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -248910,10 +249852,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5043$888_Y
+    connect \Y $eq$ls180.v:5118$939_Y
   end
-  attribute \src "ls180.v:5073.10-5073.48"
-  cell $eq $eq$ls180.v:5073$889
+  attribute \src "ls180.v:5148.10-5148.48"
+  cell $eq $eq$ls180.v:5148$940
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -248921,10 +249863,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5073$889_Y
+    connect \Y $eq$ls180.v:5148$940_Y
   end
-  attribute \src "ls180.v:5104.10-5104.78"
-  cell $eq $eq$ls180.v:5104$894
+  attribute \src "ls180.v:5179.10-5179.78"
+  cell $eq $eq$ls180.v:5179$945
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -248932,10 +249874,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_fifo0
     connect \B \main_sdcore_crc16_checker_crctmp0
-    connect \Y $eq$ls180.v:5104$894_Y
+    connect \Y $eq$ls180.v:5179$945_Y
   end
-  attribute \src "ls180.v:5104.83-5104.151"
-  cell $eq $eq$ls180.v:5104$895
+  attribute \src "ls180.v:5179.83-5179.151"
+  cell $eq $eq$ls180.v:5179$946
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -248943,10 +249885,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_fifo1
     connect \B \main_sdcore_crc16_checker_crctmp1
-    connect \Y $eq$ls180.v:5104$895_Y
+    connect \Y $eq$ls180.v:5179$946_Y
   end
-  attribute \src "ls180.v:5104.157-5104.225"
-  cell $eq $eq$ls180.v:5104$897
+  attribute \src "ls180.v:5179.157-5179.225"
+  cell $eq $eq$ls180.v:5179$948
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -248954,10 +249896,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_fifo2
     connect \B \main_sdcore_crc16_checker_crctmp2
-    connect \Y $eq$ls180.v:5104$897_Y
+    connect \Y $eq$ls180.v:5179$948_Y
   end
-  attribute \src "ls180.v:5104.231-5104.299"
-  cell $eq $eq$ls180.v:5104$899
+  attribute \src "ls180.v:5179.231-5179.299"
+  cell $eq $eq$ls180.v:5179$950
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -248965,10 +249907,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_fifo3
     connect \B \main_sdcore_crc16_checker_crctmp3
-    connect \Y $eq$ls180.v:5104$899_Y
+    connect \Y $eq$ls180.v:5179$950_Y
   end
-  attribute \src "ls180.v:5112.7-5112.44"
-  cell $eq $eq$ls180.v:5112$903
+  attribute \src "ls180.v:5187.7-5187.44"
+  cell $eq $eq$ls180.v:5187$954
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -248976,10 +249918,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5112$903_Y
+    connect \Y $eq$ls180.v:5187$954_Y
   end
-  attribute \src "ls180.v:5122.7-5122.44"
-  cell $eq $eq$ls180.v:5122$906
+  attribute \src "ls180.v:5197.7-5197.44"
+  cell $eq $eq$ls180.v:5197$957
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -248987,10 +249929,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5122$906_Y
+    connect \Y $eq$ls180.v:5197$957_Y
   end
-  attribute \src "ls180.v:5132.7-5132.44"
-  cell $eq $eq$ls180.v:5132$909
+  attribute \src "ls180.v:5207.7-5207.44"
+  cell $eq $eq$ls180.v:5207$960
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -248998,10 +249940,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5132$909_Y
+    connect \Y $eq$ls180.v:5207$960_Y
   end
-  attribute \src "ls180.v:5142.7-5142.44"
-  cell $eq $eq$ls180.v:5142$912
+  attribute \src "ls180.v:5217.7-5217.44"
+  cell $eq $eq$ls180.v:5217$963
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249009,10 +249951,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 3'111
-    connect \Y $eq$ls180.v:5142$912_Y
+    connect \Y $eq$ls180.v:5217$963_Y
   end
-  attribute \src "ls180.v:5266.36-5266.64"
-  cell $eq $eq$ls180.v:5266$963
+  attribute \src "ls180.v:5341.36-5341.64"
+  cell $eq $eq$ls180.v:5341$1014
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249020,10 +249962,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_cmd_type
     connect \B 1'0
-    connect \Y $eq$ls180.v:5266$963_Y
+    connect \Y $eq$ls180.v:5341$1014_Y
   end
-  attribute \src "ls180.v:5272.10-5272.39"
-  cell $eq $eq$ls180.v:5272$966
+  attribute \src "ls180.v:5347.10-5347.39"
+  cell $eq $eq$ls180.v:5347$1017
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249031,10 +249973,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_cmd_count
     connect \B 3'101
-    connect \Y $eq$ls180.v:5272$966_Y
+    connect \Y $eq$ls180.v:5347$1017_Y
   end
-  attribute \src "ls180.v:5273.11-5273.39"
-  cell $eq $eq$ls180.v:5273$967
+  attribute \src "ls180.v:5348.11-5348.39"
+  cell $eq $eq$ls180.v:5348$1018
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249042,10 +249984,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_cmd_type
     connect \B 1'0
-    connect \Y $eq$ls180.v:5273$967_Y
+    connect \Y $eq$ls180.v:5348$1018_Y
   end
-  attribute \src "ls180.v:5285.34-5285.63"
-  cell $eq $eq$ls180.v:5285$968
+  attribute \src "ls180.v:5360.34-5360.63"
+  cell $eq $eq$ls180.v:5360$1019
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249053,10 +249995,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_type
     connect \B 1'0
-    connect \Y $eq$ls180.v:5285$968_Y
+    connect \Y $eq$ls180.v:5360$1019_Y
   end
-  attribute \src "ls180.v:5286.9-5286.37"
-  cell $eq $eq$ls180.v:5286$969
+  attribute \src "ls180.v:5361.9-5361.37"
+  cell $eq $eq$ls180.v:5361$1020
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249064,10 +250006,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_cmd_type
     connect \B 2'10
-    connect \Y $eq$ls180.v:5286$969_Y
+    connect \Y $eq$ls180.v:5361$1020_Y
   end
-  attribute \src "ls180.v:5293.10-5293.55"
-  cell $eq $eq$ls180.v:5293$970
+  attribute \src "ls180.v:5368.10-5368.55"
+  cell $eq $eq$ls180.v:5368$1021
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249075,10 +250017,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_source_payload_status
     connect \B 1'1
-    connect \Y $eq$ls180.v:5293$970_Y
+    connect \Y $eq$ls180.v:5368$1021_Y
   end
-  attribute \src "ls180.v:5299.12-5299.41"
-  cell $eq $eq$ls180.v:5299$971
+  attribute \src "ls180.v:5374.12-5374.41"
+  cell $eq $eq$ls180.v:5374$1022
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249086,10 +250028,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_type
     connect \B 2'10
-    connect \Y $eq$ls180.v:5299$971_Y
+    connect \Y $eq$ls180.v:5374$1022_Y
   end
-  attribute \src "ls180.v:5302.13-5302.42"
-  cell $eq $eq$ls180.v:5302$972
+  attribute \src "ls180.v:5377.13-5377.42"
+  cell $eq $eq$ls180.v:5377$1023
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249097,32 +250039,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_type
     connect \B 1'1
-    connect \Y $eq$ls180.v:5302$972_Y
+    connect \Y $eq$ls180.v:5377$1023_Y
   end
-  attribute \src "ls180.v:5324.10-5324.76"
-  cell $eq $eq$ls180.v:5324$977
+  attribute \src "ls180.v:5399.10-5399.76"
+  cell $eq $eq$ls180.v:5399$1028
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_count
-    connect \B $sub$ls180.v:5324$976_Y
-    connect \Y $eq$ls180.v:5324$977_Y
+    connect \B $sub$ls180.v:5399$1027_Y
+    connect \Y $eq$ls180.v:5399$1028_Y
   end
-  attribute \src "ls180.v:5339.35-5339.101"
-  cell $eq $eq$ls180.v:5339$980
+  attribute \src "ls180.v:5414.35-5414.101"
+  cell $eq $eq$ls180.v:5414$1031
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_count
-    connect \B $sub$ls180.v:5339$979_Y
-    connect \Y $eq$ls180.v:5339$980_Y
+    connect \B $sub$ls180.v:5414$1030_Y
+    connect \Y $eq$ls180.v:5414$1031_Y
   end
-  attribute \src "ls180.v:5341.10-5341.56"
-  cell $eq $eq$ls180.v:5341$981
+  attribute \src "ls180.v:5416.10-5416.56"
+  cell $eq $eq$ls180.v:5416$1032
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249130,21 +250072,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_source_payload_status
     connect \B 1'0
-    connect \Y $eq$ls180.v:5341$981_Y
+    connect \Y $eq$ls180.v:5416$1032_Y
   end
-  attribute \src "ls180.v:5350.12-5350.78"
-  cell $eq $eq$ls180.v:5350$985
+  attribute \src "ls180.v:5425.12-5425.78"
+  cell $eq $eq$ls180.v:5425$1036
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_data_count
-    connect \B $sub$ls180.v:5350$984_Y
-    connect \Y $eq$ls180.v:5350$985_Y
+    connect \B $sub$ls180.v:5425$1035_Y
+    connect \Y $eq$ls180.v:5425$1036_Y
   end
-  attribute \src "ls180.v:5357.11-5357.57"
-  cell $eq $eq$ls180.v:5357$986
+  attribute \src "ls180.v:5432.11-5432.57"
+  cell $eq $eq$ls180.v:5432$1037
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249152,32 +250094,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_source_payload_status
     connect \B 1'1
-    connect \Y $eq$ls180.v:5357$986_Y
+    connect \Y $eq$ls180.v:5432$1037_Y
   end
-  attribute \src "ls180.v:5474.10-5474.105"
-  cell $eq $eq$ls180.v:5474$1003
+  attribute \src "ls180.v:5549.10-5549.105"
+  cell $eq $eq$ls180.v:5549$1054
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_wishbonedmawriter_offset
-    connect \B $sub$ls180.v:5474$1002_Y
-    connect \Y $eq$ls180.v:5474$1003_Y
+    connect \B $sub$ls180.v:5549$1053_Y
+    connect \Y $eq$ls180.v:5549$1054_Y
   end
-  attribute \src "ls180.v:5564.39-5564.106"
-  cell $eq $eq$ls180.v:5564$1009
+  attribute \src "ls180.v:5639.39-5639.106"
+  cell $eq $eq$ls180.v:5639$1060
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_dma_offset
-    connect \B $sub$ls180.v:5564$1008_Y
-    connect \Y $eq$ls180.v:5564$1009_Y
+    connect \B $sub$ls180.v:5639$1059_Y
+    connect \Y $eq$ls180.v:5639$1060_Y
   end
-  attribute \src "ls180.v:5594.44-5594.82"
-  cell $eq $eq$ls180.v:5594$1012
+  attribute \src "ls180.v:5669.44-5669.82"
+  cell $eq $eq$ls180.v:5669$1063
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249185,10 +250127,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_mux
     connect \B 1'0
-    connect \Y $eq$ls180.v:5594$1012_Y
+    connect \Y $eq$ls180.v:5669$1063_Y
   end
-  attribute \src "ls180.v:5595.43-5595.81"
-  cell $eq $eq$ls180.v:5595$1013
+  attribute \src "ls180.v:5670.43-5670.81"
+  cell $eq $eq$ls180.v:5670$1064
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -249196,10 +250138,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_mux
     connect \B 2'11
-    connect \Y $eq$ls180.v:5595$1013_Y
+    connect \Y $eq$ls180.v:5670$1064_Y
   end
-  attribute \src "ls180.v:5695.85-5695.106"
-  cell $eq $eq$ls180.v:5695$1029
+  attribute \src "ls180.v:5770.85-5770.106"
+  cell $eq $eq$ls180.v:5770$1080
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249207,10 +250149,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:5695$1029_Y
+    connect \Y $eq$ls180.v:5770$1080_Y
   end
-  attribute \src "ls180.v:5696.85-5696.106"
-  cell $eq $eq$ls180.v:5696$1031
+  attribute \src "ls180.v:5771.85-5771.106"
+  cell $eq $eq$ls180.v:5771$1082
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249218,10 +250160,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:5696$1031_Y
+    connect \Y $eq$ls180.v:5771$1082_Y
   end
-  attribute \src "ls180.v:5697.85-5697.106"
-  cell $eq $eq$ls180.v:5697$1033
+  attribute \src "ls180.v:5772.85-5772.106"
+  cell $eq $eq$ls180.v:5772$1084
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249229,10 +250171,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:5697$1033_Y
+    connect \Y $eq$ls180.v:5772$1084_Y
   end
-  attribute \src "ls180.v:5698.57-5698.78"
-  cell $eq $eq$ls180.v:5698$1035
+  attribute \src "ls180.v:5773.57-5773.78"
+  cell $eq $eq$ls180.v:5773$1086
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249240,10 +250182,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:5698$1035_Y
+    connect \Y $eq$ls180.v:5773$1086_Y
   end
-  attribute \src "ls180.v:5699.57-5699.78"
-  cell $eq $eq$ls180.v:5699$1037
+  attribute \src "ls180.v:5774.57-5774.78"
+  cell $eq $eq$ls180.v:5774$1088
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249251,10 +250193,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 3'100
-    connect \Y $eq$ls180.v:5699$1037_Y
+    connect \Y $eq$ls180.v:5774$1088_Y
   end
-  attribute \src "ls180.v:5700.85-5700.106"
-  cell $eq $eq$ls180.v:5700$1039
+  attribute \src "ls180.v:5775.85-5775.106"
+  cell $eq $eq$ls180.v:5775$1090
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249262,10 +250204,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:5700$1039_Y
+    connect \Y $eq$ls180.v:5775$1090_Y
   end
-  attribute \src "ls180.v:5701.85-5701.106"
-  cell $eq $eq$ls180.v:5701$1041
+  attribute \src "ls180.v:5776.85-5776.106"
+  cell $eq $eq$ls180.v:5776$1092
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249273,10 +250215,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:5701$1041_Y
+    connect \Y $eq$ls180.v:5776$1092_Y
   end
-  attribute \src "ls180.v:5702.85-5702.106"
-  cell $eq $eq$ls180.v:5702$1043
+  attribute \src "ls180.v:5777.85-5777.106"
+  cell $eq $eq$ls180.v:5777$1094
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249284,10 +250226,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:5702$1043_Y
+    connect \Y $eq$ls180.v:5777$1094_Y
   end
-  attribute \src "ls180.v:5703.57-5703.78"
-  cell $eq $eq$ls180.v:5703$1045
+  attribute \src "ls180.v:5778.57-5778.78"
+  cell $eq $eq$ls180.v:5778$1096
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249295,10 +250237,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:5703$1045_Y
+    connect \Y $eq$ls180.v:5778$1096_Y
   end
-  attribute \src "ls180.v:5704.57-5704.78"
-  cell $eq $eq$ls180.v:5704$1047
+  attribute \src "ls180.v:5779.57-5779.78"
+  cell $eq $eq$ls180.v:5779$1098
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249306,10 +250248,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_grant
     connect \B 3'100
-    connect \Y $eq$ls180.v:5704$1047_Y
+    connect \Y $eq$ls180.v:5779$1098_Y
   end
-  attribute \src "ls180.v:5708.27-5708.59"
-  cell $eq $eq$ls180.v:5708$1050
+  attribute \src "ls180.v:5783.27-5783.59"
+  cell $eq $eq$ls180.v:5783$1101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 23
     parameter \B_SIGNED 0
@@ -249317,10 +250259,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_adr [29:7]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5708$1050_Y
+    connect \Y $eq$ls180.v:5783$1101_Y
   end
-  attribute \src "ls180.v:5709.27-5709.68"
-  cell $eq $eq$ls180.v:5709$1051
+  attribute \src "ls180.v:5784.27-5784.59"
+  cell $eq $eq$ls180.v:5784$1102
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 23
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_adr [29:7]
+    connect \B 4'1000
+    connect \Y $eq$ls180.v:5784$1102_Y
+  end
+  attribute \src "ls180.v:5785.27-5785.60"
+  cell $eq $eq$ls180.v:5785$1103
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 23
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_adr [29:7]
+    connect \B 5'10000
+    connect \Y $eq$ls180.v:5785$1103_Y
+  end
+  attribute \src "ls180.v:5786.27-5786.60"
+  cell $eq $eq$ls180.v:5786$1104
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 23
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 1
+    connect \A \builder_shared_adr [29:7]
+    connect \B 5'11000
+    connect \Y $eq$ls180.v:5786$1104_Y
+  end
+  attribute \src "ls180.v:5787.27-5787.68"
+  cell $eq $eq$ls180.v:5787$1105
     parameter \A_SIGNED 0
     parameter \A_WIDTH 27
     parameter \B_SIGNED 0
@@ -249328,10 +250303,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_adr [29:3]
     connect \B 27'110000000000000100000000000
-    connect \Y $eq$ls180.v:5709$1051_Y
+    connect \Y $eq$ls180.v:5787$1105_Y
   end
-  attribute \src "ls180.v:5710.27-5710.66"
-  cell $eq $eq$ls180.v:5710$1052
+  attribute \src "ls180.v:5788.27-5788.66"
+  cell $eq $eq$ls180.v:5788$1106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -249339,10 +250314,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_adr [29:10]
     connect \B 20'11000000000000010001
-    connect \Y $eq$ls180.v:5710$1052_Y
+    connect \Y $eq$ls180.v:5788$1106_Y
   end
-  attribute \src "ls180.v:5711.27-5711.61"
-  cell $eq $eq$ls180.v:5711$1053
+  attribute \src "ls180.v:5789.27-5789.61"
+  cell $eq $eq$ls180.v:5789$1107
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -249350,10 +250325,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_adr [29:23]
     connect \B 7'1001000
-    connect \Y $eq$ls180.v:5711$1053_Y
+    connect \Y $eq$ls180.v:5789$1107_Y
   end
-  attribute \src "ls180.v:5712.27-5712.65"
-  cell $eq $eq$ls180.v:5712$1054
+  attribute \src "ls180.v:5790.27-5790.65"
+  cell $eq $eq$ls180.v:5790$1108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -249361,10 +250336,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_shared_adr [29:14]
     connect \B 16'1100000000000000
-    connect \Y $eq$ls180.v:5712$1054_Y
+    connect \Y $eq$ls180.v:5790$1108_Y
   end
-  attribute \src "ls180.v:5768.24-5768.45"
-  cell $eq $eq$ls180.v:5768$1081
+  attribute \src "ls180.v:5870.24-5870.45"
+  cell $eq $eq$ls180.v:5870$1150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -249372,10 +250347,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:5768$1081_Y
+    connect \Y $eq$ls180.v:5870$1150_Y
   end
-  attribute \src "ls180.v:5769.32-5769.77"
-  cell $eq $eq$ls180.v:5769$1082
+  attribute \src "ls180.v:5871.32-5871.77"
+  cell $eq $eq$ls180.v:5871$1151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -249383,10 +250358,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [13:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5769$1082_Y
+    connect \Y $eq$ls180.v:5871$1151_Y
   end
-  attribute \src "ls180.v:5771.97-5771.141"
-  cell $eq $eq$ls180.v:5771$1084
+  attribute \src "ls180.v:5873.97-5873.141"
+  cell $eq $eq$ls180.v:5873$1153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249394,10 +250369,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5771$1084_Y
+    connect \Y $eq$ls180.v:5873$1153_Y
   end
-  attribute \src "ls180.v:5772.100-5772.144"
-  cell $eq $eq$ls180.v:5772$1088
+  attribute \src "ls180.v:5874.100-5874.144"
+  cell $eq $eq$ls180.v:5874$1157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249405,10 +250380,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5772$1088_Y
+    connect \Y $eq$ls180.v:5874$1157_Y
   end
-  attribute \src "ls180.v:5774.99-5774.143"
-  cell $eq $eq$ls180.v:5774$1091
+  attribute \src "ls180.v:5876.99-5876.143"
+  cell $eq $eq$ls180.v:5876$1160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249416,10 +250391,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5774$1091_Y
+    connect \Y $eq$ls180.v:5876$1160_Y
   end
-  attribute \src "ls180.v:5775.102-5775.146"
-  cell $eq $eq$ls180.v:5775$1095
+  attribute \src "ls180.v:5877.102-5877.146"
+  cell $eq $eq$ls180.v:5877$1164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249427,10 +250402,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5775$1095_Y
+    connect \Y $eq$ls180.v:5877$1164_Y
   end
-  attribute \src "ls180.v:5777.99-5777.143"
-  cell $eq $eq$ls180.v:5777$1098
+  attribute \src "ls180.v:5879.99-5879.143"
+  cell $eq $eq$ls180.v:5879$1167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249438,10 +250413,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5777$1098_Y
+    connect \Y $eq$ls180.v:5879$1167_Y
   end
-  attribute \src "ls180.v:5778.102-5778.146"
-  cell $eq $eq$ls180.v:5778$1102
+  attribute \src "ls180.v:5880.102-5880.146"
+  cell $eq $eq$ls180.v:5880$1171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249449,10 +250424,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5778$1102_Y
+    connect \Y $eq$ls180.v:5880$1171_Y
   end
-  attribute \src "ls180.v:5780.99-5780.143"
-  cell $eq $eq$ls180.v:5780$1105
+  attribute \src "ls180.v:5882.99-5882.143"
+  cell $eq $eq$ls180.v:5882$1174
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249460,10 +250435,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5780$1105_Y
+    connect \Y $eq$ls180.v:5882$1174_Y
   end
-  attribute \src "ls180.v:5781.102-5781.146"
-  cell $eq $eq$ls180.v:5781$1109
+  attribute \src "ls180.v:5883.102-5883.146"
+  cell $eq $eq$ls180.v:5883$1178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249471,10 +250446,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5781$1109_Y
+    connect \Y $eq$ls180.v:5883$1178_Y
   end
-  attribute \src "ls180.v:5783.99-5783.143"
-  cell $eq $eq$ls180.v:5783$1112
+  attribute \src "ls180.v:5885.99-5885.143"
+  cell $eq $eq$ls180.v:5885$1181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249482,10 +250457,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5783$1112_Y
+    connect \Y $eq$ls180.v:5885$1181_Y
   end
-  attribute \src "ls180.v:5784.102-5784.146"
-  cell $eq $eq$ls180.v:5784$1116
+  attribute \src "ls180.v:5886.102-5886.146"
+  cell $eq $eq$ls180.v:5886$1185
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249493,10 +250468,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5784$1116_Y
+    connect \Y $eq$ls180.v:5886$1185_Y
   end
-  attribute \src "ls180.v:5786.102-5786.146"
-  cell $eq $eq$ls180.v:5786$1119
+  attribute \src "ls180.v:5888.102-5888.146"
+  cell $eq $eq$ls180.v:5888$1188
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249504,10 +250479,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5786$1119_Y
+    connect \Y $eq$ls180.v:5888$1188_Y
   end
-  attribute \src "ls180.v:5787.105-5787.149"
-  cell $eq $eq$ls180.v:5787$1123
+  attribute \src "ls180.v:5889.105-5889.149"
+  cell $eq $eq$ls180.v:5889$1192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249515,10 +250490,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5787$1123_Y
+    connect \Y $eq$ls180.v:5889$1192_Y
   end
-  attribute \src "ls180.v:5789.102-5789.146"
-  cell $eq $eq$ls180.v:5789$1126
+  attribute \src "ls180.v:5891.102-5891.146"
+  cell $eq $eq$ls180.v:5891$1195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249526,10 +250501,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5789$1126_Y
+    connect \Y $eq$ls180.v:5891$1195_Y
   end
-  attribute \src "ls180.v:5790.105-5790.149"
-  cell $eq $eq$ls180.v:5790$1130
+  attribute \src "ls180.v:5892.105-5892.149"
+  cell $eq $eq$ls180.v:5892$1199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249537,10 +250512,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5790$1130_Y
+    connect \Y $eq$ls180.v:5892$1199_Y
   end
-  attribute \src "ls180.v:5792.102-5792.146"
-  cell $eq $eq$ls180.v:5792$1133
+  attribute \src "ls180.v:5894.102-5894.146"
+  cell $eq $eq$ls180.v:5894$1202
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249548,10 +250523,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5792$1133_Y
+    connect \Y $eq$ls180.v:5894$1202_Y
   end
-  attribute \src "ls180.v:5793.105-5793.149"
-  cell $eq $eq$ls180.v:5793$1137
+  attribute \src "ls180.v:5895.105-5895.149"
+  cell $eq $eq$ls180.v:5895$1206
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249559,10 +250534,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5793$1137_Y
+    connect \Y $eq$ls180.v:5895$1206_Y
   end
-  attribute \src "ls180.v:5795.102-5795.146"
-  cell $eq $eq$ls180.v:5795$1140
+  attribute \src "ls180.v:5897.102-5897.146"
+  cell $eq $eq$ls180.v:5897$1209
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249570,10 +250545,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5795$1140_Y
+    connect \Y $eq$ls180.v:5897$1209_Y
   end
-  attribute \src "ls180.v:5796.105-5796.149"
-  cell $eq $eq$ls180.v:5796$1144
+  attribute \src "ls180.v:5898.105-5898.149"
+  cell $eq $eq$ls180.v:5898$1213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249581,10 +250556,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5796$1144_Y
+    connect \Y $eq$ls180.v:5898$1213_Y
   end
-  attribute \src "ls180.v:5807.32-5807.77"
-  cell $eq $eq$ls180.v:5807$1146
+  attribute \src "ls180.v:5909.32-5909.77"
+  cell $eq $eq$ls180.v:5909$1215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -249592,10 +250567,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [13:9]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5807$1146_Y
+    connect \Y $eq$ls180.v:5909$1215_Y
   end
-  attribute \src "ls180.v:5809.94-5809.138"
-  cell $eq $eq$ls180.v:5809$1148
+  attribute \src "ls180.v:5911.94-5911.138"
+  cell $eq $eq$ls180.v:5911$1217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249603,10 +250578,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5809$1148_Y
+    connect \Y $eq$ls180.v:5911$1217_Y
   end
-  attribute \src "ls180.v:5810.97-5810.141"
-  cell $eq $eq$ls180.v:5810$1152
+  attribute \src "ls180.v:5912.97-5912.141"
+  cell $eq $eq$ls180.v:5912$1221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249614,10 +250589,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5810$1152_Y
+    connect \Y $eq$ls180.v:5912$1221_Y
   end
-  attribute \src "ls180.v:5812.94-5812.138"
-  cell $eq $eq$ls180.v:5812$1155
+  attribute \src "ls180.v:5914.94-5914.138"
+  cell $eq $eq$ls180.v:5914$1224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249625,10 +250600,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5812$1155_Y
+    connect \Y $eq$ls180.v:5914$1224_Y
   end
-  attribute \src "ls180.v:5813.97-5813.141"
-  cell $eq $eq$ls180.v:5813$1159
+  attribute \src "ls180.v:5915.97-5915.141"
+  cell $eq $eq$ls180.v:5915$1228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249636,10 +250611,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5813$1159_Y
+    connect \Y $eq$ls180.v:5915$1228_Y
   end
-  attribute \src "ls180.v:5815.94-5815.138"
-  cell $eq $eq$ls180.v:5815$1162
+  attribute \src "ls180.v:5917.94-5917.138"
+  cell $eq $eq$ls180.v:5917$1231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249647,10 +250622,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5815$1162_Y
+    connect \Y $eq$ls180.v:5917$1231_Y
   end
-  attribute \src "ls180.v:5816.97-5816.141"
-  cell $eq $eq$ls180.v:5816$1166
+  attribute \src "ls180.v:5918.97-5918.141"
+  cell $eq $eq$ls180.v:5918$1235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249658,10 +250633,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5816$1166_Y
+    connect \Y $eq$ls180.v:5918$1235_Y
   end
-  attribute \src "ls180.v:5818.94-5818.138"
-  cell $eq $eq$ls180.v:5818$1169
+  attribute \src "ls180.v:5920.94-5920.138"
+  cell $eq $eq$ls180.v:5920$1238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249669,10 +250644,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5818$1169_Y
+    connect \Y $eq$ls180.v:5920$1238_Y
   end
-  attribute \src "ls180.v:5819.97-5819.141"
-  cell $eq $eq$ls180.v:5819$1173
+  attribute \src "ls180.v:5921.97-5921.141"
+  cell $eq $eq$ls180.v:5921$1242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249680,10 +250655,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5819$1173_Y
+    connect \Y $eq$ls180.v:5921$1242_Y
   end
-  attribute \src "ls180.v:5821.95-5821.139"
-  cell $eq $eq$ls180.v:5821$1176
+  attribute \src "ls180.v:5923.95-5923.139"
+  cell $eq $eq$ls180.v:5923$1245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249691,10 +250666,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5821$1176_Y
+    connect \Y $eq$ls180.v:5923$1245_Y
   end
-  attribute \src "ls180.v:5822.98-5822.142"
-  cell $eq $eq$ls180.v:5822$1180
+  attribute \src "ls180.v:5924.98-5924.142"
+  cell $eq $eq$ls180.v:5924$1249
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249702,10 +250677,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5822$1180_Y
+    connect \Y $eq$ls180.v:5924$1249_Y
   end
-  attribute \src "ls180.v:5824.95-5824.139"
-  cell $eq $eq$ls180.v:5824$1183
+  attribute \src "ls180.v:5926.95-5926.139"
+  cell $eq $eq$ls180.v:5926$1252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249713,10 +250688,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5824$1183_Y
+    connect \Y $eq$ls180.v:5926$1252_Y
   end
-  attribute \src "ls180.v:5825.98-5825.142"
-  cell $eq $eq$ls180.v:5825$1187
+  attribute \src "ls180.v:5927.98-5927.142"
+  cell $eq $eq$ls180.v:5927$1256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -249724,10 +250699,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5825$1187_Y
+    connect \Y $eq$ls180.v:5927$1256_Y
   end
-  attribute \src "ls180.v:5833.32-5833.78"
-  cell $eq $eq$ls180.v:5833$1189
+  attribute \src "ls180.v:5935.32-5935.78"
+  cell $eq $eq$ls180.v:5935$1258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -249735,10 +250710,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_adr [13:9]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:5833$1189_Y
+    connect \Y $eq$ls180.v:5935$1258_Y
   end
-  attribute \src "ls180.v:5835.93-5835.135"
-  cell $eq $eq$ls180.v:5835$1191
+  attribute \src "ls180.v:5937.93-5937.135"
+  cell $eq $eq$ls180.v:5937$1260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249746,10 +250721,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_adr [0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5835$1191_Y
+    connect \Y $eq$ls180.v:5937$1260_Y
   end
-  attribute \src "ls180.v:5836.96-5836.138"
-  cell $eq $eq$ls180.v:5836$1195
+  attribute \src "ls180.v:5938.96-5938.138"
+  cell $eq $eq$ls180.v:5938$1264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249757,10 +250732,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_adr [0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5836$1195_Y
+    connect \Y $eq$ls180.v:5938$1264_Y
   end
-  attribute \src "ls180.v:5838.92-5838.134"
-  cell $eq $eq$ls180.v:5838$1198
+  attribute \src "ls180.v:5940.92-5940.134"
+  cell $eq $eq$ls180.v:5940$1267
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249768,10 +250743,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_adr [0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5838$1198_Y
+    connect \Y $eq$ls180.v:5940$1267_Y
   end
-  attribute \src "ls180.v:5839.95-5839.137"
-  cell $eq $eq$ls180.v:5839$1202
+  attribute \src "ls180.v:5941.95-5941.137"
+  cell $eq $eq$ls180.v:5941$1271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249779,10 +250754,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_adr [0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5839$1202_Y
+    connect \Y $eq$ls180.v:5941$1271_Y
   end
-  attribute \src "ls180.v:5847.32-5847.77"
-  cell $eq $eq$ls180.v:5847$1204
+  attribute \src "ls180.v:5949.32-5949.77"
+  cell $eq $eq$ls180.v:5949$1273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -249790,10 +250765,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [13:9]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:5847$1204_Y
+    connect \Y $eq$ls180.v:5949$1273_Y
   end
-  attribute \src "ls180.v:5849.98-5849.142"
-  cell $eq $eq$ls180.v:5849$1206
+  attribute \src "ls180.v:5951.98-5951.142"
+  cell $eq $eq$ls180.v:5951$1275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249801,10 +250776,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5849$1206_Y
+    connect \Y $eq$ls180.v:5951$1275_Y
   end
-  attribute \src "ls180.v:5850.101-5850.145"
-  cell $eq $eq$ls180.v:5850$1210
+  attribute \src "ls180.v:5952.101-5952.145"
+  cell $eq $eq$ls180.v:5952$1279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249812,10 +250787,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5850$1210_Y
+    connect \Y $eq$ls180.v:5952$1279_Y
   end
-  attribute \src "ls180.v:5852.97-5852.141"
-  cell $eq $eq$ls180.v:5852$1213
+  attribute \src "ls180.v:5954.97-5954.141"
+  cell $eq $eq$ls180.v:5954$1282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249823,10 +250798,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5852$1213_Y
+    connect \Y $eq$ls180.v:5954$1282_Y
   end
-  attribute \src "ls180.v:5853.100-5853.144"
-  cell $eq $eq$ls180.v:5853$1217
+  attribute \src "ls180.v:5955.100-5955.144"
+  cell $eq $eq$ls180.v:5955$1286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249834,10 +250809,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5853$1217_Y
+    connect \Y $eq$ls180.v:5955$1286_Y
   end
-  attribute \src "ls180.v:5855.97-5855.141"
-  cell $eq $eq$ls180.v:5855$1220
+  attribute \src "ls180.v:5957.97-5957.141"
+  cell $eq $eq$ls180.v:5957$1289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249845,10 +250820,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5855$1220_Y
+    connect \Y $eq$ls180.v:5957$1289_Y
   end
-  attribute \src "ls180.v:5856.100-5856.144"
-  cell $eq $eq$ls180.v:5856$1224
+  attribute \src "ls180.v:5958.100-5958.144"
+  cell $eq $eq$ls180.v:5958$1293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249856,10 +250831,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5856$1224_Y
+    connect \Y $eq$ls180.v:5958$1293_Y
   end
-  attribute \src "ls180.v:5858.97-5858.141"
-  cell $eq $eq$ls180.v:5858$1227
+  attribute \src "ls180.v:5960.97-5960.141"
+  cell $eq $eq$ls180.v:5960$1296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249867,10 +250842,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5858$1227_Y
+    connect \Y $eq$ls180.v:5960$1296_Y
   end
-  attribute \src "ls180.v:5859.100-5859.144"
-  cell $eq $eq$ls180.v:5859$1231
+  attribute \src "ls180.v:5961.100-5961.144"
+  cell $eq $eq$ls180.v:5961$1300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249878,10 +250853,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5859$1231_Y
+    connect \Y $eq$ls180.v:5961$1300_Y
   end
-  attribute \src "ls180.v:5861.97-5861.141"
-  cell $eq $eq$ls180.v:5861$1234
+  attribute \src "ls180.v:5963.97-5963.141"
+  cell $eq $eq$ls180.v:5963$1303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249889,10 +250864,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5861$1234_Y
+    connect \Y $eq$ls180.v:5963$1303_Y
   end
-  attribute \src "ls180.v:5862.100-5862.144"
-  cell $eq $eq$ls180.v:5862$1238
+  attribute \src "ls180.v:5964.100-5964.144"
+  cell $eq $eq$ls180.v:5964$1307
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249900,10 +250875,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5862$1238_Y
+    connect \Y $eq$ls180.v:5964$1307_Y
   end
-  attribute \src "ls180.v:5864.98-5864.142"
-  cell $eq $eq$ls180.v:5864$1241
+  attribute \src "ls180.v:5966.98-5966.142"
+  cell $eq $eq$ls180.v:5966$1310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249911,10 +250886,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5864$1241_Y
+    connect \Y $eq$ls180.v:5966$1310_Y
   end
-  attribute \src "ls180.v:5865.101-5865.145"
-  cell $eq $eq$ls180.v:5865$1245
+  attribute \src "ls180.v:5967.101-5967.145"
+  cell $eq $eq$ls180.v:5967$1314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249922,10 +250897,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5865$1245_Y
+    connect \Y $eq$ls180.v:5967$1314_Y
   end
-  attribute \src "ls180.v:5867.98-5867.142"
-  cell $eq $eq$ls180.v:5867$1248
+  attribute \src "ls180.v:5969.98-5969.142"
+  cell $eq $eq$ls180.v:5969$1317
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249933,10 +250908,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5867$1248_Y
+    connect \Y $eq$ls180.v:5969$1317_Y
   end
-  attribute \src "ls180.v:5868.101-5868.145"
-  cell $eq $eq$ls180.v:5868$1252
+  attribute \src "ls180.v:5970.101-5970.145"
+  cell $eq $eq$ls180.v:5970$1321
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249944,10 +250919,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5868$1252_Y
+    connect \Y $eq$ls180.v:5970$1321_Y
   end
-  attribute \src "ls180.v:5870.98-5870.142"
-  cell $eq $eq$ls180.v:5870$1255
+  attribute \src "ls180.v:5972.98-5972.142"
+  cell $eq $eq$ls180.v:5972$1324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249955,10 +250930,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5870$1255_Y
+    connect \Y $eq$ls180.v:5972$1324_Y
   end
-  attribute \src "ls180.v:5871.101-5871.145"
-  cell $eq $eq$ls180.v:5871$1259
+  attribute \src "ls180.v:5973.101-5973.145"
+  cell $eq $eq$ls180.v:5973$1328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249966,10 +250941,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5871$1259_Y
+    connect \Y $eq$ls180.v:5973$1328_Y
   end
-  attribute \src "ls180.v:5873.98-5873.142"
-  cell $eq $eq$ls180.v:5873$1262
+  attribute \src "ls180.v:5975.98-5975.142"
+  cell $eq $eq$ls180.v:5975$1331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249977,10 +250952,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5873$1262_Y
+    connect \Y $eq$ls180.v:5975$1331_Y
   end
-  attribute \src "ls180.v:5874.101-5874.145"
-  cell $eq $eq$ls180.v:5874$1266
+  attribute \src "ls180.v:5976.101-5976.145"
+  cell $eq $eq$ls180.v:5976$1335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -249988,10 +250963,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5874$1266_Y
+    connect \Y $eq$ls180.v:5976$1335_Y
   end
-  attribute \src "ls180.v:5884.32-5884.78"
-  cell $eq $eq$ls180.v:5884$1268
+  attribute \src "ls180.v:5986.32-5986.78"
+  cell $eq $eq$ls180.v:5986$1337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -249999,10 +250974,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [13:9]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:5884$1268_Y
+    connect \Y $eq$ls180.v:5986$1337_Y
   end
-  attribute \src "ls180.v:5886.98-5886.142"
-  cell $eq $eq$ls180.v:5886$1270
+  attribute \src "ls180.v:5988.98-5988.142"
+  cell $eq $eq$ls180.v:5988$1339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250010,10 +250985,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5886$1270_Y
+    connect \Y $eq$ls180.v:5988$1339_Y
   end
-  attribute \src "ls180.v:5887.101-5887.145"
-  cell $eq $eq$ls180.v:5887$1274
+  attribute \src "ls180.v:5989.101-5989.145"
+  cell $eq $eq$ls180.v:5989$1343
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250021,10 +250996,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5887$1274_Y
+    connect \Y $eq$ls180.v:5989$1343_Y
   end
-  attribute \src "ls180.v:5889.97-5889.141"
-  cell $eq $eq$ls180.v:5889$1277
+  attribute \src "ls180.v:5991.97-5991.141"
+  cell $eq $eq$ls180.v:5991$1346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250032,10 +251007,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5889$1277_Y
+    connect \Y $eq$ls180.v:5991$1346_Y
   end
-  attribute \src "ls180.v:5890.100-5890.144"
-  cell $eq $eq$ls180.v:5890$1281
+  attribute \src "ls180.v:5992.100-5992.144"
+  cell $eq $eq$ls180.v:5992$1350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250043,10 +251018,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5890$1281_Y
+    connect \Y $eq$ls180.v:5992$1350_Y
   end
-  attribute \src "ls180.v:5892.97-5892.141"
-  cell $eq $eq$ls180.v:5892$1284
+  attribute \src "ls180.v:5994.97-5994.141"
+  cell $eq $eq$ls180.v:5994$1353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250054,10 +251029,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5892$1284_Y
+    connect \Y $eq$ls180.v:5994$1353_Y
   end
-  attribute \src "ls180.v:5893.100-5893.144"
-  cell $eq $eq$ls180.v:5893$1288
+  attribute \src "ls180.v:5995.100-5995.144"
+  cell $eq $eq$ls180.v:5995$1357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250065,10 +251040,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5893$1288_Y
+    connect \Y $eq$ls180.v:5995$1357_Y
   end
-  attribute \src "ls180.v:5895.97-5895.141"
-  cell $eq $eq$ls180.v:5895$1291
+  attribute \src "ls180.v:5997.97-5997.141"
+  cell $eq $eq$ls180.v:5997$1360
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250076,10 +251051,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5895$1291_Y
+    connect \Y $eq$ls180.v:5997$1360_Y
   end
-  attribute \src "ls180.v:5896.100-5896.144"
-  cell $eq $eq$ls180.v:5896$1295
+  attribute \src "ls180.v:5998.100-5998.144"
+  cell $eq $eq$ls180.v:5998$1364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250087,10 +251062,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5896$1295_Y
+    connect \Y $eq$ls180.v:5998$1364_Y
   end
-  attribute \src "ls180.v:5898.97-5898.141"
-  cell $eq $eq$ls180.v:5898$1298
+  attribute \src "ls180.v:6000.97-6000.141"
+  cell $eq $eq$ls180.v:6000$1367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250098,10 +251073,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5898$1298_Y
+    connect \Y $eq$ls180.v:6000$1367_Y
   end
-  attribute \src "ls180.v:5899.100-5899.144"
-  cell $eq $eq$ls180.v:5899$1302
+  attribute \src "ls180.v:6001.100-6001.144"
+  cell $eq $eq$ls180.v:6001$1371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250109,10 +251084,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5899$1302_Y
+    connect \Y $eq$ls180.v:6001$1371_Y
   end
-  attribute \src "ls180.v:5901.98-5901.142"
-  cell $eq $eq$ls180.v:5901$1305
+  attribute \src "ls180.v:6003.98-6003.142"
+  cell $eq $eq$ls180.v:6003$1374
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250120,10 +251095,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5901$1305_Y
+    connect \Y $eq$ls180.v:6003$1374_Y
   end
-  attribute \src "ls180.v:5902.101-5902.145"
-  cell $eq $eq$ls180.v:5902$1309
+  attribute \src "ls180.v:6004.101-6004.145"
+  cell $eq $eq$ls180.v:6004$1378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250131,10 +251106,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5902$1309_Y
+    connect \Y $eq$ls180.v:6004$1378_Y
   end
-  attribute \src "ls180.v:5904.98-5904.142"
-  cell $eq $eq$ls180.v:5904$1312
+  attribute \src "ls180.v:6006.98-6006.142"
+  cell $eq $eq$ls180.v:6006$1381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250142,10 +251117,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5904$1312_Y
+    connect \Y $eq$ls180.v:6006$1381_Y
   end
-  attribute \src "ls180.v:5905.101-5905.145"
-  cell $eq $eq$ls180.v:5905$1316
+  attribute \src "ls180.v:6007.101-6007.145"
+  cell $eq $eq$ls180.v:6007$1385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250153,10 +251128,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5905$1316_Y
+    connect \Y $eq$ls180.v:6007$1385_Y
   end
-  attribute \src "ls180.v:5907.98-5907.142"
-  cell $eq $eq$ls180.v:5907$1319
+  attribute \src "ls180.v:6009.98-6009.142"
+  cell $eq $eq$ls180.v:6009$1388
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250164,10 +251139,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5907$1319_Y
+    connect \Y $eq$ls180.v:6009$1388_Y
   end
-  attribute \src "ls180.v:5908.101-5908.145"
-  cell $eq $eq$ls180.v:5908$1323
+  attribute \src "ls180.v:6010.101-6010.145"
+  cell $eq $eq$ls180.v:6010$1392
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250175,10 +251150,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5908$1323_Y
+    connect \Y $eq$ls180.v:6010$1392_Y
   end
-  attribute \src "ls180.v:5910.98-5910.142"
-  cell $eq $eq$ls180.v:5910$1326
+  attribute \src "ls180.v:6012.98-6012.142"
+  cell $eq $eq$ls180.v:6012$1395
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250186,10 +251161,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5910$1326_Y
+    connect \Y $eq$ls180.v:6012$1395_Y
   end
-  attribute \src "ls180.v:5911.101-5911.145"
-  cell $eq $eq$ls180.v:5911$1330
+  attribute \src "ls180.v:6013.101-6013.145"
+  cell $eq $eq$ls180.v:6013$1399
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250197,10 +251172,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5911$1330_Y
+    connect \Y $eq$ls180.v:6013$1399_Y
   end
-  attribute \src "ls180.v:5921.32-5921.78"
-  cell $eq $eq$ls180.v:5921$1332
+  attribute \src "ls180.v:6023.32-6023.78"
+  cell $eq $eq$ls180.v:6023$1401
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -250208,10 +251183,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [13:9]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:5921$1332_Y
+    connect \Y $eq$ls180.v:6023$1401_Y
   end
-  attribute \src "ls180.v:5923.100-5923.144"
-  cell $eq $eq$ls180.v:5923$1334
+  attribute \src "ls180.v:6025.100-6025.144"
+  cell $eq $eq$ls180.v:6025$1403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250219,10 +251194,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5923$1334_Y
+    connect \Y $eq$ls180.v:6025$1403_Y
   end
-  attribute \src "ls180.v:5924.103-5924.147"
-  cell $eq $eq$ls180.v:5924$1338
+  attribute \src "ls180.v:6026.103-6026.147"
+  cell $eq $eq$ls180.v:6026$1407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250230,10 +251205,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5924$1338_Y
+    connect \Y $eq$ls180.v:6026$1407_Y
   end
-  attribute \src "ls180.v:5926.100-5926.144"
-  cell $eq $eq$ls180.v:5926$1341
+  attribute \src "ls180.v:6028.100-6028.144"
+  cell $eq $eq$ls180.v:6028$1410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250241,10 +251216,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5926$1341_Y
+    connect \Y $eq$ls180.v:6028$1410_Y
   end
-  attribute \src "ls180.v:5927.103-5927.147"
-  cell $eq $eq$ls180.v:5927$1345
+  attribute \src "ls180.v:6029.103-6029.147"
+  cell $eq $eq$ls180.v:6029$1414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250252,10 +251227,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5927$1345_Y
+    connect \Y $eq$ls180.v:6029$1414_Y
   end
-  attribute \src "ls180.v:5929.100-5929.144"
-  cell $eq $eq$ls180.v:5929$1348
+  attribute \src "ls180.v:6031.100-6031.144"
+  cell $eq $eq$ls180.v:6031$1417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250263,10 +251238,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5929$1348_Y
+    connect \Y $eq$ls180.v:6031$1417_Y
   end
-  attribute \src "ls180.v:5930.103-5930.147"
-  cell $eq $eq$ls180.v:5930$1352
+  attribute \src "ls180.v:6032.103-6032.147"
+  cell $eq $eq$ls180.v:6032$1421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250274,10 +251249,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5930$1352_Y
+    connect \Y $eq$ls180.v:6032$1421_Y
   end
-  attribute \src "ls180.v:5932.100-5932.144"
-  cell $eq $eq$ls180.v:5932$1355
+  attribute \src "ls180.v:6034.100-6034.144"
+  cell $eq $eq$ls180.v:6034$1424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250285,10 +251260,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5932$1355_Y
+    connect \Y $eq$ls180.v:6034$1424_Y
   end
-  attribute \src "ls180.v:5933.103-5933.147"
-  cell $eq $eq$ls180.v:5933$1359
+  attribute \src "ls180.v:6035.103-6035.147"
+  cell $eq $eq$ls180.v:6035$1428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250296,10 +251271,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5933$1359_Y
+    connect \Y $eq$ls180.v:6035$1428_Y
   end
-  attribute \src "ls180.v:5935.100-5935.144"
-  cell $eq $eq$ls180.v:5935$1362
+  attribute \src "ls180.v:6037.100-6037.144"
+  cell $eq $eq$ls180.v:6037$1431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250307,10 +251282,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5935$1362_Y
+    connect \Y $eq$ls180.v:6037$1431_Y
   end
-  attribute \src "ls180.v:5936.103-5936.147"
-  cell $eq $eq$ls180.v:5936$1366
+  attribute \src "ls180.v:6038.103-6038.147"
+  cell $eq $eq$ls180.v:6038$1435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250318,10 +251293,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5936$1366_Y
+    connect \Y $eq$ls180.v:6038$1435_Y
   end
-  attribute \src "ls180.v:5938.100-5938.144"
-  cell $eq $eq$ls180.v:5938$1369
+  attribute \src "ls180.v:6040.100-6040.144"
+  cell $eq $eq$ls180.v:6040$1438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250329,10 +251304,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5938$1369_Y
+    connect \Y $eq$ls180.v:6040$1438_Y
   end
-  attribute \src "ls180.v:5939.103-5939.147"
-  cell $eq $eq$ls180.v:5939$1373
+  attribute \src "ls180.v:6041.103-6041.147"
+  cell $eq $eq$ls180.v:6041$1442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250340,10 +251315,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:5939$1373_Y
+    connect \Y $eq$ls180.v:6041$1442_Y
   end
-  attribute \src "ls180.v:5941.100-5941.144"
-  cell $eq $eq$ls180.v:5941$1376
+  attribute \src "ls180.v:6043.100-6043.144"
+  cell $eq $eq$ls180.v:6043$1445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250351,10 +251326,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5941$1376_Y
+    connect \Y $eq$ls180.v:6043$1445_Y
   end
-  attribute \src "ls180.v:5942.103-5942.147"
-  cell $eq $eq$ls180.v:5942$1380
+  attribute \src "ls180.v:6044.103-6044.147"
+  cell $eq $eq$ls180.v:6044$1449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250362,10 +251337,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:5942$1380_Y
+    connect \Y $eq$ls180.v:6044$1449_Y
   end
-  attribute \src "ls180.v:5944.100-5944.144"
-  cell $eq $eq$ls180.v:5944$1383
+  attribute \src "ls180.v:6046.100-6046.144"
+  cell $eq $eq$ls180.v:6046$1452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250373,10 +251348,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5944$1383_Y
+    connect \Y $eq$ls180.v:6046$1452_Y
   end
-  attribute \src "ls180.v:5945.103-5945.147"
-  cell $eq $eq$ls180.v:5945$1387
+  attribute \src "ls180.v:6047.103-6047.147"
+  cell $eq $eq$ls180.v:6047$1456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250384,10 +251359,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:5945$1387_Y
+    connect \Y $eq$ls180.v:6047$1456_Y
   end
-  attribute \src "ls180.v:5947.102-5947.146"
-  cell $eq $eq$ls180.v:5947$1390
+  attribute \src "ls180.v:6049.102-6049.146"
+  cell $eq $eq$ls180.v:6049$1459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250395,10 +251370,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5947$1390_Y
+    connect \Y $eq$ls180.v:6049$1459_Y
   end
-  attribute \src "ls180.v:5948.105-5948.149"
-  cell $eq $eq$ls180.v:5948$1394
+  attribute \src "ls180.v:6050.105-6050.149"
+  cell $eq $eq$ls180.v:6050$1463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250406,10 +251381,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:5948$1394_Y
+    connect \Y $eq$ls180.v:6050$1463_Y
   end
-  attribute \src "ls180.v:5950.102-5950.146"
-  cell $eq $eq$ls180.v:5950$1397
+  attribute \src "ls180.v:6052.102-6052.146"
+  cell $eq $eq$ls180.v:6052$1466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250417,10 +251392,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:5950$1397_Y
+    connect \Y $eq$ls180.v:6052$1466_Y
   end
-  attribute \src "ls180.v:5951.105-5951.149"
-  cell $eq $eq$ls180.v:5951$1401
+  attribute \src "ls180.v:6053.105-6053.149"
+  cell $eq $eq$ls180.v:6053$1470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250428,10 +251403,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:5951$1401_Y
+    connect \Y $eq$ls180.v:6053$1470_Y
   end
-  attribute \src "ls180.v:5953.102-5953.147"
-  cell $eq $eq$ls180.v:5953$1404
+  attribute \src "ls180.v:6055.102-6055.147"
+  cell $eq $eq$ls180.v:6055$1473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250439,10 +251414,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:5953$1404_Y
+    connect \Y $eq$ls180.v:6055$1473_Y
   end
-  attribute \src "ls180.v:5954.105-5954.150"
-  cell $eq $eq$ls180.v:5954$1408
+  attribute \src "ls180.v:6056.105-6056.150"
+  cell $eq $eq$ls180.v:6056$1477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250450,10 +251425,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:5954$1408_Y
+    connect \Y $eq$ls180.v:6056$1477_Y
   end
-  attribute \src "ls180.v:5956.102-5956.147"
-  cell $eq $eq$ls180.v:5956$1411
+  attribute \src "ls180.v:6058.102-6058.147"
+  cell $eq $eq$ls180.v:6058$1480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250461,10 +251436,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:5956$1411_Y
+    connect \Y $eq$ls180.v:6058$1480_Y
   end
-  attribute \src "ls180.v:5957.105-5957.150"
-  cell $eq $eq$ls180.v:5957$1415
+  attribute \src "ls180.v:6059.105-6059.150"
+  cell $eq $eq$ls180.v:6059$1484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250472,10 +251447,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:5957$1415_Y
+    connect \Y $eq$ls180.v:6059$1484_Y
   end
-  attribute \src "ls180.v:5959.102-5959.147"
-  cell $eq $eq$ls180.v:5959$1418
+  attribute \src "ls180.v:6061.102-6061.147"
+  cell $eq $eq$ls180.v:6061$1487
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250483,10 +251458,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:5959$1418_Y
+    connect \Y $eq$ls180.v:6061$1487_Y
   end
-  attribute \src "ls180.v:5960.105-5960.150"
-  cell $eq $eq$ls180.v:5960$1422
+  attribute \src "ls180.v:6062.105-6062.150"
+  cell $eq $eq$ls180.v:6062$1491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250494,10 +251469,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:5960$1422_Y
+    connect \Y $eq$ls180.v:6062$1491_Y
   end
-  attribute \src "ls180.v:5962.99-5962.144"
-  cell $eq $eq$ls180.v:5962$1425
+  attribute \src "ls180.v:6064.99-6064.144"
+  cell $eq $eq$ls180.v:6064$1494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250505,10 +251480,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:5962$1425_Y
+    connect \Y $eq$ls180.v:6064$1494_Y
   end
-  attribute \src "ls180.v:5963.102-5963.147"
-  cell $eq $eq$ls180.v:5963$1429
+  attribute \src "ls180.v:6065.102-6065.147"
+  cell $eq $eq$ls180.v:6065$1498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250516,10 +251491,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:5963$1429_Y
+    connect \Y $eq$ls180.v:6065$1498_Y
   end
-  attribute \src "ls180.v:5965.100-5965.145"
-  cell $eq $eq$ls180.v:5965$1432
+  attribute \src "ls180.v:6067.100-6067.145"
+  cell $eq $eq$ls180.v:6067$1501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250527,10 +251502,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:5965$1432_Y
+    connect \Y $eq$ls180.v:6067$1501_Y
   end
-  attribute \src "ls180.v:5966.103-5966.148"
-  cell $eq $eq$ls180.v:5966$1436
+  attribute \src "ls180.v:6068.103-6068.148"
+  cell $eq $eq$ls180.v:6068$1505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -250538,10 +251513,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_adr [3:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:5966$1436_Y
+    connect \Y $eq$ls180.v:6068$1505_Y
   end
-  attribute \src "ls180.v:5983.32-5983.78"
-  cell $eq $eq$ls180.v:5983$1438
+  attribute \src "ls180.v:6085.32-6085.78"
+  cell $eq $eq$ls180.v:6085$1507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -250549,10 +251524,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [13:9]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:5983$1438_Y
+    connect \Y $eq$ls180.v:6085$1507_Y
   end
-  attribute \src "ls180.v:5985.104-5985.148"
-  cell $eq $eq$ls180.v:5985$1440
+  attribute \src "ls180.v:6087.104-6087.148"
+  cell $eq $eq$ls180.v:6087$1509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250560,10 +251535,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5985$1440_Y
+    connect \Y $eq$ls180.v:6087$1509_Y
   end
-  attribute \src "ls180.v:5986.107-5986.151"
-  cell $eq $eq$ls180.v:5986$1444
+  attribute \src "ls180.v:6088.107-6088.151"
+  cell $eq $eq$ls180.v:6088$1513
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250571,10 +251546,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:5986$1444_Y
+    connect \Y $eq$ls180.v:6088$1513_Y
   end
-  attribute \src "ls180.v:5988.104-5988.148"
-  cell $eq $eq$ls180.v:5988$1447
+  attribute \src "ls180.v:6090.104-6090.148"
+  cell $eq $eq$ls180.v:6090$1516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250582,10 +251557,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5988$1447_Y
+    connect \Y $eq$ls180.v:6090$1516_Y
   end
-  attribute \src "ls180.v:5989.107-5989.151"
-  cell $eq $eq$ls180.v:5989$1451
+  attribute \src "ls180.v:6091.107-6091.151"
+  cell $eq $eq$ls180.v:6091$1520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250593,10 +251568,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:5989$1451_Y
+    connect \Y $eq$ls180.v:6091$1520_Y
   end
-  attribute \src "ls180.v:5991.104-5991.148"
-  cell $eq $eq$ls180.v:5991$1454
+  attribute \src "ls180.v:6093.104-6093.148"
+  cell $eq $eq$ls180.v:6093$1523
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250604,10 +251579,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5991$1454_Y
+    connect \Y $eq$ls180.v:6093$1523_Y
   end
-  attribute \src "ls180.v:5992.107-5992.151"
-  cell $eq $eq$ls180.v:5992$1458
+  attribute \src "ls180.v:6094.107-6094.151"
+  cell $eq $eq$ls180.v:6094$1527
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250615,10 +251590,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:5992$1458_Y
+    connect \Y $eq$ls180.v:6094$1527_Y
   end
-  attribute \src "ls180.v:5994.104-5994.148"
-  cell $eq $eq$ls180.v:5994$1461
+  attribute \src "ls180.v:6096.104-6096.148"
+  cell $eq $eq$ls180.v:6096$1530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250626,10 +251601,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5994$1461_Y
+    connect \Y $eq$ls180.v:6096$1530_Y
   end
-  attribute \src "ls180.v:5995.107-5995.151"
-  cell $eq $eq$ls180.v:5995$1465
+  attribute \src "ls180.v:6097.107-6097.151"
+  cell $eq $eq$ls180.v:6097$1534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250637,10 +251612,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:5995$1465_Y
+    connect \Y $eq$ls180.v:6097$1534_Y
   end
-  attribute \src "ls180.v:5997.103-5997.147"
-  cell $eq $eq$ls180.v:5997$1468
+  attribute \src "ls180.v:6099.103-6099.147"
+  cell $eq $eq$ls180.v:6099$1537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250648,10 +251623,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5997$1468_Y
+    connect \Y $eq$ls180.v:6099$1537_Y
   end
-  attribute \src "ls180.v:5998.106-5998.150"
-  cell $eq $eq$ls180.v:5998$1472
+  attribute \src "ls180.v:6100.106-6100.150"
+  cell $eq $eq$ls180.v:6100$1541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250659,10 +251634,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:5998$1472_Y
+    connect \Y $eq$ls180.v:6100$1541_Y
   end
-  attribute \src "ls180.v:6000.103-6000.147"
-  cell $eq $eq$ls180.v:6000$1475
+  attribute \src "ls180.v:6102.103-6102.147"
+  cell $eq $eq$ls180.v:6102$1544
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250670,10 +251645,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6000$1475_Y
+    connect \Y $eq$ls180.v:6102$1544_Y
   end
-  attribute \src "ls180.v:6001.106-6001.150"
-  cell $eq $eq$ls180.v:6001$1479
+  attribute \src "ls180.v:6103.106-6103.150"
+  cell $eq $eq$ls180.v:6103$1548
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250681,10 +251656,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6001$1479_Y
+    connect \Y $eq$ls180.v:6103$1548_Y
   end
-  attribute \src "ls180.v:6003.103-6003.147"
-  cell $eq $eq$ls180.v:6003$1482
+  attribute \src "ls180.v:6105.103-6105.147"
+  cell $eq $eq$ls180.v:6105$1551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250692,10 +251667,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6003$1482_Y
+    connect \Y $eq$ls180.v:6105$1551_Y
   end
-  attribute \src "ls180.v:6004.106-6004.150"
-  cell $eq $eq$ls180.v:6004$1486
+  attribute \src "ls180.v:6106.106-6106.150"
+  cell $eq $eq$ls180.v:6106$1555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250703,10 +251678,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6004$1486_Y
+    connect \Y $eq$ls180.v:6106$1555_Y
   end
-  attribute \src "ls180.v:6006.103-6006.147"
-  cell $eq $eq$ls180.v:6006$1489
+  attribute \src "ls180.v:6108.103-6108.147"
+  cell $eq $eq$ls180.v:6108$1558
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250714,10 +251689,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6006$1489_Y
+    connect \Y $eq$ls180.v:6108$1558_Y
   end
-  attribute \src "ls180.v:6007.106-6007.150"
-  cell $eq $eq$ls180.v:6007$1493
+  attribute \src "ls180.v:6109.106-6109.150"
+  cell $eq $eq$ls180.v:6109$1562
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250725,10 +251700,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6007$1493_Y
+    connect \Y $eq$ls180.v:6109$1562_Y
   end
-  attribute \src "ls180.v:6009.94-6009.138"
-  cell $eq $eq$ls180.v:6009$1496
+  attribute \src "ls180.v:6111.94-6111.138"
+  cell $eq $eq$ls180.v:6111$1565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250736,10 +251711,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6009$1496_Y
+    connect \Y $eq$ls180.v:6111$1565_Y
   end
-  attribute \src "ls180.v:6010.97-6010.141"
-  cell $eq $eq$ls180.v:6010$1500
+  attribute \src "ls180.v:6112.97-6112.141"
+  cell $eq $eq$ls180.v:6112$1569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250747,10 +251722,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6010$1500_Y
+    connect \Y $eq$ls180.v:6112$1569_Y
   end
-  attribute \src "ls180.v:6012.105-6012.149"
-  cell $eq $eq$ls180.v:6012$1503
+  attribute \src "ls180.v:6114.105-6114.149"
+  cell $eq $eq$ls180.v:6114$1572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250758,10 +251733,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6012$1503_Y
+    connect \Y $eq$ls180.v:6114$1572_Y
   end
-  attribute \src "ls180.v:6013.108-6013.152"
-  cell $eq $eq$ls180.v:6013$1507
+  attribute \src "ls180.v:6115.108-6115.152"
+  cell $eq $eq$ls180.v:6115$1576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250769,10 +251744,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6013$1507_Y
+    connect \Y $eq$ls180.v:6115$1576_Y
   end
-  attribute \src "ls180.v:6015.105-6015.150"
-  cell $eq $eq$ls180.v:6015$1510
+  attribute \src "ls180.v:6117.105-6117.150"
+  cell $eq $eq$ls180.v:6117$1579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250780,10 +251755,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6015$1510_Y
+    connect \Y $eq$ls180.v:6117$1579_Y
   end
-  attribute \src "ls180.v:6016.108-6016.153"
-  cell $eq $eq$ls180.v:6016$1514
+  attribute \src "ls180.v:6118.108-6118.153"
+  cell $eq $eq$ls180.v:6118$1583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250791,10 +251766,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6016$1514_Y
+    connect \Y $eq$ls180.v:6118$1583_Y
   end
-  attribute \src "ls180.v:6018.105-6018.150"
-  cell $eq $eq$ls180.v:6018$1517
+  attribute \src "ls180.v:6120.105-6120.150"
+  cell $eq $eq$ls180.v:6120$1586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250802,10 +251777,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6018$1517_Y
+    connect \Y $eq$ls180.v:6120$1586_Y
   end
-  attribute \src "ls180.v:6019.108-6019.153"
-  cell $eq $eq$ls180.v:6019$1521
+  attribute \src "ls180.v:6121.108-6121.153"
+  cell $eq $eq$ls180.v:6121$1590
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250813,10 +251788,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6019$1521_Y
+    connect \Y $eq$ls180.v:6121$1590_Y
   end
-  attribute \src "ls180.v:6021.105-6021.150"
-  cell $eq $eq$ls180.v:6021$1524
+  attribute \src "ls180.v:6123.105-6123.150"
+  cell $eq $eq$ls180.v:6123$1593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250824,10 +251799,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6021$1524_Y
+    connect \Y $eq$ls180.v:6123$1593_Y
   end
-  attribute \src "ls180.v:6022.108-6022.153"
-  cell $eq $eq$ls180.v:6022$1528
+  attribute \src "ls180.v:6124.108-6124.153"
+  cell $eq $eq$ls180.v:6124$1597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250835,10 +251810,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6022$1528_Y
+    connect \Y $eq$ls180.v:6124$1597_Y
   end
-  attribute \src "ls180.v:6024.105-6024.150"
-  cell $eq $eq$ls180.v:6024$1531
+  attribute \src "ls180.v:6126.105-6126.150"
+  cell $eq $eq$ls180.v:6126$1600
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250846,10 +251821,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6024$1531_Y
+    connect \Y $eq$ls180.v:6126$1600_Y
   end
-  attribute \src "ls180.v:6025.108-6025.153"
-  cell $eq $eq$ls180.v:6025$1535
+  attribute \src "ls180.v:6127.108-6127.153"
+  cell $eq $eq$ls180.v:6127$1604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250857,10 +251832,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6025$1535_Y
+    connect \Y $eq$ls180.v:6127$1604_Y
   end
-  attribute \src "ls180.v:6027.105-6027.150"
-  cell $eq $eq$ls180.v:6027$1538
+  attribute \src "ls180.v:6129.105-6129.150"
+  cell $eq $eq$ls180.v:6129$1607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250868,10 +251843,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6027$1538_Y
+    connect \Y $eq$ls180.v:6129$1607_Y
   end
-  attribute \src "ls180.v:6028.108-6028.153"
-  cell $eq $eq$ls180.v:6028$1542
+  attribute \src "ls180.v:6130.108-6130.153"
+  cell $eq $eq$ls180.v:6130$1611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250879,10 +251854,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6028$1542_Y
+    connect \Y $eq$ls180.v:6130$1611_Y
   end
-  attribute \src "ls180.v:6030.104-6030.149"
-  cell $eq $eq$ls180.v:6030$1545
+  attribute \src "ls180.v:6132.104-6132.149"
+  cell $eq $eq$ls180.v:6132$1614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250890,10 +251865,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6030$1545_Y
+    connect \Y $eq$ls180.v:6132$1614_Y
   end
-  attribute \src "ls180.v:6031.107-6031.152"
-  cell $eq $eq$ls180.v:6031$1549
+  attribute \src "ls180.v:6133.107-6133.152"
+  cell $eq $eq$ls180.v:6133$1618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250901,10 +251876,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6031$1549_Y
+    connect \Y $eq$ls180.v:6133$1618_Y
   end
-  attribute \src "ls180.v:6033.104-6033.149"
-  cell $eq $eq$ls180.v:6033$1552
+  attribute \src "ls180.v:6135.104-6135.149"
+  cell $eq $eq$ls180.v:6135$1621
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250912,10 +251887,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6033$1552_Y
+    connect \Y $eq$ls180.v:6135$1621_Y
   end
-  attribute \src "ls180.v:6034.107-6034.152"
-  cell $eq $eq$ls180.v:6034$1556
+  attribute \src "ls180.v:6136.107-6136.152"
+  cell $eq $eq$ls180.v:6136$1625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250923,10 +251898,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6034$1556_Y
+    connect \Y $eq$ls180.v:6136$1625_Y
   end
-  attribute \src "ls180.v:6036.104-6036.149"
-  cell $eq $eq$ls180.v:6036$1559
+  attribute \src "ls180.v:6138.104-6138.149"
+  cell $eq $eq$ls180.v:6138$1628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250934,10 +251909,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10001
-    connect \Y $eq$ls180.v:6036$1559_Y
+    connect \Y $eq$ls180.v:6138$1628_Y
   end
-  attribute \src "ls180.v:6037.107-6037.152"
-  cell $eq $eq$ls180.v:6037$1563
+  attribute \src "ls180.v:6139.107-6139.152"
+  cell $eq $eq$ls180.v:6139$1632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250945,10 +251920,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10001
-    connect \Y $eq$ls180.v:6037$1563_Y
+    connect \Y $eq$ls180.v:6139$1632_Y
   end
-  attribute \src "ls180.v:6039.104-6039.149"
-  cell $eq $eq$ls180.v:6039$1566
+  attribute \src "ls180.v:6141.104-6141.149"
+  cell $eq $eq$ls180.v:6141$1635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250956,10 +251931,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10010
-    connect \Y $eq$ls180.v:6039$1566_Y
+    connect \Y $eq$ls180.v:6141$1635_Y
   end
-  attribute \src "ls180.v:6040.107-6040.152"
-  cell $eq $eq$ls180.v:6040$1570
+  attribute \src "ls180.v:6142.107-6142.152"
+  cell $eq $eq$ls180.v:6142$1639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250967,10 +251942,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10010
-    connect \Y $eq$ls180.v:6040$1570_Y
+    connect \Y $eq$ls180.v:6142$1639_Y
   end
-  attribute \src "ls180.v:6042.104-6042.149"
-  cell $eq $eq$ls180.v:6042$1573
+  attribute \src "ls180.v:6144.104-6144.149"
+  cell $eq $eq$ls180.v:6144$1642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250978,10 +251953,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10011
-    connect \Y $eq$ls180.v:6042$1573_Y
+    connect \Y $eq$ls180.v:6144$1642_Y
   end
-  attribute \src "ls180.v:6043.107-6043.152"
-  cell $eq $eq$ls180.v:6043$1577
+  attribute \src "ls180.v:6145.107-6145.152"
+  cell $eq $eq$ls180.v:6145$1646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -250989,10 +251964,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10011
-    connect \Y $eq$ls180.v:6043$1577_Y
+    connect \Y $eq$ls180.v:6145$1646_Y
   end
-  attribute \src "ls180.v:6045.104-6045.149"
-  cell $eq $eq$ls180.v:6045$1580
+  attribute \src "ls180.v:6147.104-6147.149"
+  cell $eq $eq$ls180.v:6147$1649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251000,10 +251975,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10100
-    connect \Y $eq$ls180.v:6045$1580_Y
+    connect \Y $eq$ls180.v:6147$1649_Y
   end
-  attribute \src "ls180.v:6046.107-6046.152"
-  cell $eq $eq$ls180.v:6046$1584
+  attribute \src "ls180.v:6148.107-6148.152"
+  cell $eq $eq$ls180.v:6148$1653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251011,10 +251986,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10100
-    connect \Y $eq$ls180.v:6046$1584_Y
+    connect \Y $eq$ls180.v:6148$1653_Y
   end
-  attribute \src "ls180.v:6048.104-6048.149"
-  cell $eq $eq$ls180.v:6048$1587
+  attribute \src "ls180.v:6150.104-6150.149"
+  cell $eq $eq$ls180.v:6150$1656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251022,10 +251997,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10101
-    connect \Y $eq$ls180.v:6048$1587_Y
+    connect \Y $eq$ls180.v:6150$1656_Y
   end
-  attribute \src "ls180.v:6049.107-6049.152"
-  cell $eq $eq$ls180.v:6049$1591
+  attribute \src "ls180.v:6151.107-6151.152"
+  cell $eq $eq$ls180.v:6151$1660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251033,10 +252008,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10101
-    connect \Y $eq$ls180.v:6049$1591_Y
+    connect \Y $eq$ls180.v:6151$1660_Y
   end
-  attribute \src "ls180.v:6051.104-6051.149"
-  cell $eq $eq$ls180.v:6051$1594
+  attribute \src "ls180.v:6153.104-6153.149"
+  cell $eq $eq$ls180.v:6153$1663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251044,10 +252019,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10110
-    connect \Y $eq$ls180.v:6051$1594_Y
+    connect \Y $eq$ls180.v:6153$1663_Y
   end
-  attribute \src "ls180.v:6052.107-6052.152"
-  cell $eq $eq$ls180.v:6052$1598
+  attribute \src "ls180.v:6154.107-6154.152"
+  cell $eq $eq$ls180.v:6154$1667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251055,10 +252030,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10110
-    connect \Y $eq$ls180.v:6052$1598_Y
+    connect \Y $eq$ls180.v:6154$1667_Y
   end
-  attribute \src "ls180.v:6054.104-6054.149"
-  cell $eq $eq$ls180.v:6054$1601
+  attribute \src "ls180.v:6156.104-6156.149"
+  cell $eq $eq$ls180.v:6156$1670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251066,10 +252041,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10111
-    connect \Y $eq$ls180.v:6054$1601_Y
+    connect \Y $eq$ls180.v:6156$1670_Y
   end
-  attribute \src "ls180.v:6055.107-6055.152"
-  cell $eq $eq$ls180.v:6055$1605
+  attribute \src "ls180.v:6157.107-6157.152"
+  cell $eq $eq$ls180.v:6157$1674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251077,10 +252052,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'10111
-    connect \Y $eq$ls180.v:6055$1605_Y
+    connect \Y $eq$ls180.v:6157$1674_Y
   end
-  attribute \src "ls180.v:6057.104-6057.149"
-  cell $eq $eq$ls180.v:6057$1608
+  attribute \src "ls180.v:6159.104-6159.149"
+  cell $eq $eq$ls180.v:6159$1677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251088,10 +252063,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11000
-    connect \Y $eq$ls180.v:6057$1608_Y
+    connect \Y $eq$ls180.v:6159$1677_Y
   end
-  attribute \src "ls180.v:6058.107-6058.152"
-  cell $eq $eq$ls180.v:6058$1612
+  attribute \src "ls180.v:6160.107-6160.152"
+  cell $eq $eq$ls180.v:6160$1681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251099,10 +252074,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11000
-    connect \Y $eq$ls180.v:6058$1612_Y
+    connect \Y $eq$ls180.v:6160$1681_Y
   end
-  attribute \src "ls180.v:6060.100-6060.145"
-  cell $eq $eq$ls180.v:6060$1615
+  attribute \src "ls180.v:6162.100-6162.145"
+  cell $eq $eq$ls180.v:6162$1684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251110,10 +252085,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11001
-    connect \Y $eq$ls180.v:6060$1615_Y
+    connect \Y $eq$ls180.v:6162$1684_Y
   end
-  attribute \src "ls180.v:6061.103-6061.148"
-  cell $eq $eq$ls180.v:6061$1619
+  attribute \src "ls180.v:6163.103-6163.148"
+  cell $eq $eq$ls180.v:6163$1688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251121,10 +252096,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11001
-    connect \Y $eq$ls180.v:6061$1619_Y
+    connect \Y $eq$ls180.v:6163$1688_Y
   end
-  attribute \src "ls180.v:6063.101-6063.146"
-  cell $eq $eq$ls180.v:6063$1622
+  attribute \src "ls180.v:6165.101-6165.146"
+  cell $eq $eq$ls180.v:6165$1691
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251132,10 +252107,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11010
-    connect \Y $eq$ls180.v:6063$1622_Y
+    connect \Y $eq$ls180.v:6165$1691_Y
   end
-  attribute \src "ls180.v:6064.104-6064.149"
-  cell $eq $eq$ls180.v:6064$1626
+  attribute \src "ls180.v:6166.104-6166.149"
+  cell $eq $eq$ls180.v:6166$1695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251143,10 +252118,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11010
-    connect \Y $eq$ls180.v:6064$1626_Y
+    connect \Y $eq$ls180.v:6166$1695_Y
   end
-  attribute \src "ls180.v:6066.104-6066.149"
-  cell $eq $eq$ls180.v:6066$1629
+  attribute \src "ls180.v:6168.104-6168.149"
+  cell $eq $eq$ls180.v:6168$1698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251154,10 +252129,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11011
-    connect \Y $eq$ls180.v:6066$1629_Y
+    connect \Y $eq$ls180.v:6168$1698_Y
   end
-  attribute \src "ls180.v:6067.107-6067.152"
-  cell $eq $eq$ls180.v:6067$1633
+  attribute \src "ls180.v:6169.107-6169.152"
+  cell $eq $eq$ls180.v:6169$1702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251165,10 +252140,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11011
-    connect \Y $eq$ls180.v:6067$1633_Y
+    connect \Y $eq$ls180.v:6169$1702_Y
   end
-  attribute \src "ls180.v:6069.104-6069.149"
-  cell $eq $eq$ls180.v:6069$1636
+  attribute \src "ls180.v:6171.104-6171.149"
+  cell $eq $eq$ls180.v:6171$1705
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251176,10 +252151,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11100
-    connect \Y $eq$ls180.v:6069$1636_Y
+    connect \Y $eq$ls180.v:6171$1705_Y
   end
-  attribute \src "ls180.v:6070.107-6070.152"
-  cell $eq $eq$ls180.v:6070$1640
+  attribute \src "ls180.v:6172.107-6172.152"
+  cell $eq $eq$ls180.v:6172$1709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251187,10 +252162,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11100
-    connect \Y $eq$ls180.v:6070$1640_Y
+    connect \Y $eq$ls180.v:6172$1709_Y
   end
-  attribute \src "ls180.v:6072.103-6072.148"
-  cell $eq $eq$ls180.v:6072$1643
+  attribute \src "ls180.v:6174.103-6174.148"
+  cell $eq $eq$ls180.v:6174$1712
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251198,10 +252173,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11101
-    connect \Y $eq$ls180.v:6072$1643_Y
+    connect \Y $eq$ls180.v:6174$1712_Y
   end
-  attribute \src "ls180.v:6073.106-6073.151"
-  cell $eq $eq$ls180.v:6073$1647
+  attribute \src "ls180.v:6175.106-6175.151"
+  cell $eq $eq$ls180.v:6175$1716
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251209,10 +252184,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11101
-    connect \Y $eq$ls180.v:6073$1647_Y
+    connect \Y $eq$ls180.v:6175$1716_Y
   end
-  attribute \src "ls180.v:6075.103-6075.148"
-  cell $eq $eq$ls180.v:6075$1650
+  attribute \src "ls180.v:6177.103-6177.148"
+  cell $eq $eq$ls180.v:6177$1719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251220,10 +252195,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11110
-    connect \Y $eq$ls180.v:6075$1650_Y
+    connect \Y $eq$ls180.v:6177$1719_Y
   end
-  attribute \src "ls180.v:6076.106-6076.151"
-  cell $eq $eq$ls180.v:6076$1654
+  attribute \src "ls180.v:6178.106-6178.151"
+  cell $eq $eq$ls180.v:6178$1723
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251231,10 +252206,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11110
-    connect \Y $eq$ls180.v:6076$1654_Y
+    connect \Y $eq$ls180.v:6178$1723_Y
   end
-  attribute \src "ls180.v:6078.103-6078.148"
-  cell $eq $eq$ls180.v:6078$1657
+  attribute \src "ls180.v:6180.103-6180.148"
+  cell $eq $eq$ls180.v:6180$1726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251242,10 +252217,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11111
-    connect \Y $eq$ls180.v:6078$1657_Y
+    connect \Y $eq$ls180.v:6180$1726_Y
   end
-  attribute \src "ls180.v:6079.106-6079.151"
-  cell $eq $eq$ls180.v:6079$1661
+  attribute \src "ls180.v:6181.106-6181.151"
+  cell $eq $eq$ls180.v:6181$1730
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251253,10 +252228,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 5'11111
-    connect \Y $eq$ls180.v:6079$1661_Y
+    connect \Y $eq$ls180.v:6181$1730_Y
   end
-  attribute \src "ls180.v:6081.103-6081.148"
-  cell $eq $eq$ls180.v:6081$1664
+  attribute \src "ls180.v:6183.103-6183.148"
+  cell $eq $eq$ls180.v:6183$1733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251264,10 +252239,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 6'100000
-    connect \Y $eq$ls180.v:6081$1664_Y
+    connect \Y $eq$ls180.v:6183$1733_Y
   end
-  attribute \src "ls180.v:6082.106-6082.151"
-  cell $eq $eq$ls180.v:6082$1668
+  attribute \src "ls180.v:6184.106-6184.151"
+  cell $eq $eq$ls180.v:6184$1737
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -251275,10 +252250,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_adr [5:0]
     connect \B 6'100000
-    connect \Y $eq$ls180.v:6082$1668_Y
+    connect \Y $eq$ls180.v:6184$1737_Y
   end
-  attribute \src "ls180.v:6118.32-6118.78"
-  cell $eq $eq$ls180.v:6118$1670
+  attribute \src "ls180.v:6220.32-6220.78"
+  cell $eq $eq$ls180.v:6220$1739
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251286,10 +252261,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [13:9]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6118$1670_Y
+    connect \Y $eq$ls180.v:6220$1739_Y
   end
-  attribute \src "ls180.v:6120.100-6120.144"
-  cell $eq $eq$ls180.v:6120$1672
+  attribute \src "ls180.v:6222.100-6222.144"
+  cell $eq $eq$ls180.v:6222$1741
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251297,10 +252272,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6120$1672_Y
+    connect \Y $eq$ls180.v:6222$1741_Y
   end
-  attribute \src "ls180.v:6121.103-6121.147"
-  cell $eq $eq$ls180.v:6121$1676
+  attribute \src "ls180.v:6223.103-6223.147"
+  cell $eq $eq$ls180.v:6223$1745
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251308,10 +252283,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6121$1676_Y
+    connect \Y $eq$ls180.v:6223$1745_Y
   end
-  attribute \src "ls180.v:6123.100-6123.144"
-  cell $eq $eq$ls180.v:6123$1679
+  attribute \src "ls180.v:6225.100-6225.144"
+  cell $eq $eq$ls180.v:6225$1748
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251319,10 +252294,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6123$1679_Y
+    connect \Y $eq$ls180.v:6225$1748_Y
   end
-  attribute \src "ls180.v:6124.103-6124.147"
-  cell $eq $eq$ls180.v:6124$1683
+  attribute \src "ls180.v:6226.103-6226.147"
+  cell $eq $eq$ls180.v:6226$1752
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251330,10 +252305,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6124$1683_Y
+    connect \Y $eq$ls180.v:6226$1752_Y
   end
-  attribute \src "ls180.v:6126.100-6126.144"
-  cell $eq $eq$ls180.v:6126$1686
+  attribute \src "ls180.v:6228.100-6228.144"
+  cell $eq $eq$ls180.v:6228$1755
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251341,10 +252316,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6126$1686_Y
+    connect \Y $eq$ls180.v:6228$1755_Y
   end
-  attribute \src "ls180.v:6127.103-6127.147"
-  cell $eq $eq$ls180.v:6127$1690
+  attribute \src "ls180.v:6229.103-6229.147"
+  cell $eq $eq$ls180.v:6229$1759
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251352,10 +252327,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6127$1690_Y
+    connect \Y $eq$ls180.v:6229$1759_Y
   end
-  attribute \src "ls180.v:6129.100-6129.144"
-  cell $eq $eq$ls180.v:6129$1693
+  attribute \src "ls180.v:6231.100-6231.144"
+  cell $eq $eq$ls180.v:6231$1762
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251363,10 +252338,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6129$1693_Y
+    connect \Y $eq$ls180.v:6231$1762_Y
   end
-  attribute \src "ls180.v:6130.103-6130.147"
-  cell $eq $eq$ls180.v:6130$1697
+  attribute \src "ls180.v:6232.103-6232.147"
+  cell $eq $eq$ls180.v:6232$1766
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251374,10 +252349,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6130$1697_Y
+    connect \Y $eq$ls180.v:6232$1766_Y
   end
-  attribute \src "ls180.v:6132.100-6132.144"
-  cell $eq $eq$ls180.v:6132$1700
+  attribute \src "ls180.v:6234.100-6234.144"
+  cell $eq $eq$ls180.v:6234$1769
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251385,10 +252360,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6132$1700_Y
+    connect \Y $eq$ls180.v:6234$1769_Y
   end
-  attribute \src "ls180.v:6133.103-6133.147"
-  cell $eq $eq$ls180.v:6133$1704
+  attribute \src "ls180.v:6235.103-6235.147"
+  cell $eq $eq$ls180.v:6235$1773
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251396,10 +252371,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6133$1704_Y
+    connect \Y $eq$ls180.v:6235$1773_Y
   end
-  attribute \src "ls180.v:6135.100-6135.144"
-  cell $eq $eq$ls180.v:6135$1707
+  attribute \src "ls180.v:6237.100-6237.144"
+  cell $eq $eq$ls180.v:6237$1776
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251407,10 +252382,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6135$1707_Y
+    connect \Y $eq$ls180.v:6237$1776_Y
   end
-  attribute \src "ls180.v:6136.103-6136.147"
-  cell $eq $eq$ls180.v:6136$1711
+  attribute \src "ls180.v:6238.103-6238.147"
+  cell $eq $eq$ls180.v:6238$1780
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251418,10 +252393,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6136$1711_Y
+    connect \Y $eq$ls180.v:6238$1780_Y
   end
-  attribute \src "ls180.v:6138.100-6138.144"
-  cell $eq $eq$ls180.v:6138$1714
+  attribute \src "ls180.v:6240.100-6240.144"
+  cell $eq $eq$ls180.v:6240$1783
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251429,10 +252404,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6138$1714_Y
+    connect \Y $eq$ls180.v:6240$1783_Y
   end
-  attribute \src "ls180.v:6139.103-6139.147"
-  cell $eq $eq$ls180.v:6139$1718
+  attribute \src "ls180.v:6241.103-6241.147"
+  cell $eq $eq$ls180.v:6241$1787
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251440,10 +252415,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6139$1718_Y
+    connect \Y $eq$ls180.v:6241$1787_Y
   end
-  attribute \src "ls180.v:6141.100-6141.144"
-  cell $eq $eq$ls180.v:6141$1721
+  attribute \src "ls180.v:6243.100-6243.144"
+  cell $eq $eq$ls180.v:6243$1790
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251451,10 +252426,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6141$1721_Y
+    connect \Y $eq$ls180.v:6243$1790_Y
   end
-  attribute \src "ls180.v:6142.103-6142.147"
-  cell $eq $eq$ls180.v:6142$1725
+  attribute \src "ls180.v:6244.103-6244.147"
+  cell $eq $eq$ls180.v:6244$1794
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251462,10 +252437,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6142$1725_Y
+    connect \Y $eq$ls180.v:6244$1794_Y
   end
-  attribute \src "ls180.v:6144.102-6144.146"
-  cell $eq $eq$ls180.v:6144$1728
+  attribute \src "ls180.v:6246.102-6246.146"
+  cell $eq $eq$ls180.v:6246$1797
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251473,10 +252448,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6144$1728_Y
+    connect \Y $eq$ls180.v:6246$1797_Y
   end
-  attribute \src "ls180.v:6145.105-6145.149"
-  cell $eq $eq$ls180.v:6145$1732
+  attribute \src "ls180.v:6247.105-6247.149"
+  cell $eq $eq$ls180.v:6247$1801
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251484,10 +252459,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6145$1732_Y
+    connect \Y $eq$ls180.v:6247$1801_Y
   end
-  attribute \src "ls180.v:6147.102-6147.146"
-  cell $eq $eq$ls180.v:6147$1735
+  attribute \src "ls180.v:6249.102-6249.146"
+  cell $eq $eq$ls180.v:6249$1804
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251495,10 +252470,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6147$1735_Y
+    connect \Y $eq$ls180.v:6249$1804_Y
   end
-  attribute \src "ls180.v:6148.105-6148.149"
-  cell $eq $eq$ls180.v:6148$1739
+  attribute \src "ls180.v:6250.105-6250.149"
+  cell $eq $eq$ls180.v:6250$1808
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251506,10 +252481,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6148$1739_Y
+    connect \Y $eq$ls180.v:6250$1808_Y
   end
-  attribute \src "ls180.v:6150.102-6150.147"
-  cell $eq $eq$ls180.v:6150$1742
+  attribute \src "ls180.v:6252.102-6252.147"
+  cell $eq $eq$ls180.v:6252$1811
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251517,10 +252492,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6150$1742_Y
+    connect \Y $eq$ls180.v:6252$1811_Y
   end
-  attribute \src "ls180.v:6151.105-6151.150"
-  cell $eq $eq$ls180.v:6151$1746
+  attribute \src "ls180.v:6253.105-6253.150"
+  cell $eq $eq$ls180.v:6253$1815
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251528,10 +252503,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6151$1746_Y
+    connect \Y $eq$ls180.v:6253$1815_Y
   end
-  attribute \src "ls180.v:6153.102-6153.147"
-  cell $eq $eq$ls180.v:6153$1749
+  attribute \src "ls180.v:6255.102-6255.147"
+  cell $eq $eq$ls180.v:6255$1818
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251539,10 +252514,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6153$1749_Y
+    connect \Y $eq$ls180.v:6255$1818_Y
   end
-  attribute \src "ls180.v:6154.105-6154.150"
-  cell $eq $eq$ls180.v:6154$1753
+  attribute \src "ls180.v:6256.105-6256.150"
+  cell $eq $eq$ls180.v:6256$1822
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251550,10 +252525,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6154$1753_Y
+    connect \Y $eq$ls180.v:6256$1822_Y
   end
-  attribute \src "ls180.v:6156.102-6156.147"
-  cell $eq $eq$ls180.v:6156$1756
+  attribute \src "ls180.v:6258.102-6258.147"
+  cell $eq $eq$ls180.v:6258$1825
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251561,10 +252536,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6156$1756_Y
+    connect \Y $eq$ls180.v:6258$1825_Y
   end
-  attribute \src "ls180.v:6157.105-6157.150"
-  cell $eq $eq$ls180.v:6157$1760
+  attribute \src "ls180.v:6259.105-6259.150"
+  cell $eq $eq$ls180.v:6259$1829
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251572,10 +252547,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6157$1760_Y
+    connect \Y $eq$ls180.v:6259$1829_Y
   end
-  attribute \src "ls180.v:6159.99-6159.144"
-  cell $eq $eq$ls180.v:6159$1763
+  attribute \src "ls180.v:6261.99-6261.144"
+  cell $eq $eq$ls180.v:6261$1832
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251583,10 +252558,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6159$1763_Y
+    connect \Y $eq$ls180.v:6261$1832_Y
   end
-  attribute \src "ls180.v:6160.102-6160.147"
-  cell $eq $eq$ls180.v:6160$1767
+  attribute \src "ls180.v:6262.102-6262.147"
+  cell $eq $eq$ls180.v:6262$1836
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251594,10 +252569,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6160$1767_Y
+    connect \Y $eq$ls180.v:6262$1836_Y
   end
-  attribute \src "ls180.v:6162.100-6162.145"
-  cell $eq $eq$ls180.v:6162$1770
+  attribute \src "ls180.v:6264.100-6264.145"
+  cell $eq $eq$ls180.v:6264$1839
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251605,10 +252580,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6162$1770_Y
+    connect \Y $eq$ls180.v:6264$1839_Y
   end
-  attribute \src "ls180.v:6163.103-6163.148"
-  cell $eq $eq$ls180.v:6163$1774
+  attribute \src "ls180.v:6265.103-6265.148"
+  cell $eq $eq$ls180.v:6265$1843
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251616,10 +252591,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6163$1774_Y
+    connect \Y $eq$ls180.v:6265$1843_Y
   end
-  attribute \src "ls180.v:6165.102-6165.147"
-  cell $eq $eq$ls180.v:6165$1777
+  attribute \src "ls180.v:6267.102-6267.147"
+  cell $eq $eq$ls180.v:6267$1846
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251627,10 +252602,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6165$1777_Y
+    connect \Y $eq$ls180.v:6267$1846_Y
   end
-  attribute \src "ls180.v:6166.105-6166.150"
-  cell $eq $eq$ls180.v:6166$1781
+  attribute \src "ls180.v:6268.105-6268.150"
+  cell $eq $eq$ls180.v:6268$1850
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251638,10 +252613,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6166$1781_Y
+    connect \Y $eq$ls180.v:6268$1850_Y
   end
-  attribute \src "ls180.v:6168.102-6168.147"
-  cell $eq $eq$ls180.v:6168$1784
+  attribute \src "ls180.v:6270.102-6270.147"
+  cell $eq $eq$ls180.v:6270$1853
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251649,10 +252624,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6168$1784_Y
+    connect \Y $eq$ls180.v:6270$1853_Y
   end
-  attribute \src "ls180.v:6169.105-6169.150"
-  cell $eq $eq$ls180.v:6169$1788
+  attribute \src "ls180.v:6271.105-6271.150"
+  cell $eq $eq$ls180.v:6271$1857
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251660,10 +252635,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6169$1788_Y
+    connect \Y $eq$ls180.v:6271$1857_Y
   end
-  attribute \src "ls180.v:6171.102-6171.147"
-  cell $eq $eq$ls180.v:6171$1791
+  attribute \src "ls180.v:6273.102-6273.147"
+  cell $eq $eq$ls180.v:6273$1860
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251671,10 +252646,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10001
-    connect \Y $eq$ls180.v:6171$1791_Y
+    connect \Y $eq$ls180.v:6273$1860_Y
   end
-  attribute \src "ls180.v:6172.105-6172.150"
-  cell $eq $eq$ls180.v:6172$1795
+  attribute \src "ls180.v:6274.105-6274.150"
+  cell $eq $eq$ls180.v:6274$1864
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251682,10 +252657,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10001
-    connect \Y $eq$ls180.v:6172$1795_Y
+    connect \Y $eq$ls180.v:6274$1864_Y
   end
-  attribute \src "ls180.v:6174.102-6174.147"
-  cell $eq $eq$ls180.v:6174$1798
+  attribute \src "ls180.v:6276.102-6276.147"
+  cell $eq $eq$ls180.v:6276$1867
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251693,10 +252668,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10010
-    connect \Y $eq$ls180.v:6174$1798_Y
+    connect \Y $eq$ls180.v:6276$1867_Y
   end
-  attribute \src "ls180.v:6175.105-6175.150"
-  cell $eq $eq$ls180.v:6175$1802
+  attribute \src "ls180.v:6277.105-6277.150"
+  cell $eq $eq$ls180.v:6277$1871
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251704,10 +252679,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_adr [4:0]
     connect \B 5'10010
-    connect \Y $eq$ls180.v:6175$1802_Y
+    connect \Y $eq$ls180.v:6277$1871_Y
   end
-  attribute \src "ls180.v:6197.32-6197.78"
-  cell $eq $eq$ls180.v:6197$1804
+  attribute \src "ls180.v:6299.32-6299.78"
+  cell $eq $eq$ls180.v:6299$1873
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251715,10 +252690,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [13:9]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6197$1804_Y
+    connect \Y $eq$ls180.v:6299$1873_Y
   end
-  attribute \src "ls180.v:6199.102-6199.146"
-  cell $eq $eq$ls180.v:6199$1806
+  attribute \src "ls180.v:6301.102-6301.146"
+  cell $eq $eq$ls180.v:6301$1875
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251726,10 +252701,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6199$1806_Y
+    connect \Y $eq$ls180.v:6301$1875_Y
   end
-  attribute \src "ls180.v:6200.105-6200.149"
-  cell $eq $eq$ls180.v:6200$1810
+  attribute \src "ls180.v:6302.105-6302.149"
+  cell $eq $eq$ls180.v:6302$1879
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251737,10 +252712,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6200$1810_Y
+    connect \Y $eq$ls180.v:6302$1879_Y
   end
-  attribute \src "ls180.v:6202.107-6202.151"
-  cell $eq $eq$ls180.v:6202$1813
+  attribute \src "ls180.v:6304.107-6304.151"
+  cell $eq $eq$ls180.v:6304$1882
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251748,10 +252723,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6202$1813_Y
+    connect \Y $eq$ls180.v:6304$1882_Y
   end
-  attribute \src "ls180.v:6203.110-6203.154"
-  cell $eq $eq$ls180.v:6203$1817
+  attribute \src "ls180.v:6305.110-6305.154"
+  cell $eq $eq$ls180.v:6305$1886
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251759,10 +252734,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6203$1817_Y
+    connect \Y $eq$ls180.v:6305$1886_Y
   end
-  attribute \src "ls180.v:6205.107-6205.151"
-  cell $eq $eq$ls180.v:6205$1820
+  attribute \src "ls180.v:6307.107-6307.151"
+  cell $eq $eq$ls180.v:6307$1889
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251770,10 +252745,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6205$1820_Y
+    connect \Y $eq$ls180.v:6307$1889_Y
   end
-  attribute \src "ls180.v:6206.110-6206.154"
-  cell $eq $eq$ls180.v:6206$1824
+  attribute \src "ls180.v:6308.110-6308.154"
+  cell $eq $eq$ls180.v:6308$1893
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251781,10 +252756,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6206$1824_Y
+    connect \Y $eq$ls180.v:6308$1893_Y
   end
-  attribute \src "ls180.v:6208.100-6208.144"
-  cell $eq $eq$ls180.v:6208$1827
+  attribute \src "ls180.v:6310.100-6310.144"
+  cell $eq $eq$ls180.v:6310$1896
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251792,10 +252767,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6208$1827_Y
+    connect \Y $eq$ls180.v:6310$1896_Y
   end
-  attribute \src "ls180.v:6209.103-6209.147"
-  cell $eq $eq$ls180.v:6209$1831
+  attribute \src "ls180.v:6311.103-6311.147"
+  cell $eq $eq$ls180.v:6311$1900
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -251803,10 +252778,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6209$1831_Y
+    connect \Y $eq$ls180.v:6311$1900_Y
   end
-  attribute \src "ls180.v:6214.32-6214.77"
-  cell $eq $eq$ls180.v:6214$1833
+  attribute \src "ls180.v:6316.32-6316.77"
+  cell $eq $eq$ls180.v:6316$1902
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -251814,10 +252789,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [13:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6214$1833_Y
+    connect \Y $eq$ls180.v:6316$1902_Y
   end
-  attribute \src "ls180.v:6216.104-6216.148"
-  cell $eq $eq$ls180.v:6216$1835
+  attribute \src "ls180.v:6318.104-6318.148"
+  cell $eq $eq$ls180.v:6318$1904
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251825,10 +252800,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6216$1835_Y
+    connect \Y $eq$ls180.v:6318$1904_Y
   end
-  attribute \src "ls180.v:6217.107-6217.151"
-  cell $eq $eq$ls180.v:6217$1839
+  attribute \src "ls180.v:6319.107-6319.151"
+  cell $eq $eq$ls180.v:6319$1908
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251836,10 +252811,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6217$1839_Y
+    connect \Y $eq$ls180.v:6319$1908_Y
   end
-  attribute \src "ls180.v:6219.108-6219.152"
-  cell $eq $eq$ls180.v:6219$1842
+  attribute \src "ls180.v:6321.108-6321.152"
+  cell $eq $eq$ls180.v:6321$1911
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251847,10 +252822,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6219$1842_Y
+    connect \Y $eq$ls180.v:6321$1911_Y
   end
-  attribute \src "ls180.v:6220.111-6220.155"
-  cell $eq $eq$ls180.v:6220$1846
+  attribute \src "ls180.v:6322.111-6322.155"
+  cell $eq $eq$ls180.v:6322$1915
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251858,10 +252833,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6220$1846_Y
+    connect \Y $eq$ls180.v:6322$1915_Y
   end
-  attribute \src "ls180.v:6222.98-6222.142"
-  cell $eq $eq$ls180.v:6222$1849
+  attribute \src "ls180.v:6324.98-6324.142"
+  cell $eq $eq$ls180.v:6324$1918
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251869,10 +252844,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6222$1849_Y
+    connect \Y $eq$ls180.v:6324$1918_Y
   end
-  attribute \src "ls180.v:6223.101-6223.145"
-  cell $eq $eq$ls180.v:6223$1853
+  attribute \src "ls180.v:6325.101-6325.145"
+  cell $eq $eq$ls180.v:6325$1922
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251880,10 +252855,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6223$1853_Y
+    connect \Y $eq$ls180.v:6325$1922_Y
   end
-  attribute \src "ls180.v:6225.108-6225.152"
-  cell $eq $eq$ls180.v:6225$1856
+  attribute \src "ls180.v:6327.108-6327.152"
+  cell $eq $eq$ls180.v:6327$1925
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251891,10 +252866,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6225$1856_Y
+    connect \Y $eq$ls180.v:6327$1925_Y
   end
-  attribute \src "ls180.v:6226.111-6226.155"
-  cell $eq $eq$ls180.v:6226$1860
+  attribute \src "ls180.v:6328.111-6328.155"
+  cell $eq $eq$ls180.v:6328$1929
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251902,10 +252877,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6226$1860_Y
+    connect \Y $eq$ls180.v:6328$1929_Y
   end
-  attribute \src "ls180.v:6228.108-6228.152"
-  cell $eq $eq$ls180.v:6228$1863
+  attribute \src "ls180.v:6330.108-6330.152"
+  cell $eq $eq$ls180.v:6330$1932
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251913,10 +252888,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6228$1863_Y
+    connect \Y $eq$ls180.v:6330$1932_Y
   end
-  attribute \src "ls180.v:6229.111-6229.155"
-  cell $eq $eq$ls180.v:6229$1867
+  attribute \src "ls180.v:6331.111-6331.155"
+  cell $eq $eq$ls180.v:6331$1936
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251924,10 +252899,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6229$1867_Y
+    connect \Y $eq$ls180.v:6331$1936_Y
   end
-  attribute \src "ls180.v:6231.109-6231.153"
-  cell $eq $eq$ls180.v:6231$1870
+  attribute \src "ls180.v:6333.109-6333.153"
+  cell $eq $eq$ls180.v:6333$1939
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251935,10 +252910,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6231$1870_Y
+    connect \Y $eq$ls180.v:6333$1939_Y
   end
-  attribute \src "ls180.v:6232.112-6232.156"
-  cell $eq $eq$ls180.v:6232$1874
+  attribute \src "ls180.v:6334.112-6334.156"
+  cell $eq $eq$ls180.v:6334$1943
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251946,10 +252921,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6232$1874_Y
+    connect \Y $eq$ls180.v:6334$1943_Y
   end
-  attribute \src "ls180.v:6234.107-6234.151"
-  cell $eq $eq$ls180.v:6234$1877
+  attribute \src "ls180.v:6336.107-6336.151"
+  cell $eq $eq$ls180.v:6336$1946
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251957,10 +252932,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6234$1877_Y
+    connect \Y $eq$ls180.v:6336$1946_Y
   end
-  attribute \src "ls180.v:6235.110-6235.154"
-  cell $eq $eq$ls180.v:6235$1881
+  attribute \src "ls180.v:6337.110-6337.154"
+  cell $eq $eq$ls180.v:6337$1950
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251968,10 +252943,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6235$1881_Y
+    connect \Y $eq$ls180.v:6337$1950_Y
   end
-  attribute \src "ls180.v:6237.107-6237.151"
-  cell $eq $eq$ls180.v:6237$1884
+  attribute \src "ls180.v:6339.107-6339.151"
+  cell $eq $eq$ls180.v:6339$1953
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251979,10 +252954,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6237$1884_Y
+    connect \Y $eq$ls180.v:6339$1953_Y
   end
-  attribute \src "ls180.v:6238.110-6238.154"
-  cell $eq $eq$ls180.v:6238$1888
+  attribute \src "ls180.v:6340.110-6340.154"
+  cell $eq $eq$ls180.v:6340$1957
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -251990,10 +252965,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6238$1888_Y
+    connect \Y $eq$ls180.v:6340$1957_Y
   end
-  attribute \src "ls180.v:6240.107-6240.151"
-  cell $eq $eq$ls180.v:6240$1891
+  attribute \src "ls180.v:6342.107-6342.151"
+  cell $eq $eq$ls180.v:6342$1960
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252001,10 +252976,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6240$1891_Y
+    connect \Y $eq$ls180.v:6342$1960_Y
   end
-  attribute \src "ls180.v:6241.110-6241.154"
-  cell $eq $eq$ls180.v:6241$1895
+  attribute \src "ls180.v:6343.110-6343.154"
+  cell $eq $eq$ls180.v:6343$1964
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252012,10 +252987,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6241$1895_Y
+    connect \Y $eq$ls180.v:6343$1964_Y
   end
-  attribute \src "ls180.v:6243.107-6243.151"
-  cell $eq $eq$ls180.v:6243$1898
+  attribute \src "ls180.v:6345.107-6345.151"
+  cell $eq $eq$ls180.v:6345$1967
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252023,10 +252998,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6243$1898_Y
+    connect \Y $eq$ls180.v:6345$1967_Y
   end
-  attribute \src "ls180.v:6244.110-6244.154"
-  cell $eq $eq$ls180.v:6244$1902
+  attribute \src "ls180.v:6346.110-6346.154"
+  cell $eq $eq$ls180.v:6346$1971
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252034,10 +253009,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6244$1902_Y
+    connect \Y $eq$ls180.v:6346$1971_Y
   end
-  attribute \src "ls180.v:6259.33-6259.79"
-  cell $eq $eq$ls180.v:6259$1904
+  attribute \src "ls180.v:6361.33-6361.79"
+  cell $eq $eq$ls180.v:6361$1973
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252045,10 +253020,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [13:9]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6259$1904_Y
+    connect \Y $eq$ls180.v:6361$1973_Y
   end
-  attribute \src "ls180.v:6261.102-6261.147"
-  cell $eq $eq$ls180.v:6261$1906
+  attribute \src "ls180.v:6363.102-6363.147"
+  cell $eq $eq$ls180.v:6363$1975
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252056,10 +253031,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6261$1906_Y
+    connect \Y $eq$ls180.v:6363$1975_Y
   end
-  attribute \src "ls180.v:6262.105-6262.150"
-  cell $eq $eq$ls180.v:6262$1910
+  attribute \src "ls180.v:6364.105-6364.150"
+  cell $eq $eq$ls180.v:6364$1979
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252067,10 +253042,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6262$1910_Y
+    connect \Y $eq$ls180.v:6364$1979_Y
   end
-  attribute \src "ls180.v:6264.102-6264.147"
-  cell $eq $eq$ls180.v:6264$1913
+  attribute \src "ls180.v:6366.102-6366.147"
+  cell $eq $eq$ls180.v:6366$1982
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252078,10 +253053,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6264$1913_Y
+    connect \Y $eq$ls180.v:6366$1982_Y
   end
-  attribute \src "ls180.v:6265.105-6265.150"
-  cell $eq $eq$ls180.v:6265$1917
+  attribute \src "ls180.v:6367.105-6367.150"
+  cell $eq $eq$ls180.v:6367$1986
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252089,10 +253064,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6265$1917_Y
+    connect \Y $eq$ls180.v:6367$1986_Y
   end
-  attribute \src "ls180.v:6267.100-6267.145"
-  cell $eq $eq$ls180.v:6267$1920
+  attribute \src "ls180.v:6369.100-6369.145"
+  cell $eq $eq$ls180.v:6369$1989
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252100,10 +253075,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6267$1920_Y
+    connect \Y $eq$ls180.v:6369$1989_Y
   end
-  attribute \src "ls180.v:6268.103-6268.148"
-  cell $eq $eq$ls180.v:6268$1924
+  attribute \src "ls180.v:6370.103-6370.148"
+  cell $eq $eq$ls180.v:6370$1993
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252111,10 +253086,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6268$1924_Y
+    connect \Y $eq$ls180.v:6370$1993_Y
   end
-  attribute \src "ls180.v:6270.99-6270.144"
-  cell $eq $eq$ls180.v:6270$1927
+  attribute \src "ls180.v:6372.99-6372.144"
+  cell $eq $eq$ls180.v:6372$1996
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252122,10 +253097,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6270$1927_Y
+    connect \Y $eq$ls180.v:6372$1996_Y
   end
-  attribute \src "ls180.v:6271.102-6271.147"
-  cell $eq $eq$ls180.v:6271$1931
+  attribute \src "ls180.v:6373.102-6373.147"
+  cell $eq $eq$ls180.v:6373$2000
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252133,10 +253108,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6271$1931_Y
+    connect \Y $eq$ls180.v:6373$2000_Y
   end
-  attribute \src "ls180.v:6273.98-6273.143"
-  cell $eq $eq$ls180.v:6273$1934
+  attribute \src "ls180.v:6375.98-6375.143"
+  cell $eq $eq$ls180.v:6375$2003
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252144,10 +253119,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6273$1934_Y
+    connect \Y $eq$ls180.v:6375$2003_Y
   end
-  attribute \src "ls180.v:6274.101-6274.146"
-  cell $eq $eq$ls180.v:6274$1938
+  attribute \src "ls180.v:6376.101-6376.146"
+  cell $eq $eq$ls180.v:6376$2007
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252155,10 +253130,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6274$1938_Y
+    connect \Y $eq$ls180.v:6376$2007_Y
   end
-  attribute \src "ls180.v:6276.97-6276.142"
-  cell $eq $eq$ls180.v:6276$1941
+  attribute \src "ls180.v:6378.97-6378.142"
+  cell $eq $eq$ls180.v:6378$2010
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252166,10 +253141,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6276$1941_Y
+    connect \Y $eq$ls180.v:6378$2010_Y
   end
-  attribute \src "ls180.v:6277.100-6277.145"
-  cell $eq $eq$ls180.v:6277$1945
+  attribute \src "ls180.v:6379.100-6379.145"
+  cell $eq $eq$ls180.v:6379$2014
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252177,10 +253152,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6277$1945_Y
+    connect \Y $eq$ls180.v:6379$2014_Y
   end
-  attribute \src "ls180.v:6279.103-6279.148"
-  cell $eq $eq$ls180.v:6279$1948
+  attribute \src "ls180.v:6381.103-6381.148"
+  cell $eq $eq$ls180.v:6381$2017
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252188,10 +253163,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6279$1948_Y
+    connect \Y $eq$ls180.v:6381$2017_Y
   end
-  attribute \src "ls180.v:6280.106-6280.151"
-  cell $eq $eq$ls180.v:6280$1952
+  attribute \src "ls180.v:6382.106-6382.151"
+  cell $eq $eq$ls180.v:6382$2021
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252199,10 +253174,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6280$1952_Y
+    connect \Y $eq$ls180.v:6382$2021_Y
   end
-  attribute \src "ls180.v:6299.33-6299.79"
-  cell $eq $eq$ls180.v:6299$1955
+  attribute \src "ls180.v:6401.33-6401.79"
+  cell $eq $eq$ls180.v:6401$2024
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252210,10 +253185,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [13:9]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6299$1955_Y
+    connect \Y $eq$ls180.v:6401$2024_Y
   end
-  attribute \src "ls180.v:6301.102-6301.147"
-  cell $eq $eq$ls180.v:6301$1957
+  attribute \src "ls180.v:6403.102-6403.147"
+  cell $eq $eq$ls180.v:6403$2026
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252221,10 +253196,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6301$1957_Y
+    connect \Y $eq$ls180.v:6403$2026_Y
   end
-  attribute \src "ls180.v:6302.105-6302.150"
-  cell $eq $eq$ls180.v:6302$1961
+  attribute \src "ls180.v:6404.105-6404.150"
+  cell $eq $eq$ls180.v:6404$2030
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252232,10 +253207,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6302$1961_Y
+    connect \Y $eq$ls180.v:6404$2030_Y
   end
-  attribute \src "ls180.v:6304.102-6304.147"
-  cell $eq $eq$ls180.v:6304$1964
+  attribute \src "ls180.v:6406.102-6406.147"
+  cell $eq $eq$ls180.v:6406$2033
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252243,10 +253218,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6304$1964_Y
+    connect \Y $eq$ls180.v:6406$2033_Y
   end
-  attribute \src "ls180.v:6305.105-6305.150"
-  cell $eq $eq$ls180.v:6305$1968
+  attribute \src "ls180.v:6407.105-6407.150"
+  cell $eq $eq$ls180.v:6407$2037
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252254,10 +253229,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6305$1968_Y
+    connect \Y $eq$ls180.v:6407$2037_Y
   end
-  attribute \src "ls180.v:6307.100-6307.145"
-  cell $eq $eq$ls180.v:6307$1971
+  attribute \src "ls180.v:6409.100-6409.145"
+  cell $eq $eq$ls180.v:6409$2040
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252265,10 +253240,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6307$1971_Y
+    connect \Y $eq$ls180.v:6409$2040_Y
   end
-  attribute \src "ls180.v:6308.103-6308.148"
-  cell $eq $eq$ls180.v:6308$1975
+  attribute \src "ls180.v:6410.103-6410.148"
+  cell $eq $eq$ls180.v:6410$2044
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252276,10 +253251,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6308$1975_Y
+    connect \Y $eq$ls180.v:6410$2044_Y
   end
-  attribute \src "ls180.v:6310.99-6310.144"
-  cell $eq $eq$ls180.v:6310$1978
+  attribute \src "ls180.v:6412.99-6412.144"
+  cell $eq $eq$ls180.v:6412$2047
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252287,10 +253262,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6310$1978_Y
+    connect \Y $eq$ls180.v:6412$2047_Y
   end
-  attribute \src "ls180.v:6311.102-6311.147"
-  cell $eq $eq$ls180.v:6311$1982
+  attribute \src "ls180.v:6413.102-6413.147"
+  cell $eq $eq$ls180.v:6413$2051
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252298,10 +253273,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6311$1982_Y
+    connect \Y $eq$ls180.v:6413$2051_Y
   end
-  attribute \src "ls180.v:6313.98-6313.143"
-  cell $eq $eq$ls180.v:6313$1985
+  attribute \src "ls180.v:6415.98-6415.143"
+  cell $eq $eq$ls180.v:6415$2054
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252309,10 +253284,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6313$1985_Y
+    connect \Y $eq$ls180.v:6415$2054_Y
   end
-  attribute \src "ls180.v:6314.101-6314.146"
-  cell $eq $eq$ls180.v:6314$1989
+  attribute \src "ls180.v:6416.101-6416.146"
+  cell $eq $eq$ls180.v:6416$2058
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252320,10 +253295,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6314$1989_Y
+    connect \Y $eq$ls180.v:6416$2058_Y
   end
-  attribute \src "ls180.v:6316.97-6316.142"
-  cell $eq $eq$ls180.v:6316$1992
+  attribute \src "ls180.v:6418.97-6418.142"
+  cell $eq $eq$ls180.v:6418$2061
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252331,10 +253306,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6316$1992_Y
+    connect \Y $eq$ls180.v:6418$2061_Y
   end
-  attribute \src "ls180.v:6317.100-6317.145"
-  cell $eq $eq$ls180.v:6317$1996
+  attribute \src "ls180.v:6419.100-6419.145"
+  cell $eq $eq$ls180.v:6419$2065
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252342,10 +253317,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6317$1996_Y
+    connect \Y $eq$ls180.v:6419$2065_Y
   end
-  attribute \src "ls180.v:6319.103-6319.148"
-  cell $eq $eq$ls180.v:6319$1999
+  attribute \src "ls180.v:6421.103-6421.148"
+  cell $eq $eq$ls180.v:6421$2068
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252353,10 +253328,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6319$1999_Y
+    connect \Y $eq$ls180.v:6421$2068_Y
   end
-  attribute \src "ls180.v:6320.106-6320.151"
-  cell $eq $eq$ls180.v:6320$2003
+  attribute \src "ls180.v:6422.106-6422.151"
+  cell $eq $eq$ls180.v:6422$2072
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252364,10 +253339,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6320$2003_Y
+    connect \Y $eq$ls180.v:6422$2072_Y
   end
-  attribute \src "ls180.v:6322.106-6322.151"
-  cell $eq $eq$ls180.v:6322$2006
+  attribute \src "ls180.v:6424.106-6424.151"
+  cell $eq $eq$ls180.v:6424$2075
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252375,10 +253350,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6322$2006_Y
+    connect \Y $eq$ls180.v:6424$2075_Y
   end
-  attribute \src "ls180.v:6323.109-6323.154"
-  cell $eq $eq$ls180.v:6323$2010
+  attribute \src "ls180.v:6425.109-6425.154"
+  cell $eq $eq$ls180.v:6425$2079
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252386,10 +253361,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6323$2010_Y
+    connect \Y $eq$ls180.v:6425$2079_Y
   end
-  attribute \src "ls180.v:6325.106-6325.151"
-  cell $eq $eq$ls180.v:6325$2013
+  attribute \src "ls180.v:6427.106-6427.151"
+  cell $eq $eq$ls180.v:6427$2082
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252397,10 +253372,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6325$2013_Y
+    connect \Y $eq$ls180.v:6427$2082_Y
   end
-  attribute \src "ls180.v:6326.109-6326.154"
-  cell $eq $eq$ls180.v:6326$2017
+  attribute \src "ls180.v:6428.109-6428.154"
+  cell $eq $eq$ls180.v:6428$2086
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -252408,10 +253383,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6326$2017_Y
+    connect \Y $eq$ls180.v:6428$2086_Y
   end
-  attribute \src "ls180.v:6347.33-6347.79"
-  cell $eq $eq$ls180.v:6347$2020
+  attribute \src "ls180.v:6449.33-6449.79"
+  cell $eq $eq$ls180.v:6449$2089
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252419,10 +253394,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [13:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6347$2020_Y
+    connect \Y $eq$ls180.v:6449$2089_Y
   end
-  attribute \src "ls180.v:6349.99-6349.144"
-  cell $eq $eq$ls180.v:6349$2022
+  attribute \src "ls180.v:6451.99-6451.144"
+  cell $eq $eq$ls180.v:6451$2091
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252430,10 +253405,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6349$2022_Y
+    connect \Y $eq$ls180.v:6451$2091_Y
   end
-  attribute \src "ls180.v:6350.102-6350.147"
-  cell $eq $eq$ls180.v:6350$2026
+  attribute \src "ls180.v:6452.102-6452.147"
+  cell $eq $eq$ls180.v:6452$2095
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252441,10 +253416,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6350$2026_Y
+    connect \Y $eq$ls180.v:6452$2095_Y
   end
-  attribute \src "ls180.v:6352.99-6352.144"
-  cell $eq $eq$ls180.v:6352$2029
+  attribute \src "ls180.v:6454.99-6454.144"
+  cell $eq $eq$ls180.v:6454$2098
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252452,10 +253427,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6352$2029_Y
+    connect \Y $eq$ls180.v:6454$2098_Y
   end
-  attribute \src "ls180.v:6353.102-6353.147"
-  cell $eq $eq$ls180.v:6353$2033
+  attribute \src "ls180.v:6455.102-6455.147"
+  cell $eq $eq$ls180.v:6455$2102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252463,10 +253438,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6353$2033_Y
+    connect \Y $eq$ls180.v:6455$2102_Y
   end
-  attribute \src "ls180.v:6355.99-6355.144"
-  cell $eq $eq$ls180.v:6355$2036
+  attribute \src "ls180.v:6457.99-6457.144"
+  cell $eq $eq$ls180.v:6457$2105
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252474,10 +253449,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6355$2036_Y
+    connect \Y $eq$ls180.v:6457$2105_Y
   end
-  attribute \src "ls180.v:6356.102-6356.147"
-  cell $eq $eq$ls180.v:6356$2040
+  attribute \src "ls180.v:6458.102-6458.147"
+  cell $eq $eq$ls180.v:6458$2109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252485,10 +253460,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6356$2040_Y
+    connect \Y $eq$ls180.v:6458$2109_Y
   end
-  attribute \src "ls180.v:6358.99-6358.144"
-  cell $eq $eq$ls180.v:6358$2043
+  attribute \src "ls180.v:6460.99-6460.144"
+  cell $eq $eq$ls180.v:6460$2112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252496,10 +253471,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6358$2043_Y
+    connect \Y $eq$ls180.v:6460$2112_Y
   end
-  attribute \src "ls180.v:6359.102-6359.147"
-  cell $eq $eq$ls180.v:6359$2047
+  attribute \src "ls180.v:6461.102-6461.147"
+  cell $eq $eq$ls180.v:6461$2116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252507,10 +253482,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6359$2047_Y
+    connect \Y $eq$ls180.v:6461$2116_Y
   end
-  attribute \src "ls180.v:6361.101-6361.146"
-  cell $eq $eq$ls180.v:6361$2050
+  attribute \src "ls180.v:6463.101-6463.146"
+  cell $eq $eq$ls180.v:6463$2119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252518,10 +253493,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6361$2050_Y
+    connect \Y $eq$ls180.v:6463$2119_Y
   end
-  attribute \src "ls180.v:6362.104-6362.149"
-  cell $eq $eq$ls180.v:6362$2054
+  attribute \src "ls180.v:6464.104-6464.149"
+  cell $eq $eq$ls180.v:6464$2123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252529,10 +253504,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6362$2054_Y
+    connect \Y $eq$ls180.v:6464$2123_Y
   end
-  attribute \src "ls180.v:6364.101-6364.146"
-  cell $eq $eq$ls180.v:6364$2057
+  attribute \src "ls180.v:6466.101-6466.146"
+  cell $eq $eq$ls180.v:6466$2126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252540,10 +253515,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6364$2057_Y
+    connect \Y $eq$ls180.v:6466$2126_Y
   end
-  attribute \src "ls180.v:6365.104-6365.149"
-  cell $eq $eq$ls180.v:6365$2061
+  attribute \src "ls180.v:6467.104-6467.149"
+  cell $eq $eq$ls180.v:6467$2130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252551,10 +253526,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6365$2061_Y
+    connect \Y $eq$ls180.v:6467$2130_Y
   end
-  attribute \src "ls180.v:6367.101-6367.146"
-  cell $eq $eq$ls180.v:6367$2064
+  attribute \src "ls180.v:6469.101-6469.146"
+  cell $eq $eq$ls180.v:6469$2133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252562,10 +253537,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6367$2064_Y
+    connect \Y $eq$ls180.v:6469$2133_Y
   end
-  attribute \src "ls180.v:6368.104-6368.149"
-  cell $eq $eq$ls180.v:6368$2068
+  attribute \src "ls180.v:6470.104-6470.149"
+  cell $eq $eq$ls180.v:6470$2137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252573,10 +253548,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6368$2068_Y
+    connect \Y $eq$ls180.v:6470$2137_Y
   end
-  attribute \src "ls180.v:6370.101-6370.146"
-  cell $eq $eq$ls180.v:6370$2071
+  attribute \src "ls180.v:6472.101-6472.146"
+  cell $eq $eq$ls180.v:6472$2140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252584,10 +253559,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6370$2071_Y
+    connect \Y $eq$ls180.v:6472$2140_Y
   end
-  attribute \src "ls180.v:6371.104-6371.149"
-  cell $eq $eq$ls180.v:6371$2075
+  attribute \src "ls180.v:6473.104-6473.149"
+  cell $eq $eq$ls180.v:6473$2144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252595,10 +253570,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6371$2075_Y
+    connect \Y $eq$ls180.v:6473$2144_Y
   end
-  attribute \src "ls180.v:6373.97-6373.142"
-  cell $eq $eq$ls180.v:6373$2078
+  attribute \src "ls180.v:6475.97-6475.142"
+  cell $eq $eq$ls180.v:6475$2147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252606,10 +253581,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6373$2078_Y
+    connect \Y $eq$ls180.v:6475$2147_Y
   end
-  attribute \src "ls180.v:6374.100-6374.145"
-  cell $eq $eq$ls180.v:6374$2082
+  attribute \src "ls180.v:6476.100-6476.145"
+  cell $eq $eq$ls180.v:6476$2151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252617,10 +253592,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:6374$2082_Y
+    connect \Y $eq$ls180.v:6476$2151_Y
   end
-  attribute \src "ls180.v:6376.107-6376.152"
-  cell $eq $eq$ls180.v:6376$2085
+  attribute \src "ls180.v:6478.107-6478.152"
+  cell $eq $eq$ls180.v:6478$2154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252628,10 +253603,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6376$2085_Y
+    connect \Y $eq$ls180.v:6478$2154_Y
   end
-  attribute \src "ls180.v:6377.110-6377.155"
-  cell $eq $eq$ls180.v:6377$2089
+  attribute \src "ls180.v:6479.110-6479.155"
+  cell $eq $eq$ls180.v:6479$2158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252639,10 +253614,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:6377$2089_Y
+    connect \Y $eq$ls180.v:6479$2158_Y
   end
-  attribute \src "ls180.v:6379.100-6379.146"
-  cell $eq $eq$ls180.v:6379$2092
+  attribute \src "ls180.v:6481.100-6481.146"
+  cell $eq $eq$ls180.v:6481$2161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252650,10 +253625,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6379$2092_Y
+    connect \Y $eq$ls180.v:6481$2161_Y
   end
-  attribute \src "ls180.v:6380.103-6380.149"
-  cell $eq $eq$ls180.v:6380$2096
+  attribute \src "ls180.v:6482.103-6482.149"
+  cell $eq $eq$ls180.v:6482$2165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252661,10 +253636,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:6380$2096_Y
+    connect \Y $eq$ls180.v:6482$2165_Y
   end
-  attribute \src "ls180.v:6382.100-6382.146"
-  cell $eq $eq$ls180.v:6382$2099
+  attribute \src "ls180.v:6484.100-6484.146"
+  cell $eq $eq$ls180.v:6484$2168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252672,10 +253647,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6382$2099_Y
+    connect \Y $eq$ls180.v:6484$2168_Y
   end
-  attribute \src "ls180.v:6383.103-6383.149"
-  cell $eq $eq$ls180.v:6383$2103
+  attribute \src "ls180.v:6485.103-6485.149"
+  cell $eq $eq$ls180.v:6485$2172
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252683,10 +253658,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:6383$2103_Y
+    connect \Y $eq$ls180.v:6485$2172_Y
   end
-  attribute \src "ls180.v:6385.100-6385.146"
-  cell $eq $eq$ls180.v:6385$2106
+  attribute \src "ls180.v:6487.100-6487.146"
+  cell $eq $eq$ls180.v:6487$2175
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252694,10 +253669,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6385$2106_Y
+    connect \Y $eq$ls180.v:6487$2175_Y
   end
-  attribute \src "ls180.v:6386.103-6386.149"
-  cell $eq $eq$ls180.v:6386$2110
+  attribute \src "ls180.v:6488.103-6488.149"
+  cell $eq $eq$ls180.v:6488$2179
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252705,10 +253680,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:6386$2110_Y
+    connect \Y $eq$ls180.v:6488$2179_Y
   end
-  attribute \src "ls180.v:6388.100-6388.146"
-  cell $eq $eq$ls180.v:6388$2113
+  attribute \src "ls180.v:6490.100-6490.146"
+  cell $eq $eq$ls180.v:6490$2182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252716,10 +253691,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6388$2113_Y
+    connect \Y $eq$ls180.v:6490$2182_Y
   end
-  attribute \src "ls180.v:6389.103-6389.149"
-  cell $eq $eq$ls180.v:6389$2117
+  attribute \src "ls180.v:6491.103-6491.149"
+  cell $eq $eq$ls180.v:6491$2186
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252727,10 +253702,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:6389$2117_Y
+    connect \Y $eq$ls180.v:6491$2186_Y
   end
-  attribute \src "ls180.v:6391.112-6391.158"
-  cell $eq $eq$ls180.v:6391$2120
+  attribute \src "ls180.v:6493.112-6493.158"
+  cell $eq $eq$ls180.v:6493$2189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252738,10 +253713,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6391$2120_Y
+    connect \Y $eq$ls180.v:6493$2189_Y
   end
-  attribute \src "ls180.v:6392.115-6392.161"
-  cell $eq $eq$ls180.v:6392$2124
+  attribute \src "ls180.v:6494.115-6494.161"
+  cell $eq $eq$ls180.v:6494$2193
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252749,10 +253724,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:6392$2124_Y
+    connect \Y $eq$ls180.v:6494$2193_Y
   end
-  attribute \src "ls180.v:6394.113-6394.159"
-  cell $eq $eq$ls180.v:6394$2127
+  attribute \src "ls180.v:6496.113-6496.159"
+  cell $eq $eq$ls180.v:6496$2196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252760,10 +253735,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6394$2127_Y
+    connect \Y $eq$ls180.v:6496$2196_Y
   end
-  attribute \src "ls180.v:6395.116-6395.162"
-  cell $eq $eq$ls180.v:6395$2131
+  attribute \src "ls180.v:6497.116-6497.162"
+  cell $eq $eq$ls180.v:6497$2200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252771,10 +253746,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:6395$2131_Y
+    connect \Y $eq$ls180.v:6497$2200_Y
   end
-  attribute \src "ls180.v:6397.104-6397.150"
-  cell $eq $eq$ls180.v:6397$2134
+  attribute \src "ls180.v:6499.104-6499.150"
+  cell $eq $eq$ls180.v:6499$2203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252782,10 +253757,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6397$2134_Y
+    connect \Y $eq$ls180.v:6499$2203_Y
   end
-  attribute \src "ls180.v:6398.107-6398.153"
-  cell $eq $eq$ls180.v:6398$2138
+  attribute \src "ls180.v:6500.107-6500.153"
+  cell $eq $eq$ls180.v:6500$2207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252793,10 +253768,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:6398$2138_Y
+    connect \Y $eq$ls180.v:6500$2207_Y
   end
-  attribute \src "ls180.v:6415.33-6415.79"
-  cell $eq $eq$ls180.v:6415$2140
+  attribute \src "ls180.v:6517.33-6517.79"
+  cell $eq $eq$ls180.v:6517$2209
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252804,10 +253779,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [13:9]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6415$2140_Y
+    connect \Y $eq$ls180.v:6517$2209_Y
   end
-  attribute \src "ls180.v:6417.90-6417.135"
-  cell $eq $eq$ls180.v:6417$2142
+  attribute \src "ls180.v:6519.90-6519.135"
+  cell $eq $eq$ls180.v:6519$2211
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252815,10 +253790,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6417$2142_Y
+    connect \Y $eq$ls180.v:6519$2211_Y
   end
-  attribute \src "ls180.v:6418.93-6418.138"
-  cell $eq $eq$ls180.v:6418$2146
+  attribute \src "ls180.v:6520.93-6520.138"
+  cell $eq $eq$ls180.v:6520$2215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252826,10 +253801,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6418$2146_Y
+    connect \Y $eq$ls180.v:6520$2215_Y
   end
-  attribute \src "ls180.v:6420.100-6420.145"
-  cell $eq $eq$ls180.v:6420$2149
+  attribute \src "ls180.v:6522.100-6522.145"
+  cell $eq $eq$ls180.v:6522$2218
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252837,10 +253812,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6420$2149_Y
+    connect \Y $eq$ls180.v:6522$2218_Y
   end
-  attribute \src "ls180.v:6421.103-6421.148"
-  cell $eq $eq$ls180.v:6421$2153
+  attribute \src "ls180.v:6523.103-6523.148"
+  cell $eq $eq$ls180.v:6523$2222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252848,10 +253823,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6421$2153_Y
+    connect \Y $eq$ls180.v:6523$2222_Y
   end
-  attribute \src "ls180.v:6423.101-6423.146"
-  cell $eq $eq$ls180.v:6423$2156
+  attribute \src "ls180.v:6525.101-6525.146"
+  cell $eq $eq$ls180.v:6525$2225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252859,10 +253834,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6423$2156_Y
+    connect \Y $eq$ls180.v:6525$2225_Y
   end
-  attribute \src "ls180.v:6424.104-6424.149"
-  cell $eq $eq$ls180.v:6424$2160
+  attribute \src "ls180.v:6526.104-6526.149"
+  cell $eq $eq$ls180.v:6526$2229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252870,10 +253845,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6424$2160_Y
+    connect \Y $eq$ls180.v:6526$2229_Y
   end
-  attribute \src "ls180.v:6426.105-6426.150"
-  cell $eq $eq$ls180.v:6426$2163
+  attribute \src "ls180.v:6528.105-6528.150"
+  cell $eq $eq$ls180.v:6528$2232
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252881,10 +253856,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6426$2163_Y
+    connect \Y $eq$ls180.v:6528$2232_Y
   end
-  attribute \src "ls180.v:6427.108-6427.153"
-  cell $eq $eq$ls180.v:6427$2167
+  attribute \src "ls180.v:6529.108-6529.153"
+  cell $eq $eq$ls180.v:6529$2236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252892,10 +253867,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6427$2167_Y
+    connect \Y $eq$ls180.v:6529$2236_Y
   end
-  attribute \src "ls180.v:6429.106-6429.151"
-  cell $eq $eq$ls180.v:6429$2170
+  attribute \src "ls180.v:6531.106-6531.151"
+  cell $eq $eq$ls180.v:6531$2239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252903,10 +253878,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6429$2170_Y
+    connect \Y $eq$ls180.v:6531$2239_Y
   end
-  attribute \src "ls180.v:6430.109-6430.154"
-  cell $eq $eq$ls180.v:6430$2174
+  attribute \src "ls180.v:6532.109-6532.154"
+  cell $eq $eq$ls180.v:6532$2243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252914,10 +253889,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6430$2174_Y
+    connect \Y $eq$ls180.v:6532$2243_Y
   end
-  attribute \src "ls180.v:6432.104-6432.149"
-  cell $eq $eq$ls180.v:6432$2177
+  attribute \src "ls180.v:6534.104-6534.149"
+  cell $eq $eq$ls180.v:6534$2246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252925,10 +253900,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6432$2177_Y
+    connect \Y $eq$ls180.v:6534$2246_Y
   end
-  attribute \src "ls180.v:6433.107-6433.152"
-  cell $eq $eq$ls180.v:6433$2181
+  attribute \src "ls180.v:6535.107-6535.152"
+  cell $eq $eq$ls180.v:6535$2250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252936,10 +253911,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:6433$2181_Y
+    connect \Y $eq$ls180.v:6535$2250_Y
   end
-  attribute \src "ls180.v:6435.101-6435.146"
-  cell $eq $eq$ls180.v:6435$2184
+  attribute \src "ls180.v:6537.101-6537.146"
+  cell $eq $eq$ls180.v:6537$2253
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252947,10 +253922,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6435$2184_Y
+    connect \Y $eq$ls180.v:6537$2253_Y
   end
-  attribute \src "ls180.v:6436.104-6436.149"
-  cell $eq $eq$ls180.v:6436$2188
+  attribute \src "ls180.v:6538.104-6538.149"
+  cell $eq $eq$ls180.v:6538$2257
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252958,10 +253933,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:6436$2188_Y
+    connect \Y $eq$ls180.v:6538$2257_Y
   end
-  attribute \src "ls180.v:6438.100-6438.145"
-  cell $eq $eq$ls180.v:6438$2191
+  attribute \src "ls180.v:6540.100-6540.145"
+  cell $eq $eq$ls180.v:6540$2260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252969,10 +253944,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6438$2191_Y
+    connect \Y $eq$ls180.v:6540$2260_Y
   end
-  attribute \src "ls180.v:6439.103-6439.148"
-  cell $eq $eq$ls180.v:6439$2195
+  attribute \src "ls180.v:6541.103-6541.148"
+  cell $eq $eq$ls180.v:6541$2264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -252980,10 +253955,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_adr [2:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:6439$2195_Y
+    connect \Y $eq$ls180.v:6541$2264_Y
   end
-  attribute \src "ls180.v:6449.33-6449.79"
-  cell $eq $eq$ls180.v:6449$2197
+  attribute \src "ls180.v:6551.33-6551.79"
+  cell $eq $eq$ls180.v:6551$2266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -252991,10 +253966,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [13:9]
     connect \B 3'100
-    connect \Y $eq$ls180.v:6449$2197_Y
+    connect \Y $eq$ls180.v:6551$2266_Y
   end
-  attribute \src "ls180.v:6451.106-6451.151"
-  cell $eq $eq$ls180.v:6451$2199
+  attribute \src "ls180.v:6553.106-6553.151"
+  cell $eq $eq$ls180.v:6553$2268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253002,10 +253977,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6451$2199_Y
+    connect \Y $eq$ls180.v:6553$2268_Y
   end
-  attribute \src "ls180.v:6452.109-6452.154"
-  cell $eq $eq$ls180.v:6452$2203
+  attribute \src "ls180.v:6554.109-6554.154"
+  cell $eq $eq$ls180.v:6554$2272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253013,10 +253988,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6452$2203_Y
+    connect \Y $eq$ls180.v:6554$2272_Y
   end
-  attribute \src "ls180.v:6454.106-6454.151"
-  cell $eq $eq$ls180.v:6454$2206
+  attribute \src "ls180.v:6556.106-6556.151"
+  cell $eq $eq$ls180.v:6556$2275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253024,10 +253999,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6454$2206_Y
+    connect \Y $eq$ls180.v:6556$2275_Y
   end
-  attribute \src "ls180.v:6455.109-6455.154"
-  cell $eq $eq$ls180.v:6455$2210
+  attribute \src "ls180.v:6557.109-6557.154"
+  cell $eq $eq$ls180.v:6557$2279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253035,10 +254010,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6455$2210_Y
+    connect \Y $eq$ls180.v:6557$2279_Y
   end
-  attribute \src "ls180.v:6457.106-6457.151"
-  cell $eq $eq$ls180.v:6457$2213
+  attribute \src "ls180.v:6559.106-6559.151"
+  cell $eq $eq$ls180.v:6559$2282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253046,10 +254021,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6457$2213_Y
+    connect \Y $eq$ls180.v:6559$2282_Y
   end
-  attribute \src "ls180.v:6458.109-6458.154"
-  cell $eq $eq$ls180.v:6458$2217
+  attribute \src "ls180.v:6560.109-6560.154"
+  cell $eq $eq$ls180.v:6560$2286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253057,10 +254032,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6458$2217_Y
+    connect \Y $eq$ls180.v:6560$2286_Y
   end
-  attribute \src "ls180.v:6460.106-6460.151"
-  cell $eq $eq$ls180.v:6460$2220
+  attribute \src "ls180.v:6562.106-6562.151"
+  cell $eq $eq$ls180.v:6562$2289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253068,10 +254043,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6460$2220_Y
+    connect \Y $eq$ls180.v:6562$2289_Y
   end
-  attribute \src "ls180.v:6461.109-6461.154"
-  cell $eq $eq$ls180.v:6461$2224
+  attribute \src "ls180.v:6563.109-6563.154"
+  cell $eq $eq$ls180.v:6563$2293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253079,10 +254054,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6461$2224_Y
+    connect \Y $eq$ls180.v:6563$2293_Y
   end
-  attribute \src "ls180.v:6842.41-6842.81"
-  cell $eq $eq$ls180.v:6842$2261
+  attribute \src "ls180.v:6944.41-6944.81"
+  cell $eq $eq$ls180.v:6944$2330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253090,10 +254065,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:6842$2261_Y
+    connect \Y $eq$ls180.v:6944$2330_Y
   end
-  attribute \src "ls180.v:6842.144-6842.177"
-  cell $eq $eq$ls180.v:6842$2262
+  attribute \src "ls180.v:6944.144-6944.177"
+  cell $eq $eq$ls180.v:6944$2331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253101,10 +254076,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6842$2262_Y
+    connect \Y $eq$ls180.v:6944$2331_Y
   end
-  attribute \src "ls180.v:6842.219-6842.252"
-  cell $eq $eq$ls180.v:6842$2265
+  attribute \src "ls180.v:6944.219-6944.252"
+  cell $eq $eq$ls180.v:6944$2334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253112,10 +254087,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6842$2265_Y
+    connect \Y $eq$ls180.v:6944$2334_Y
   end
-  attribute \src "ls180.v:6842.294-6842.327"
-  cell $eq $eq$ls180.v:6842$2268
+  attribute \src "ls180.v:6944.294-6944.327"
+  cell $eq $eq$ls180.v:6944$2337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253123,10 +254098,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6842$2268_Y
+    connect \Y $eq$ls180.v:6944$2337_Y
   end
-  attribute \src "ls180.v:6866.41-6866.81"
-  cell $eq $eq$ls180.v:6866$2277
+  attribute \src "ls180.v:6968.41-6968.81"
+  cell $eq $eq$ls180.v:6968$2346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253134,10 +254109,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:6866$2277_Y
+    connect \Y $eq$ls180.v:6968$2346_Y
   end
-  attribute \src "ls180.v:6866.144-6866.177"
-  cell $eq $eq$ls180.v:6866$2278
+  attribute \src "ls180.v:6968.144-6968.177"
+  cell $eq $eq$ls180.v:6968$2347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253145,10 +254120,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6866$2278_Y
+    connect \Y $eq$ls180.v:6968$2347_Y
   end
-  attribute \src "ls180.v:6866.219-6866.252"
-  cell $eq $eq$ls180.v:6866$2281
+  attribute \src "ls180.v:6968.219-6968.252"
+  cell $eq $eq$ls180.v:6968$2350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253156,10 +254131,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6866$2281_Y
+    connect \Y $eq$ls180.v:6968$2350_Y
   end
-  attribute \src "ls180.v:6866.294-6866.327"
-  cell $eq $eq$ls180.v:6866$2284
+  attribute \src "ls180.v:6968.294-6968.327"
+  cell $eq $eq$ls180.v:6968$2353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253167,10 +254142,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6866$2284_Y
+    connect \Y $eq$ls180.v:6968$2353_Y
   end
-  attribute \src "ls180.v:6890.41-6890.81"
-  cell $eq $eq$ls180.v:6890$2293
+  attribute \src "ls180.v:6992.41-6992.81"
+  cell $eq $eq$ls180.v:6992$2362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253178,10 +254153,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:6890$2293_Y
+    connect \Y $eq$ls180.v:6992$2362_Y
   end
-  attribute \src "ls180.v:6890.144-6890.177"
-  cell $eq $eq$ls180.v:6890$2294
+  attribute \src "ls180.v:6992.144-6992.177"
+  cell $eq $eq$ls180.v:6992$2363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253189,10 +254164,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6890$2294_Y
+    connect \Y $eq$ls180.v:6992$2363_Y
   end
-  attribute \src "ls180.v:6890.219-6890.252"
-  cell $eq $eq$ls180.v:6890$2297
+  attribute \src "ls180.v:6992.219-6992.252"
+  cell $eq $eq$ls180.v:6992$2366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253200,10 +254175,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6890$2297_Y
+    connect \Y $eq$ls180.v:6992$2366_Y
   end
-  attribute \src "ls180.v:6890.294-6890.327"
-  cell $eq $eq$ls180.v:6890$2300
+  attribute \src "ls180.v:6992.294-6992.327"
+  cell $eq $eq$ls180.v:6992$2369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253211,10 +254186,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6890$2300_Y
+    connect \Y $eq$ls180.v:6992$2369_Y
   end
-  attribute \src "ls180.v:6914.41-6914.81"
-  cell $eq $eq$ls180.v:6914$2309
+  attribute \src "ls180.v:7016.41-7016.81"
+  cell $eq $eq$ls180.v:7016$2378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253222,10 +254197,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:6914$2309_Y
+    connect \Y $eq$ls180.v:7016$2378_Y
   end
-  attribute \src "ls180.v:6914.144-6914.177"
-  cell $eq $eq$ls180.v:6914$2310
+  attribute \src "ls180.v:7016.144-7016.177"
+  cell $eq $eq$ls180.v:7016$2379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253233,10 +254208,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6914$2310_Y
+    connect \Y $eq$ls180.v:7016$2379_Y
   end
-  attribute \src "ls180.v:6914.219-6914.252"
-  cell $eq $eq$ls180.v:6914$2313
+  attribute \src "ls180.v:7016.219-7016.252"
+  cell $eq $eq$ls180.v:7016$2382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253244,10 +254219,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6914$2313_Y
+    connect \Y $eq$ls180.v:7016$2382_Y
   end
-  attribute \src "ls180.v:6914.294-6914.327"
-  cell $eq $eq$ls180.v:6914$2316
+  attribute \src "ls180.v:7016.294-7016.327"
+  cell $eq $eq$ls180.v:7016$2385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253255,10 +254230,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:6914$2316_Y
+    connect \Y $eq$ls180.v:7016$2385_Y
   end
-  attribute \src "ls180.v:7495.8-7495.38"
-  cell $eq $eq$ls180.v:7495$2407
+  attribute \src "ls180.v:7597.8-7597.38"
+  cell $eq $eq$ls180.v:7597$2476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -253266,10 +254241,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_value
     connect \B 1'0
-    connect \Y $eq$ls180.v:7495$2407_Y
+    connect \Y $eq$ls180.v:7597$2476_Y
   end
-  attribute \src "ls180.v:7526.8-7526.42"
-  cell $eq $eq$ls180.v:7526$2415
+  attribute \src "ls180.v:7640.8-7640.42"
+  cell $eq $eq$ls180.v:7640$2493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253277,10 +254252,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_postponer_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:7526$2415_Y
+    connect \Y $eq$ls180.v:7640$2493_Y
   end
-  attribute \src "ls180.v:7546.38-7546.74"
-  cell $eq $eq$ls180.v:7546$2418
+  attribute \src "ls180.v:7660.38-7660.74"
+  cell $eq $eq$ls180.v:7660$2496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253288,10 +254263,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $eq$ls180.v:7546$2418_Y
+    connect \Y $eq$ls180.v:7660$2496_Y
   end
-  attribute \src "ls180.v:7553.7-7553.43"
-  cell $eq $eq$ls180.v:7553$2420
+  attribute \src "ls180.v:7667.7-7667.43"
+  cell $eq $eq$ls180.v:7667$2498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253299,10 +254274,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 2'10
-    connect \Y $eq$ls180.v:7553$2420_Y
+    connect \Y $eq$ls180.v:7667$2498_Y
   end
-  attribute \src "ls180.v:7560.7-7560.43"
-  cell $eq $eq$ls180.v:7560$2421
+  attribute \src "ls180.v:7674.7-7674.43"
+  cell $eq $eq$ls180.v:7674$2499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253310,10 +254285,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7560$2421_Y
+    connect \Y $eq$ls180.v:7674$2499_Y
   end
-  attribute \src "ls180.v:7568.7-7568.43"
-  cell $eq $eq$ls180.v:7568$2422
+  attribute \src "ls180.v:7682.7-7682.43"
+  cell $eq $eq$ls180.v:7682$2500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253321,10 +254296,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7568$2422_Y
+    connect \Y $eq$ls180.v:7682$2500_Y
   end
-  attribute \src "ls180.v:7620.9-7620.54"
-  cell $eq $eq$ls180.v:7620$2440
+  attribute \src "ls180.v:7734.9-7734.54"
+  cell $eq $eq$ls180.v:7734$2518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253332,10 +254307,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7620$2440_Y
+    connect \Y $eq$ls180.v:7734$2518_Y
   end
-  attribute \src "ls180.v:7666.9-7666.54"
-  cell $eq $eq$ls180.v:7666$2456
+  attribute \src "ls180.v:7780.9-7780.54"
+  cell $eq $eq$ls180.v:7780$2534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253343,10 +254318,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7666$2456_Y
+    connect \Y $eq$ls180.v:7780$2534_Y
   end
-  attribute \src "ls180.v:7712.9-7712.54"
-  cell $eq $eq$ls180.v:7712$2472
+  attribute \src "ls180.v:7826.9-7826.54"
+  cell $eq $eq$ls180.v:7826$2550
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253354,10 +254329,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7712$2472_Y
+    connect \Y $eq$ls180.v:7826$2550_Y
   end
-  attribute \src "ls180.v:7758.9-7758.54"
-  cell $eq $eq$ls180.v:7758$2488
+  attribute \src "ls180.v:7872.9-7872.54"
+  cell $eq $eq$ls180.v:7872$2566
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253365,10 +254340,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7758$2488_Y
+    connect \Y $eq$ls180.v:7872$2566_Y
   end
-  attribute \src "ls180.v:7908.9-7908.41"
-  cell $eq $eq$ls180.v:7908$2500
+  attribute \src "ls180.v:8022.9-8022.41"
+  cell $eq $eq$ls180.v:8022$2578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253376,10 +254351,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7908$2500_Y
+    connect \Y $eq$ls180.v:8022$2578_Y
   end
-  attribute \src "ls180.v:7923.9-7923.41"
-  cell $eq $eq$ls180.v:7923$2503
+  attribute \src "ls180.v:8037.9-8037.41"
+  cell $eq $eq$ls180.v:8037$2581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253387,10 +254362,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7923$2503_Y
+    connect \Y $eq$ls180.v:8037$2581_Y
   end
-  attribute \src "ls180.v:7929.49-7929.82"
-  cell $eq $eq$ls180.v:7929$2504
+  attribute \src "ls180.v:8043.49-8043.82"
+  cell $eq $eq$ls180.v:8043$2582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253398,10 +254373,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7929$2504_Y
+    connect \Y $eq$ls180.v:8043$2582_Y
   end
-  attribute \src "ls180.v:7929.131-7929.164"
-  cell $eq $eq$ls180.v:7929$2507
+  attribute \src "ls180.v:8043.131-8043.164"
+  cell $eq $eq$ls180.v:8043$2585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253409,10 +254384,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7929$2507_Y
+    connect \Y $eq$ls180.v:8043$2585_Y
   end
-  attribute \src "ls180.v:7929.213-7929.246"
-  cell $eq $eq$ls180.v:7929$2510
+  attribute \src "ls180.v:8043.213-8043.246"
+  cell $eq $eq$ls180.v:8043$2588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253420,10 +254395,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7929$2510_Y
+    connect \Y $eq$ls180.v:8043$2588_Y
   end
-  attribute \src "ls180.v:7929.295-7929.328"
-  cell $eq $eq$ls180.v:7929$2513
+  attribute \src "ls180.v:8043.295-8043.328"
+  cell $eq $eq$ls180.v:8043$2591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253431,10 +254406,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7929$2513_Y
+    connect \Y $eq$ls180.v:8043$2591_Y
   end
-  attribute \src "ls180.v:7930.50-7930.83"
-  cell $eq $eq$ls180.v:7930$2516
+  attribute \src "ls180.v:8044.50-8044.83"
+  cell $eq $eq$ls180.v:8044$2594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253442,10 +254417,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7930$2516_Y
+    connect \Y $eq$ls180.v:8044$2594_Y
   end
-  attribute \src "ls180.v:7930.132-7930.165"
-  cell $eq $eq$ls180.v:7930$2519
+  attribute \src "ls180.v:8044.132-8044.165"
+  cell $eq $eq$ls180.v:8044$2597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253453,10 +254428,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7930$2519_Y
+    connect \Y $eq$ls180.v:8044$2597_Y
   end
-  attribute \src "ls180.v:7930.214-7930.247"
-  cell $eq $eq$ls180.v:7930$2522
+  attribute \src "ls180.v:8044.214-8044.247"
+  cell $eq $eq$ls180.v:8044$2600
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253464,10 +254439,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7930$2522_Y
+    connect \Y $eq$ls180.v:8044$2600_Y
   end
-  attribute \src "ls180.v:7930.296-7930.329"
-  cell $eq $eq$ls180.v:7930$2525
+  attribute \src "ls180.v:8044.296-8044.329"
+  cell $eq $eq$ls180.v:8044$2603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253475,10 +254450,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7930$2525_Y
+    connect \Y $eq$ls180.v:8044$2603_Y
   end
-  attribute \src "ls180.v:7965.9-7965.42"
-  cell $eq $eq$ls180.v:7965$2537
+  attribute \src "ls180.v:8079.9-8079.42"
+  cell $eq $eq$ls180.v:8079$2615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253486,10 +254461,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_bitcount
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7965$2537_Y
+    connect \Y $eq$ls180.v:8079$2615_Y
   end
-  attribute \src "ls180.v:7968.10-7968.43"
-  cell $eq $eq$ls180.v:7968$2538
+  attribute \src "ls180.v:8082.10-8082.43"
+  cell $eq $eq$ls180.v:8082$2616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253497,10 +254472,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:7968$2538_Y
+    connect \Y $eq$ls180.v:8082$2616_Y
   end
-  attribute \src "ls180.v:7994.9-7994.42"
-  cell $eq $eq$ls180.v:7994$2544
+  attribute \src "ls180.v:8108.9-8108.42"
+  cell $eq $eq$ls180.v:8108$2622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253508,10 +254483,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_bitcount
     connect \B 1'0
-    connect \Y $eq$ls180.v:7994$2544_Y
+    connect \Y $eq$ls180.v:8108$2622_Y
   end
-  attribute \src "ls180.v:7999.10-7999.43"
-  cell $eq $eq$ls180.v:7999$2545
+  attribute \src "ls180.v:8113.10-8113.43"
+  cell $eq $eq$ls180.v:8113$2623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253519,10 +254494,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:7999$2545_Y
+    connect \Y $eq$ls180.v:8113$2623_Y
   end
-  attribute \src "ls180.v:8206.9-8206.53"
-  cell $eq $eq$ls180.v:8206$2594
+  attribute \src "ls180.v:8320.9-8320.53"
+  cell $eq $eq$ls180.v:8320$2672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253530,10 +254505,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 3'111
-    connect \Y $eq$ls180.v:8206$2594_Y
+    connect \Y $eq$ls180.v:8320$2672_Y
   end
-  attribute \src "ls180.v:8287.9-8287.54"
-  cell $eq $eq$ls180.v:8287$2606
+  attribute \src "ls180.v:8401.9-8401.54"
+  cell $eq $eq$ls180.v:8401$2684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -253541,10 +254516,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 3'111
-    connect \Y $eq$ls180.v:8287$2606_Y
+    connect \Y $eq$ls180.v:8401$2684_Y
   end
-  attribute \src "ls180.v:8366.9-8366.55"
-  cell $eq $eq$ls180.v:8366$2618
+  attribute \src "ls180.v:8480.9-8480.55"
+  cell $eq $eq$ls180.v:8480$2696
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253552,10 +254527,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $eq$ls180.v:8366$2618_Y
+    connect \Y $eq$ls180.v:8480$2696_Y
   end
-  attribute \src "ls180.v:8589.9-8589.49"
-  cell $eq $eq$ls180.v:8589$2651
+  attribute \src "ls180.v:8703.9-8703.49"
+  cell $eq $eq$ls180.v:8703$2729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -253563,32 +254538,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_demux
     connect \B 2'11
-    connect \Y $eq$ls180.v:8589$2651_Y
+    connect \Y $eq$ls180.v:8703$2729_Y
   end
-  attribute \src "ls180.v:8165.8-8165.54"
-  cell $ge $ge$ls180.v:8165$2586
+  attribute \src "ls180.v:8279.8-8279.54"
+  cell $ge $ge$ls180.v:8279$2664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_pwm0_counter
-    connect \B $sub$ls180.v:8165$2585_Y
-    connect \Y $ge$ls180.v:8165$2586_Y
+    connect \B $sub$ls180.v:8279$2663_Y
+    connect \Y $ge$ls180.v:8279$2664_Y
   end
-  attribute \src "ls180.v:8179.8-8179.54"
-  cell $ge $ge$ls180.v:8179$2590
+  attribute \src "ls180.v:8293.8-8293.54"
+  cell $ge $ge$ls180.v:8293$2668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_pwm1_counter
-    connect \B $sub$ls180.v:8179$2589_Y
-    connect \Y $ge$ls180.v:8179$2590_Y
+    connect \B $sub$ls180.v:8293$2667_Y
+    connect \Y $ge$ls180.v:8293$2668_Y
   end
-  attribute \src "ls180.v:5151.47-5151.83"
-  cell $gt $gt$ls180.v:5151$914
+  attribute \src "ls180.v:5226.47-5226.83"
+  cell $gt $gt$ls180.v:5226$965
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253596,10 +254571,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 3'111
-    connect \Y $gt$ls180.v:5151$914_Y
+    connect \Y $gt$ls180.v:5226$965_Y
   end
-  attribute \src "ls180.v:5157.7-5157.43"
-  cell $lt $lt$ls180.v:5157$917
+  attribute \src "ls180.v:5232.7-5232.43"
+  cell $lt $lt$ls180.v:5232$968
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -253607,10 +254582,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 4'1000
-    connect \Y $lt$ls180.v:5157$917_Y
+    connect \Y $lt$ls180.v:5232$968_Y
   end
-  attribute \src "ls180.v:8160.8-8160.43"
-  cell $lt $lt$ls180.v:8160$2584
+  attribute \src "ls180.v:8274.8-8274.43"
+  cell $lt $lt$ls180.v:8274$2662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -253618,10 +254593,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_pwm0_counter
     connect \B \main_pwm0_width
-    connect \Y $lt$ls180.v:8160$2584_Y
+    connect \Y $lt$ls180.v:8274$2662_Y
   end
-  attribute \src "ls180.v:8174.8-8174.43"
-  cell $lt $lt$ls180.v:8174$2588
+  attribute \src "ls180.v:8288.8-8288.43"
+  cell $lt $lt$ls180.v:8288$2666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -253629,10 +254604,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_pwm1_counter
     connect \B \main_pwm1_width
-    connect \Y $lt$ls180.v:8174$2588_Y
+    connect \Y $lt$ls180.v:8288$2666_Y
   end
-  attribute \src "ls180.v:10055.33-10055.36"
-  cell $memrd $memrd$\mem$ls180.v:10055$2693
+  attribute \src "ls180.v:10172.33-10172.36"
+  cell $memrd $memrd$\mem$ls180.v:10172$2771
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253641,11 +254616,50 @@ module \ls180
     parameter \WIDTH 32
     connect \ADDR \memadr
     connect \CLK 1'x
-    connect \DATA $memrd$\mem$ls180.v:10055$2693_DATA
+    connect \DATA $memrd$\mem$ls180.v:10172$2771_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10066.12-10066.19"
-  cell $memrd $memrd$\storage$ls180.v:10066$2698
+  attribute \src "ls180.v:10192.27-10192.32"
+  cell $memrd $memrd$\mem_1$ls180.v:10192$2785
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_1"
+    parameter \TRANSPARENT 0
+    parameter \WIDTH 32
+    connect \ADDR \memadr_1
+    connect \CLK 1'x
+    connect \DATA $memrd$\mem_1$ls180.v:10192$2785_DATA
+    connect \EN 1'x
+  end
+  attribute \src "ls180.v:10212.27-10212.32"
+  cell $memrd $memrd$\mem_2$ls180.v:10212$2799
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_2"
+    parameter \TRANSPARENT 0
+    parameter \WIDTH 32
+    connect \ADDR \memadr_2
+    connect \CLK 1'x
+    connect \DATA $memrd$\mem_2$ls180.v:10212$2799_DATA
+    connect \EN 1'x
+  end
+  attribute \src "ls180.v:10232.27-10232.32"
+  cell $memrd $memrd$\mem_3$ls180.v:10232$2813
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_3"
+    parameter \TRANSPARENT 0
+    parameter \WIDTH 32
+    connect \ADDR \memadr_3
+    connect \CLK 1'x
+    connect \DATA $memrd$\mem_3$ls180.v:10232$2813_DATA
+    connect \EN 1'x
+  end
+  attribute \src "ls180.v:10243.12-10243.19"
+  cell $memrd $memrd$\storage$ls180.v:10243$2818
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253654,11 +254668,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:10066$2698_DATA
+    connect \DATA $memrd$\storage$ls180.v:10243$2818_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10073.68-10073.75"
-  cell $memrd $memrd$\storage$ls180.v:10073$2700
+  attribute \src "ls180.v:10250.68-10250.75"
+  cell $memrd $memrd$\storage$ls180.v:10250$2820
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253667,11 +254681,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:10073$2700_DATA
+    connect \DATA $memrd$\storage$ls180.v:10250$2820_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10080.14-10080.23"
-  cell $memrd $memrd$\storage_1$ls180.v:10080$2705
+  attribute \src "ls180.v:10257.14-10257.23"
+  cell $memrd $memrd$\storage_1$ls180.v:10257$2825
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253680,11 +254694,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:10080$2705_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:10257$2825_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10087.68-10087.77"
-  cell $memrd $memrd$\storage_1$ls180.v:10087$2707
+  attribute \src "ls180.v:10264.68-10264.77"
+  cell $memrd $memrd$\storage_1$ls180.v:10264$2827
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253693,11 +254707,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:10087$2707_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:10264$2827_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10094.14-10094.23"
-  cell $memrd $memrd$\storage_2$ls180.v:10094$2712
+  attribute \src "ls180.v:10271.14-10271.23"
+  cell $memrd $memrd$\storage_2$ls180.v:10271$2832
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253706,11 +254720,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:10094$2712_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:10271$2832_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10101.68-10101.77"
-  cell $memrd $memrd$\storage_2$ls180.v:10101$2714
+  attribute \src "ls180.v:10278.68-10278.77"
+  cell $memrd $memrd$\storage_2$ls180.v:10278$2834
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253719,11 +254733,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:10101$2714_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:10278$2834_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10108.14-10108.23"
-  cell $memrd $memrd$\storage_3$ls180.v:10108$2719
+  attribute \src "ls180.v:10285.14-10285.23"
+  cell $memrd $memrd$\storage_3$ls180.v:10285$2839
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253732,11 +254746,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:10108$2719_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:10285$2839_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10115.68-10115.77"
-  cell $memrd $memrd$\storage_3$ls180.v:10115$2721
+  attribute \src "ls180.v:10292.68-10292.77"
+  cell $memrd $memrd$\storage_3$ls180.v:10292$2841
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253745,11 +254759,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:10115$2721_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:10292$2841_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10123.14-10123.23"
-  cell $memrd $memrd$\storage_4$ls180.v:10123$2726
+  attribute \src "ls180.v:10300.14-10300.23"
+  cell $memrd $memrd$\storage_4$ls180.v:10300$2846
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253758,11 +254772,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_tx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:10123$2726_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:10300$2846_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10128.15-10128.24"
-  cell $memrd $memrd$\storage_4$ls180.v:10128$2728
+  attribute \src "ls180.v:10305.15-10305.24"
+  cell $memrd $memrd$\storage_4$ls180.v:10305$2848
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253771,11 +254785,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_tx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:10128$2728_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:10305$2848_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10140.14-10140.23"
-  cell $memrd $memrd$\storage_5$ls180.v:10140$2733
+  attribute \src "ls180.v:10317.14-10317.23"
+  cell $memrd $memrd$\storage_5$ls180.v:10317$2853
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253784,11 +254798,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_rx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:10140$2733_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:10317$2853_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10145.15-10145.24"
-  cell $memrd $memrd$\storage_5$ls180.v:10145$2735
+  attribute \src "ls180.v:10322.15-10322.24"
+  cell $memrd $memrd$\storage_5$ls180.v:10322$2855
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253797,11 +254811,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_rx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:10145$2735_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:10322$2855_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10156.14-10156.23"
-  cell $memrd $memrd$\storage_6$ls180.v:10156$2740
+  attribute \src "ls180.v:10333.14-10333.23"
+  cell $memrd $memrd$\storage_6$ls180.v:10333$2860
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253810,11 +254824,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdblock2mem_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_6$ls180.v:10156$2740_DATA
+    connect \DATA $memrd$\storage_6$ls180.v:10333$2860_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10163.45-10163.54"
-  cell $memrd $memrd$\storage_6$ls180.v:10163$2742
+  attribute \src "ls180.v:10340.45-10340.54"
+  cell $memrd $memrd$\storage_6$ls180.v:10340$2862
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253823,11 +254837,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdblock2mem_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_6$ls180.v:10163$2742_DATA
+    connect \DATA $memrd$\storage_6$ls180.v:10340$2862_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10170.14-10170.23"
-  cell $memrd $memrd$\storage_7$ls180.v:10170$2747
+  attribute \src "ls180.v:10347.14-10347.23"
+  cell $memrd $memrd$\storage_7$ls180.v:10347$2867
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253836,11 +254850,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdmem2block_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_7$ls180.v:10170$2747_DATA
+    connect \DATA $memrd$\storage_7$ls180.v:10347$2867_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10177.45-10177.54"
-  cell $memrd $memrd$\storage_7$ls180.v:10177$2749
+  attribute \src "ls180.v:10354.45-10354.54"
+  cell $memrd $memrd$\storage_7$ls180.v:10354$2869
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -253849,167 +254863,323 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdmem2block_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_7$ls180.v:10177$2749_DATA
+    connect \DATA $memrd$\storage_7$ls180.v:10354$2869_DATA
     connect \EN 1'x
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2751
+  cell $memwr $memwr$\mem$ls180.v:0$2871
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2751
+    parameter \PRIORITY 2871
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10045$1_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10162$1_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10045$1_DATA
-    connect \EN $memwr$\mem$ls180.v:10045$1_EN
+    connect \DATA $memwr$\mem$ls180.v:10162$1_DATA
+    connect \EN $memwr$\mem$ls180.v:10162$1_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2752
+  cell $memwr $memwr$\mem$ls180.v:0$2872
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2752
+    parameter \PRIORITY 2872
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10047$2_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10164$2_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10047$2_DATA
-    connect \EN $memwr$\mem$ls180.v:10047$2_EN
+    connect \DATA $memwr$\mem$ls180.v:10164$2_DATA
+    connect \EN $memwr$\mem$ls180.v:10164$2_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2753
+  cell $memwr $memwr$\mem$ls180.v:0$2873
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2753
+    parameter \PRIORITY 2873
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10049$3_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10166$3_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10049$3_DATA
-    connect \EN $memwr$\mem$ls180.v:10049$3_EN
+    connect \DATA $memwr$\mem$ls180.v:10166$3_DATA
+    connect \EN $memwr$\mem$ls180.v:10166$3_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2754
+  cell $memwr $memwr$\mem$ls180.v:0$2874
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2754
+    parameter \PRIORITY 2874
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem$ls180.v:10168$4_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem$ls180.v:10168$4_DATA
+    connect \EN $memwr$\mem$ls180.v:10168$4_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_1$ls180.v:0$2875
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_1"
+    parameter \PRIORITY 2875
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_1$ls180.v:10182$5_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_1$ls180.v:10182$5_DATA
+    connect \EN $memwr$\mem_1$ls180.v:10182$5_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_1$ls180.v:0$2876
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_1"
+    parameter \PRIORITY 2876
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_1$ls180.v:10184$6_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_1$ls180.v:10184$6_DATA
+    connect \EN $memwr$\mem_1$ls180.v:10184$6_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_1$ls180.v:0$2877
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_1"
+    parameter \PRIORITY 2877
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_1$ls180.v:10186$7_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_1$ls180.v:10186$7_DATA
+    connect \EN $memwr$\mem_1$ls180.v:10186$7_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_1$ls180.v:0$2878
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_1"
+    parameter \PRIORITY 2878
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_1$ls180.v:10188$8_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_1$ls180.v:10188$8_DATA
+    connect \EN $memwr$\mem_1$ls180.v:10188$8_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_2$ls180.v:0$2879
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_2"
+    parameter \PRIORITY 2879
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_2$ls180.v:10202$9_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_2$ls180.v:10202$9_DATA
+    connect \EN $memwr$\mem_2$ls180.v:10202$9_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_2$ls180.v:0$2880
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_2"
+    parameter \PRIORITY 2880
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_2$ls180.v:10204$10_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_2$ls180.v:10204$10_DATA
+    connect \EN $memwr$\mem_2$ls180.v:10204$10_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_2$ls180.v:0$2881
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_2"
+    parameter \PRIORITY 2881
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_2$ls180.v:10206$11_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_2$ls180.v:10206$11_DATA
+    connect \EN $memwr$\mem_2$ls180.v:10206$11_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_2$ls180.v:0$2882
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_2"
+    parameter \PRIORITY 2882
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_2$ls180.v:10208$12_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_2$ls180.v:10208$12_DATA
+    connect \EN $memwr$\mem_2$ls180.v:10208$12_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_3$ls180.v:0$2883
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_3"
+    parameter \PRIORITY 2883
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_3$ls180.v:10222$13_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_3$ls180.v:10222$13_DATA
+    connect \EN $memwr$\mem_3$ls180.v:10222$13_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_3$ls180.v:0$2884
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_3"
+    parameter \PRIORITY 2884
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_3$ls180.v:10224$14_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_3$ls180.v:10224$14_DATA
+    connect \EN $memwr$\mem_3$ls180.v:10224$14_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\mem_3$ls180.v:0$2885
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_3"
+    parameter \PRIORITY 2885
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10051$4_ADDR
+    connect \ADDR $memwr$\mem_3$ls180.v:10226$15_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10051$4_DATA
-    connect \EN $memwr$\mem$ls180.v:10051$4_EN
+    connect \DATA $memwr$\mem_3$ls180.v:10226$15_DATA
+    connect \EN $memwr$\mem_3$ls180.v:10226$15_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage$ls180.v:0$2755
+  cell $memwr $memwr$\mem_3$ls180.v:0$2886
+    parameter \ABITS 7
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 0
+    parameter \MEMID "\\mem_3"
+    parameter \PRIORITY 2886
+    parameter \WIDTH 32
+    connect \ADDR $memwr$\mem_3$ls180.v:10228$16_ADDR
+    connect \CLK 1'x
+    connect \DATA $memwr$\mem_3$ls180.v:10228$16_DATA
+    connect \EN $memwr$\mem_3$ls180.v:10228$16_EN
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  cell $memwr $memwr$\storage$ls180.v:0$2887
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage"
-    parameter \PRIORITY 2755
+    parameter \PRIORITY 2887
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage$ls180.v:10065$5_ADDR
+    connect \ADDR $memwr$\storage$ls180.v:10242$17_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage$ls180.v:10065$5_DATA
-    connect \EN $memwr$\storage$ls180.v:10065$5_EN
+    connect \DATA $memwr$\storage$ls180.v:10242$17_DATA
+    connect \EN $memwr$\storage$ls180.v:10242$17_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_1$ls180.v:0$2756
+  cell $memwr $memwr$\storage_1$ls180.v:0$2888
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_1"
-    parameter \PRIORITY 2756
+    parameter \PRIORITY 2888
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_1$ls180.v:10079$6_ADDR
+    connect \ADDR $memwr$\storage_1$ls180.v:10256$18_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_1$ls180.v:10079$6_DATA
-    connect \EN $memwr$\storage_1$ls180.v:10079$6_EN
+    connect \DATA $memwr$\storage_1$ls180.v:10256$18_DATA
+    connect \EN $memwr$\storage_1$ls180.v:10256$18_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_2$ls180.v:0$2757
+  cell $memwr $memwr$\storage_2$ls180.v:0$2889
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_2"
-    parameter \PRIORITY 2757
+    parameter \PRIORITY 2889
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_2$ls180.v:10093$7_ADDR
+    connect \ADDR $memwr$\storage_2$ls180.v:10270$19_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_2$ls180.v:10093$7_DATA
-    connect \EN $memwr$\storage_2$ls180.v:10093$7_EN
+    connect \DATA $memwr$\storage_2$ls180.v:10270$19_DATA
+    connect \EN $memwr$\storage_2$ls180.v:10270$19_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_3$ls180.v:0$2758
+  cell $memwr $memwr$\storage_3$ls180.v:0$2890
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_3"
-    parameter \PRIORITY 2758
+    parameter \PRIORITY 2890
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_3$ls180.v:10107$8_ADDR
+    connect \ADDR $memwr$\storage_3$ls180.v:10284$20_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_3$ls180.v:10107$8_DATA
-    connect \EN $memwr$\storage_3$ls180.v:10107$8_EN
+    connect \DATA $memwr$\storage_3$ls180.v:10284$20_DATA
+    connect \EN $memwr$\storage_3$ls180.v:10284$20_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_4$ls180.v:0$2759
+  cell $memwr $memwr$\storage_4$ls180.v:0$2891
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_4"
-    parameter \PRIORITY 2759
+    parameter \PRIORITY 2891
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_4$ls180.v:10122$9_ADDR
+    connect \ADDR $memwr$\storage_4$ls180.v:10299$21_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_4$ls180.v:10122$9_DATA
-    connect \EN $memwr$\storage_4$ls180.v:10122$9_EN
+    connect \DATA $memwr$\storage_4$ls180.v:10299$21_DATA
+    connect \EN $memwr$\storage_4$ls180.v:10299$21_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_5$ls180.v:0$2760
+  cell $memwr $memwr$\storage_5$ls180.v:0$2892
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_5"
-    parameter \PRIORITY 2760
+    parameter \PRIORITY 2892
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_5$ls180.v:10139$10_ADDR
+    connect \ADDR $memwr$\storage_5$ls180.v:10316$22_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_5$ls180.v:10139$10_DATA
-    connect \EN $memwr$\storage_5$ls180.v:10139$10_EN
+    connect \DATA $memwr$\storage_5$ls180.v:10316$22_DATA
+    connect \EN $memwr$\storage_5$ls180.v:10316$22_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_6$ls180.v:0$2761
+  cell $memwr $memwr$\storage_6$ls180.v:0$2893
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_6"
-    parameter \PRIORITY 2761
+    parameter \PRIORITY 2893
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_6$ls180.v:10155$11_ADDR
+    connect \ADDR $memwr$\storage_6$ls180.v:10332$23_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_6$ls180.v:10155$11_DATA
-    connect \EN $memwr$\storage_6$ls180.v:10155$11_EN
+    connect \DATA $memwr$\storage_6$ls180.v:10332$23_DATA
+    connect \EN $memwr$\storage_6$ls180.v:10332$23_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_7$ls180.v:0$2762
+  cell $memwr $memwr$\storage_7$ls180.v:0$2894
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_7"
-    parameter \PRIORITY 2762
+    parameter \PRIORITY 2894
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_7$ls180.v:10169$12_ADDR
+    connect \ADDR $memwr$\storage_7$ls180.v:10346$24_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_7$ls180.v:10169$12_DATA
-    connect \EN $memwr$\storage_7$ls180.v:10169$12_EN
+    connect \DATA $memwr$\storage_7$ls180.v:10346$24_DATA
+    connect \EN $memwr$\storage_7$ls180.v:10346$24_EN
   end
-  attribute \src "ls180.v:2965.41-2965.71"
-  cell $ne $ne$ls180.v:2965$60
+  attribute \src "ls180.v:3010.41-3010.71"
+  cell $ne $ne$ls180.v:3010$72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -254017,10 +255187,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_value
     connect \B 1'0
-    connect \Y $ne$ls180.v:2965$60_Y
+    connect \Y $ne$ls180.v:3010$72_Y
   end
-  attribute \src "ls180.v:3126.70-3126.104"
-  cell $ne $ne$ls180.v:3126$74
+  attribute \src "ls180.v:3201.70-3201.104"
+  cell $ne $ne$ls180.v:3201$125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254028,10 +255198,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'0
-    connect \Y $ne$ls180.v:3126$74_Y
+    connect \Y $ne$ls180.v:3201$125_Y
   end
-  attribute \src "ls180.v:3187.8-3187.142"
-  cell $ne $ne$ls180.v:3187$93
+  attribute \src "ls180.v:3262.8-3262.142"
+  cell $ne $ne$ls180.v:3262$144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254039,10 +255209,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:3187$93_Y
+    connect \Y $ne$ls180.v:3262$144_Y
   end
-  attribute \src "ls180.v:3219.75-3219.133"
-  cell $ne $ne$ls180.v:3219$100
+  attribute \src "ls180.v:3294.75-3294.133"
+  cell $ne $ne$ls180.v:3294$151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254050,10 +255220,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:3219$100_Y
+    connect \Y $ne$ls180.v:3294$151_Y
   end
-  attribute \src "ls180.v:3220.75-3220.133"
-  cell $ne $ne$ls180.v:3220$101
+  attribute \src "ls180.v:3295.75-3295.133"
+  cell $ne $ne$ls180.v:3295$152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254061,10 +255231,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:3220$101_Y
+    connect \Y $ne$ls180.v:3295$152_Y
   end
-  attribute \src "ls180.v:3344.8-3344.142"
-  cell $ne $ne$ls180.v:3344$123
+  attribute \src "ls180.v:3419.8-3419.142"
+  cell $ne $ne$ls180.v:3419$174
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254072,10 +255242,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:3344$123_Y
+    connect \Y $ne$ls180.v:3419$174_Y
   end
-  attribute \src "ls180.v:3376.75-3376.133"
-  cell $ne $ne$ls180.v:3376$130
+  attribute \src "ls180.v:3451.75-3451.133"
+  cell $ne $ne$ls180.v:3451$181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254083,10 +255253,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:3376$130_Y
+    connect \Y $ne$ls180.v:3451$181_Y
   end
-  attribute \src "ls180.v:3377.75-3377.133"
-  cell $ne $ne$ls180.v:3377$131
+  attribute \src "ls180.v:3452.75-3452.133"
+  cell $ne $ne$ls180.v:3452$182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254094,10 +255264,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:3377$131_Y
+    connect \Y $ne$ls180.v:3452$182_Y
   end
-  attribute \src "ls180.v:3501.8-3501.142"
-  cell $ne $ne$ls180.v:3501$153
+  attribute \src "ls180.v:3576.8-3576.142"
+  cell $ne $ne$ls180.v:3576$204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254105,10 +255275,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:3501$153_Y
+    connect \Y $ne$ls180.v:3576$204_Y
   end
-  attribute \src "ls180.v:3533.75-3533.133"
-  cell $ne $ne$ls180.v:3533$160
+  attribute \src "ls180.v:3608.75-3608.133"
+  cell $ne $ne$ls180.v:3608$211
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254116,10 +255286,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:3533$160_Y
+    connect \Y $ne$ls180.v:3608$211_Y
   end
-  attribute \src "ls180.v:3534.75-3534.133"
-  cell $ne $ne$ls180.v:3534$161
+  attribute \src "ls180.v:3609.75-3609.133"
+  cell $ne $ne$ls180.v:3609$212
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254127,10 +255297,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:3534$161_Y
+    connect \Y $ne$ls180.v:3609$212_Y
   end
-  attribute \src "ls180.v:3658.8-3658.142"
-  cell $ne $ne$ls180.v:3658$183
+  attribute \src "ls180.v:3733.8-3733.142"
+  cell $ne $ne$ls180.v:3733$234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254138,10 +255308,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:3658$183_Y
+    connect \Y $ne$ls180.v:3733$234_Y
   end
-  attribute \src "ls180.v:3690.75-3690.133"
-  cell $ne $ne$ls180.v:3690$190
+  attribute \src "ls180.v:3765.75-3765.133"
+  cell $ne $ne$ls180.v:3765$241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254149,10 +255319,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:3690$190_Y
+    connect \Y $ne$ls180.v:3765$241_Y
   end
-  attribute \src "ls180.v:3691.75-3691.133"
-  cell $ne $ne$ls180.v:3691$191
+  attribute \src "ls180.v:3766.75-3766.133"
+  cell $ne $ne$ls180.v:3766$242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254160,10 +255330,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:3691$191_Y
+    connect \Y $ne$ls180.v:3766$242_Y
   end
-  attribute \src "ls180.v:4183.47-4183.80"
-  cell $ne $ne$ls180.v:4183$589
+  attribute \src "ls180.v:4258.47-4258.80"
+  cell $ne $ne$ls180.v:4258$640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -254171,10 +255341,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_level0
     connect \B 5'10000
-    connect \Y $ne$ls180.v:4183$589_Y
+    connect \Y $ne$ls180.v:4258$640_Y
   end
-  attribute \src "ls180.v:4184.47-4184.79"
-  cell $ne $ne$ls180.v:4184$590
+  attribute \src "ls180.v:4259.47-4259.79"
+  cell $ne $ne$ls180.v:4259$641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -254182,10 +255352,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_level0
     connect \B 1'0
-    connect \Y $ne$ls180.v:4184$590_Y
+    connect \Y $ne$ls180.v:4259$641_Y
   end
-  attribute \src "ls180.v:4213.47-4213.80"
-  cell $ne $ne$ls180.v:4213$600
+  attribute \src "ls180.v:4288.47-4288.80"
+  cell $ne $ne$ls180.v:4288$651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -254193,10 +255363,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_level0
     connect \B 5'10000
-    connect \Y $ne$ls180.v:4213$600_Y
+    connect \Y $ne$ls180.v:4288$651_Y
   end
-  attribute \src "ls180.v:4214.47-4214.79"
-  cell $ne $ne$ls180.v:4214$601
+  attribute \src "ls180.v:4289.47-4289.79"
+  cell $ne $ne$ls180.v:4289$652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -254204,10 +255374,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_level0
     connect \B 1'0
-    connect \Y $ne$ls180.v:4214$601_Y
+    connect \Y $ne$ls180.v:4289$652_Y
   end
-  attribute \src "ls180.v:4683.32-4683.89"
-  cell $ne $ne$ls180.v:4683$681
+  attribute \src "ls180.v:4758.32-4758.89"
+  cell $ne $ne$ls180.v:4758$732
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -254215,10 +255385,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
     connect \B 3'101
-    connect \Y $ne$ls180.v:4683$681_Y
+    connect \Y $ne$ls180.v:4758$732_Y
   end
-  attribute \src "ls180.v:5330.10-5330.56"
-  cell $ne $ne$ls180.v:5330$978
+  attribute \src "ls180.v:5405.10-5405.56"
+  cell $ne $ne$ls180.v:5405$1029
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -254226,10 +255396,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_source_payload_status
     connect \B 2'10
-    connect \Y $ne$ls180.v:5330$978_Y
+    connect \Y $ne$ls180.v:5405$1029_Y
   end
-  attribute \src "ls180.v:5435.51-5435.87"
-  cell $ne $ne$ls180.v:5435$992
+  attribute \src "ls180.v:5510.51-5510.87"
+  cell $ne $ne$ls180.v:5510$1043
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -254237,10 +255407,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_level
     connect \B 6'100000
-    connect \Y $ne$ls180.v:5435$992_Y
+    connect \Y $ne$ls180.v:5510$1043_Y
   end
-  attribute \src "ls180.v:5436.51-5436.86"
-  cell $ne $ne$ls180.v:5436$993
+  attribute \src "ls180.v:5511.51-5511.86"
+  cell $ne $ne$ls180.v:5511$1044
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -254248,10 +255418,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:5436$993_Y
+    connect \Y $ne$ls180.v:5511$1044_Y
   end
-  attribute \src "ls180.v:5643.51-5643.87"
-  cell $ne $ne$ls180.v:5643$1023
+  attribute \src "ls180.v:5718.51-5718.87"
+  cell $ne $ne$ls180.v:5718$1074
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -254259,10 +255429,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_level
     connect \B 6'100000
-    connect \Y $ne$ls180.v:5643$1023_Y
+    connect \Y $ne$ls180.v:5718$1074_Y
   end
-  attribute \src "ls180.v:5644.51-5644.86"
-  cell $ne $ne$ls180.v:5644$1024
+  attribute \src "ls180.v:5719.51-5719.86"
+  cell $ne $ne$ls180.v:5719$1075
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -254270,10 +255440,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:5644$1024_Y
+    connect \Y $ne$ls180.v:5719$1075_Y
   end
-  attribute \src "ls180.v:5675.79-5675.119"
-  cell $ne $ne$ls180.v:5675$1027
+  attribute \src "ls180.v:5750.79-5750.119"
+  cell $ne $ne$ls180.v:5750$1078
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254281,10 +255451,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_libresocsim_wishbone_sel
     connect \B 1'0
-    connect \Y $ne$ls180.v:5675$1027_Y
+    connect \Y $ne$ls180.v:5750$1078_Y
   end
-  attribute \src "ls180.v:7485.7-7485.52"
-  cell $ne $ne$ls180.v:7485$2402
+  attribute \src "ls180.v:7587.7-7587.52"
+  cell $ne $ne$ls180.v:7587$2471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -254292,10 +255462,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_bus_errors
     connect \B 32'11111111111111111111111111111111
-    connect \Y $ne$ls180.v:7485$2402_Y
+    connect \Y $ne$ls180.v:7587$2471_Y
   end
-  attribute \src "ls180.v:7535.9-7535.43"
-  cell $ne $ne$ls180.v:7535$2416
+  attribute \src "ls180.v:7649.9-7649.43"
+  cell $ne $ne$ls180.v:7649$2494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254303,10 +255473,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'0
-    connect \Y $ne$ls180.v:7535$2416_Y
+    connect \Y $ne$ls180.v:7649$2494_Y
   end
-  attribute \src "ls180.v:7571.8-7571.44"
-  cell $ne $ne$ls180.v:7571$2423
+  attribute \src "ls180.v:7685.8-7685.44"
+  cell $ne $ne$ls180.v:7685$2501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254314,10 +255484,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $ne$ls180.v:7571$2423_Y
+    connect \Y $ne$ls180.v:7685$2501_Y
   end
-  attribute \src "ls180.v:8509.9-8509.47"
-  cell $ne $ne$ls180.v:8509$2638
+  attribute \src "ls180.v:8623.9-8623.47"
+  cell $ne $ne$ls180.v:8623$2716
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254325,2706 +255495,2730 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 4'1010
-    connect \Y $ne$ls180.v:8509$2638_Y
+    connect \Y $ne$ls180.v:8623$2716_Y
   end
-  attribute \src "ls180.v:2773.45-2773.80"
-  cell $not $not$ls180.v:2773$14
+  attribute \src "ls180.v:2818.45-2818.80"
+  cell $not $not$ls180.v:2818$26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_ibus_cyc
-    connect \Y $not$ls180.v:2773$14_Y
+    connect \Y $not$ls180.v:2818$26_Y
   end
-  attribute \src "ls180.v:2812.61-2812.94"
-  cell $not $not$ls180.v:2812$19
+  attribute \src "ls180.v:2857.61-2857.94"
+  cell $not $not$ls180.v:2857$31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter0_skip
-    connect \Y $not$ls180.v:2812$19_Y
+    connect \Y $not$ls180.v:2857$31_Y
   end
-  attribute \src "ls180.v:2813.61-2813.94"
-  cell $not $not$ls180.v:2813$20
+  attribute \src "ls180.v:2858.61-2858.94"
+  cell $not $not$ls180.v:2858$32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter0_skip
-    connect \Y $not$ls180.v:2813$20_Y
+    connect \Y $not$ls180.v:2858$32_Y
   end
-  attribute \src "ls180.v:2833.45-2833.80"
-  cell $not $not$ls180.v:2833$25
+  attribute \src "ls180.v:2878.45-2878.80"
+  cell $not $not$ls180.v:2878$37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_dbus_cyc
-    connect \Y $not$ls180.v:2833$25_Y
+    connect \Y $not$ls180.v:2878$37_Y
   end
-  attribute \src "ls180.v:2872.61-2872.94"
-  cell $not $not$ls180.v:2872$30
+  attribute \src "ls180.v:2917.61-2917.94"
+  cell $not $not$ls180.v:2917$42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter1_skip
-    connect \Y $not$ls180.v:2872$30_Y
+    connect \Y $not$ls180.v:2917$42_Y
   end
-  attribute \src "ls180.v:2873.61-2873.94"
-  cell $not $not$ls180.v:2873$31
+  attribute \src "ls180.v:2918.61-2918.94"
+  cell $not $not$ls180.v:2918$43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter1_skip
-    connect \Y $not$ls180.v:2873$31_Y
+    connect \Y $not$ls180.v:2918$43_Y
   end
-  attribute \src "ls180.v:2893.45-2893.83"
-  cell $not $not$ls180.v:2893$36
+  attribute \src "ls180.v:2938.45-2938.83"
+  cell $not $not$ls180.v:2938$48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_libresoc_jtag_wb_cyc
-    connect \Y $not$ls180.v:2893$36_Y
+    connect \Y $not$ls180.v:2938$48_Y
   end
-  attribute \src "ls180.v:2932.61-2932.94"
-  cell $not $not$ls180.v:2932$41
+  attribute \src "ls180.v:2977.61-2977.94"
+  cell $not $not$ls180.v:2977$53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter2_skip
-    connect \Y $not$ls180.v:2932$41_Y
+    connect \Y $not$ls180.v:2977$53_Y
   end
-  attribute \src "ls180.v:2933.61-2933.94"
-  cell $not $not$ls180.v:2933$42
+  attribute \src "ls180.v:2978.61-2978.94"
+  cell $not $not$ls180.v:2978$54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_converter2_skip
-    connect \Y $not$ls180.v:2933$42_Y
+    connect \Y $not$ls180.v:2978$54_Y
   end
-  attribute \src "ls180.v:3075.34-3075.64"
-  cell $not $not$ls180.v:3075$66
+  attribute \src "ls180.v:3150.34-3150.64"
+  cell $not $not$ls180.v:3150$117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_storage [0]
-    connect \Y $not$ls180.v:3075$66_Y
+    connect \Y $not$ls180.v:3150$117_Y
   end
-  attribute \src "ls180.v:3076.31-3076.61"
-  cell $not $not$ls180.v:3076$67
+  attribute \src "ls180.v:3151.31-3151.61"
+  cell $not $not$ls180.v:3151$118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_storage [1]
-    connect \Y $not$ls180.v:3076$67_Y
+    connect \Y $not$ls180.v:3151$118_Y
   end
-  attribute \src "ls180.v:3077.32-3077.62"
-  cell $not $not$ls180.v:3077$68
+  attribute \src "ls180.v:3152.32-3152.62"
+  cell $not $not$ls180.v:3152$119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_storage [2]
-    connect \Y $not$ls180.v:3077$68_Y
+    connect \Y $not$ls180.v:3152$119_Y
   end
-  attribute \src "ls180.v:3078.32-3078.62"
-  cell $not $not$ls180.v:3078$69
+  attribute \src "ls180.v:3153.32-3153.62"
+  cell $not $not$ls180.v:3153$120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_command_storage [3]
-    connect \Y $not$ls180.v:3078$69_Y
+    connect \Y $not$ls180.v:3153$120_Y
   end
-  attribute \src "ls180.v:3120.33-3120.56"
-  cell $not $not$ls180.v:3120$72
+  attribute \src "ls180.v:3195.33-3195.56"
+  cell $not $not$ls180.v:3195$123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_done0
-    connect \Y $not$ls180.v:3120$72_Y
+    connect \Y $not$ls180.v:3195$123_Y
   end
-  attribute \src "ls180.v:3221.58-3221.106"
-  cell $not $not$ls180.v:3221$102
+  attribute \src "ls180.v:3296.58-3296.106"
+  cell $not $not$ls180.v:3296$153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:3221$102_Y
+    connect \Y $not$ls180.v:3296$153_Y
   end
-  attribute \src "ls180.v:3275.9-3275.45"
-  cell $not $not$ls180.v:3275$107
+  attribute \src "ls180.v:3350.9-3350.45"
+  cell $not $not$ls180.v:3350$158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_refresh_req
-    connect \Y $not$ls180.v:3275$107_Y
+    connect \Y $not$ls180.v:3350$158_Y
   end
-  attribute \src "ls180.v:3378.58-3378.106"
-  cell $not $not$ls180.v:3378$132
+  attribute \src "ls180.v:3453.58-3453.106"
+  cell $not $not$ls180.v:3453$183
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:3378$132_Y
+    connect \Y $not$ls180.v:3453$183_Y
   end
-  attribute \src "ls180.v:3432.9-3432.45"
-  cell $not $not$ls180.v:3432$137
+  attribute \src "ls180.v:3507.9-3507.45"
+  cell $not $not$ls180.v:3507$188
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_refresh_req
-    connect \Y $not$ls180.v:3432$137_Y
+    connect \Y $not$ls180.v:3507$188_Y
   end
-  attribute \src "ls180.v:3535.58-3535.106"
-  cell $not $not$ls180.v:3535$162
+  attribute \src "ls180.v:3610.58-3610.106"
+  cell $not $not$ls180.v:3610$213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:3535$162_Y
+    connect \Y $not$ls180.v:3610$213_Y
   end
-  attribute \src "ls180.v:3589.9-3589.45"
-  cell $not $not$ls180.v:3589$167
+  attribute \src "ls180.v:3664.9-3664.45"
+  cell $not $not$ls180.v:3664$218
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_refresh_req
-    connect \Y $not$ls180.v:3589$167_Y
+    connect \Y $not$ls180.v:3664$218_Y
   end
-  attribute \src "ls180.v:3692.58-3692.106"
-  cell $not $not$ls180.v:3692$192
+  attribute \src "ls180.v:3767.58-3767.106"
+  cell $not $not$ls180.v:3767$243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:3692$192_Y
+    connect \Y $not$ls180.v:3767$243_Y
   end
-  attribute \src "ls180.v:3746.9-3746.45"
-  cell $not $not$ls180.v:3746$197
+  attribute \src "ls180.v:3821.9-3821.45"
+  cell $not $not$ls180.v:3821$248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_refresh_req
-    connect \Y $not$ls180.v:3746$197_Y
+    connect \Y $not$ls180.v:3821$248_Y
   end
-  attribute \src "ls180.v:3788.149-3788.187"
-  cell $not $not$ls180.v:3788$200
+  attribute \src "ls180.v:3863.149-3863.187"
+  cell $not $not$ls180.v:3863$251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:3788$200_Y
+    connect \Y $not$ls180.v:3863$251_Y
   end
-  attribute \src "ls180.v:3788.193-3788.230"
-  cell $not $not$ls180.v:3788$202
+  attribute \src "ls180.v:3863.193-3863.230"
+  cell $not $not$ls180.v:3863$253
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:3788$202_Y
+    connect \Y $not$ls180.v:3863$253_Y
   end
-  attribute \src "ls180.v:3789.149-3789.187"
-  cell $not $not$ls180.v:3789$206
+  attribute \src "ls180.v:3864.149-3864.187"
+  cell $not $not$ls180.v:3864$257
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:3789$206_Y
+    connect \Y $not$ls180.v:3864$257_Y
   end
-  attribute \src "ls180.v:3789.193-3789.230"
-  cell $not $not$ls180.v:3789$208
+  attribute \src "ls180.v:3864.193-3864.230"
+  cell $not $not$ls180.v:3864$259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:3789$208_Y
+    connect \Y $not$ls180.v:3864$259_Y
   end
-  attribute \src "ls180.v:3805.43-3805.73"
-  cell $not $not$ls180.v:3805$236
+  attribute \src "ls180.v:3880.43-3880.73"
+  cell $not $not$ls180.v:3880$287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \main_sdram_interface_wdata_we
-    connect \Y $not$ls180.v:3805$236_Y
+    connect \Y $not$ls180.v:3880$287_Y
   end
-  attribute \src "ls180.v:3808.205-3808.245"
-  cell $not $not$ls180.v:3808$239
+  attribute \src "ls180.v:3883.205-3883.245"
+  cell $not $not$ls180.v:3883$290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_cas
-    connect \Y $not$ls180.v:3808$239_Y
+    connect \Y $not$ls180.v:3883$290_Y
   end
-  attribute \src "ls180.v:3808.251-3808.290"
-  cell $not $not$ls180.v:3808$241
+  attribute \src "ls180.v:3883.251-3883.290"
+  cell $not $not$ls180.v:3883$292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_we
-    connect \Y $not$ls180.v:3808$241_Y
+    connect \Y $not$ls180.v:3883$292_Y
   end
-  attribute \src "ls180.v:3808.159-3808.292"
-  cell $not $not$ls180.v:3808$243
+  attribute \src "ls180.v:3883.159-3883.292"
+  cell $not $not$ls180.v:3883$294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3808$242_Y
-    connect \Y $not$ls180.v:3808$243_Y
+    connect \A $and$ls180.v:3883$293_Y
+    connect \Y $not$ls180.v:3883$294_Y
   end
-  attribute \src "ls180.v:3809.205-3809.245"
-  cell $not $not$ls180.v:3809$252
+  attribute \src "ls180.v:3884.205-3884.245"
+  cell $not $not$ls180.v:3884$303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_cas
-    connect \Y $not$ls180.v:3809$252_Y
+    connect \Y $not$ls180.v:3884$303_Y
   end
-  attribute \src "ls180.v:3809.251-3809.290"
-  cell $not $not$ls180.v:3809$254
+  attribute \src "ls180.v:3884.251-3884.290"
+  cell $not $not$ls180.v:3884$305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_we
-    connect \Y $not$ls180.v:3809$254_Y
+    connect \Y $not$ls180.v:3884$305_Y
   end
-  attribute \src "ls180.v:3809.159-3809.292"
-  cell $not $not$ls180.v:3809$256
+  attribute \src "ls180.v:3884.159-3884.292"
+  cell $not $not$ls180.v:3884$307
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3809$255_Y
-    connect \Y $not$ls180.v:3809$256_Y
+    connect \A $and$ls180.v:3884$306_Y
+    connect \Y $not$ls180.v:3884$307_Y
   end
-  attribute \src "ls180.v:3810.205-3810.245"
-  cell $not $not$ls180.v:3810$265
+  attribute \src "ls180.v:3885.205-3885.245"
+  cell $not $not$ls180.v:3885$316
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_cas
-    connect \Y $not$ls180.v:3810$265_Y
+    connect \Y $not$ls180.v:3885$316_Y
   end
-  attribute \src "ls180.v:3810.251-3810.290"
-  cell $not $not$ls180.v:3810$267
+  attribute \src "ls180.v:3885.251-3885.290"
+  cell $not $not$ls180.v:3885$318
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_we
-    connect \Y $not$ls180.v:3810$267_Y
+    connect \Y $not$ls180.v:3885$318_Y
   end
-  attribute \src "ls180.v:3810.159-3810.292"
-  cell $not $not$ls180.v:3810$269
+  attribute \src "ls180.v:3885.159-3885.292"
+  cell $not $not$ls180.v:3885$320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3810$268_Y
-    connect \Y $not$ls180.v:3810$269_Y
+    connect \A $and$ls180.v:3885$319_Y
+    connect \Y $not$ls180.v:3885$320_Y
   end
-  attribute \src "ls180.v:3811.205-3811.245"
-  cell $not $not$ls180.v:3811$278
+  attribute \src "ls180.v:3886.205-3886.245"
+  cell $not $not$ls180.v:3886$329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_cas
-    connect \Y $not$ls180.v:3811$278_Y
+    connect \Y $not$ls180.v:3886$329_Y
   end
-  attribute \src "ls180.v:3811.251-3811.290"
-  cell $not $not$ls180.v:3811$280
+  attribute \src "ls180.v:3886.251-3886.290"
+  cell $not $not$ls180.v:3886$331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_we
-    connect \Y $not$ls180.v:3811$280_Y
+    connect \Y $not$ls180.v:3886$331_Y
   end
-  attribute \src "ls180.v:3811.159-3811.292"
-  cell $not $not$ls180.v:3811$282
+  attribute \src "ls180.v:3886.159-3886.292"
+  cell $not $not$ls180.v:3886$333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3811$281_Y
-    connect \Y $not$ls180.v:3811$282_Y
+    connect \A $and$ls180.v:3886$332_Y
+    connect \Y $not$ls180.v:3886$333_Y
   end
-  attribute \src "ls180.v:3838.71-3838.103"
-  cell $not $not$ls180.v:3838$293
+  attribute \src "ls180.v:3913.71-3913.103"
+  cell $not $not$ls180.v:3913$344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_valid
-    connect \Y $not$ls180.v:3838$293_Y
+    connect \Y $not$ls180.v:3913$344_Y
   end
-  attribute \src "ls180.v:3841.205-3841.245"
-  cell $not $not$ls180.v:3841$297
+  attribute \src "ls180.v:3916.205-3916.245"
+  cell $not $not$ls180.v:3916$348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_cas
-    connect \Y $not$ls180.v:3841$297_Y
+    connect \Y $not$ls180.v:3916$348_Y
   end
-  attribute \src "ls180.v:3841.251-3841.290"
-  cell $not $not$ls180.v:3841$299
+  attribute \src "ls180.v:3916.251-3916.290"
+  cell $not $not$ls180.v:3916$350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_payload_we
-    connect \Y $not$ls180.v:3841$299_Y
+    connect \Y $not$ls180.v:3916$350_Y
   end
-  attribute \src "ls180.v:3841.159-3841.292"
-  cell $not $not$ls180.v:3841$301
+  attribute \src "ls180.v:3916.159-3916.292"
+  cell $not $not$ls180.v:3916$352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3841$300_Y
-    connect \Y $not$ls180.v:3841$301_Y
+    connect \A $and$ls180.v:3916$351_Y
+    connect \Y $not$ls180.v:3916$352_Y
   end
-  attribute \src "ls180.v:3842.205-3842.245"
-  cell $not $not$ls180.v:3842$310
+  attribute \src "ls180.v:3917.205-3917.245"
+  cell $not $not$ls180.v:3917$361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_cas
-    connect \Y $not$ls180.v:3842$310_Y
+    connect \Y $not$ls180.v:3917$361_Y
   end
-  attribute \src "ls180.v:3842.251-3842.290"
-  cell $not $not$ls180.v:3842$312
+  attribute \src "ls180.v:3917.251-3917.290"
+  cell $not $not$ls180.v:3917$363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_payload_we
-    connect \Y $not$ls180.v:3842$312_Y
+    connect \Y $not$ls180.v:3917$363_Y
   end
-  attribute \src "ls180.v:3842.159-3842.292"
-  cell $not $not$ls180.v:3842$314
+  attribute \src "ls180.v:3917.159-3917.292"
+  cell $not $not$ls180.v:3917$365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3842$313_Y
-    connect \Y $not$ls180.v:3842$314_Y
+    connect \A $and$ls180.v:3917$364_Y
+    connect \Y $not$ls180.v:3917$365_Y
   end
-  attribute \src "ls180.v:3843.205-3843.245"
-  cell $not $not$ls180.v:3843$323
+  attribute \src "ls180.v:3918.205-3918.245"
+  cell $not $not$ls180.v:3918$374
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_cas
-    connect \Y $not$ls180.v:3843$323_Y
+    connect \Y $not$ls180.v:3918$374_Y
   end
-  attribute \src "ls180.v:3843.251-3843.290"
-  cell $not $not$ls180.v:3843$325
+  attribute \src "ls180.v:3918.251-3918.290"
+  cell $not $not$ls180.v:3918$376
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_payload_we
-    connect \Y $not$ls180.v:3843$325_Y
+    connect \Y $not$ls180.v:3918$376_Y
   end
-  attribute \src "ls180.v:3843.159-3843.292"
-  cell $not $not$ls180.v:3843$327
+  attribute \src "ls180.v:3918.159-3918.292"
+  cell $not $not$ls180.v:3918$378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3843$326_Y
-    connect \Y $not$ls180.v:3843$327_Y
+    connect \A $and$ls180.v:3918$377_Y
+    connect \Y $not$ls180.v:3918$378_Y
   end
-  attribute \src "ls180.v:3844.205-3844.245"
-  cell $not $not$ls180.v:3844$336
+  attribute \src "ls180.v:3919.205-3919.245"
+  cell $not $not$ls180.v:3919$387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_cas
-    connect \Y $not$ls180.v:3844$336_Y
+    connect \Y $not$ls180.v:3919$387_Y
   end
-  attribute \src "ls180.v:3844.251-3844.290"
-  cell $not $not$ls180.v:3844$338
+  attribute \src "ls180.v:3919.251-3919.290"
+  cell $not $not$ls180.v:3919$389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_payload_we
-    connect \Y $not$ls180.v:3844$338_Y
+    connect \Y $not$ls180.v:3919$389_Y
   end
-  attribute \src "ls180.v:3844.159-3844.292"
-  cell $not $not$ls180.v:3844$340
+  attribute \src "ls180.v:3919.159-3919.292"
+  cell $not $not$ls180.v:3919$391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3844$339_Y
-    connect \Y $not$ls180.v:3844$340_Y
+    connect \A $and$ls180.v:3919$390_Y
+    connect \Y $not$ls180.v:3919$391_Y
   end
-  attribute \src "ls180.v:3907.71-3907.103"
-  cell $not $not$ls180.v:3907$379
+  attribute \src "ls180.v:3982.71-3982.103"
+  cell $not $not$ls180.v:3982$430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_valid
-    connect \Y $not$ls180.v:3907$379_Y
+    connect \Y $not$ls180.v:3982$430_Y
   end
-  attribute \src "ls180.v:3928.112-3928.150"
-  cell $not $not$ls180.v:3928$382
+  attribute \src "ls180.v:4003.112-4003.150"
+  cell $not $not$ls180.v:4003$433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:3928$382_Y
+    connect \Y $not$ls180.v:4003$433_Y
   end
-  attribute \src "ls180.v:3928.156-3928.193"
-  cell $not $not$ls180.v:3928$384
+  attribute \src "ls180.v:4003.156-4003.193"
+  cell $not $not$ls180.v:4003$435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:3928$384_Y
+    connect \Y $not$ls180.v:4003$435_Y
   end
-  attribute \src "ls180.v:3928.68-3928.195"
-  cell $not $not$ls180.v:3928$386
+  attribute \src "ls180.v:4003.68-4003.195"
+  cell $not $not$ls180.v:4003$437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3928$385_Y
-    connect \Y $not$ls180.v:3928$386_Y
+    connect \A $and$ls180.v:4003$436_Y
+    connect \Y $not$ls180.v:4003$437_Y
   end
-  attribute \src "ls180.v:3936.11-3936.38"
-  cell $not $not$ls180.v:3936$389
+  attribute \src "ls180.v:4011.11-4011.38"
+  cell $not $not$ls180.v:4011$440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_write_available
-    connect \Y $not$ls180.v:3936$389_Y
+    connect \Y $not$ls180.v:4011$440_Y
   end
-  attribute \src "ls180.v:3966.112-3966.150"
-  cell $not $not$ls180.v:3966$391
+  attribute \src "ls180.v:4041.112-4041.150"
+  cell $not $not$ls180.v:4041$442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:3966$391_Y
+    connect \Y $not$ls180.v:4041$442_Y
   end
-  attribute \src "ls180.v:3966.156-3966.193"
-  cell $not $not$ls180.v:3966$393
+  attribute \src "ls180.v:4041.156-4041.193"
+  cell $not $not$ls180.v:4041$444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:3966$393_Y
+    connect \Y $not$ls180.v:4041$444_Y
   end
-  attribute \src "ls180.v:3966.68-3966.195"
-  cell $not $not$ls180.v:3966$395
+  attribute \src "ls180.v:4041.68-4041.195"
+  cell $not $not$ls180.v:4041$446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3966$394_Y
-    connect \Y $not$ls180.v:3966$395_Y
+    connect \A $and$ls180.v:4041$445_Y
+    connect \Y $not$ls180.v:4041$446_Y
   end
-  attribute \src "ls180.v:3974.11-3974.37"
-  cell $not $not$ls180.v:3974$398
+  attribute \src "ls180.v:4049.11-4049.37"
+  cell $not $not$ls180.v:4049$449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_read_available
-    connect \Y $not$ls180.v:3974$398_Y
+    connect \Y $not$ls180.v:4049$449_Y
   end
-  attribute \src "ls180.v:3984.87-3984.331"
-  cell $not $not$ls180.v:3984$410
+  attribute \src "ls180.v:4059.87-4059.331"
+  cell $not $not$ls180.v:4059$461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3984$409_Y
-    connect \Y $not$ls180.v:3984$410_Y
+    connect \A $or$ls180.v:4059$460_Y
+    connect \Y $not$ls180.v:4059$461_Y
   end
-  attribute \src "ls180.v:3985.35-3985.68"
-  cell $not $not$ls180.v:3985$413
+  attribute \src "ls180.v:4060.35-4060.68"
+  cell $not $not$ls180.v:4060$464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_valid
-    connect \Y $not$ls180.v:3985$413_Y
+    connect \Y $not$ls180.v:4060$464_Y
   end
-  attribute \src "ls180.v:3985.73-3985.105"
-  cell $not $not$ls180.v:3985$414
+  attribute \src "ls180.v:4060.73-4060.105"
+  cell $not $not$ls180.v:4060$465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank0_lock
-    connect \Y $not$ls180.v:3985$414_Y
+    connect \Y $not$ls180.v:4060$465_Y
   end
-  attribute \src "ls180.v:3989.87-3989.331"
-  cell $not $not$ls180.v:3989$426
+  attribute \src "ls180.v:4064.87-4064.331"
+  cell $not $not$ls180.v:4064$477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3989$425_Y
-    connect \Y $not$ls180.v:3989$426_Y
+    connect \A $or$ls180.v:4064$476_Y
+    connect \Y $not$ls180.v:4064$477_Y
   end
-  attribute \src "ls180.v:3990.35-3990.68"
-  cell $not $not$ls180.v:3990$429
+  attribute \src "ls180.v:4065.35-4065.68"
+  cell $not $not$ls180.v:4065$480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_valid
-    connect \Y $not$ls180.v:3990$429_Y
+    connect \Y $not$ls180.v:4065$480_Y
   end
-  attribute \src "ls180.v:3990.73-3990.105"
-  cell $not $not$ls180.v:3990$430
+  attribute \src "ls180.v:4065.73-4065.105"
+  cell $not $not$ls180.v:4065$481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank1_lock
-    connect \Y $not$ls180.v:3990$430_Y
+    connect \Y $not$ls180.v:4065$481_Y
   end
-  attribute \src "ls180.v:3994.87-3994.331"
-  cell $not $not$ls180.v:3994$442
+  attribute \src "ls180.v:4069.87-4069.331"
+  cell $not $not$ls180.v:4069$493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3994$441_Y
-    connect \Y $not$ls180.v:3994$442_Y
+    connect \A $or$ls180.v:4069$492_Y
+    connect \Y $not$ls180.v:4069$493_Y
   end
-  attribute \src "ls180.v:3995.35-3995.68"
-  cell $not $not$ls180.v:3995$445
+  attribute \src "ls180.v:4070.35-4070.68"
+  cell $not $not$ls180.v:4070$496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_valid
-    connect \Y $not$ls180.v:3995$445_Y
+    connect \Y $not$ls180.v:4070$496_Y
   end
-  attribute \src "ls180.v:3995.73-3995.105"
-  cell $not $not$ls180.v:3995$446
+  attribute \src "ls180.v:4070.73-4070.105"
+  cell $not $not$ls180.v:4070$497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank2_lock
-    connect \Y $not$ls180.v:3995$446_Y
+    connect \Y $not$ls180.v:4070$497_Y
   end
-  attribute \src "ls180.v:3999.87-3999.331"
-  cell $not $not$ls180.v:3999$458
+  attribute \src "ls180.v:4074.87-4074.331"
+  cell $not $not$ls180.v:4074$509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3999$457_Y
-    connect \Y $not$ls180.v:3999$458_Y
+    connect \A $or$ls180.v:4074$508_Y
+    connect \Y $not$ls180.v:4074$509_Y
   end
-  attribute \src "ls180.v:4000.35-4000.68"
-  cell $not $not$ls180.v:4000$461
+  attribute \src "ls180.v:4075.35-4075.68"
+  cell $not $not$ls180.v:4075$512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_valid
-    connect \Y $not$ls180.v:4000$461_Y
+    connect \Y $not$ls180.v:4075$512_Y
   end
-  attribute \src "ls180.v:4000.73-4000.105"
-  cell $not $not$ls180.v:4000$462
+  attribute \src "ls180.v:4075.73-4075.105"
+  cell $not $not$ls180.v:4075$513
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_interface_bank3_lock
-    connect \Y $not$ls180.v:4000$462_Y
+    connect \Y $not$ls180.v:4075$513_Y
   end
-  attribute \src "ls180.v:4004.128-4004.372"
-  cell $not $not$ls180.v:4004$475
+  attribute \src "ls180.v:4079.128-4079.372"
+  cell $not $not$ls180.v:4079$526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$474_Y
-    connect \Y $not$ls180.v:4004$475_Y
+    connect \A $or$ls180.v:4079$525_Y
+    connect \Y $not$ls180.v:4079$526_Y
   end
-  attribute \src "ls180.v:4004.502-4004.746"
-  cell $not $not$ls180.v:4004$491
+  attribute \src "ls180.v:4079.502-4079.746"
+  cell $not $not$ls180.v:4079$542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$490_Y
-    connect \Y $not$ls180.v:4004$491_Y
+    connect \A $or$ls180.v:4079$541_Y
+    connect \Y $not$ls180.v:4079$542_Y
   end
-  attribute \src "ls180.v:4004.876-4004.1120"
-  cell $not $not$ls180.v:4004$507
+  attribute \src "ls180.v:4079.876-4079.1120"
+  cell $not $not$ls180.v:4079$558
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$506_Y
-    connect \Y $not$ls180.v:4004$507_Y
+    connect \A $or$ls180.v:4079$557_Y
+    connect \Y $not$ls180.v:4079$558_Y
   end
-  attribute \src "ls180.v:4004.1250-4004.1494"
-  cell $not $not$ls180.v:4004$523
+  attribute \src "ls180.v:4079.1250-4079.1494"
+  cell $not $not$ls180.v:4079$574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$522_Y
-    connect \Y $not$ls180.v:4004$523_Y
+    connect \A $or$ls180.v:4079$573_Y
+    connect \Y $not$ls180.v:4079$574_Y
   end
-  attribute \src "ls180.v:4026.32-4026.50"
-  cell $not $not$ls180.v:4026$529
+  attribute \src "ls180.v:4101.32-4101.50"
+  cell $not $not$ls180.v:4101$580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_wb_sdram_cyc
-    connect \Y $not$ls180.v:4026$529_Y
+    connect \Y $not$ls180.v:4101$580_Y
   end
-  attribute \src "ls180.v:4065.30-4065.50"
-  cell $not $not$ls180.v:4065$534
+  attribute \src "ls180.v:4140.30-4140.50"
+  cell $not $not$ls180.v:4140$585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_converter_skip
-    connect \Y $not$ls180.v:4065$534_Y
+    connect \Y $not$ls180.v:4140$585_Y
   end
-  attribute \src "ls180.v:4066.30-4066.50"
-  cell $not $not$ls180.v:4066$535
+  attribute \src "ls180.v:4141.30-4141.50"
+  cell $not $not$ls180.v:4141$586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_converter_skip
-    connect \Y $not$ls180.v:4066$535_Y
+    connect \Y $not$ls180.v:4141$586_Y
   end
-  attribute \src "ls180.v:4091.27-4091.48"
-  cell $not $not$ls180.v:4091$541
+  attribute \src "ls180.v:4166.27-4166.48"
+  cell $not $not$ls180.v:4166$592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_cyc
-    connect \Y $not$ls180.v:4091$541_Y
+    connect \Y $not$ls180.v:4166$592_Y
   end
-  attribute \src "ls180.v:4092.30-4092.50"
-  cell $not $not$ls180.v:4092$542
+  attribute \src "ls180.v:4167.30-4167.50"
+  cell $not $not$ls180.v:4167$593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_we
-    connect \Y $not$ls180.v:4092$542_Y
+    connect \Y $not$ls180.v:4167$593_Y
   end
-  attribute \src "ls180.v:4093.80-4093.98"
-  cell $not $not$ls180.v:4093$544
+  attribute \src "ls180.v:4168.80-4168.98"
+  cell $not $not$ls180.v:4168$595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_cmd_consumed
-    connect \Y $not$ls180.v:4093$544_Y
+    connect \Y $not$ls180.v:4168$595_Y
   end
-  attribute \src "ls180.v:4094.107-4094.127"
-  cell $not $not$ls180.v:4094$548
+  attribute \src "ls180.v:4169.107-4169.127"
+  cell $not $not$ls180.v:4169$599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_wdata_consumed
-    connect \Y $not$ls180.v:4094$548_Y
+    connect \Y $not$ls180.v:4169$599_Y
   end
-  attribute \src "ls180.v:4095.78-4095.103"
-  cell $not $not$ls180.v:4095$551
+  attribute \src "ls180.v:4170.78-4170.103"
+  cell $not $not$ls180.v:4170$602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_payload_we
-    connect \Y $not$ls180.v:4095$551_Y
+    connect \Y $not$ls180.v:4170$602_Y
   end
-  attribute \src "ls180.v:4096.91-4096.111"
-  cell $not $not$ls180.v:4096$554
+  attribute \src "ls180.v:4171.91-4171.111"
+  cell $not $not$ls180.v:4171$605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_we
-    connect \Y $not$ls180.v:4096$554_Y
+    connect \Y $not$ls180.v:4171$605_Y
   end
-  attribute \src "ls180.v:4112.35-4112.64"
-  cell $not $not$ls180.v:4112$563
+  attribute \src "ls180.v:4187.35-4187.64"
+  cell $not $not$ls180.v:4187$614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_sink_ready
-    connect \Y $not$ls180.v:4112$563_Y
+    connect \Y $not$ls180.v:4187$614_Y
   end
-  attribute \src "ls180.v:4113.36-4113.67"
-  cell $not $not$ls180.v:4113$564
+  attribute \src "ls180.v:4188.36-4188.67"
+  cell $not $not$ls180.v:4188$615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_source_valid
-    connect \Y $not$ls180.v:4113$564_Y
+    connect \Y $not$ls180.v:4188$615_Y
   end
-  attribute \src "ls180.v:4119.32-4119.61"
-  cell $not $not$ls180.v:4119$565
+  attribute \src "ls180.v:4194.32-4194.61"
+  cell $not $not$ls180.v:4194$616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_sink_ready
-    connect \Y $not$ls180.v:4119$565_Y
+    connect \Y $not$ls180.v:4194$616_Y
   end
-  attribute \src "ls180.v:4125.36-4125.67"
-  cell $not $not$ls180.v:4125$566
+  attribute \src "ls180.v:4200.36-4200.67"
+  cell $not $not$ls180.v:4200$617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_source_valid
-    connect \Y $not$ls180.v:4125$566_Y
+    connect \Y $not$ls180.v:4200$617_Y
   end
-  attribute \src "ls180.v:4126.35-4126.64"
-  cell $not $not$ls180.v:4126$567
+  attribute \src "ls180.v:4201.35-4201.64"
+  cell $not $not$ls180.v:4201$618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_sink_ready
-    connect \Y $not$ls180.v:4126$567_Y
+    connect \Y $not$ls180.v:4201$618_Y
   end
-  attribute \src "ls180.v:4129.32-4129.63"
-  cell $not $not$ls180.v:4129$570
+  attribute \src "ls180.v:4204.32-4204.63"
+  cell $not $not$ls180.v:4204$621
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_source_valid
-    connect \Y $not$ls180.v:4129$570_Y
+    connect \Y $not$ls180.v:4204$621_Y
   end
-  attribute \src "ls180.v:4167.81-4167.108"
-  cell $not $not$ls180.v:4167$580
+  attribute \src "ls180.v:4242.81-4242.108"
+  cell $not $not$ls180.v:4242$631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_readable
-    connect \Y $not$ls180.v:4167$580_Y
+    connect \Y $not$ls180.v:4242$631_Y
   end
-  attribute \src "ls180.v:4197.81-4197.108"
-  cell $not $not$ls180.v:4197$591
+  attribute \src "ls180.v:4272.81-4272.108"
+  cell $not $not$ls180.v:4272$642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_readable
-    connect \Y $not$ls180.v:4197$591_Y
+    connect \Y $not$ls180.v:4272$642_Y
   end
-  attribute \src "ls180.v:4397.60-4397.85"
-  cell $not $not$ls180.v:4397$640
+  attribute \src "ls180.v:4472.60-4472.85"
+  cell $not $not$ls180.v:4472$691
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_clocker_clk_d
-    connect \Y $not$ls180.v:4397$640_Y
+    connect \Y $not$ls180.v:4472$691_Y
   end
-  attribute \src "ls180.v:4538.54-4538.96"
-  cell $not $not$ls180.v:4538$654
+  attribute \src "ls180.v:4613.54-4613.96"
+  cell $not $not$ls180.v:4613$705
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all
-    connect \Y $not$ls180.v:4538$654_Y
+    connect \Y $not$ls180.v:4613$705_Y
   end
-  attribute \src "ls180.v:4541.48-4541.86"
-  cell $not $not$ls180.v:4541$657
+  attribute \src "ls180.v:4616.48-4616.86"
+  cell $not $not$ls180.v:4616$708
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
-    connect \Y $not$ls180.v:4541$657_Y
+    connect \Y $not$ls180.v:4616$708_Y
   end
-  attribute \src "ls180.v:4665.55-4665.98"
-  cell $not $not$ls180.v:4665$675
+  attribute \src "ls180.v:4740.55-4740.98"
+  cell $not $not$ls180.v:4740$726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_strobe_all
-    connect \Y $not$ls180.v:4665$675_Y
+    connect \Y $not$ls180.v:4740$726_Y
   end
-  attribute \src "ls180.v:4668.49-4668.88"
-  cell $not $not$ls180.v:4668$678
+  attribute \src "ls180.v:4743.49-4743.88"
+  cell $not $not$ls180.v:4743$729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_buf_source_valid
-    connect \Y $not$ls180.v:4668$678_Y
+    connect \Y $not$ls180.v:4743$729_Y
   end
-  attribute \src "ls180.v:4718.30-4718.58"
-  cell $not $not$ls180.v:4718$684
+  attribute \src "ls180.v:4793.30-4793.58"
+  cell $not $not$ls180.v:4793$735
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_sink_valid
-    connect \Y $not$ls180.v:4718$684_Y
+    connect \Y $not$ls180.v:4793$735_Y
   end
-  attribute \src "ls180.v:4799.56-4799.100"
-  cell $not $not$ls180.v:4799$690
+  attribute \src "ls180.v:4874.56-4874.100"
+  cell $not $not$ls180.v:4874$741
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_strobe_all
-    connect \Y $not$ls180.v:4799$690_Y
+    connect \Y $not$ls180.v:4874$741_Y
   end
-  attribute \src "ls180.v:4802.50-4802.90"
-  cell $not $not$ls180.v:4802$693
+  attribute \src "ls180.v:4877.50-4877.90"
+  cell $not $not$ls180.v:4877$744
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_buf_source_valid
-    connect \Y $not$ls180.v:4802$693_Y
+    connect \Y $not$ls180.v:4877$744_Y
   end
-  attribute \src "ls180.v:4918.42-4918.74"
-  cell $not $not$ls180.v:4918$709
+  attribute \src "ls180.v:4993.42-4993.74"
+  cell $not $not$ls180.v:4993$760
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_valid
-    connect \Y $not$ls180.v:4918$709_Y
+    connect \Y $not$ls180.v:4993$760_Y
   end
-  attribute \src "ls180.v:5442.50-5442.88"
-  cell $not $not$ls180.v:5442$994
+  attribute \src "ls180.v:5517.50-5517.88"
+  cell $not $not$ls180.v:5517$1045
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_strobe_all
-    connect \Y $not$ls180.v:5442$994_Y
+    connect \Y $not$ls180.v:5517$1045_Y
   end
-  attribute \src "ls180.v:5454.52-5454.102"
-  cell $not $not$ls180.v:5454$997
+  attribute \src "ls180.v:5529.52-5529.102"
+  cell $not $not$ls180.v:5529$1048
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage
-    connect \Y $not$ls180.v:5454$997_Y
+    connect \Y $not$ls180.v:5529$1048_Y
   end
-  attribute \src "ls180.v:5513.38-5513.74"
-  cell $not $not$ls180.v:5513$1004
+  attribute \src "ls180.v:5588.38-5588.74"
+  cell $not $not$ls180.v:5588$1055
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_dma_enable_storage
-    connect \Y $not$ls180.v:5513$1004_Y
+    connect \Y $not$ls180.v:5588$1055_Y
   end
-  attribute \src "ls180.v:5755.69-5755.88"
-  cell $not $not$ls180.v:5755$1065
+  attribute \src "ls180.v:5857.69-5857.88"
+  cell $not $not$ls180.v:5857$1125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_shared_ack
-    connect \Y $not$ls180.v:5755$1065_Y
+    connect \Y $not$ls180.v:5857$1125_Y
   end
-  attribute \src "ls180.v:5772.63-5772.94"
-  cell $not $not$ls180.v:5772$1086
+  attribute \src "ls180.v:5874.63-5874.94"
+  cell $not $not$ls180.v:5874$1155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5772$1086_Y
+    connect \Y $not$ls180.v:5874$1155_Y
   end
-  attribute \src "ls180.v:5775.65-5775.96"
-  cell $not $not$ls180.v:5775$1093
+  attribute \src "ls180.v:5877.65-5877.96"
+  cell $not $not$ls180.v:5877$1162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5775$1093_Y
+    connect \Y $not$ls180.v:5877$1162_Y
   end
-  attribute \src "ls180.v:5778.65-5778.96"
-  cell $not $not$ls180.v:5778$1100
+  attribute \src "ls180.v:5880.65-5880.96"
+  cell $not $not$ls180.v:5880$1169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5778$1100_Y
+    connect \Y $not$ls180.v:5880$1169_Y
   end
-  attribute \src "ls180.v:5781.65-5781.96"
-  cell $not $not$ls180.v:5781$1107
+  attribute \src "ls180.v:5883.65-5883.96"
+  cell $not $not$ls180.v:5883$1176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5781$1107_Y
+    connect \Y $not$ls180.v:5883$1176_Y
   end
-  attribute \src "ls180.v:5784.65-5784.96"
-  cell $not $not$ls180.v:5784$1114
+  attribute \src "ls180.v:5886.65-5886.96"
+  cell $not $not$ls180.v:5886$1183
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5784$1114_Y
+    connect \Y $not$ls180.v:5886$1183_Y
   end
-  attribute \src "ls180.v:5787.68-5787.99"
-  cell $not $not$ls180.v:5787$1121
+  attribute \src "ls180.v:5889.68-5889.99"
+  cell $not $not$ls180.v:5889$1190
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5787$1121_Y
+    connect \Y $not$ls180.v:5889$1190_Y
   end
-  attribute \src "ls180.v:5790.68-5790.99"
-  cell $not $not$ls180.v:5790$1128
+  attribute \src "ls180.v:5892.68-5892.99"
+  cell $not $not$ls180.v:5892$1197
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5790$1128_Y
+    connect \Y $not$ls180.v:5892$1197_Y
   end
-  attribute \src "ls180.v:5793.68-5793.99"
-  cell $not $not$ls180.v:5793$1135
+  attribute \src "ls180.v:5895.68-5895.99"
+  cell $not $not$ls180.v:5895$1204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5793$1135_Y
+    connect \Y $not$ls180.v:5895$1204_Y
   end
-  attribute \src "ls180.v:5796.68-5796.99"
-  cell $not $not$ls180.v:5796$1142
+  attribute \src "ls180.v:5898.68-5898.99"
+  cell $not $not$ls180.v:5898$1211
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface0_bank_bus_we
-    connect \Y $not$ls180.v:5796$1142_Y
+    connect \Y $not$ls180.v:5898$1211_Y
   end
-  attribute \src "ls180.v:5810.60-5810.91"
-  cell $not $not$ls180.v:5810$1150
+  attribute \src "ls180.v:5912.60-5912.91"
+  cell $not $not$ls180.v:5912$1219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5810$1150_Y
+    connect \Y $not$ls180.v:5912$1219_Y
   end
-  attribute \src "ls180.v:5813.60-5813.91"
-  cell $not $not$ls180.v:5813$1157
+  attribute \src "ls180.v:5915.60-5915.91"
+  cell $not $not$ls180.v:5915$1226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5813$1157_Y
+    connect \Y $not$ls180.v:5915$1226_Y
   end
-  attribute \src "ls180.v:5816.60-5816.91"
-  cell $not $not$ls180.v:5816$1164
+  attribute \src "ls180.v:5918.60-5918.91"
+  cell $not $not$ls180.v:5918$1233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5816$1164_Y
+    connect \Y $not$ls180.v:5918$1233_Y
   end
-  attribute \src "ls180.v:5819.60-5819.91"
-  cell $not $not$ls180.v:5819$1171
+  attribute \src "ls180.v:5921.60-5921.91"
+  cell $not $not$ls180.v:5921$1240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5819$1171_Y
+    connect \Y $not$ls180.v:5921$1240_Y
   end
-  attribute \src "ls180.v:5822.61-5822.92"
-  cell $not $not$ls180.v:5822$1178
+  attribute \src "ls180.v:5924.61-5924.92"
+  cell $not $not$ls180.v:5924$1247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5822$1178_Y
+    connect \Y $not$ls180.v:5924$1247_Y
   end
-  attribute \src "ls180.v:5825.61-5825.92"
-  cell $not $not$ls180.v:5825$1185
+  attribute \src "ls180.v:5927.61-5927.92"
+  cell $not $not$ls180.v:5927$1254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface1_bank_bus_we
-    connect \Y $not$ls180.v:5825$1185_Y
+    connect \Y $not$ls180.v:5927$1254_Y
   end
-  attribute \src "ls180.v:5836.59-5836.90"
-  cell $not $not$ls180.v:5836$1193
+  attribute \src "ls180.v:5938.59-5938.90"
+  cell $not $not$ls180.v:5938$1262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_we
-    connect \Y $not$ls180.v:5836$1193_Y
+    connect \Y $not$ls180.v:5938$1262_Y
   end
-  attribute \src "ls180.v:5839.58-5839.89"
-  cell $not $not$ls180.v:5839$1200
+  attribute \src "ls180.v:5941.58-5941.89"
+  cell $not $not$ls180.v:5941$1269
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface2_bank_bus_we
-    connect \Y $not$ls180.v:5839$1200_Y
+    connect \Y $not$ls180.v:5941$1269_Y
   end
-  attribute \src "ls180.v:5850.64-5850.95"
-  cell $not $not$ls180.v:5850$1208
+  attribute \src "ls180.v:5952.64-5952.95"
+  cell $not $not$ls180.v:5952$1277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5850$1208_Y
+    connect \Y $not$ls180.v:5952$1277_Y
   end
-  attribute \src "ls180.v:5853.63-5853.94"
-  cell $not $not$ls180.v:5853$1215
+  attribute \src "ls180.v:5955.63-5955.94"
+  cell $not $not$ls180.v:5955$1284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5853$1215_Y
+    connect \Y $not$ls180.v:5955$1284_Y
   end
-  attribute \src "ls180.v:5856.63-5856.94"
-  cell $not $not$ls180.v:5856$1222
+  attribute \src "ls180.v:5958.63-5958.94"
+  cell $not $not$ls180.v:5958$1291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5856$1222_Y
+    connect \Y $not$ls180.v:5958$1291_Y
   end
-  attribute \src "ls180.v:5859.63-5859.94"
-  cell $not $not$ls180.v:5859$1229
+  attribute \src "ls180.v:5961.63-5961.94"
+  cell $not $not$ls180.v:5961$1298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5859$1229_Y
+    connect \Y $not$ls180.v:5961$1298_Y
   end
-  attribute \src "ls180.v:5862.63-5862.94"
-  cell $not $not$ls180.v:5862$1236
+  attribute \src "ls180.v:5964.63-5964.94"
+  cell $not $not$ls180.v:5964$1305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5862$1236_Y
+    connect \Y $not$ls180.v:5964$1305_Y
   end
-  attribute \src "ls180.v:5865.64-5865.95"
-  cell $not $not$ls180.v:5865$1243
+  attribute \src "ls180.v:5967.64-5967.95"
+  cell $not $not$ls180.v:5967$1312
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5865$1243_Y
+    connect \Y $not$ls180.v:5967$1312_Y
   end
-  attribute \src "ls180.v:5868.64-5868.95"
-  cell $not $not$ls180.v:5868$1250
+  attribute \src "ls180.v:5970.64-5970.95"
+  cell $not $not$ls180.v:5970$1319
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5868$1250_Y
+    connect \Y $not$ls180.v:5970$1319_Y
   end
-  attribute \src "ls180.v:5871.64-5871.95"
-  cell $not $not$ls180.v:5871$1257
+  attribute \src "ls180.v:5973.64-5973.95"
+  cell $not $not$ls180.v:5973$1326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5871$1257_Y
+    connect \Y $not$ls180.v:5973$1326_Y
   end
-  attribute \src "ls180.v:5874.64-5874.95"
-  cell $not $not$ls180.v:5874$1264
+  attribute \src "ls180.v:5976.64-5976.95"
+  cell $not $not$ls180.v:5976$1333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface3_bank_bus_we
-    connect \Y $not$ls180.v:5874$1264_Y
+    connect \Y $not$ls180.v:5976$1333_Y
   end
-  attribute \src "ls180.v:5887.64-5887.95"
-  cell $not $not$ls180.v:5887$1272
+  attribute \src "ls180.v:5989.64-5989.95"
+  cell $not $not$ls180.v:5989$1341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5887$1272_Y
+    connect \Y $not$ls180.v:5989$1341_Y
   end
-  attribute \src "ls180.v:5890.63-5890.94"
-  cell $not $not$ls180.v:5890$1279
+  attribute \src "ls180.v:5992.63-5992.94"
+  cell $not $not$ls180.v:5992$1348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5890$1279_Y
+    connect \Y $not$ls180.v:5992$1348_Y
   end
-  attribute \src "ls180.v:5893.63-5893.94"
-  cell $not $not$ls180.v:5893$1286
+  attribute \src "ls180.v:5995.63-5995.94"
+  cell $not $not$ls180.v:5995$1355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5893$1286_Y
+    connect \Y $not$ls180.v:5995$1355_Y
   end
-  attribute \src "ls180.v:5896.63-5896.94"
-  cell $not $not$ls180.v:5896$1293
+  attribute \src "ls180.v:5998.63-5998.94"
+  cell $not $not$ls180.v:5998$1362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5896$1293_Y
+    connect \Y $not$ls180.v:5998$1362_Y
   end
-  attribute \src "ls180.v:5899.63-5899.94"
-  cell $not $not$ls180.v:5899$1300
+  attribute \src "ls180.v:6001.63-6001.94"
+  cell $not $not$ls180.v:6001$1369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5899$1300_Y
+    connect \Y $not$ls180.v:6001$1369_Y
   end
-  attribute \src "ls180.v:5902.64-5902.95"
-  cell $not $not$ls180.v:5902$1307
+  attribute \src "ls180.v:6004.64-6004.95"
+  cell $not $not$ls180.v:6004$1376
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5902$1307_Y
+    connect \Y $not$ls180.v:6004$1376_Y
   end
-  attribute \src "ls180.v:5905.64-5905.95"
-  cell $not $not$ls180.v:5905$1314
+  attribute \src "ls180.v:6007.64-6007.95"
+  cell $not $not$ls180.v:6007$1383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5905$1314_Y
+    connect \Y $not$ls180.v:6007$1383_Y
   end
-  attribute \src "ls180.v:5908.64-5908.95"
-  cell $not $not$ls180.v:5908$1321
+  attribute \src "ls180.v:6010.64-6010.95"
+  cell $not $not$ls180.v:6010$1390
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5908$1321_Y
+    connect \Y $not$ls180.v:6010$1390_Y
   end
-  attribute \src "ls180.v:5911.64-5911.95"
-  cell $not $not$ls180.v:5911$1328
+  attribute \src "ls180.v:6013.64-6013.95"
+  cell $not $not$ls180.v:6013$1397
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface4_bank_bus_we
-    connect \Y $not$ls180.v:5911$1328_Y
+    connect \Y $not$ls180.v:6013$1397_Y
   end
-  attribute \src "ls180.v:5924.66-5924.97"
-  cell $not $not$ls180.v:5924$1336
+  attribute \src "ls180.v:6026.66-6026.97"
+  cell $not $not$ls180.v:6026$1405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5924$1336_Y
+    connect \Y $not$ls180.v:6026$1405_Y
   end
-  attribute \src "ls180.v:5927.66-5927.97"
-  cell $not $not$ls180.v:5927$1343
+  attribute \src "ls180.v:6029.66-6029.97"
+  cell $not $not$ls180.v:6029$1412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5927$1343_Y
+    connect \Y $not$ls180.v:6029$1412_Y
   end
-  attribute \src "ls180.v:5930.66-5930.97"
-  cell $not $not$ls180.v:5930$1350
+  attribute \src "ls180.v:6032.66-6032.97"
+  cell $not $not$ls180.v:6032$1419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5930$1350_Y
+    connect \Y $not$ls180.v:6032$1419_Y
   end
-  attribute \src "ls180.v:5933.66-5933.97"
-  cell $not $not$ls180.v:5933$1357
+  attribute \src "ls180.v:6035.66-6035.97"
+  cell $not $not$ls180.v:6035$1426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5933$1357_Y
+    connect \Y $not$ls180.v:6035$1426_Y
   end
-  attribute \src "ls180.v:5936.66-5936.97"
-  cell $not $not$ls180.v:5936$1364
+  attribute \src "ls180.v:6038.66-6038.97"
+  cell $not $not$ls180.v:6038$1433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5936$1364_Y
+    connect \Y $not$ls180.v:6038$1433_Y
   end
-  attribute \src "ls180.v:5939.66-5939.97"
-  cell $not $not$ls180.v:5939$1371
+  attribute \src "ls180.v:6041.66-6041.97"
+  cell $not $not$ls180.v:6041$1440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5939$1371_Y
+    connect \Y $not$ls180.v:6041$1440_Y
   end
-  attribute \src "ls180.v:5942.66-5942.97"
-  cell $not $not$ls180.v:5942$1378
+  attribute \src "ls180.v:6044.66-6044.97"
+  cell $not $not$ls180.v:6044$1447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5942$1378_Y
+    connect \Y $not$ls180.v:6044$1447_Y
   end
-  attribute \src "ls180.v:5945.66-5945.97"
-  cell $not $not$ls180.v:5945$1385
+  attribute \src "ls180.v:6047.66-6047.97"
+  cell $not $not$ls180.v:6047$1454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5945$1385_Y
+    connect \Y $not$ls180.v:6047$1454_Y
   end
-  attribute \src "ls180.v:5948.68-5948.99"
-  cell $not $not$ls180.v:5948$1392
+  attribute \src "ls180.v:6050.68-6050.99"
+  cell $not $not$ls180.v:6050$1461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5948$1392_Y
+    connect \Y $not$ls180.v:6050$1461_Y
   end
-  attribute \src "ls180.v:5951.68-5951.99"
-  cell $not $not$ls180.v:5951$1399
+  attribute \src "ls180.v:6053.68-6053.99"
+  cell $not $not$ls180.v:6053$1468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5951$1399_Y
+    connect \Y $not$ls180.v:6053$1468_Y
   end
-  attribute \src "ls180.v:5954.68-5954.99"
-  cell $not $not$ls180.v:5954$1406
+  attribute \src "ls180.v:6056.68-6056.99"
+  cell $not $not$ls180.v:6056$1475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5954$1406_Y
+    connect \Y $not$ls180.v:6056$1475_Y
   end
-  attribute \src "ls180.v:5957.68-5957.99"
-  cell $not $not$ls180.v:5957$1413
+  attribute \src "ls180.v:6059.68-6059.99"
+  cell $not $not$ls180.v:6059$1482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5957$1413_Y
+    connect \Y $not$ls180.v:6059$1482_Y
   end
-  attribute \src "ls180.v:5960.68-5960.99"
-  cell $not $not$ls180.v:5960$1420
+  attribute \src "ls180.v:6062.68-6062.99"
+  cell $not $not$ls180.v:6062$1489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5960$1420_Y
+    connect \Y $not$ls180.v:6062$1489_Y
   end
-  attribute \src "ls180.v:5963.65-5963.96"
-  cell $not $not$ls180.v:5963$1427
+  attribute \src "ls180.v:6065.65-6065.96"
+  cell $not $not$ls180.v:6065$1496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5963$1427_Y
+    connect \Y $not$ls180.v:6065$1496_Y
   end
-  attribute \src "ls180.v:5966.66-5966.97"
-  cell $not $not$ls180.v:5966$1434
+  attribute \src "ls180.v:6068.66-6068.97"
+  cell $not $not$ls180.v:6068$1503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface5_bank_bus_we
-    connect \Y $not$ls180.v:5966$1434_Y
+    connect \Y $not$ls180.v:6068$1503_Y
   end
-  attribute \src "ls180.v:5986.70-5986.101"
-  cell $not $not$ls180.v:5986$1442
+  attribute \src "ls180.v:6088.70-6088.101"
+  cell $not $not$ls180.v:6088$1511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:5986$1442_Y
+    connect \Y $not$ls180.v:6088$1511_Y
   end
-  attribute \src "ls180.v:5989.70-5989.101"
-  cell $not $not$ls180.v:5989$1449
+  attribute \src "ls180.v:6091.70-6091.101"
+  cell $not $not$ls180.v:6091$1518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:5989$1449_Y
+    connect \Y $not$ls180.v:6091$1518_Y
   end
-  attribute \src "ls180.v:5992.70-5992.101"
-  cell $not $not$ls180.v:5992$1456
+  attribute \src "ls180.v:6094.70-6094.101"
+  cell $not $not$ls180.v:6094$1525
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:5992$1456_Y
+    connect \Y $not$ls180.v:6094$1525_Y
   end
-  attribute \src "ls180.v:5995.70-5995.101"
-  cell $not $not$ls180.v:5995$1463
+  attribute \src "ls180.v:6097.70-6097.101"
+  cell $not $not$ls180.v:6097$1532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:5995$1463_Y
+    connect \Y $not$ls180.v:6097$1532_Y
   end
-  attribute \src "ls180.v:5998.69-5998.100"
-  cell $not $not$ls180.v:5998$1470
+  attribute \src "ls180.v:6100.69-6100.100"
+  cell $not $not$ls180.v:6100$1539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:5998$1470_Y
+    connect \Y $not$ls180.v:6100$1539_Y
   end
-  attribute \src "ls180.v:6001.69-6001.100"
-  cell $not $not$ls180.v:6001$1477
+  attribute \src "ls180.v:6103.69-6103.100"
+  cell $not $not$ls180.v:6103$1546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6001$1477_Y
+    connect \Y $not$ls180.v:6103$1546_Y
   end
-  attribute \src "ls180.v:6004.69-6004.100"
-  cell $not $not$ls180.v:6004$1484
+  attribute \src "ls180.v:6106.69-6106.100"
+  cell $not $not$ls180.v:6106$1553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6004$1484_Y
+    connect \Y $not$ls180.v:6106$1553_Y
   end
-  attribute \src "ls180.v:6007.69-6007.100"
-  cell $not $not$ls180.v:6007$1491
+  attribute \src "ls180.v:6109.69-6109.100"
+  cell $not $not$ls180.v:6109$1560
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6007$1491_Y
+    connect \Y $not$ls180.v:6109$1560_Y
   end
-  attribute \src "ls180.v:6010.60-6010.91"
-  cell $not $not$ls180.v:6010$1498
+  attribute \src "ls180.v:6112.60-6112.91"
+  cell $not $not$ls180.v:6112$1567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6010$1498_Y
+    connect \Y $not$ls180.v:6112$1567_Y
   end
-  attribute \src "ls180.v:6013.71-6013.102"
-  cell $not $not$ls180.v:6013$1505
+  attribute \src "ls180.v:6115.71-6115.102"
+  cell $not $not$ls180.v:6115$1574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6013$1505_Y
+    connect \Y $not$ls180.v:6115$1574_Y
   end
-  attribute \src "ls180.v:6016.71-6016.102"
-  cell $not $not$ls180.v:6016$1512
+  attribute \src "ls180.v:6118.71-6118.102"
+  cell $not $not$ls180.v:6118$1581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6016$1512_Y
+    connect \Y $not$ls180.v:6118$1581_Y
   end
-  attribute \src "ls180.v:6019.71-6019.102"
-  cell $not $not$ls180.v:6019$1519
+  attribute \src "ls180.v:6121.71-6121.102"
+  cell $not $not$ls180.v:6121$1588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6019$1519_Y
+    connect \Y $not$ls180.v:6121$1588_Y
   end
-  attribute \src "ls180.v:6022.71-6022.102"
-  cell $not $not$ls180.v:6022$1526
+  attribute \src "ls180.v:6124.71-6124.102"
+  cell $not $not$ls180.v:6124$1595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6022$1526_Y
+    connect \Y $not$ls180.v:6124$1595_Y
   end
-  attribute \src "ls180.v:6025.71-6025.102"
-  cell $not $not$ls180.v:6025$1533
+  attribute \src "ls180.v:6127.71-6127.102"
+  cell $not $not$ls180.v:6127$1602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6025$1533_Y
+    connect \Y $not$ls180.v:6127$1602_Y
   end
-  attribute \src "ls180.v:6028.71-6028.102"
-  cell $not $not$ls180.v:6028$1540
+  attribute \src "ls180.v:6130.71-6130.102"
+  cell $not $not$ls180.v:6130$1609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6028$1540_Y
+    connect \Y $not$ls180.v:6130$1609_Y
   end
-  attribute \src "ls180.v:6031.70-6031.101"
-  cell $not $not$ls180.v:6031$1547
+  attribute \src "ls180.v:6133.70-6133.101"
+  cell $not $not$ls180.v:6133$1616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6031$1547_Y
+    connect \Y $not$ls180.v:6133$1616_Y
   end
-  attribute \src "ls180.v:6034.70-6034.101"
-  cell $not $not$ls180.v:6034$1554
+  attribute \src "ls180.v:6136.70-6136.101"
+  cell $not $not$ls180.v:6136$1623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6034$1554_Y
+    connect \Y $not$ls180.v:6136$1623_Y
   end
-  attribute \src "ls180.v:6037.70-6037.101"
-  cell $not $not$ls180.v:6037$1561
+  attribute \src "ls180.v:6139.70-6139.101"
+  cell $not $not$ls180.v:6139$1630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6037$1561_Y
+    connect \Y $not$ls180.v:6139$1630_Y
   end
-  attribute \src "ls180.v:6040.70-6040.101"
-  cell $not $not$ls180.v:6040$1568
+  attribute \src "ls180.v:6142.70-6142.101"
+  cell $not $not$ls180.v:6142$1637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6040$1568_Y
+    connect \Y $not$ls180.v:6142$1637_Y
   end
-  attribute \src "ls180.v:6043.70-6043.101"
-  cell $not $not$ls180.v:6043$1575
+  attribute \src "ls180.v:6145.70-6145.101"
+  cell $not $not$ls180.v:6145$1644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6043$1575_Y
+    connect \Y $not$ls180.v:6145$1644_Y
   end
-  attribute \src "ls180.v:6046.70-6046.101"
-  cell $not $not$ls180.v:6046$1582
+  attribute \src "ls180.v:6148.70-6148.101"
+  cell $not $not$ls180.v:6148$1651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6046$1582_Y
+    connect \Y $not$ls180.v:6148$1651_Y
   end
-  attribute \src "ls180.v:6049.70-6049.101"
-  cell $not $not$ls180.v:6049$1589
+  attribute \src "ls180.v:6151.70-6151.101"
+  cell $not $not$ls180.v:6151$1658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6049$1589_Y
+    connect \Y $not$ls180.v:6151$1658_Y
   end
-  attribute \src "ls180.v:6052.70-6052.101"
-  cell $not $not$ls180.v:6052$1596
+  attribute \src "ls180.v:6154.70-6154.101"
+  cell $not $not$ls180.v:6154$1665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6052$1596_Y
+    connect \Y $not$ls180.v:6154$1665_Y
   end
-  attribute \src "ls180.v:6055.70-6055.101"
-  cell $not $not$ls180.v:6055$1603
+  attribute \src "ls180.v:6157.70-6157.101"
+  cell $not $not$ls180.v:6157$1672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6055$1603_Y
+    connect \Y $not$ls180.v:6157$1672_Y
   end
-  attribute \src "ls180.v:6058.70-6058.101"
-  cell $not $not$ls180.v:6058$1610
+  attribute \src "ls180.v:6160.70-6160.101"
+  cell $not $not$ls180.v:6160$1679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6058$1610_Y
+    connect \Y $not$ls180.v:6160$1679_Y
   end
-  attribute \src "ls180.v:6061.66-6061.97"
-  cell $not $not$ls180.v:6061$1617
+  attribute \src "ls180.v:6163.66-6163.97"
+  cell $not $not$ls180.v:6163$1686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6061$1617_Y
+    connect \Y $not$ls180.v:6163$1686_Y
   end
-  attribute \src "ls180.v:6064.67-6064.98"
-  cell $not $not$ls180.v:6064$1624
+  attribute \src "ls180.v:6166.67-6166.98"
+  cell $not $not$ls180.v:6166$1693
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6064$1624_Y
+    connect \Y $not$ls180.v:6166$1693_Y
   end
-  attribute \src "ls180.v:6067.70-6067.101"
-  cell $not $not$ls180.v:6067$1631
+  attribute \src "ls180.v:6169.70-6169.101"
+  cell $not $not$ls180.v:6169$1700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6067$1631_Y
+    connect \Y $not$ls180.v:6169$1700_Y
   end
-  attribute \src "ls180.v:6070.70-6070.101"
-  cell $not $not$ls180.v:6070$1638
+  attribute \src "ls180.v:6172.70-6172.101"
+  cell $not $not$ls180.v:6172$1707
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6070$1638_Y
+    connect \Y $not$ls180.v:6172$1707_Y
   end
-  attribute \src "ls180.v:6073.69-6073.100"
-  cell $not $not$ls180.v:6073$1645
+  attribute \src "ls180.v:6175.69-6175.100"
+  cell $not $not$ls180.v:6175$1714
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6073$1645_Y
+    connect \Y $not$ls180.v:6175$1714_Y
   end
-  attribute \src "ls180.v:6076.69-6076.100"
-  cell $not $not$ls180.v:6076$1652
+  attribute \src "ls180.v:6178.69-6178.100"
+  cell $not $not$ls180.v:6178$1721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6076$1652_Y
+    connect \Y $not$ls180.v:6178$1721_Y
   end
-  attribute \src "ls180.v:6079.69-6079.100"
-  cell $not $not$ls180.v:6079$1659
+  attribute \src "ls180.v:6181.69-6181.100"
+  cell $not $not$ls180.v:6181$1728
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6079$1659_Y
+    connect \Y $not$ls180.v:6181$1728_Y
   end
-  attribute \src "ls180.v:6082.69-6082.100"
-  cell $not $not$ls180.v:6082$1666
+  attribute \src "ls180.v:6184.69-6184.100"
+  cell $not $not$ls180.v:6184$1735
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface6_bank_bus_we
-    connect \Y $not$ls180.v:6082$1666_Y
+    connect \Y $not$ls180.v:6184$1735_Y
   end
-  attribute \src "ls180.v:6121.66-6121.97"
-  cell $not $not$ls180.v:6121$1674
+  attribute \src "ls180.v:6223.66-6223.97"
+  cell $not $not$ls180.v:6223$1743
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6121$1674_Y
+    connect \Y $not$ls180.v:6223$1743_Y
   end
-  attribute \src "ls180.v:6124.66-6124.97"
-  cell $not $not$ls180.v:6124$1681
+  attribute \src "ls180.v:6226.66-6226.97"
+  cell $not $not$ls180.v:6226$1750
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6124$1681_Y
+    connect \Y $not$ls180.v:6226$1750_Y
   end
-  attribute \src "ls180.v:6127.66-6127.97"
-  cell $not $not$ls180.v:6127$1688
+  attribute \src "ls180.v:6229.66-6229.97"
+  cell $not $not$ls180.v:6229$1757
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6127$1688_Y
+    connect \Y $not$ls180.v:6229$1757_Y
   end
-  attribute \src "ls180.v:6130.66-6130.97"
-  cell $not $not$ls180.v:6130$1695
+  attribute \src "ls180.v:6232.66-6232.97"
+  cell $not $not$ls180.v:6232$1764
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6130$1695_Y
+    connect \Y $not$ls180.v:6232$1764_Y
   end
-  attribute \src "ls180.v:6133.66-6133.97"
-  cell $not $not$ls180.v:6133$1702
+  attribute \src "ls180.v:6235.66-6235.97"
+  cell $not $not$ls180.v:6235$1771
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6133$1702_Y
+    connect \Y $not$ls180.v:6235$1771_Y
   end
-  attribute \src "ls180.v:6136.66-6136.97"
-  cell $not $not$ls180.v:6136$1709
+  attribute \src "ls180.v:6238.66-6238.97"
+  cell $not $not$ls180.v:6238$1778
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6136$1709_Y
+    connect \Y $not$ls180.v:6238$1778_Y
   end
-  attribute \src "ls180.v:6139.66-6139.97"
-  cell $not $not$ls180.v:6139$1716
+  attribute \src "ls180.v:6241.66-6241.97"
+  cell $not $not$ls180.v:6241$1785
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6139$1716_Y
+    connect \Y $not$ls180.v:6241$1785_Y
   end
-  attribute \src "ls180.v:6142.66-6142.97"
-  cell $not $not$ls180.v:6142$1723
+  attribute \src "ls180.v:6244.66-6244.97"
+  cell $not $not$ls180.v:6244$1792
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6142$1723_Y
+    connect \Y $not$ls180.v:6244$1792_Y
   end
-  attribute \src "ls180.v:6145.68-6145.99"
-  cell $not $not$ls180.v:6145$1730
+  attribute \src "ls180.v:6247.68-6247.99"
+  cell $not $not$ls180.v:6247$1799
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6145$1730_Y
+    connect \Y $not$ls180.v:6247$1799_Y
   end
-  attribute \src "ls180.v:6148.68-6148.99"
-  cell $not $not$ls180.v:6148$1737
+  attribute \src "ls180.v:6250.68-6250.99"
+  cell $not $not$ls180.v:6250$1806
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6148$1737_Y
+    connect \Y $not$ls180.v:6250$1806_Y
   end
-  attribute \src "ls180.v:6151.68-6151.99"
-  cell $not $not$ls180.v:6151$1744
+  attribute \src "ls180.v:6253.68-6253.99"
+  cell $not $not$ls180.v:6253$1813
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6151$1744_Y
+    connect \Y $not$ls180.v:6253$1813_Y
   end
-  attribute \src "ls180.v:6154.68-6154.99"
-  cell $not $not$ls180.v:6154$1751
+  attribute \src "ls180.v:6256.68-6256.99"
+  cell $not $not$ls180.v:6256$1820
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6154$1751_Y
+    connect \Y $not$ls180.v:6256$1820_Y
   end
-  attribute \src "ls180.v:6157.68-6157.99"
-  cell $not $not$ls180.v:6157$1758
+  attribute \src "ls180.v:6259.68-6259.99"
+  cell $not $not$ls180.v:6259$1827
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6157$1758_Y
+    connect \Y $not$ls180.v:6259$1827_Y
   end
-  attribute \src "ls180.v:6160.65-6160.96"
-  cell $not $not$ls180.v:6160$1765
+  attribute \src "ls180.v:6262.65-6262.96"
+  cell $not $not$ls180.v:6262$1834
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6160$1765_Y
+    connect \Y $not$ls180.v:6262$1834_Y
   end
-  attribute \src "ls180.v:6163.66-6163.97"
-  cell $not $not$ls180.v:6163$1772
+  attribute \src "ls180.v:6265.66-6265.97"
+  cell $not $not$ls180.v:6265$1841
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6163$1772_Y
+    connect \Y $not$ls180.v:6265$1841_Y
   end
-  attribute \src "ls180.v:6166.68-6166.99"
-  cell $not $not$ls180.v:6166$1779
+  attribute \src "ls180.v:6268.68-6268.99"
+  cell $not $not$ls180.v:6268$1848
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6166$1779_Y
+    connect \Y $not$ls180.v:6268$1848_Y
   end
-  attribute \src "ls180.v:6169.68-6169.99"
-  cell $not $not$ls180.v:6169$1786
+  attribute \src "ls180.v:6271.68-6271.99"
+  cell $not $not$ls180.v:6271$1855
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6169$1786_Y
+    connect \Y $not$ls180.v:6271$1855_Y
   end
-  attribute \src "ls180.v:6172.68-6172.99"
-  cell $not $not$ls180.v:6172$1793
+  attribute \src "ls180.v:6274.68-6274.99"
+  cell $not $not$ls180.v:6274$1862
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6172$1793_Y
+    connect \Y $not$ls180.v:6274$1862_Y
   end
-  attribute \src "ls180.v:6175.68-6175.99"
-  cell $not $not$ls180.v:6175$1800
+  attribute \src "ls180.v:6277.68-6277.99"
+  cell $not $not$ls180.v:6277$1869
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface7_bank_bus_we
-    connect \Y $not$ls180.v:6175$1800_Y
+    connect \Y $not$ls180.v:6277$1869_Y
   end
-  attribute \src "ls180.v:6200.68-6200.99"
-  cell $not $not$ls180.v:6200$1808
+  attribute \src "ls180.v:6302.68-6302.99"
+  cell $not $not$ls180.v:6302$1877
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_we
-    connect \Y $not$ls180.v:6200$1808_Y
+    connect \Y $not$ls180.v:6302$1877_Y
   end
-  attribute \src "ls180.v:6203.73-6203.104"
-  cell $not $not$ls180.v:6203$1815
+  attribute \src "ls180.v:6305.73-6305.104"
+  cell $not $not$ls180.v:6305$1884
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_we
-    connect \Y $not$ls180.v:6203$1815_Y
+    connect \Y $not$ls180.v:6305$1884_Y
   end
-  attribute \src "ls180.v:6206.73-6206.104"
-  cell $not $not$ls180.v:6206$1822
+  attribute \src "ls180.v:6308.73-6308.104"
+  cell $not $not$ls180.v:6308$1891
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_we
-    connect \Y $not$ls180.v:6206$1822_Y
+    connect \Y $not$ls180.v:6308$1891_Y
   end
-  attribute \src "ls180.v:6209.66-6209.97"
-  cell $not $not$ls180.v:6209$1829
+  attribute \src "ls180.v:6311.66-6311.97"
+  cell $not $not$ls180.v:6311$1898
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface8_bank_bus_we
-    connect \Y $not$ls180.v:6209$1829_Y
+    connect \Y $not$ls180.v:6311$1898_Y
   end
-  attribute \src "ls180.v:6217.70-6217.101"
-  cell $not $not$ls180.v:6217$1837
+  attribute \src "ls180.v:6319.70-6319.101"
+  cell $not $not$ls180.v:6319$1906
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6217$1837_Y
+    connect \Y $not$ls180.v:6319$1906_Y
   end
-  attribute \src "ls180.v:6220.74-6220.105"
-  cell $not $not$ls180.v:6220$1844
+  attribute \src "ls180.v:6322.74-6322.105"
+  cell $not $not$ls180.v:6322$1913
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6220$1844_Y
+    connect \Y $not$ls180.v:6322$1913_Y
   end
-  attribute \src "ls180.v:6223.64-6223.95"
-  cell $not $not$ls180.v:6223$1851
+  attribute \src "ls180.v:6325.64-6325.95"
+  cell $not $not$ls180.v:6325$1920
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6223$1851_Y
+    connect \Y $not$ls180.v:6325$1920_Y
   end
-  attribute \src "ls180.v:6226.74-6226.105"
-  cell $not $not$ls180.v:6226$1858
+  attribute \src "ls180.v:6328.74-6328.105"
+  cell $not $not$ls180.v:6328$1927
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6226$1858_Y
+    connect \Y $not$ls180.v:6328$1927_Y
   end
-  attribute \src "ls180.v:6229.74-6229.105"
-  cell $not $not$ls180.v:6229$1865
+  attribute \src "ls180.v:6331.74-6331.105"
+  cell $not $not$ls180.v:6331$1934
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6229$1865_Y
+    connect \Y $not$ls180.v:6331$1934_Y
   end
-  attribute \src "ls180.v:6232.75-6232.106"
-  cell $not $not$ls180.v:6232$1872
+  attribute \src "ls180.v:6334.75-6334.106"
+  cell $not $not$ls180.v:6334$1941
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6232$1872_Y
+    connect \Y $not$ls180.v:6334$1941_Y
   end
-  attribute \src "ls180.v:6235.73-6235.104"
-  cell $not $not$ls180.v:6235$1879
+  attribute \src "ls180.v:6337.73-6337.104"
+  cell $not $not$ls180.v:6337$1948
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6235$1879_Y
+    connect \Y $not$ls180.v:6337$1948_Y
   end
-  attribute \src "ls180.v:6238.73-6238.104"
-  cell $not $not$ls180.v:6238$1886
+  attribute \src "ls180.v:6340.73-6340.104"
+  cell $not $not$ls180.v:6340$1955
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6238$1886_Y
+    connect \Y $not$ls180.v:6340$1955_Y
   end
-  attribute \src "ls180.v:6241.73-6241.104"
-  cell $not $not$ls180.v:6241$1893
+  attribute \src "ls180.v:6343.73-6343.104"
+  cell $not $not$ls180.v:6343$1962
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6241$1893_Y
+    connect \Y $not$ls180.v:6343$1962_Y
   end
-  attribute \src "ls180.v:6244.73-6244.104"
-  cell $not $not$ls180.v:6244$1900
+  attribute \src "ls180.v:6346.73-6346.104"
+  cell $not $not$ls180.v:6346$1969
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface9_bank_bus_we
-    connect \Y $not$ls180.v:6244$1900_Y
+    connect \Y $not$ls180.v:6346$1969_Y
   end
-  attribute \src "ls180.v:6262.67-6262.99"
-  cell $not $not$ls180.v:6262$1908
+  attribute \src "ls180.v:6364.67-6364.99"
+  cell $not $not$ls180.v:6364$1977
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6262$1908_Y
+    connect \Y $not$ls180.v:6364$1977_Y
   end
-  attribute \src "ls180.v:6265.67-6265.99"
-  cell $not $not$ls180.v:6265$1915
+  attribute \src "ls180.v:6367.67-6367.99"
+  cell $not $not$ls180.v:6367$1984
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6265$1915_Y
+    connect \Y $not$ls180.v:6367$1984_Y
   end
-  attribute \src "ls180.v:6268.65-6268.97"
-  cell $not $not$ls180.v:6268$1922
+  attribute \src "ls180.v:6370.65-6370.97"
+  cell $not $not$ls180.v:6370$1991
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6268$1922_Y
+    connect \Y $not$ls180.v:6370$1991_Y
   end
-  attribute \src "ls180.v:6271.64-6271.96"
-  cell $not $not$ls180.v:6271$1929
+  attribute \src "ls180.v:6373.64-6373.96"
+  cell $not $not$ls180.v:6373$1998
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6271$1929_Y
+    connect \Y $not$ls180.v:6373$1998_Y
   end
-  attribute \src "ls180.v:6274.63-6274.95"
-  cell $not $not$ls180.v:6274$1936
+  attribute \src "ls180.v:6376.63-6376.95"
+  cell $not $not$ls180.v:6376$2005
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6274$1936_Y
+    connect \Y $not$ls180.v:6376$2005_Y
   end
-  attribute \src "ls180.v:6277.62-6277.94"
-  cell $not $not$ls180.v:6277$1943
+  attribute \src "ls180.v:6379.62-6379.94"
+  cell $not $not$ls180.v:6379$2012
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6277$1943_Y
+    connect \Y $not$ls180.v:6379$2012_Y
   end
-  attribute \src "ls180.v:6280.68-6280.100"
-  cell $not $not$ls180.v:6280$1950
+  attribute \src "ls180.v:6382.68-6382.100"
+  cell $not $not$ls180.v:6382$2019
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface10_bank_bus_we
-    connect \Y $not$ls180.v:6280$1950_Y
+    connect \Y $not$ls180.v:6382$2019_Y
   end
-  attribute \src "ls180.v:6302.67-6302.99"
-  cell $not $not$ls180.v:6302$1959
+  attribute \src "ls180.v:6404.67-6404.99"
+  cell $not $not$ls180.v:6404$2028
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6302$1959_Y
+    connect \Y $not$ls180.v:6404$2028_Y
   end
-  attribute \src "ls180.v:6305.67-6305.99"
-  cell $not $not$ls180.v:6305$1966
+  attribute \src "ls180.v:6407.67-6407.99"
+  cell $not $not$ls180.v:6407$2035
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6305$1966_Y
+    connect \Y $not$ls180.v:6407$2035_Y
   end
-  attribute \src "ls180.v:6308.65-6308.97"
-  cell $not $not$ls180.v:6308$1973
+  attribute \src "ls180.v:6410.65-6410.97"
+  cell $not $not$ls180.v:6410$2042
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6308$1973_Y
+    connect \Y $not$ls180.v:6410$2042_Y
   end
-  attribute \src "ls180.v:6311.64-6311.96"
-  cell $not $not$ls180.v:6311$1980
+  attribute \src "ls180.v:6413.64-6413.96"
+  cell $not $not$ls180.v:6413$2049
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6311$1980_Y
+    connect \Y $not$ls180.v:6413$2049_Y
   end
-  attribute \src "ls180.v:6314.63-6314.95"
-  cell $not $not$ls180.v:6314$1987
+  attribute \src "ls180.v:6416.63-6416.95"
+  cell $not $not$ls180.v:6416$2056
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6314$1987_Y
+    connect \Y $not$ls180.v:6416$2056_Y
   end
-  attribute \src "ls180.v:6317.62-6317.94"
-  cell $not $not$ls180.v:6317$1994
+  attribute \src "ls180.v:6419.62-6419.94"
+  cell $not $not$ls180.v:6419$2063
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6317$1994_Y
+    connect \Y $not$ls180.v:6419$2063_Y
   end
-  attribute \src "ls180.v:6320.68-6320.100"
-  cell $not $not$ls180.v:6320$2001
+  attribute \src "ls180.v:6422.68-6422.100"
+  cell $not $not$ls180.v:6422$2070
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6320$2001_Y
+    connect \Y $not$ls180.v:6422$2070_Y
   end
-  attribute \src "ls180.v:6323.71-6323.103"
-  cell $not $not$ls180.v:6323$2008
+  attribute \src "ls180.v:6425.71-6425.103"
+  cell $not $not$ls180.v:6425$2077
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6323$2008_Y
+    connect \Y $not$ls180.v:6425$2077_Y
   end
-  attribute \src "ls180.v:6326.71-6326.103"
-  cell $not $not$ls180.v:6326$2015
+  attribute \src "ls180.v:6428.71-6428.103"
+  cell $not $not$ls180.v:6428$2084
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface11_bank_bus_we
-    connect \Y $not$ls180.v:6326$2015_Y
+    connect \Y $not$ls180.v:6428$2084_Y
   end
-  attribute \src "ls180.v:6350.64-6350.96"
-  cell $not $not$ls180.v:6350$2024
+  attribute \src "ls180.v:6452.64-6452.96"
+  cell $not $not$ls180.v:6452$2093
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6350$2024_Y
+    connect \Y $not$ls180.v:6452$2093_Y
   end
-  attribute \src "ls180.v:6353.64-6353.96"
-  cell $not $not$ls180.v:6353$2031
+  attribute \src "ls180.v:6455.64-6455.96"
+  cell $not $not$ls180.v:6455$2100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6353$2031_Y
+    connect \Y $not$ls180.v:6455$2100_Y
   end
-  attribute \src "ls180.v:6356.64-6356.96"
-  cell $not $not$ls180.v:6356$2038
+  attribute \src "ls180.v:6458.64-6458.96"
+  cell $not $not$ls180.v:6458$2107
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6356$2038_Y
+    connect \Y $not$ls180.v:6458$2107_Y
   end
-  attribute \src "ls180.v:6359.64-6359.96"
-  cell $not $not$ls180.v:6359$2045
+  attribute \src "ls180.v:6461.64-6461.96"
+  cell $not $not$ls180.v:6461$2114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6359$2045_Y
+    connect \Y $not$ls180.v:6461$2114_Y
   end
-  attribute \src "ls180.v:6362.66-6362.98"
-  cell $not $not$ls180.v:6362$2052
+  attribute \src "ls180.v:6464.66-6464.98"
+  cell $not $not$ls180.v:6464$2121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6362$2052_Y
+    connect \Y $not$ls180.v:6464$2121_Y
   end
-  attribute \src "ls180.v:6365.66-6365.98"
-  cell $not $not$ls180.v:6365$2059
+  attribute \src "ls180.v:6467.66-6467.98"
+  cell $not $not$ls180.v:6467$2128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6365$2059_Y
+    connect \Y $not$ls180.v:6467$2128_Y
   end
-  attribute \src "ls180.v:6368.66-6368.98"
-  cell $not $not$ls180.v:6368$2066
+  attribute \src "ls180.v:6470.66-6470.98"
+  cell $not $not$ls180.v:6470$2135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6368$2066_Y
+    connect \Y $not$ls180.v:6470$2135_Y
   end
-  attribute \src "ls180.v:6371.66-6371.98"
-  cell $not $not$ls180.v:6371$2073
+  attribute \src "ls180.v:6473.66-6473.98"
+  cell $not $not$ls180.v:6473$2142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6371$2073_Y
+    connect \Y $not$ls180.v:6473$2142_Y
   end
-  attribute \src "ls180.v:6374.62-6374.94"
-  cell $not $not$ls180.v:6374$2080
+  attribute \src "ls180.v:6476.62-6476.94"
+  cell $not $not$ls180.v:6476$2149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6374$2080_Y
+    connect \Y $not$ls180.v:6476$2149_Y
   end
-  attribute \src "ls180.v:6377.72-6377.104"
-  cell $not $not$ls180.v:6377$2087
+  attribute \src "ls180.v:6479.72-6479.104"
+  cell $not $not$ls180.v:6479$2156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6377$2087_Y
+    connect \Y $not$ls180.v:6479$2156_Y
   end
-  attribute \src "ls180.v:6380.65-6380.97"
-  cell $not $not$ls180.v:6380$2094
+  attribute \src "ls180.v:6482.65-6482.97"
+  cell $not $not$ls180.v:6482$2163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6380$2094_Y
+    connect \Y $not$ls180.v:6482$2163_Y
   end
-  attribute \src "ls180.v:6383.65-6383.97"
-  cell $not $not$ls180.v:6383$2101
+  attribute \src "ls180.v:6485.65-6485.97"
+  cell $not $not$ls180.v:6485$2170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6383$2101_Y
+    connect \Y $not$ls180.v:6485$2170_Y
   end
-  attribute \src "ls180.v:6386.65-6386.97"
-  cell $not $not$ls180.v:6386$2108
+  attribute \src "ls180.v:6488.65-6488.97"
+  cell $not $not$ls180.v:6488$2177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6386$2108_Y
+    connect \Y $not$ls180.v:6488$2177_Y
   end
-  attribute \src "ls180.v:6389.65-6389.97"
-  cell $not $not$ls180.v:6389$2115
+  attribute \src "ls180.v:6491.65-6491.97"
+  cell $not $not$ls180.v:6491$2184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6389$2115_Y
+    connect \Y $not$ls180.v:6491$2184_Y
   end
-  attribute \src "ls180.v:6392.77-6392.109"
-  cell $not $not$ls180.v:6392$2122
+  attribute \src "ls180.v:6494.77-6494.109"
+  cell $not $not$ls180.v:6494$2191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6392$2122_Y
+    connect \Y $not$ls180.v:6494$2191_Y
   end
-  attribute \src "ls180.v:6395.78-6395.110"
-  cell $not $not$ls180.v:6395$2129
+  attribute \src "ls180.v:6497.78-6497.110"
+  cell $not $not$ls180.v:6497$2198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6395$2129_Y
+    connect \Y $not$ls180.v:6497$2198_Y
   end
-  attribute \src "ls180.v:6398.69-6398.101"
-  cell $not $not$ls180.v:6398$2136
+  attribute \src "ls180.v:6500.69-6500.101"
+  cell $not $not$ls180.v:6500$2205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface12_bank_bus_we
-    connect \Y $not$ls180.v:6398$2136_Y
+    connect \Y $not$ls180.v:6500$2205_Y
   end
-  attribute \src "ls180.v:6418.55-6418.87"
-  cell $not $not$ls180.v:6418$2144
+  attribute \src "ls180.v:6520.55-6520.87"
+  cell $not $not$ls180.v:6520$2213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6418$2144_Y
+    connect \Y $not$ls180.v:6520$2213_Y
   end
-  attribute \src "ls180.v:6421.65-6421.97"
-  cell $not $not$ls180.v:6421$2151
+  attribute \src "ls180.v:6523.65-6523.97"
+  cell $not $not$ls180.v:6523$2220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6421$2151_Y
+    connect \Y $not$ls180.v:6523$2220_Y
   end
-  attribute \src "ls180.v:6424.66-6424.98"
-  cell $not $not$ls180.v:6424$2158
+  attribute \src "ls180.v:6526.66-6526.98"
+  cell $not $not$ls180.v:6526$2227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6424$2158_Y
+    connect \Y $not$ls180.v:6526$2227_Y
   end
-  attribute \src "ls180.v:6427.70-6427.102"
-  cell $not $not$ls180.v:6427$2165
+  attribute \src "ls180.v:6529.70-6529.102"
+  cell $not $not$ls180.v:6529$2234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6427$2165_Y
+    connect \Y $not$ls180.v:6529$2234_Y
   end
-  attribute \src "ls180.v:6430.71-6430.103"
-  cell $not $not$ls180.v:6430$2172
+  attribute \src "ls180.v:6532.71-6532.103"
+  cell $not $not$ls180.v:6532$2241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6430$2172_Y
+    connect \Y $not$ls180.v:6532$2241_Y
   end
-  attribute \src "ls180.v:6433.69-6433.101"
-  cell $not $not$ls180.v:6433$2179
+  attribute \src "ls180.v:6535.69-6535.101"
+  cell $not $not$ls180.v:6535$2248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6433$2179_Y
+    connect \Y $not$ls180.v:6535$2248_Y
   end
-  attribute \src "ls180.v:6436.66-6436.98"
-  cell $not $not$ls180.v:6436$2186
+  attribute \src "ls180.v:6538.66-6538.98"
+  cell $not $not$ls180.v:6538$2255
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6436$2186_Y
+    connect \Y $not$ls180.v:6538$2255_Y
   end
-  attribute \src "ls180.v:6439.65-6439.97"
-  cell $not $not$ls180.v:6439$2193
+  attribute \src "ls180.v:6541.65-6541.97"
+  cell $not $not$ls180.v:6541$2262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface13_bank_bus_we
-    connect \Y $not$ls180.v:6439$2193_Y
+    connect \Y $not$ls180.v:6541$2262_Y
   end
-  attribute \src "ls180.v:6452.71-6452.103"
-  cell $not $not$ls180.v:6452$2201
+  attribute \src "ls180.v:6554.71-6554.103"
+  cell $not $not$ls180.v:6554$2270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_we
-    connect \Y $not$ls180.v:6452$2201_Y
+    connect \Y $not$ls180.v:6554$2270_Y
   end
-  attribute \src "ls180.v:6455.71-6455.103"
-  cell $not $not$ls180.v:6455$2208
+  attribute \src "ls180.v:6557.71-6557.103"
+  cell $not $not$ls180.v:6557$2277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_we
-    connect \Y $not$ls180.v:6455$2208_Y
+    connect \Y $not$ls180.v:6557$2277_Y
   end
-  attribute \src "ls180.v:6458.71-6458.103"
-  cell $not $not$ls180.v:6458$2215
+  attribute \src "ls180.v:6560.71-6560.103"
+  cell $not $not$ls180.v:6560$2284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_we
-    connect \Y $not$ls180.v:6458$2215_Y
+    connect \Y $not$ls180.v:6560$2284_Y
   end
-  attribute \src "ls180.v:6461.71-6461.103"
-  cell $not $not$ls180.v:6461$2222
+  attribute \src "ls180.v:6563.71-6563.103"
+  cell $not $not$ls180.v:6563$2291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_interface14_bank_bus_we
-    connect \Y $not$ls180.v:6461$2222_Y
+    connect \Y $not$ls180.v:6563$2291_Y
   end
-  attribute \src "ls180.v:6842.86-6842.330"
-  cell $not $not$ls180.v:6842$2271
+  attribute \src "ls180.v:6944.86-6944.330"
+  cell $not $not$ls180.v:6944$2340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6842$2270_Y
-    connect \Y $not$ls180.v:6842$2271_Y
+    connect \A $or$ls180.v:6944$2339_Y
+    connect \Y $not$ls180.v:6944$2340_Y
   end
-  attribute \src "ls180.v:6866.86-6866.330"
-  cell $not $not$ls180.v:6866$2287
+  attribute \src "ls180.v:6968.86-6968.330"
+  cell $not $not$ls180.v:6968$2356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6866$2286_Y
-    connect \Y $not$ls180.v:6866$2287_Y
+    connect \A $or$ls180.v:6968$2355_Y
+    connect \Y $not$ls180.v:6968$2356_Y
   end
-  attribute \src "ls180.v:6890.86-6890.330"
-  cell $not $not$ls180.v:6890$2303
+  attribute \src "ls180.v:6992.86-6992.330"
+  cell $not $not$ls180.v:6992$2372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6890$2302_Y
-    connect \Y $not$ls180.v:6890$2303_Y
+    connect \A $or$ls180.v:6992$2371_Y
+    connect \Y $not$ls180.v:6992$2372_Y
   end
-  attribute \src "ls180.v:6914.86-6914.330"
-  cell $not $not$ls180.v:6914$2319
+  attribute \src "ls180.v:7016.86-7016.330"
+  cell $not $not$ls180.v:7016$2388
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6914$2318_Y
-    connect \Y $not$ls180.v:6914$2319_Y
+    connect \A $or$ls180.v:7016$2387_Y
+    connect \Y $not$ls180.v:7016$2388_Y
   end
-  attribute \src "ls180.v:7412.18-7412.42"
-  cell $not $not$ls180.v:7412$2372
+  attribute \src "ls180.v:7514.18-7514.42"
+  cell $not $not$ls180.v:7514$2441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_clocker_clk0
-    connect \Y $not$ls180.v:7412$2372_Y
+    connect \Y $not$ls180.v:7514$2441_Y
   end
-  attribute \src "ls180.v:7491.72-7491.101"
-  cell $not $not$ls180.v:7491$2405
+  attribute \src "ls180.v:7593.72-7593.101"
+  cell $not $not$ls180.v:7593$2474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_ack
-    connect \Y $not$ls180.v:7491$2405_Y
+    connect \Y $not$ls180.v:7593$2474_Y
   end
-  attribute \src "ls180.v:7510.8-7510.38"
-  cell $not $not$ls180.v:7510$2409
+  attribute \src "ls180.v:7612.8-7612.38"
+  cell $not $not$ls180.v:7612$2478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_zero_trigger
-    connect \Y $not$ls180.v:7510$2409_Y
+    connect \Y $not$ls180.v:7612$2478_Y
+  end
+  attribute \src "ls180.v:7616.70-7616.98"
+  cell $not $not$ls180.v:7616$2481
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface0_ram_bus_ack
+    connect \Y $not$ls180.v:7616$2481_Y
   end
-  attribute \src "ls180.v:7518.32-7518.55"
-  cell $not $not$ls180.v:7518$2411
+  attribute \src "ls180.v:7620.70-7620.98"
+  cell $not $not$ls180.v:7620$2484
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface1_ram_bus_ack
+    connect \Y $not$ls180.v:7620$2484_Y
+  end
+  attribute \src "ls180.v:7624.70-7624.98"
+  cell $not $not$ls180.v:7624$2487
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \main_interface2_ram_bus_ack
+    connect \Y $not$ls180.v:7624$2487_Y
+  end
+  attribute \src "ls180.v:7632.32-7632.55"
+  cell $not $not$ls180.v:7632$2489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_done0
-    connect \Y $not$ls180.v:7518$2411_Y
+    connect \Y $not$ls180.v:7632$2489_Y
   end
-  attribute \src "ls180.v:7588.136-7588.189"
-  cell $not $not$ls180.v:7588$2426
+  attribute \src "ls180.v:7702.136-7702.189"
+  cell $not $not$ls180.v:7702$2504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7588$2426_Y
+    connect \Y $not$ls180.v:7702$2504_Y
   end
-  attribute \src "ls180.v:7594.136-7594.189"
-  cell $not $not$ls180.v:7594$2431
+  attribute \src "ls180.v:7708.136-7708.189"
+  cell $not $not$ls180.v:7708$2509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7594$2431_Y
+    connect \Y $not$ls180.v:7708$2509_Y
   end
-  attribute \src "ls180.v:7595.8-7595.61"
-  cell $not $not$ls180.v:7595$2433
+  attribute \src "ls180.v:7709.8-7709.61"
+  cell $not $not$ls180.v:7709$2511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7595$2433_Y
+    connect \Y $not$ls180.v:7709$2511_Y
   end
-  attribute \src "ls180.v:7603.8-7603.56"
-  cell $not $not$ls180.v:7603$2436
+  attribute \src "ls180.v:7717.8-7717.56"
+  cell $not $not$ls180.v:7717$2514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7603$2436_Y
+    connect \Y $not$ls180.v:7717$2514_Y
   end
-  attribute \src "ls180.v:7618.8-7618.46"
-  cell $not $not$ls180.v:7618$2438
+  attribute \src "ls180.v:7732.8-7732.46"
+  cell $not $not$ls180.v:7732$2516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_ready
-    connect \Y $not$ls180.v:7618$2438_Y
+    connect \Y $not$ls180.v:7732$2516_Y
   end
-  attribute \src "ls180.v:7634.136-7634.189"
-  cell $not $not$ls180.v:7634$2442
+  attribute \src "ls180.v:7748.136-7748.189"
+  cell $not $not$ls180.v:7748$2520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7634$2442_Y
+    connect \Y $not$ls180.v:7748$2520_Y
   end
-  attribute \src "ls180.v:7640.136-7640.189"
-  cell $not $not$ls180.v:7640$2447
+  attribute \src "ls180.v:7754.136-7754.189"
+  cell $not $not$ls180.v:7754$2525
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7640$2447_Y
+    connect \Y $not$ls180.v:7754$2525_Y
   end
-  attribute \src "ls180.v:7641.8-7641.61"
-  cell $not $not$ls180.v:7641$2449
+  attribute \src "ls180.v:7755.8-7755.61"
+  cell $not $not$ls180.v:7755$2527
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7641$2449_Y
+    connect \Y $not$ls180.v:7755$2527_Y
   end
-  attribute \src "ls180.v:7649.8-7649.56"
-  cell $not $not$ls180.v:7649$2452
+  attribute \src "ls180.v:7763.8-7763.56"
+  cell $not $not$ls180.v:7763$2530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7649$2452_Y
+    connect \Y $not$ls180.v:7763$2530_Y
   end
-  attribute \src "ls180.v:7664.8-7664.46"
-  cell $not $not$ls180.v:7664$2454
+  attribute \src "ls180.v:7778.8-7778.46"
+  cell $not $not$ls180.v:7778$2532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_ready
-    connect \Y $not$ls180.v:7664$2454_Y
+    connect \Y $not$ls180.v:7778$2532_Y
   end
-  attribute \src "ls180.v:7680.136-7680.189"
-  cell $not $not$ls180.v:7680$2458
+  attribute \src "ls180.v:7794.136-7794.189"
+  cell $not $not$ls180.v:7794$2536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7680$2458_Y
+    connect \Y $not$ls180.v:7794$2536_Y
   end
-  attribute \src "ls180.v:7686.136-7686.189"
-  cell $not $not$ls180.v:7686$2463
+  attribute \src "ls180.v:7800.136-7800.189"
+  cell $not $not$ls180.v:7800$2541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7686$2463_Y
+    connect \Y $not$ls180.v:7800$2541_Y
   end
-  attribute \src "ls180.v:7687.8-7687.61"
-  cell $not $not$ls180.v:7687$2465
+  attribute \src "ls180.v:7801.8-7801.61"
+  cell $not $not$ls180.v:7801$2543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7687$2465_Y
+    connect \Y $not$ls180.v:7801$2543_Y
   end
-  attribute \src "ls180.v:7695.8-7695.56"
-  cell $not $not$ls180.v:7695$2468
+  attribute \src "ls180.v:7809.8-7809.56"
+  cell $not $not$ls180.v:7809$2546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7695$2468_Y
+    connect \Y $not$ls180.v:7809$2546_Y
   end
-  attribute \src "ls180.v:7710.8-7710.46"
-  cell $not $not$ls180.v:7710$2470
+  attribute \src "ls180.v:7824.8-7824.46"
+  cell $not $not$ls180.v:7824$2548
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_ready
-    connect \Y $not$ls180.v:7710$2470_Y
+    connect \Y $not$ls180.v:7824$2548_Y
   end
-  attribute \src "ls180.v:7726.136-7726.189"
-  cell $not $not$ls180.v:7726$2474
+  attribute \src "ls180.v:7840.136-7840.189"
+  cell $not $not$ls180.v:7840$2552
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7726$2474_Y
+    connect \Y $not$ls180.v:7840$2552_Y
   end
-  attribute \src "ls180.v:7732.136-7732.189"
-  cell $not $not$ls180.v:7732$2479
+  attribute \src "ls180.v:7846.136-7846.189"
+  cell $not $not$ls180.v:7846$2557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7732$2479_Y
+    connect \Y $not$ls180.v:7846$2557_Y
   end
-  attribute \src "ls180.v:7733.8-7733.61"
-  cell $not $not$ls180.v:7733$2481
+  attribute \src "ls180.v:7847.8-7847.61"
+  cell $not $not$ls180.v:7847$2559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7733$2481_Y
+    connect \Y $not$ls180.v:7847$2559_Y
   end
-  attribute \src "ls180.v:7741.8-7741.56"
-  cell $not $not$ls180.v:7741$2484
+  attribute \src "ls180.v:7855.8-7855.56"
+  cell $not $not$ls180.v:7855$2562
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7741$2484_Y
+    connect \Y $not$ls180.v:7855$2562_Y
   end
-  attribute \src "ls180.v:7756.8-7756.46"
-  cell $not $not$ls180.v:7756$2486
+  attribute \src "ls180.v:7870.8-7870.46"
+  cell $not $not$ls180.v:7870$2564
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_ready
-    connect \Y $not$ls180.v:7756$2486_Y
+    connect \Y $not$ls180.v:7870$2564_Y
   end
-  attribute \src "ls180.v:7764.7-7764.22"
-  cell $not $not$ls180.v:7764$2489
+  attribute \src "ls180.v:7878.7-7878.22"
+  cell $not $not$ls180.v:7878$2567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_en0
-    connect \Y $not$ls180.v:7764$2489_Y
+    connect \Y $not$ls180.v:7878$2567_Y
   end
-  attribute \src "ls180.v:7767.8-7767.29"
-  cell $not $not$ls180.v:7767$2490
+  attribute \src "ls180.v:7881.8-7881.29"
+  cell $not $not$ls180.v:7881$2568
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_max_time0
-    connect \Y $not$ls180.v:7767$2490_Y
+    connect \Y $not$ls180.v:7881$2568_Y
   end
-  attribute \src "ls180.v:7771.7-7771.22"
-  cell $not $not$ls180.v:7771$2492
+  attribute \src "ls180.v:7885.7-7885.22"
+  cell $not $not$ls180.v:7885$2570
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_en1
-    connect \Y $not$ls180.v:7771$2492_Y
+    connect \Y $not$ls180.v:7885$2570_Y
   end
-  attribute \src "ls180.v:7774.8-7774.29"
-  cell $not $not$ls180.v:7774$2493
+  attribute \src "ls180.v:7888.8-7888.29"
+  cell $not $not$ls180.v:7888$2571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_max_time1
-    connect \Y $not$ls180.v:7774$2493_Y
+    connect \Y $not$ls180.v:7888$2571_Y
   end
-  attribute \src "ls180.v:7893.30-7893.60"
-  cell $not $not$ls180.v:7893$2495
+  attribute \src "ls180.v:8007.30-8007.60"
+  cell $not $not$ls180.v:8007$2573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed2
-    connect \Y $not$ls180.v:7893$2495_Y
+    connect \Y $not$ls180.v:8007$2573_Y
   end
-  attribute \src "ls180.v:7894.30-7894.60"
-  cell $not $not$ls180.v:7894$2496
+  attribute \src "ls180.v:8008.30-8008.60"
+  cell $not $not$ls180.v:8008$2574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed3
-    connect \Y $not$ls180.v:7894$2496_Y
+    connect \Y $not$ls180.v:8008$2574_Y
   end
-  attribute \src "ls180.v:7895.29-7895.59"
-  cell $not $not$ls180.v:7895$2497
+  attribute \src "ls180.v:8009.29-8009.59"
+  cell $not $not$ls180.v:8009$2575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed4
-    connect \Y $not$ls180.v:7895$2497_Y
+    connect \Y $not$ls180.v:8009$2575_Y
   end
-  attribute \src "ls180.v:7906.8-7906.33"
-  cell $not $not$ls180.v:7906$2498
+  attribute \src "ls180.v:8020.8-8020.33"
+  cell $not $not$ls180.v:8020$2576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_ready
-    connect \Y $not$ls180.v:7906$2498_Y
+    connect \Y $not$ls180.v:8020$2576_Y
   end
-  attribute \src "ls180.v:7921.8-7921.33"
-  cell $not $not$ls180.v:7921$2501
+  attribute \src "ls180.v:8035.8-8035.33"
+  cell $not $not$ls180.v:8035$2579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_twtrcon_ready
-    connect \Y $not$ls180.v:7921$2501_Y
+    connect \Y $not$ls180.v:8035$2579_Y
   end
-  attribute \src "ls180.v:7957.36-7957.58"
-  cell $not $not$ls180.v:7957$2531
+  attribute \src "ls180.v:8071.36-8071.58"
+  cell $not $not$ls180.v:8071$2609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_busy
-    connect \Y $not$ls180.v:7957$2531_Y
+    connect \Y $not$ls180.v:8071$2609_Y
   end
-  attribute \src "ls180.v:7957.64-7957.89"
-  cell $not $not$ls180.v:7957$2533
+  attribute \src "ls180.v:8071.64-8071.89"
+  cell $not $not$ls180.v:8071$2611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_sink_ready
-    connect \Y $not$ls180.v:7957$2533_Y
+    connect \Y $not$ls180.v:8071$2611_Y
   end
-  attribute \src "ls180.v:7986.7-7986.29"
-  cell $not $not$ls180.v:7986$2540
+  attribute \src "ls180.v:8100.7-8100.29"
+  cell $not $not$ls180.v:8100$2618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_busy
-    connect \Y $not$ls180.v:7986$2540_Y
+    connect \Y $not$ls180.v:8100$2618_Y
   end
-  attribute \src "ls180.v:7987.9-7987.26"
-  cell $not $not$ls180.v:7987$2541
+  attribute \src "ls180.v:8101.9-8101.26"
+  cell $not $not$ls180.v:8101$2619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx
-    connect \Y $not$ls180.v:7987$2541_Y
+    connect \Y $not$ls180.v:8101$2619_Y
   end
-  attribute \src "ls180.v:8020.8-8020.29"
-  cell $not $not$ls180.v:8020$2547
+  attribute \src "ls180.v:8134.8-8134.29"
+  cell $not $not$ls180.v:8134$2625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_trigger
-    connect \Y $not$ls180.v:8020$2547_Y
+    connect \Y $not$ls180.v:8134$2625_Y
   end
-  attribute \src "ls180.v:8027.8-8027.29"
-  cell $not $not$ls180.v:8027$2549
+  attribute \src "ls180.v:8141.8-8141.29"
+  cell $not $not$ls180.v:8141$2627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_trigger
-    connect \Y $not$ls180.v:8027$2549_Y
+    connect \Y $not$ls180.v:8141$2627_Y
   end
-  attribute \src "ls180.v:8037.80-8037.106"
-  cell $not $not$ls180.v:8037$2552
+  attribute \src "ls180.v:8151.80-8151.106"
+  cell $not $not$ls180.v:8151$2630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_replace
-    connect \Y $not$ls180.v:8037$2552_Y
+    connect \Y $not$ls180.v:8151$2630_Y
   end
-  attribute \src "ls180.v:8043.80-8043.106"
-  cell $not $not$ls180.v:8043$2557
+  attribute \src "ls180.v:8157.80-8157.106"
+  cell $not $not$ls180.v:8157$2635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_replace
-    connect \Y $not$ls180.v:8043$2557_Y
+    connect \Y $not$ls180.v:8157$2635_Y
   end
-  attribute \src "ls180.v:8044.8-8044.34"
-  cell $not $not$ls180.v:8044$2559
+  attribute \src "ls180.v:8158.8-8158.34"
+  cell $not $not$ls180.v:8158$2637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_do_read
-    connect \Y $not$ls180.v:8044$2559_Y
+    connect \Y $not$ls180.v:8158$2637_Y
   end
-  attribute \src "ls180.v:8059.80-8059.106"
-  cell $not $not$ls180.v:8059$2563
+  attribute \src "ls180.v:8173.80-8173.106"
+  cell $not $not$ls180.v:8173$2641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_replace
-    connect \Y $not$ls180.v:8059$2563_Y
+    connect \Y $not$ls180.v:8173$2641_Y
   end
-  attribute \src "ls180.v:8065.80-8065.106"
-  cell $not $not$ls180.v:8065$2568
+  attribute \src "ls180.v:8179.80-8179.106"
+  cell $not $not$ls180.v:8179$2646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_replace
-    connect \Y $not$ls180.v:8065$2568_Y
+    connect \Y $not$ls180.v:8179$2646_Y
   end
-  attribute \src "ls180.v:8066.8-8066.34"
-  cell $not $not$ls180.v:8066$2570
+  attribute \src "ls180.v:8180.8-8180.34"
+  cell $not $not$ls180.v:8180$2648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_do_read
-    connect \Y $not$ls180.v:8066$2570_Y
+    connect \Y $not$ls180.v:8180$2648_Y
   end
-  attribute \src "ls180.v:8097.22-8097.41"
-  cell $not $not$ls180.v:8097$2574
+  attribute \src "ls180.v:8211.22-8211.41"
+  cell $not $not$ls180.v:8211$2652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spimaster6_cs
-    connect \Y $not$ls180.v:8097$2574_Y
+    connect \Y $not$ls180.v:8211$2652_Y
   end
-  attribute \src "ls180.v:8097.46-8097.73"
-  cell $not $not$ls180.v:8097$2575
+  attribute \src "ls180.v:8211.46-8211.73"
+  cell $not $not$ls180.v:8211$2653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spimaster26_cs_enable
-    connect \Y $not$ls180.v:8097$2575_Y
+    connect \Y $not$ls180.v:8211$2653_Y
   end
-  attribute \src "ls180.v:8132.22-8132.40"
-  cell $not $not$ls180.v:8132$2579
+  attribute \src "ls180.v:8246.22-8246.40"
+  cell $not $not$ls180.v:8246$2657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_cs
-    connect \Y $not$ls180.v:8132$2579_Y
+    connect \Y $not$ls180.v:8246$2657_Y
   end
-  attribute \src "ls180.v:8132.45-8132.70"
-  cell $not $not$ls180.v:8132$2580
+  attribute \src "ls180.v:8246.45-8246.70"
+  cell $not $not$ls180.v:8246$2658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_cs_enable
-    connect \Y $not$ls180.v:8132$2580_Y
+    connect \Y $not$ls180.v:8246$2658_Y
   end
-  attribute \src "ls180.v:8186.7-8186.31"
-  cell $not $not$ls180.v:8186$2591
+  attribute \src "ls180.v:8300.7-8300.31"
+  cell $not $not$ls180.v:8300$2669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_clocker_stop
-    connect \Y $not$ls180.v:8186$2591_Y
+    connect \Y $not$ls180.v:8300$2669_Y
   end
-  attribute \src "ls180.v:8258.8-8258.46"
-  cell $not $not$ls180.v:8258$2603
+  attribute \src "ls180.v:8372.8-8372.46"
+  cell $not $not$ls180.v:8372$2681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
-    connect \Y $not$ls180.v:8258$2603_Y
+    connect \Y $not$ls180.v:8372$2681_Y
   end
-  attribute \src "ls180.v:8339.8-8339.47"
-  cell $not $not$ls180.v:8339$2615
+  attribute \src "ls180.v:8453.8-8453.47"
+  cell $not $not$ls180.v:8453$2693
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_buf_source_valid
-    connect \Y $not$ls180.v:8339$2615_Y
+    connect \Y $not$ls180.v:8453$2693_Y
   end
-  attribute \src "ls180.v:8400.8-8400.48"
-  cell $not $not$ls180.v:8400$2627
+  attribute \src "ls180.v:8514.8-8514.48"
+  cell $not $not$ls180.v:8514$2705
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_buf_source_valid
-    connect \Y $not$ls180.v:8400$2627_Y
+    connect \Y $not$ls180.v:8514$2705_Y
   end
-  attribute \src "ls180.v:8570.88-8570.118"
-  cell $not $not$ls180.v:8570$2641
+  attribute \src "ls180.v:8684.88-8684.118"
+  cell $not $not$ls180.v:8684$2719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_replace
-    connect \Y $not$ls180.v:8570$2641_Y
+    connect \Y $not$ls180.v:8684$2719_Y
   end
-  attribute \src "ls180.v:8576.88-8576.118"
-  cell $not $not$ls180.v:8576$2646
+  attribute \src "ls180.v:8690.88-8690.118"
+  cell $not $not$ls180.v:8690$2724
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_replace
-    connect \Y $not$ls180.v:8576$2646_Y
+    connect \Y $not$ls180.v:8690$2724_Y
   end
-  attribute \src "ls180.v:8577.8-8577.38"
-  cell $not $not$ls180.v:8577$2648
+  attribute \src "ls180.v:8691.8-8691.38"
+  cell $not $not$ls180.v:8691$2726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_do_read
-    connect \Y $not$ls180.v:8577$2648_Y
+    connect \Y $not$ls180.v:8691$2726_Y
   end
-  attribute \src "ls180.v:8656.88-8656.118"
-  cell $not $not$ls180.v:8656$2663
+  attribute \src "ls180.v:8770.88-8770.118"
+  cell $not $not$ls180.v:8770$2741
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_replace
-    connect \Y $not$ls180.v:8656$2663_Y
+    connect \Y $not$ls180.v:8770$2741_Y
   end
-  attribute \src "ls180.v:8662.88-8662.118"
-  cell $not $not$ls180.v:8662$2668
+  attribute \src "ls180.v:8776.88-8776.118"
+  cell $not $not$ls180.v:8776$2746
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_replace
-    connect \Y $not$ls180.v:8662$2668_Y
+    connect \Y $not$ls180.v:8776$2746_Y
   end
-  attribute \src "ls180.v:8663.8-8663.38"
-  cell $not $not$ls180.v:8663$2670
+  attribute \src "ls180.v:8777.8-8777.38"
+  cell $not $not$ls180.v:8777$2748
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_do_read
-    connect \Y $not$ls180.v:8663$2670_Y
+    connect \Y $not$ls180.v:8777$2748_Y
   end
-  attribute \src "ls180.v:8683.9-8683.28"
-  cell $not $not$ls180.v:8683$2673
+  attribute \src "ls180.v:8797.9-8797.28"
+  cell $not $not$ls180.v:8797$2751
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [0]
-    connect \Y $not$ls180.v:8683$2673_Y
+    connect \Y $not$ls180.v:8797$2751_Y
   end
-  attribute \src "ls180.v:8702.9-8702.28"
-  cell $not $not$ls180.v:8702$2674
+  attribute \src "ls180.v:8816.9-8816.28"
+  cell $not $not$ls180.v:8816$2752
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [1]
-    connect \Y $not$ls180.v:8702$2674_Y
+    connect \Y $not$ls180.v:8816$2752_Y
   end
-  attribute \src "ls180.v:8721.9-8721.28"
-  cell $not $not$ls180.v:8721$2675
+  attribute \src "ls180.v:8835.9-8835.28"
+  cell $not $not$ls180.v:8835$2753
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [2]
-    connect \Y $not$ls180.v:8721$2675_Y
+    connect \Y $not$ls180.v:8835$2753_Y
   end
-  attribute \src "ls180.v:8740.9-8740.28"
-  cell $not $not$ls180.v:8740$2676
+  attribute \src "ls180.v:8854.9-8854.28"
+  cell $not $not$ls180.v:8854$2754
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [3]
-    connect \Y $not$ls180.v:8740$2676_Y
+    connect \Y $not$ls180.v:8854$2754_Y
   end
-  attribute \src "ls180.v:8759.9-8759.28"
-  cell $not $not$ls180.v:8759$2677
+  attribute \src "ls180.v:8873.9-8873.28"
+  cell $not $not$ls180.v:8873$2755
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [4]
-    connect \Y $not$ls180.v:8759$2677_Y
+    connect \Y $not$ls180.v:8873$2755_Y
   end
-  attribute \src "ls180.v:8780.8-8780.21"
-  cell $not $not$ls180.v:8780$2678
+  attribute \src "ls180.v:8894.8-8894.21"
+  cell $not $not$ls180.v:8894$2756
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_done
-    connect \Y $not$ls180.v:8780$2678_Y
+    connect \Y $not$ls180.v:8894$2756_Y
   end
-  attribute \src "ls180.v:10279.8-10279.51"
-  cell $or $or$ls180.v:10279$2750
+  attribute \src "ls180.v:10456.8-10456.51"
+  cell $or $or$ls180.v:10456$2870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257032,10 +258226,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sys_rst_1
     connect \B \main_libresocsim_libresoc_reset
-    connect \Y $or$ls180.v:10279$2750_Y
+    connect \Y $or$ls180.v:10456$2870_Y
   end
-  attribute \src "ls180.v:2814.10-2814.96"
-  cell $or $or$ls180.v:2814$21
+  attribute \src "ls180.v:2859.10-2859.96"
+  cell $or $or$ls180.v:2859$33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257043,10 +258237,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface0_converted_interface_ack
     connect \B \main_libresocsim_converter0_skip
-    connect \Y $or$ls180.v:2814$21_Y
+    connect \Y $or$ls180.v:2859$33_Y
   end
-  attribute \src "ls180.v:2874.10-2874.96"
-  cell $or $or$ls180.v:2874$32
+  attribute \src "ls180.v:2919.10-2919.96"
+  cell $or $or$ls180.v:2919$44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257054,10 +258248,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface1_converted_interface_ack
     connect \B \main_libresocsim_converter1_skip
-    connect \Y $or$ls180.v:2874$32_Y
+    connect \Y $or$ls180.v:2919$44_Y
   end
-  attribute \src "ls180.v:2934.10-2934.96"
-  cell $or $or$ls180.v:2934$43
+  attribute \src "ls180.v:2979.10-2979.96"
+  cell $or $or$ls180.v:2979$55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257065,21 +258259,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface2_converted_interface_ack
     connect \B \main_libresocsim_converter2_skip
-    connect \Y $or$ls180.v:2934$43_Y
+    connect \Y $or$ls180.v:2979$55_Y
   end
-  attribute \src "ls180.v:3126.39-3126.105"
-  cell $or $or$ls180.v:3126$75
+  attribute \src "ls180.v:3201.39-3201.105"
+  cell $or $or$ls180.v:3201$126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_start0
-    connect \B $ne$ls180.v:3126$74_Y
-    connect \Y $or$ls180.v:3126$75_Y
+    connect \B $ne$ls180.v:3201$125_Y
+    connect \Y $or$ls180.v:3201$126_Y
   end
-  attribute \src "ls180.v:3169.59-3169.140"
-  cell $or $or$ls180.v:3169$79
+  attribute \src "ls180.v:3244.59-3244.140"
+  cell $or $or$ls180.v:3244$130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257087,10 +258281,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_req_wdata_ready
     connect \B \main_sdram_bankmachine0_req_rdata_valid
-    connect \Y $or$ls180.v:3169$79_Y
+    connect \Y $or$ls180.v:3244$130_Y
   end
-  attribute \src "ls180.v:3170.44-3170.151"
-  cell $or $or$ls180.v:3170$80
+  attribute \src "ls180.v:3245.44-3245.151"
+  cell $or $or$ls180.v:3245$131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257098,21 +258292,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:3170$80_Y
+    connect \Y $or$ls180.v:3245$131_Y
   end
-  attribute \src "ls180.v:3178.45-3178.170"
-  cell $or $or$ls180.v:3178$84
+  attribute \src "ls180.v:3253.45-3253.170"
+  cell $or $or$ls180.v:3253$135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:3178$83_Y
+    connect \A $sshl$ls180.v:3253$134_Y
     connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:3178$84_Y
+    connect \Y $or$ls180.v:3253$135_Y
   end
-  attribute \src "ls180.v:3215.127-3215.245"
-  cell $or $or$ls180.v:3215$97
+  attribute \src "ls180.v:3290.127-3290.245"
+  cell $or $or$ls180.v:3290$148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257120,21 +258314,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:3215$97_Y
+    connect \Y $or$ls180.v:3290$148_Y
   end
-  attribute \src "ls180.v:3221.57-3221.157"
-  cell $or $or$ls180.v:3221$103
+  attribute \src "ls180.v:3296.57-3296.157"
+  cell $or $or$ls180.v:3296$154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3221$102_Y
+    connect \A $not$ls180.v:3296$153_Y
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:3221$103_Y
+    connect \Y $or$ls180.v:3296$154_Y
   end
-  attribute \src "ls180.v:3326.59-3326.140"
-  cell $or $or$ls180.v:3326$109
+  attribute \src "ls180.v:3401.59-3401.140"
+  cell $or $or$ls180.v:3401$160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257142,10 +258336,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_req_wdata_ready
     connect \B \main_sdram_bankmachine1_req_rdata_valid
-    connect \Y $or$ls180.v:3326$109_Y
+    connect \Y $or$ls180.v:3401$160_Y
   end
-  attribute \src "ls180.v:3327.44-3327.151"
-  cell $or $or$ls180.v:3327$110
+  attribute \src "ls180.v:3402.44-3402.151"
+  cell $or $or$ls180.v:3402$161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257153,21 +258347,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:3327$110_Y
+    connect \Y $or$ls180.v:3402$161_Y
   end
-  attribute \src "ls180.v:3335.45-3335.170"
-  cell $or $or$ls180.v:3335$114
+  attribute \src "ls180.v:3410.45-3410.170"
+  cell $or $or$ls180.v:3410$165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:3335$113_Y
+    connect \A $sshl$ls180.v:3410$164_Y
     connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:3335$114_Y
+    connect \Y $or$ls180.v:3410$165_Y
   end
-  attribute \src "ls180.v:3372.127-3372.245"
-  cell $or $or$ls180.v:3372$127
+  attribute \src "ls180.v:3447.127-3447.245"
+  cell $or $or$ls180.v:3447$178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257175,21 +258369,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:3372$127_Y
+    connect \Y $or$ls180.v:3447$178_Y
   end
-  attribute \src "ls180.v:3378.57-3378.157"
-  cell $or $or$ls180.v:3378$133
+  attribute \src "ls180.v:3453.57-3453.157"
+  cell $or $or$ls180.v:3453$184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3378$132_Y
+    connect \A $not$ls180.v:3453$183_Y
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:3378$133_Y
+    connect \Y $or$ls180.v:3453$184_Y
   end
-  attribute \src "ls180.v:3483.59-3483.140"
-  cell $or $or$ls180.v:3483$139
+  attribute \src "ls180.v:3558.59-3558.140"
+  cell $or $or$ls180.v:3558$190
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257197,10 +258391,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_req_wdata_ready
     connect \B \main_sdram_bankmachine2_req_rdata_valid
-    connect \Y $or$ls180.v:3483$139_Y
+    connect \Y $or$ls180.v:3558$190_Y
   end
-  attribute \src "ls180.v:3484.44-3484.151"
-  cell $or $or$ls180.v:3484$140
+  attribute \src "ls180.v:3559.44-3559.151"
+  cell $or $or$ls180.v:3559$191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257208,21 +258402,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:3484$140_Y
+    connect \Y $or$ls180.v:3559$191_Y
   end
-  attribute \src "ls180.v:3492.45-3492.170"
-  cell $or $or$ls180.v:3492$144
+  attribute \src "ls180.v:3567.45-3567.170"
+  cell $or $or$ls180.v:3567$195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:3492$143_Y
+    connect \A $sshl$ls180.v:3567$194_Y
     connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:3492$144_Y
+    connect \Y $or$ls180.v:3567$195_Y
   end
-  attribute \src "ls180.v:3529.127-3529.245"
-  cell $or $or$ls180.v:3529$157
+  attribute \src "ls180.v:3604.127-3604.245"
+  cell $or $or$ls180.v:3604$208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257230,21 +258424,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:3529$157_Y
+    connect \Y $or$ls180.v:3604$208_Y
   end
-  attribute \src "ls180.v:3535.57-3535.157"
-  cell $or $or$ls180.v:3535$163
+  attribute \src "ls180.v:3610.57-3610.157"
+  cell $or $or$ls180.v:3610$214
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3535$162_Y
+    connect \A $not$ls180.v:3610$213_Y
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:3535$163_Y
+    connect \Y $or$ls180.v:3610$214_Y
   end
-  attribute \src "ls180.v:3640.59-3640.140"
-  cell $or $or$ls180.v:3640$169
+  attribute \src "ls180.v:3715.59-3715.140"
+  cell $or $or$ls180.v:3715$220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257252,10 +258446,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_req_wdata_ready
     connect \B \main_sdram_bankmachine3_req_rdata_valid
-    connect \Y $or$ls180.v:3640$169_Y
+    connect \Y $or$ls180.v:3715$220_Y
   end
-  attribute \src "ls180.v:3641.44-3641.151"
-  cell $or $or$ls180.v:3641$170
+  attribute \src "ls180.v:3716.44-3716.151"
+  cell $or $or$ls180.v:3716$221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257263,21 +258457,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:3641$170_Y
+    connect \Y $or$ls180.v:3716$221_Y
   end
-  attribute \src "ls180.v:3649.45-3649.170"
-  cell $or $or$ls180.v:3649$174
+  attribute \src "ls180.v:3724.45-3724.170"
+  cell $or $or$ls180.v:3724$225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:3649$173_Y
+    connect \A $sshl$ls180.v:3724$224_Y
     connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:3649$174_Y
+    connect \Y $or$ls180.v:3724$225_Y
   end
-  attribute \src "ls180.v:3686.127-3686.245"
-  cell $or $or$ls180.v:3686$187
+  attribute \src "ls180.v:3761.127-3761.245"
+  cell $or $or$ls180.v:3761$238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257285,21 +258479,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:3686$187_Y
+    connect \Y $or$ls180.v:3761$238_Y
   end
-  attribute \src "ls180.v:3692.57-3692.157"
-  cell $or $or$ls180.v:3692$193
+  attribute \src "ls180.v:3767.57-3767.157"
+  cell $or $or$ls180.v:3767$244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3692$192_Y
+    connect \A $not$ls180.v:3767$243_Y
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:3692$193_Y
+    connect \Y $or$ls180.v:3767$244_Y
   end
-  attribute \src "ls180.v:3791.107-3791.193"
-  cell $or $or$ls180.v:3791$213
+  attribute \src "ls180.v:3866.107-3866.193"
+  cell $or $or$ls180.v:3866$264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257307,626 +258501,626 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_payload_is_write
     connect \B \main_sdram_choose_req_cmd_payload_is_read
-    connect \Y $or$ls180.v:3791$213_Y
+    connect \Y $or$ls180.v:3866$264_Y
   end
-  attribute \src "ls180.v:3794.39-3794.204"
-  cell $or $or$ls180.v:3794$219
+  attribute \src "ls180.v:3869.39-3869.204"
+  cell $or $or$ls180.v:3869$270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3794$217_Y
-    connect \B $and$ls180.v:3794$218_Y
-    connect \Y $or$ls180.v:3794$219_Y
+    connect \A $and$ls180.v:3869$268_Y
+    connect \B $and$ls180.v:3869$269_Y
+    connect \Y $or$ls180.v:3869$270_Y
   end
-  attribute \src "ls180.v:3794.38-3794.289"
-  cell $or $or$ls180.v:3794$221
+  attribute \src "ls180.v:3869.38-3869.289"
+  cell $or $or$ls180.v:3869$272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3794$219_Y
-    connect \B $and$ls180.v:3794$220_Y
-    connect \Y $or$ls180.v:3794$221_Y
+    connect \A $or$ls180.v:3869$270_Y
+    connect \B $and$ls180.v:3869$271_Y
+    connect \Y $or$ls180.v:3869$272_Y
   end
-  attribute \src "ls180.v:3794.37-3794.374"
-  cell $or $or$ls180.v:3794$223
+  attribute \src "ls180.v:3869.37-3869.374"
+  cell $or $or$ls180.v:3869$274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3794$221_Y
-    connect \B $and$ls180.v:3794$222_Y
-    connect \Y $or$ls180.v:3794$223_Y
+    connect \A $or$ls180.v:3869$272_Y
+    connect \B $and$ls180.v:3869$273_Y
+    connect \Y $or$ls180.v:3869$274_Y
   end
-  attribute \src "ls180.v:3795.40-3795.207"
-  cell $or $or$ls180.v:3795$226
+  attribute \src "ls180.v:3870.40-3870.207"
+  cell $or $or$ls180.v:3870$277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3795$224_Y
-    connect \B $and$ls180.v:3795$225_Y
-    connect \Y $or$ls180.v:3795$226_Y
+    connect \A $and$ls180.v:3870$275_Y
+    connect \B $and$ls180.v:3870$276_Y
+    connect \Y $or$ls180.v:3870$277_Y
   end
-  attribute \src "ls180.v:3795.39-3795.293"
-  cell $or $or$ls180.v:3795$228
+  attribute \src "ls180.v:3870.39-3870.293"
+  cell $or $or$ls180.v:3870$279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3795$226_Y
-    connect \B $and$ls180.v:3795$227_Y
-    connect \Y $or$ls180.v:3795$228_Y
+    connect \A $or$ls180.v:3870$277_Y
+    connect \B $and$ls180.v:3870$278_Y
+    connect \Y $or$ls180.v:3870$279_Y
   end
-  attribute \src "ls180.v:3795.38-3795.379"
-  cell $or $or$ls180.v:3795$230
+  attribute \src "ls180.v:3870.38-3870.379"
+  cell $or $or$ls180.v:3870$281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3795$228_Y
-    connect \B $and$ls180.v:3795$229_Y
-    connect \Y $or$ls180.v:3795$230_Y
+    connect \A $or$ls180.v:3870$279_Y
+    connect \B $and$ls180.v:3870$280_Y
+    connect \Y $or$ls180.v:3870$281_Y
   end
-  attribute \src "ls180.v:3808.158-3808.332"
-  cell $or $or$ls180.v:3808$244
+  attribute \src "ls180.v:3883.158-3883.332"
+  cell $or $or$ls180.v:3883$295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3808$243_Y
+    connect \A $not$ls180.v:3883$294_Y
     connect \B \main_sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:3808$244_Y
+    connect \Y $or$ls180.v:3883$295_Y
   end
-  attribute \src "ls180.v:3808.75-3808.506"
-  cell $or $or$ls180.v:3808$249
+  attribute \src "ls180.v:3883.75-3883.506"
+  cell $or $or$ls180.v:3883$300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3808$245_Y
-    connect \B $and$ls180.v:3808$248_Y
-    connect \Y $or$ls180.v:3808$249_Y
+    connect \A $and$ls180.v:3883$296_Y
+    connect \B $and$ls180.v:3883$299_Y
+    connect \Y $or$ls180.v:3883$300_Y
   end
-  attribute \src "ls180.v:3809.158-3809.332"
-  cell $or $or$ls180.v:3809$257
+  attribute \src "ls180.v:3884.158-3884.332"
+  cell $or $or$ls180.v:3884$308
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3809$256_Y
+    connect \A $not$ls180.v:3884$307_Y
     connect \B \main_sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:3809$257_Y
+    connect \Y $or$ls180.v:3884$308_Y
   end
-  attribute \src "ls180.v:3809.75-3809.506"
-  cell $or $or$ls180.v:3809$262
+  attribute \src "ls180.v:3884.75-3884.506"
+  cell $or $or$ls180.v:3884$313
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3809$258_Y
-    connect \B $and$ls180.v:3809$261_Y
-    connect \Y $or$ls180.v:3809$262_Y
+    connect \A $and$ls180.v:3884$309_Y
+    connect \B $and$ls180.v:3884$312_Y
+    connect \Y $or$ls180.v:3884$313_Y
   end
-  attribute \src "ls180.v:3810.158-3810.332"
-  cell $or $or$ls180.v:3810$270
+  attribute \src "ls180.v:3885.158-3885.332"
+  cell $or $or$ls180.v:3885$321
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3810$269_Y
+    connect \A $not$ls180.v:3885$320_Y
     connect \B \main_sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:3810$270_Y
+    connect \Y $or$ls180.v:3885$321_Y
   end
-  attribute \src "ls180.v:3810.75-3810.506"
-  cell $or $or$ls180.v:3810$275
+  attribute \src "ls180.v:3885.75-3885.506"
+  cell $or $or$ls180.v:3885$326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3810$271_Y
-    connect \B $and$ls180.v:3810$274_Y
-    connect \Y $or$ls180.v:3810$275_Y
+    connect \A $and$ls180.v:3885$322_Y
+    connect \B $and$ls180.v:3885$325_Y
+    connect \Y $or$ls180.v:3885$326_Y
   end
-  attribute \src "ls180.v:3811.158-3811.332"
-  cell $or $or$ls180.v:3811$283
+  attribute \src "ls180.v:3886.158-3886.332"
+  cell $or $or$ls180.v:3886$334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3811$282_Y
+    connect \A $not$ls180.v:3886$333_Y
     connect \B \main_sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:3811$283_Y
+    connect \Y $or$ls180.v:3886$334_Y
   end
-  attribute \src "ls180.v:3811.75-3811.506"
-  cell $or $or$ls180.v:3811$288
+  attribute \src "ls180.v:3886.75-3886.506"
+  cell $or $or$ls180.v:3886$339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3811$284_Y
-    connect \B $and$ls180.v:3811$287_Y
-    connect \Y $or$ls180.v:3811$288_Y
+    connect \A $and$ls180.v:3886$335_Y
+    connect \B $and$ls180.v:3886$338_Y
+    connect \Y $or$ls180.v:3886$339_Y
   end
-  attribute \src "ls180.v:3838.36-3838.104"
-  cell $or $or$ls180.v:3838$294
+  attribute \src "ls180.v:3913.36-3913.104"
+  cell $or $or$ls180.v:3913$345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_cmd_cmd_ready
-    connect \B $not$ls180.v:3838$293_Y
-    connect \Y $or$ls180.v:3838$294_Y
+    connect \B $not$ls180.v:3913$344_Y
+    connect \Y $or$ls180.v:3913$345_Y
   end
-  attribute \src "ls180.v:3841.158-3841.332"
-  cell $or $or$ls180.v:3841$302
+  attribute \src "ls180.v:3916.158-3916.332"
+  cell $or $or$ls180.v:3916$353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3841$301_Y
+    connect \A $not$ls180.v:3916$352_Y
     connect \B \main_sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:3841$302_Y
+    connect \Y $or$ls180.v:3916$353_Y
   end
-  attribute \src "ls180.v:3841.75-3841.506"
-  cell $or $or$ls180.v:3841$307
+  attribute \src "ls180.v:3916.75-3916.506"
+  cell $or $or$ls180.v:3916$358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3841$303_Y
-    connect \B $and$ls180.v:3841$306_Y
-    connect \Y $or$ls180.v:3841$307_Y
+    connect \A $and$ls180.v:3916$354_Y
+    connect \B $and$ls180.v:3916$357_Y
+    connect \Y $or$ls180.v:3916$358_Y
   end
-  attribute \src "ls180.v:3842.158-3842.332"
-  cell $or $or$ls180.v:3842$315
+  attribute \src "ls180.v:3917.158-3917.332"
+  cell $or $or$ls180.v:3917$366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3842$314_Y
+    connect \A $not$ls180.v:3917$365_Y
     connect \B \main_sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:3842$315_Y
+    connect \Y $or$ls180.v:3917$366_Y
   end
-  attribute \src "ls180.v:3842.75-3842.506"
-  cell $or $or$ls180.v:3842$320
+  attribute \src "ls180.v:3917.75-3917.506"
+  cell $or $or$ls180.v:3917$371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3842$316_Y
-    connect \B $and$ls180.v:3842$319_Y
-    connect \Y $or$ls180.v:3842$320_Y
+    connect \A $and$ls180.v:3917$367_Y
+    connect \B $and$ls180.v:3917$370_Y
+    connect \Y $or$ls180.v:3917$371_Y
   end
-  attribute \src "ls180.v:3843.158-3843.332"
-  cell $or $or$ls180.v:3843$328
+  attribute \src "ls180.v:3918.158-3918.332"
+  cell $or $or$ls180.v:3918$379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3843$327_Y
+    connect \A $not$ls180.v:3918$378_Y
     connect \B \main_sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:3843$328_Y
+    connect \Y $or$ls180.v:3918$379_Y
   end
-  attribute \src "ls180.v:3843.75-3843.506"
-  cell $or $or$ls180.v:3843$333
+  attribute \src "ls180.v:3918.75-3918.506"
+  cell $or $or$ls180.v:3918$384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3843$329_Y
-    connect \B $and$ls180.v:3843$332_Y
-    connect \Y $or$ls180.v:3843$333_Y
+    connect \A $and$ls180.v:3918$380_Y
+    connect \B $and$ls180.v:3918$383_Y
+    connect \Y $or$ls180.v:3918$384_Y
   end
-  attribute \src "ls180.v:3844.158-3844.332"
-  cell $or $or$ls180.v:3844$341
+  attribute \src "ls180.v:3919.158-3919.332"
+  cell $or $or$ls180.v:3919$392
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3844$340_Y
+    connect \A $not$ls180.v:3919$391_Y
     connect \B \main_sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:3844$341_Y
+    connect \Y $or$ls180.v:3919$392_Y
   end
-  attribute \src "ls180.v:3844.75-3844.506"
-  cell $or $or$ls180.v:3844$346
+  attribute \src "ls180.v:3919.75-3919.506"
+  cell $or $or$ls180.v:3919$397
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3844$342_Y
-    connect \B $and$ls180.v:3844$345_Y
-    connect \Y $or$ls180.v:3844$346_Y
+    connect \A $and$ls180.v:3919$393_Y
+    connect \B $and$ls180.v:3919$396_Y
+    connect \Y $or$ls180.v:3919$397_Y
   end
-  attribute \src "ls180.v:3907.36-3907.104"
-  cell $or $or$ls180.v:3907$380
+  attribute \src "ls180.v:3982.36-3982.104"
+  cell $or $or$ls180.v:3982$431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_choose_req_cmd_ready
-    connect \B $not$ls180.v:3907$379_Y
-    connect \Y $or$ls180.v:3907$380_Y
+    connect \B $not$ls180.v:3982$430_Y
+    connect \Y $or$ls180.v:3982$431_Y
   end
-  attribute \src "ls180.v:3928.67-3928.221"
-  cell $or $or$ls180.v:3928$387
+  attribute \src "ls180.v:4003.67-4003.221"
+  cell $or $or$ls180.v:4003$438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3928$386_Y
+    connect \A $not$ls180.v:4003$437_Y
     connect \B \main_sdram_ras_allowed
-    connect \Y $or$ls180.v:3928$387_Y
+    connect \Y $or$ls180.v:4003$438_Y
   end
-  attribute \src "ls180.v:3936.10-3936.62"
-  cell $or $or$ls180.v:3936$390
+  attribute \src "ls180.v:4011.10-4011.62"
+  cell $or $or$ls180.v:4011$441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3936$389_Y
+    connect \A $not$ls180.v:4011$440_Y
     connect \B \main_sdram_max_time1
-    connect \Y $or$ls180.v:3936$390_Y
+    connect \Y $or$ls180.v:4011$441_Y
   end
-  attribute \src "ls180.v:3966.67-3966.221"
-  cell $or $or$ls180.v:3966$396
+  attribute \src "ls180.v:4041.67-4041.221"
+  cell $or $or$ls180.v:4041$447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3966$395_Y
+    connect \A $not$ls180.v:4041$446_Y
     connect \B \main_sdram_ras_allowed
-    connect \Y $or$ls180.v:3966$396_Y
+    connect \Y $or$ls180.v:4041$447_Y
   end
-  attribute \src "ls180.v:3974.10-3974.61"
-  cell $or $or$ls180.v:3974$399
+  attribute \src "ls180.v:4049.10-4049.61"
+  cell $or $or$ls180.v:4049$450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:3974$398_Y
+    connect \A $not$ls180.v:4049$449_Y
     connect \B \main_sdram_max_time0
-    connect \Y $or$ls180.v:3974$399_Y
+    connect \Y $or$ls180.v:4049$450_Y
   end
-  attribute \src "ls180.v:3984.91-3984.180"
-  cell $or $or$ls180.v:3984$403
+  attribute \src "ls180.v:4059.91-4059.180"
+  cell $or $or$ls180.v:4059$454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked0
-    connect \B $and$ls180.v:3984$402_Y
-    connect \Y $or$ls180.v:3984$403_Y
+    connect \B $and$ls180.v:4059$453_Y
+    connect \Y $or$ls180.v:4059$454_Y
   end
-  attribute \src "ls180.v:3984.90-3984.255"
-  cell $or $or$ls180.v:3984$406
+  attribute \src "ls180.v:4059.90-4059.255"
+  cell $or $or$ls180.v:4059$457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3984$403_Y
-    connect \B $and$ls180.v:3984$405_Y
-    connect \Y $or$ls180.v:3984$406_Y
+    connect \A $or$ls180.v:4059$454_Y
+    connect \B $and$ls180.v:4059$456_Y
+    connect \Y $or$ls180.v:4059$457_Y
   end
-  attribute \src "ls180.v:3984.89-3984.330"
-  cell $or $or$ls180.v:3984$409
+  attribute \src "ls180.v:4059.89-4059.330"
+  cell $or $or$ls180.v:4059$460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3984$406_Y
-    connect \B $and$ls180.v:3984$408_Y
-    connect \Y $or$ls180.v:3984$409_Y
+    connect \A $or$ls180.v:4059$457_Y
+    connect \B $and$ls180.v:4059$459_Y
+    connect \Y $or$ls180.v:4059$460_Y
   end
-  attribute \src "ls180.v:3989.91-3989.180"
-  cell $or $or$ls180.v:3989$419
+  attribute \src "ls180.v:4064.91-4064.180"
+  cell $or $or$ls180.v:4064$470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked1
-    connect \B $and$ls180.v:3989$418_Y
-    connect \Y $or$ls180.v:3989$419_Y
+    connect \B $and$ls180.v:4064$469_Y
+    connect \Y $or$ls180.v:4064$470_Y
   end
-  attribute \src "ls180.v:3989.90-3989.255"
-  cell $or $or$ls180.v:3989$422
+  attribute \src "ls180.v:4064.90-4064.255"
+  cell $or $or$ls180.v:4064$473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3989$419_Y
-    connect \B $and$ls180.v:3989$421_Y
-    connect \Y $or$ls180.v:3989$422_Y
+    connect \A $or$ls180.v:4064$470_Y
+    connect \B $and$ls180.v:4064$472_Y
+    connect \Y $or$ls180.v:4064$473_Y
   end
-  attribute \src "ls180.v:3989.89-3989.330"
-  cell $or $or$ls180.v:3989$425
+  attribute \src "ls180.v:4064.89-4064.330"
+  cell $or $or$ls180.v:4064$476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3989$422_Y
-    connect \B $and$ls180.v:3989$424_Y
-    connect \Y $or$ls180.v:3989$425_Y
+    connect \A $or$ls180.v:4064$473_Y
+    connect \B $and$ls180.v:4064$475_Y
+    connect \Y $or$ls180.v:4064$476_Y
   end
-  attribute \src "ls180.v:3994.91-3994.180"
-  cell $or $or$ls180.v:3994$435
+  attribute \src "ls180.v:4069.91-4069.180"
+  cell $or $or$ls180.v:4069$486
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked2
-    connect \B $and$ls180.v:3994$434_Y
-    connect \Y $or$ls180.v:3994$435_Y
+    connect \B $and$ls180.v:4069$485_Y
+    connect \Y $or$ls180.v:4069$486_Y
   end
-  attribute \src "ls180.v:3994.90-3994.255"
-  cell $or $or$ls180.v:3994$438
+  attribute \src "ls180.v:4069.90-4069.255"
+  cell $or $or$ls180.v:4069$489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3994$435_Y
-    connect \B $and$ls180.v:3994$437_Y
-    connect \Y $or$ls180.v:3994$438_Y
+    connect \A $or$ls180.v:4069$486_Y
+    connect \B $and$ls180.v:4069$488_Y
+    connect \Y $or$ls180.v:4069$489_Y
   end
-  attribute \src "ls180.v:3994.89-3994.330"
-  cell $or $or$ls180.v:3994$441
+  attribute \src "ls180.v:4069.89-4069.330"
+  cell $or $or$ls180.v:4069$492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3994$438_Y
-    connect \B $and$ls180.v:3994$440_Y
-    connect \Y $or$ls180.v:3994$441_Y
+    connect \A $or$ls180.v:4069$489_Y
+    connect \B $and$ls180.v:4069$491_Y
+    connect \Y $or$ls180.v:4069$492_Y
   end
-  attribute \src "ls180.v:3999.91-3999.180"
-  cell $or $or$ls180.v:3999$451
+  attribute \src "ls180.v:4074.91-4074.180"
+  cell $or $or$ls180.v:4074$502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked3
-    connect \B $and$ls180.v:3999$450_Y
-    connect \Y $or$ls180.v:3999$451_Y
+    connect \B $and$ls180.v:4074$501_Y
+    connect \Y $or$ls180.v:4074$502_Y
   end
-  attribute \src "ls180.v:3999.90-3999.255"
-  cell $or $or$ls180.v:3999$454
+  attribute \src "ls180.v:4074.90-4074.255"
+  cell $or $or$ls180.v:4074$505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3999$451_Y
-    connect \B $and$ls180.v:3999$453_Y
-    connect \Y $or$ls180.v:3999$454_Y
+    connect \A $or$ls180.v:4074$502_Y
+    connect \B $and$ls180.v:4074$504_Y
+    connect \Y $or$ls180.v:4074$505_Y
   end
-  attribute \src "ls180.v:3999.89-3999.330"
-  cell $or $or$ls180.v:3999$457
+  attribute \src "ls180.v:4074.89-4074.330"
+  cell $or $or$ls180.v:4074$508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3999$454_Y
-    connect \B $and$ls180.v:3999$456_Y
-    connect \Y $or$ls180.v:3999$457_Y
+    connect \A $or$ls180.v:4074$505_Y
+    connect \B $and$ls180.v:4074$507_Y
+    connect \Y $or$ls180.v:4074$508_Y
   end
-  attribute \src "ls180.v:4004.132-4004.221"
-  cell $or $or$ls180.v:4004$468
+  attribute \src "ls180.v:4079.132-4079.221"
+  cell $or $or$ls180.v:4079$519
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked0
-    connect \B $and$ls180.v:4004$467_Y
-    connect \Y $or$ls180.v:4004$468_Y
+    connect \B $and$ls180.v:4079$518_Y
+    connect \Y $or$ls180.v:4079$519_Y
   end
-  attribute \src "ls180.v:4004.131-4004.296"
-  cell $or $or$ls180.v:4004$471
+  attribute \src "ls180.v:4079.131-4079.296"
+  cell $or $or$ls180.v:4079$522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$468_Y
-    connect \B $and$ls180.v:4004$470_Y
-    connect \Y $or$ls180.v:4004$471_Y
+    connect \A $or$ls180.v:4079$519_Y
+    connect \B $and$ls180.v:4079$521_Y
+    connect \Y $or$ls180.v:4079$522_Y
   end
-  attribute \src "ls180.v:4004.130-4004.371"
-  cell $or $or$ls180.v:4004$474
+  attribute \src "ls180.v:4079.130-4079.371"
+  cell $or $or$ls180.v:4079$525
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$471_Y
-    connect \B $and$ls180.v:4004$473_Y
-    connect \Y $or$ls180.v:4004$474_Y
+    connect \A $or$ls180.v:4079$522_Y
+    connect \B $and$ls180.v:4079$524_Y
+    connect \Y $or$ls180.v:4079$525_Y
   end
-  attribute \src "ls180.v:4004.34-4004.411"
-  cell $or $or$ls180.v:4004$479
+  attribute \src "ls180.v:4079.34-4079.411"
+  cell $or $or$ls180.v:4079$530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:4004$478_Y
-    connect \Y $or$ls180.v:4004$479_Y
+    connect \B $and$ls180.v:4079$529_Y
+    connect \Y $or$ls180.v:4079$530_Y
   end
-  attribute \src "ls180.v:4004.506-4004.595"
-  cell $or $or$ls180.v:4004$484
+  attribute \src "ls180.v:4079.506-4079.595"
+  cell $or $or$ls180.v:4079$535
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked1
-    connect \B $and$ls180.v:4004$483_Y
-    connect \Y $or$ls180.v:4004$484_Y
+    connect \B $and$ls180.v:4079$534_Y
+    connect \Y $or$ls180.v:4079$535_Y
   end
-  attribute \src "ls180.v:4004.505-4004.670"
-  cell $or $or$ls180.v:4004$487
+  attribute \src "ls180.v:4079.505-4079.670"
+  cell $or $or$ls180.v:4079$538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$484_Y
-    connect \B $and$ls180.v:4004$486_Y
-    connect \Y $or$ls180.v:4004$487_Y
+    connect \A $or$ls180.v:4079$535_Y
+    connect \B $and$ls180.v:4079$537_Y
+    connect \Y $or$ls180.v:4079$538_Y
   end
-  attribute \src "ls180.v:4004.504-4004.745"
-  cell $or $or$ls180.v:4004$490
+  attribute \src "ls180.v:4079.504-4079.745"
+  cell $or $or$ls180.v:4079$541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$487_Y
-    connect \B $and$ls180.v:4004$489_Y
-    connect \Y $or$ls180.v:4004$490_Y
+    connect \A $or$ls180.v:4079$538_Y
+    connect \B $and$ls180.v:4079$540_Y
+    connect \Y $or$ls180.v:4079$541_Y
   end
-  attribute \src "ls180.v:4004.33-4004.785"
-  cell $or $or$ls180.v:4004$495
+  attribute \src "ls180.v:4079.33-4079.785"
+  cell $or $or$ls180.v:4079$546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$479_Y
-    connect \B $and$ls180.v:4004$494_Y
-    connect \Y $or$ls180.v:4004$495_Y
+    connect \A $or$ls180.v:4079$530_Y
+    connect \B $and$ls180.v:4079$545_Y
+    connect \Y $or$ls180.v:4079$546_Y
   end
-  attribute \src "ls180.v:4004.880-4004.969"
-  cell $or $or$ls180.v:4004$500
+  attribute \src "ls180.v:4079.880-4079.969"
+  cell $or $or$ls180.v:4079$551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked2
-    connect \B $and$ls180.v:4004$499_Y
-    connect \Y $or$ls180.v:4004$500_Y
+    connect \B $and$ls180.v:4079$550_Y
+    connect \Y $or$ls180.v:4079$551_Y
   end
-  attribute \src "ls180.v:4004.879-4004.1044"
-  cell $or $or$ls180.v:4004$503
+  attribute \src "ls180.v:4079.879-4079.1044"
+  cell $or $or$ls180.v:4079$554
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$500_Y
-    connect \B $and$ls180.v:4004$502_Y
-    connect \Y $or$ls180.v:4004$503_Y
+    connect \A $or$ls180.v:4079$551_Y
+    connect \B $and$ls180.v:4079$553_Y
+    connect \Y $or$ls180.v:4079$554_Y
   end
-  attribute \src "ls180.v:4004.878-4004.1119"
-  cell $or $or$ls180.v:4004$506
+  attribute \src "ls180.v:4079.878-4079.1119"
+  cell $or $or$ls180.v:4079$557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$503_Y
-    connect \B $and$ls180.v:4004$505_Y
-    connect \Y $or$ls180.v:4004$506_Y
+    connect \A $or$ls180.v:4079$554_Y
+    connect \B $and$ls180.v:4079$556_Y
+    connect \Y $or$ls180.v:4079$557_Y
   end
-  attribute \src "ls180.v:4004.32-4004.1159"
-  cell $or $or$ls180.v:4004$511
+  attribute \src "ls180.v:4079.32-4079.1159"
+  cell $or $or$ls180.v:4079$562
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$495_Y
-    connect \B $and$ls180.v:4004$510_Y
-    connect \Y $or$ls180.v:4004$511_Y
+    connect \A $or$ls180.v:4079$546_Y
+    connect \B $and$ls180.v:4079$561_Y
+    connect \Y $or$ls180.v:4079$562_Y
   end
-  attribute \src "ls180.v:4004.1254-4004.1343"
-  cell $or $or$ls180.v:4004$516
+  attribute \src "ls180.v:4079.1254-4079.1343"
+  cell $or $or$ls180.v:4079$567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked3
-    connect \B $and$ls180.v:4004$515_Y
-    connect \Y $or$ls180.v:4004$516_Y
+    connect \B $and$ls180.v:4079$566_Y
+    connect \Y $or$ls180.v:4079$567_Y
   end
-  attribute \src "ls180.v:4004.1253-4004.1418"
-  cell $or $or$ls180.v:4004$519
+  attribute \src "ls180.v:4079.1253-4079.1418"
+  cell $or $or$ls180.v:4079$570
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$516_Y
-    connect \B $and$ls180.v:4004$518_Y
-    connect \Y $or$ls180.v:4004$519_Y
+    connect \A $or$ls180.v:4079$567_Y
+    connect \B $and$ls180.v:4079$569_Y
+    connect \Y $or$ls180.v:4079$570_Y
   end
-  attribute \src "ls180.v:4004.1252-4004.1493"
-  cell $or $or$ls180.v:4004$522
+  attribute \src "ls180.v:4079.1252-4079.1493"
+  cell $or $or$ls180.v:4079$573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$519_Y
-    connect \B $and$ls180.v:4004$521_Y
-    connect \Y $or$ls180.v:4004$522_Y
+    connect \A $or$ls180.v:4079$570_Y
+    connect \B $and$ls180.v:4079$572_Y
+    connect \Y $or$ls180.v:4079$573_Y
   end
-  attribute \src "ls180.v:4004.31-4004.1533"
-  cell $or $or$ls180.v:4004$527
+  attribute \src "ls180.v:4079.31-4079.1533"
+  cell $or $or$ls180.v:4079$578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4004$511_Y
-    connect \B $and$ls180.v:4004$526_Y
-    connect \Y $or$ls180.v:4004$527_Y
+    connect \A $or$ls180.v:4079$562_Y
+    connect \B $and$ls180.v:4079$577_Y
+    connect \Y $or$ls180.v:4079$578_Y
   end
-  attribute \src "ls180.v:4067.10-4067.52"
-  cell $or $or$ls180.v:4067$536
+  attribute \src "ls180.v:4142.10-4142.52"
+  cell $or $or$ls180.v:4142$587
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257934,10 +259128,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_ack
     connect \B \main_converter_skip
-    connect \Y $or$ls180.v:4067$536_Y
+    connect \Y $or$ls180.v:4142$587_Y
   end
-  attribute \src "ls180.v:4094.35-4094.74"
-  cell $or $or$ls180.v:4094$546
+  attribute \src "ls180.v:4169.35-4169.74"
+  cell $or $or$ls180.v:4169$597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257945,10 +259139,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_valid
     connect \B \main_cmd_consumed
-    connect \Y $or$ls180.v:4094$546_Y
+    connect \Y $or$ls180.v:4169$597_Y
   end
-  attribute \src "ls180.v:4095.34-4095.73"
-  cell $or $or$ls180.v:4095$550
+  attribute \src "ls180.v:4170.34-4170.73"
+  cell $or $or$ls180.v:4170$601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257956,76 +259150,76 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_valid
     connect \B \main_cmd_consumed
-    connect \Y $or$ls180.v:4095$550_Y
+    connect \Y $or$ls180.v:4170$601_Y
   end
-  attribute \src "ls180.v:4096.48-4096.130"
-  cell $or $or$ls180.v:4096$556
+  attribute \src "ls180.v:4171.48-4171.130"
+  cell $or $or$ls180.v:4171$607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4096$553_Y
-    connect \B $and$ls180.v:4096$555_Y
-    connect \Y $or$ls180.v:4096$556_Y
+    connect \A $and$ls180.v:4171$604_Y
+    connect \B $and$ls180.v:4171$606_Y
+    connect \Y $or$ls180.v:4171$607_Y
   end
-  attribute \src "ls180.v:4097.24-4097.87"
-  cell $or $or$ls180.v:4097$559
+  attribute \src "ls180.v:4172.24-4172.87"
+  cell $or $or$ls180.v:4172$610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4097$558_Y
+    connect \A $and$ls180.v:4172$609_Y
     connect \B \main_cmd_consumed
-    connect \Y $or$ls180.v:4097$559_Y
+    connect \Y $or$ls180.v:4172$610_Y
   end
-  attribute \src "ls180.v:4098.26-4098.95"
-  cell $or $or$ls180.v:4098$561
+  attribute \src "ls180.v:4173.26-4173.95"
+  cell $or $or$ls180.v:4173$612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4098$560_Y
+    connect \A $and$ls180.v:4173$611_Y
     connect \B \main_wdata_consumed
-    connect \Y $or$ls180.v:4098$561_Y
+    connect \Y $or$ls180.v:4173$612_Y
   end
-  attribute \src "ls180.v:4128.42-4128.89"
-  cell $or $or$ls180.v:4128$569
+  attribute \src "ls180.v:4203.42-4203.89"
+  cell $or $or$ls180.v:4203$620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_clear
-    connect \B $and$ls180.v:4128$568_Y
-    connect \Y $or$ls180.v:4128$569_Y
+    connect \B $and$ls180.v:4203$619_Y
+    connect \Y $or$ls180.v:4203$620_Y
   end
-  attribute \src "ls180.v:4152.25-4152.174"
-  cell $or $or$ls180.v:4152$579
+  attribute \src "ls180.v:4227.25-4227.174"
+  cell $or $or$ls180.v:4227$630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4152$577_Y
-    connect \B $and$ls180.v:4152$578_Y
-    connect \Y $or$ls180.v:4152$579_Y
+    connect \A $and$ls180.v:4227$628_Y
+    connect \B $and$ls180.v:4227$629_Y
+    connect \Y $or$ls180.v:4227$630_Y
   end
-  attribute \src "ls180.v:4167.80-4167.132"
-  cell $or $or$ls180.v:4167$581
+  attribute \src "ls180.v:4242.80-4242.132"
+  cell $or $or$ls180.v:4242$632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4167$580_Y
+    connect \A $not$ls180.v:4242$631_Y
     connect \B \main_uart_tx_fifo_re
-    connect \Y $or$ls180.v:4167$581_Y
+    connect \Y $or$ls180.v:4242$632_Y
   end
-  attribute \src "ls180.v:4178.72-4178.135"
-  cell $or $or$ls180.v:4178$586
+  attribute \src "ls180.v:4253.72-4253.135"
+  cell $or $or$ls180.v:4253$637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258033,21 +259227,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_writable
     connect \B \main_uart_tx_fifo_replace
-    connect \Y $or$ls180.v:4178$586_Y
+    connect \Y $or$ls180.v:4253$637_Y
   end
-  attribute \src "ls180.v:4197.80-4197.132"
-  cell $or $or$ls180.v:4197$592
+  attribute \src "ls180.v:4272.80-4272.132"
+  cell $or $or$ls180.v:4272$643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4197$591_Y
+    connect \A $not$ls180.v:4272$642_Y
     connect \B \main_uart_rx_fifo_re
-    connect \Y $or$ls180.v:4197$592_Y
+    connect \Y $or$ls180.v:4272$643_Y
   end
-  attribute \src "ls180.v:4208.72-4208.135"
-  cell $or $or$ls180.v:4208$597
+  attribute \src "ls180.v:4283.72-4283.135"
+  cell $or $or$ls180.v:4283$648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258055,10 +259249,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_writable
     connect \B \main_uart_rx_fifo_replace
-    connect \Y $or$ls180.v:4208$597_Y
+    connect \Y $or$ls180.v:4283$648_Y
   end
-  attribute \src "ls180.v:4342.36-4342.111"
-  cell $or $or$ls180.v:4342$618
+  attribute \src "ls180.v:4417.36-4417.111"
+  cell $or $or$ls180.v:4417$669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258066,43 +259260,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_init_pads_out_payload_clk
     connect \B \main_sdphy_cmdw_pads_out_payload_clk
-    connect \Y $or$ls180.v:4342$618_Y
+    connect \Y $or$ls180.v:4417$669_Y
   end
-  attribute \src "ls180.v:4342.35-4342.151"
-  cell $or $or$ls180.v:4342$619
+  attribute \src "ls180.v:4417.35-4417.151"
+  cell $or $or$ls180.v:4417$670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4342$618_Y
+    connect \A $or$ls180.v:4417$669_Y
     connect \B \main_sdphy_cmdr_pads_out_payload_clk
-    connect \Y $or$ls180.v:4342$619_Y
+    connect \Y $or$ls180.v:4417$670_Y
   end
-  attribute \src "ls180.v:4342.34-4342.192"
-  cell $or $or$ls180.v:4342$620
+  attribute \src "ls180.v:4417.34-4417.192"
+  cell $or $or$ls180.v:4417$671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4342$619_Y
+    connect \A $or$ls180.v:4417$670_Y
     connect \B \main_sdphy_dataw_pads_out_payload_clk
-    connect \Y $or$ls180.v:4342$620_Y
+    connect \Y $or$ls180.v:4417$671_Y
   end
-  attribute \src "ls180.v:4342.33-4342.233"
-  cell $or $or$ls180.v:4342$621
+  attribute \src "ls180.v:4417.33-4417.233"
+  cell $or $or$ls180.v:4417$672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4342$620_Y
+    connect \A $or$ls180.v:4417$671_Y
     connect \B \main_sdphy_datar_pads_out_payload_clk
-    connect \Y $or$ls180.v:4342$621_Y
+    connect \Y $or$ls180.v:4417$672_Y
   end
-  attribute \src "ls180.v:4343.39-4343.120"
-  cell $or $or$ls180.v:4343$622
+  attribute \src "ls180.v:4418.39-4418.120"
+  cell $or $or$ls180.v:4418$673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258110,43 +259304,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_init_pads_out_payload_cmd_oe
     connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe
-    connect \Y $or$ls180.v:4343$622_Y
+    connect \Y $or$ls180.v:4418$673_Y
   end
-  attribute \src "ls180.v:4343.38-4343.163"
-  cell $or $or$ls180.v:4343$623
+  attribute \src "ls180.v:4418.38-4418.163"
+  cell $or $or$ls180.v:4418$674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4343$622_Y
+    connect \A $or$ls180.v:4418$673_Y
     connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe
-    connect \Y $or$ls180.v:4343$623_Y
+    connect \Y $or$ls180.v:4418$674_Y
   end
-  attribute \src "ls180.v:4343.37-4343.207"
-  cell $or $or$ls180.v:4343$624
+  attribute \src "ls180.v:4418.37-4418.207"
+  cell $or $or$ls180.v:4418$675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4343$623_Y
+    connect \A $or$ls180.v:4418$674_Y
     connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe
-    connect \Y $or$ls180.v:4343$624_Y
+    connect \Y $or$ls180.v:4418$675_Y
   end
-  attribute \src "ls180.v:4343.36-4343.251"
-  cell $or $or$ls180.v:4343$625
+  attribute \src "ls180.v:4418.36-4418.251"
+  cell $or $or$ls180.v:4418$676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4343$624_Y
+    connect \A $or$ls180.v:4418$675_Y
     connect \B \main_sdphy_datar_pads_out_payload_cmd_oe
-    connect \Y $or$ls180.v:4343$625_Y
+    connect \Y $or$ls180.v:4418$676_Y
   end
-  attribute \src "ls180.v:4344.38-4344.117"
-  cell $or $or$ls180.v:4344$626
+  attribute \src "ls180.v:4419.38-4419.117"
+  cell $or $or$ls180.v:4419$677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258154,43 +259348,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_init_pads_out_payload_cmd_o
     connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o
-    connect \Y $or$ls180.v:4344$626_Y
+    connect \Y $or$ls180.v:4419$677_Y
   end
-  attribute \src "ls180.v:4344.37-4344.159"
-  cell $or $or$ls180.v:4344$627
+  attribute \src "ls180.v:4419.37-4419.159"
+  cell $or $or$ls180.v:4419$678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4344$626_Y
+    connect \A $or$ls180.v:4419$677_Y
     connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o
-    connect \Y $or$ls180.v:4344$627_Y
+    connect \Y $or$ls180.v:4419$678_Y
   end
-  attribute \src "ls180.v:4344.36-4344.202"
-  cell $or $or$ls180.v:4344$628
+  attribute \src "ls180.v:4419.36-4419.202"
+  cell $or $or$ls180.v:4419$679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4344$627_Y
+    connect \A $or$ls180.v:4419$678_Y
     connect \B \main_sdphy_dataw_pads_out_payload_cmd_o
-    connect \Y $or$ls180.v:4344$628_Y
+    connect \Y $or$ls180.v:4419$679_Y
   end
-  attribute \src "ls180.v:4344.35-4344.245"
-  cell $or $or$ls180.v:4344$629
+  attribute \src "ls180.v:4419.35-4419.245"
+  cell $or $or$ls180.v:4419$680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4344$628_Y
+    connect \A $or$ls180.v:4419$679_Y
     connect \B \main_sdphy_datar_pads_out_payload_cmd_o
-    connect \Y $or$ls180.v:4344$629_Y
+    connect \Y $or$ls180.v:4419$680_Y
   end
-  attribute \src "ls180.v:4345.40-4345.123"
-  cell $or $or$ls180.v:4345$630
+  attribute \src "ls180.v:4420.40-4420.123"
+  cell $or $or$ls180.v:4420$681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258198,43 +259392,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_init_pads_out_payload_data_oe
     connect \B \main_sdphy_cmdw_pads_out_payload_data_oe
-    connect \Y $or$ls180.v:4345$630_Y
+    connect \Y $or$ls180.v:4420$681_Y
   end
-  attribute \src "ls180.v:4345.39-4345.167"
-  cell $or $or$ls180.v:4345$631
+  attribute \src "ls180.v:4420.39-4420.167"
+  cell $or $or$ls180.v:4420$682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4345$630_Y
+    connect \A $or$ls180.v:4420$681_Y
     connect \B \main_sdphy_cmdr_pads_out_payload_data_oe
-    connect \Y $or$ls180.v:4345$631_Y
+    connect \Y $or$ls180.v:4420$682_Y
   end
-  attribute \src "ls180.v:4345.38-4345.212"
-  cell $or $or$ls180.v:4345$632
+  attribute \src "ls180.v:4420.38-4420.212"
+  cell $or $or$ls180.v:4420$683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4345$631_Y
+    connect \A $or$ls180.v:4420$682_Y
     connect \B \main_sdphy_dataw_pads_out_payload_data_oe
-    connect \Y $or$ls180.v:4345$632_Y
+    connect \Y $or$ls180.v:4420$683_Y
   end
-  attribute \src "ls180.v:4345.37-4345.257"
-  cell $or $or$ls180.v:4345$633
+  attribute \src "ls180.v:4420.37-4420.257"
+  cell $or $or$ls180.v:4420$684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4345$632_Y
+    connect \A $or$ls180.v:4420$683_Y
     connect \B \main_sdphy_datar_pads_out_payload_data_oe
-    connect \Y $or$ls180.v:4345$633_Y
+    connect \Y $or$ls180.v:4420$684_Y
   end
-  attribute \src "ls180.v:4346.39-4346.120"
-  cell $or $or$ls180.v:4346$634
+  attribute \src "ls180.v:4421.39-4421.120"
+  cell $or $or$ls180.v:4421$685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -258242,43 +259436,43 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdphy_init_pads_out_payload_data_o
     connect \B \main_sdphy_cmdw_pads_out_payload_data_o
-    connect \Y $or$ls180.v:4346$634_Y
+    connect \Y $or$ls180.v:4421$685_Y
   end
-  attribute \src "ls180.v:4346.38-4346.163"
-  cell $or $or$ls180.v:4346$635
+  attribute \src "ls180.v:4421.38-4421.163"
+  cell $or $or$ls180.v:4421$686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A $or$ls180.v:4346$634_Y
+    connect \A $or$ls180.v:4421$685_Y
     connect \B \main_sdphy_cmdr_pads_out_payload_data_o
-    connect \Y $or$ls180.v:4346$635_Y
+    connect \Y $or$ls180.v:4421$686_Y
   end
-  attribute \src "ls180.v:4346.37-4346.207"
-  cell $or $or$ls180.v:4346$636
+  attribute \src "ls180.v:4421.37-4421.207"
+  cell $or $or$ls180.v:4421$687
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A $or$ls180.v:4346$635_Y
+    connect \A $or$ls180.v:4421$686_Y
     connect \B \main_sdphy_dataw_pads_out_payload_data_o
-    connect \Y $or$ls180.v:4346$636_Y
+    connect \Y $or$ls180.v:4421$687_Y
   end
-  attribute \src "ls180.v:4346.36-4346.251"
-  cell $or $or$ls180.v:4346$637
+  attribute \src "ls180.v:4421.36-4421.251"
+  cell $or $or$ls180.v:4421$688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A $or$ls180.v:4346$636_Y
+    connect \A $or$ls180.v:4421$687_Y
     connect \B \main_sdphy_datar_pads_out_payload_data_o
-    connect \Y $or$ls180.v:4346$637_Y
+    connect \Y $or$ls180.v:4421$688_Y
   end
-  attribute \src "ls180.v:4367.35-4367.80"
-  cell $or $or$ls180.v:4367$638
+  attribute \src "ls180.v:4442.35-4442.80"
+  cell $or $or$ls180.v:4442$689
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258286,10 +259480,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_stop
     connect \B \main_sdphy_datar_stop
-    connect \Y $or$ls180.v:4367$638_Y
+    connect \Y $or$ls180.v:4442$689_Y
   end
-  attribute \src "ls180.v:4521.91-4521.144"
-  cell $or $or$ls180.v:4521$652
+  attribute \src "ls180.v:4596.91-4596.144"
+  cell $or $or$ls180.v:4596$703
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258297,76 +259491,76 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_start
     connect \B \main_sdphy_cmdr_cmdr_run
-    connect \Y $or$ls180.v:4521$652_Y
+    connect \Y $or$ls180.v:4596$703_Y
   end
-  attribute \src "ls180.v:4538.53-4538.143"
-  cell $or $or$ls180.v:4538$655
+  attribute \src "ls180.v:4613.53-4613.143"
+  cell $or $or$ls180.v:4613$706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4538$654_Y
+    connect \A $not$ls180.v:4613$705_Y
     connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
-    connect \Y $or$ls180.v:4538$655_Y
+    connect \Y $or$ls180.v:4613$706_Y
   end
-  attribute \src "ls180.v:4541.47-4541.127"
-  cell $or $or$ls180.v:4541$658
+  attribute \src "ls180.v:4616.47-4616.127"
+  cell $or $or$ls180.v:4616$709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4541$657_Y
+    connect \A $not$ls180.v:4616$708_Y
     connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
-    connect \Y $or$ls180.v:4541$658_Y
+    connect \Y $or$ls180.v:4616$709_Y
   end
-  attribute \src "ls180.v:4665.54-4665.146"
-  cell $or $or$ls180.v:4665$676
+  attribute \src "ls180.v:4740.54-4740.146"
+  cell $or $or$ls180.v:4740$727
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4665$675_Y
+    connect \A $not$ls180.v:4740$726_Y
     connect \B \main_sdphy_dataw_crcr_converter_source_ready
-    connect \Y $or$ls180.v:4665$676_Y
+    connect \Y $or$ls180.v:4740$727_Y
   end
-  attribute \src "ls180.v:4668.48-4668.130"
-  cell $or $or$ls180.v:4668$679
+  attribute \src "ls180.v:4743.48-4743.130"
+  cell $or $or$ls180.v:4743$730
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4668$678_Y
+    connect \A $not$ls180.v:4743$729_Y
     connect \B \main_sdphy_dataw_crcr_buf_source_ready
-    connect \Y $or$ls180.v:4668$679_Y
+    connect \Y $or$ls180.v:4743$730_Y
   end
-  attribute \src "ls180.v:4799.55-4799.149"
-  cell $or $or$ls180.v:4799$691
+  attribute \src "ls180.v:4874.55-4874.149"
+  cell $or $or$ls180.v:4874$742
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4799$690_Y
+    connect \A $not$ls180.v:4874$741_Y
     connect \B \main_sdphy_datar_datar_converter_source_ready
-    connect \Y $or$ls180.v:4799$691_Y
+    connect \Y $or$ls180.v:4874$742_Y
   end
-  attribute \src "ls180.v:4802.49-4802.133"
-  cell $or $or$ls180.v:4802$694
+  attribute \src "ls180.v:4877.49-4877.133"
+  cell $or $or$ls180.v:4877$745
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4802$693_Y
+    connect \A $not$ls180.v:4877$744_Y
     connect \B \main_sdphy_datar_datar_buf_source_ready
-    connect \Y $or$ls180.v:4802$694_Y
+    connect \Y $or$ls180.v:4877$745_Y
   end
-  attribute \src "ls180.v:5431.80-5431.151"
-  cell $or $or$ls180.v:5431$989
+  attribute \src "ls180.v:5506.80-5506.151"
+  cell $or $or$ls180.v:5506$1040
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258374,21 +259568,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_writable
     connect \B \main_sdblock2mem_fifo_replace
-    connect \Y $or$ls180.v:5431$989_Y
+    connect \Y $or$ls180.v:5506$1040_Y
   end
-  attribute \src "ls180.v:5442.49-5442.131"
-  cell $or $or$ls180.v:5442$995
+  attribute \src "ls180.v:5517.49-5517.131"
+  cell $or $or$ls180.v:5517$1046
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:5442$994_Y
+    connect \A $not$ls180.v:5517$1045_Y
     connect \B \main_sdblock2mem_converter_source_ready
-    connect \Y $or$ls180.v:5442$995_Y
+    connect \Y $or$ls180.v:5517$1046_Y
   end
-  attribute \src "ls180.v:5639.80-5639.151"
-  cell $or $or$ls180.v:5639$1020
+  attribute \src "ls180.v:5714.80-5714.151"
+  cell $or $or$ls180.v:5714$1071
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258396,142 +259590,241 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_writable
     connect \B \main_sdmem2block_fifo_replace
-    connect \Y $or$ls180.v:5639$1020_Y
+    connect \Y $or$ls180.v:5714$1071_Y
   end
-  attribute \src "ls180.v:5754.33-5754.102"
-  cell $or $or$ls180.v:5754$1060
+  attribute \src "ls180.v:5856.36-5856.94"
+  cell $or $or$ls180.v:5856$1117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_err
+    connect \B \main_interface0_ram_bus_err
+    connect \Y $or$ls180.v:5856$1117_Y
+  end
+  attribute \src "ls180.v:5856.35-5856.125"
+  cell $or $or$ls180.v:5856$1118
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5856$1117_Y
+    connect \B \main_interface1_ram_bus_err
+    connect \Y $or$ls180.v:5856$1118_Y
+  end
+  attribute \src "ls180.v:5856.34-5856.156"
+  cell $or $or$ls180.v:5856$1119
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5856$1118_Y
+    connect \B \main_interface2_ram_bus_err
+    connect \Y $or$ls180.v:5856$1119_Y
+  end
+  attribute \src "ls180.v:5856.33-5856.198"
+  cell $or $or$ls180.v:5856$1120
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5856$1119_Y
     connect \B \main_libresocsim_libresoc_xics_icp_err
-    connect \Y $or$ls180.v:5754$1060_Y
+    connect \Y $or$ls180.v:5856$1120_Y
   end
-  attribute \src "ls180.v:5754.32-5754.144"
-  cell $or $or$ls180.v:5754$1061
+  attribute \src "ls180.v:5856.32-5856.240"
+  cell $or $or$ls180.v:5856$1121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5754$1060_Y
+    connect \A $or$ls180.v:5856$1120_Y
     connect \B \main_libresocsim_libresoc_xics_ics_err
-    connect \Y $or$ls180.v:5754$1061_Y
+    connect \Y $or$ls180.v:5856$1121_Y
   end
-  attribute \src "ls180.v:5754.31-5754.165"
-  cell $or $or$ls180.v:5754$1062
+  attribute \src "ls180.v:5856.31-5856.261"
+  cell $or $or$ls180.v:5856$1122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5754$1061_Y
+    connect \A $or$ls180.v:5856$1121_Y
     connect \B \main_wb_sdram_err
-    connect \Y $or$ls180.v:5754$1062_Y
+    connect \Y $or$ls180.v:5856$1122_Y
   end
-  attribute \src "ls180.v:5754.30-5754.201"
-  cell $or $or$ls180.v:5754$1063
+  attribute \src "ls180.v:5856.30-5856.297"
+  cell $or $or$ls180.v:5856$1123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5754$1062_Y
+    connect \A $or$ls180.v:5856$1122_Y
     connect \B \builder_libresocsim_wishbone_err
-    connect \Y $or$ls180.v:5754$1063_Y
+    connect \Y $or$ls180.v:5856$1123_Y
   end
-  attribute \src "ls180.v:5760.28-5760.97"
-  cell $or $or$ls180.v:5760$1068
+  attribute \src "ls180.v:5862.31-5862.89"
+  cell $or $or$ls180.v:5862$1128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_ack
+    connect \B \main_interface0_ram_bus_ack
+    connect \Y $or$ls180.v:5862$1128_Y
+  end
+  attribute \src "ls180.v:5862.30-5862.120"
+  cell $or $or$ls180.v:5862$1129
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5862$1128_Y
+    connect \B \main_interface1_ram_bus_ack
+    connect \Y $or$ls180.v:5862$1129_Y
+  end
+  attribute \src "ls180.v:5862.29-5862.151"
+  cell $or $or$ls180.v:5862$1130
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5862$1129_Y
+    connect \B \main_interface2_ram_bus_ack
+    connect \Y $or$ls180.v:5862$1130_Y
+  end
+  attribute \src "ls180.v:5862.28-5862.193"
+  cell $or $or$ls180.v:5862$1131
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $or$ls180.v:5862$1130_Y
     connect \B \main_libresocsim_libresoc_xics_icp_ack
-    connect \Y $or$ls180.v:5760$1068_Y
+    connect \Y $or$ls180.v:5862$1131_Y
   end
-  attribute \src "ls180.v:5760.27-5760.139"
-  cell $or $or$ls180.v:5760$1069
+  attribute \src "ls180.v:5862.27-5862.235"
+  cell $or $or$ls180.v:5862$1132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5760$1068_Y
+    connect \A $or$ls180.v:5862$1131_Y
     connect \B \main_libresocsim_libresoc_xics_ics_ack
-    connect \Y $or$ls180.v:5760$1069_Y
+    connect \Y $or$ls180.v:5862$1132_Y
   end
-  attribute \src "ls180.v:5760.26-5760.160"
-  cell $or $or$ls180.v:5760$1070
+  attribute \src "ls180.v:5862.26-5862.256"
+  cell $or $or$ls180.v:5862$1133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5760$1069_Y
+    connect \A $or$ls180.v:5862$1132_Y
     connect \B \main_wb_sdram_ack
-    connect \Y $or$ls180.v:5760$1070_Y
+    connect \Y $or$ls180.v:5862$1133_Y
   end
-  attribute \src "ls180.v:5760.25-5760.196"
-  cell $or $or$ls180.v:5760$1071
+  attribute \src "ls180.v:5862.25-5862.292"
+  cell $or $or$ls180.v:5862$1134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:5760$1070_Y
+    connect \A $or$ls180.v:5862$1133_Y
     connect \B \builder_libresocsim_wishbone_ack
-    connect \Y $or$ls180.v:5760$1071_Y
+    connect \Y $or$ls180.v:5862$1134_Y
+  end
+  attribute \src "ls180.v:5863.33-5863.161"
+  cell $or $or$ls180.v:5863$1137
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $and$ls180.v:5863$1135_Y
+    connect \B $and$ls180.v:5863$1136_Y
+    connect \Y $or$ls180.v:5863$1137_Y
   end
-  attribute \src "ls180.v:5761.30-5761.169"
-  cell $or $or$ls180.v:5761$1074
+  attribute \src "ls180.v:5863.32-5863.227"
+  cell $or $or$ls180.v:5863$1139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
-    connect \A $and$ls180.v:5761$1072_Y
-    connect \B $and$ls180.v:5761$1073_Y
-    connect \Y $or$ls180.v:5761$1074_Y
+    connect \A $or$ls180.v:5863$1137_Y
+    connect \B $and$ls180.v:5863$1138_Y
+    connect \Y $or$ls180.v:5863$1139_Y
   end
-  attribute \src "ls180.v:5761.29-5761.246"
-  cell $or $or$ls180.v:5761$1076
+  attribute \src "ls180.v:5863.31-5863.293"
+  cell $or $or$ls180.v:5863$1141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
-    connect \A $or$ls180.v:5761$1074_Y
-    connect \B $and$ls180.v:5761$1075_Y
-    connect \Y $or$ls180.v:5761$1076_Y
+    connect \A $or$ls180.v:5863$1139_Y
+    connect \B $and$ls180.v:5863$1140_Y
+    connect \Y $or$ls180.v:5863$1141_Y
   end
-  attribute \src "ls180.v:5761.28-5761.302"
-  cell $or $or$ls180.v:5761$1078
+  attribute \src "ls180.v:5863.30-5863.370"
+  cell $or $or$ls180.v:5863$1143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
-    connect \A $or$ls180.v:5761$1076_Y
-    connect \B $and$ls180.v:5761$1077_Y
-    connect \Y $or$ls180.v:5761$1078_Y
+    connect \A $or$ls180.v:5863$1141_Y
+    connect \B $and$ls180.v:5863$1142_Y
+    connect \Y $or$ls180.v:5863$1143_Y
   end
-  attribute \src "ls180.v:5761.27-5761.373"
-  cell $or $or$ls180.v:5761$1080
+  attribute \src "ls180.v:5863.29-5863.447"
+  cell $or $or$ls180.v:5863$1145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 32
-    connect \A $or$ls180.v:5761$1078_Y
-    connect \B $and$ls180.v:5761$1079_Y
-    connect \Y $or$ls180.v:5761$1080_Y
+    connect \A $or$ls180.v:5863$1143_Y
+    connect \B $and$ls180.v:5863$1144_Y
+    connect \Y $or$ls180.v:5863$1145_Y
   end
-  attribute \src "ls180.v:6515.55-6515.124"
-  cell $or $or$ls180.v:6515$2226
+  attribute \src "ls180.v:5863.28-5863.503"
+  cell $or $or$ls180.v:5863$1147
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:5863$1145_Y
+    connect \B $and$ls180.v:5863$1146_Y
+    connect \Y $or$ls180.v:5863$1147_Y
+  end
+  attribute \src "ls180.v:5863.27-5863.574"
+  cell $or $or$ls180.v:5863$1149
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:5863$1147_Y
+    connect \B $and$ls180.v:5863$1148_Y
+    connect \Y $or$ls180.v:5863$1149_Y
+  end
+  attribute \src "ls180.v:6617.55-6617.124"
+  cell $or $or$ls180.v:6617$2295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -258539,285 +259832,285 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \builder_interface0_bank_bus_dat_r
     connect \B \builder_interface1_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2226_Y
+    connect \Y $or$ls180.v:6617$2295_Y
   end
-  attribute \src "ls180.v:6515.54-6515.161"
-  cell $or $or$ls180.v:6515$2227
+  attribute \src "ls180.v:6617.54-6617.161"
+  cell $or $or$ls180.v:6617$2296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2226_Y
+    connect \A $or$ls180.v:6617$2295_Y
     connect \B \builder_interface2_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2227_Y
+    connect \Y $or$ls180.v:6617$2296_Y
   end
-  attribute \src "ls180.v:6515.53-6515.198"
-  cell $or $or$ls180.v:6515$2228
+  attribute \src "ls180.v:6617.53-6617.198"
+  cell $or $or$ls180.v:6617$2297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2227_Y
+    connect \A $or$ls180.v:6617$2296_Y
     connect \B \builder_interface3_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2228_Y
+    connect \Y $or$ls180.v:6617$2297_Y
   end
-  attribute \src "ls180.v:6515.52-6515.235"
-  cell $or $or$ls180.v:6515$2229
+  attribute \src "ls180.v:6617.52-6617.235"
+  cell $or $or$ls180.v:6617$2298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2228_Y
+    connect \A $or$ls180.v:6617$2297_Y
     connect \B \builder_interface4_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2229_Y
+    connect \Y $or$ls180.v:6617$2298_Y
   end
-  attribute \src "ls180.v:6515.51-6515.272"
-  cell $or $or$ls180.v:6515$2230
+  attribute \src "ls180.v:6617.51-6617.272"
+  cell $or $or$ls180.v:6617$2299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2229_Y
+    connect \A $or$ls180.v:6617$2298_Y
     connect \B \builder_interface5_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2230_Y
+    connect \Y $or$ls180.v:6617$2299_Y
   end
-  attribute \src "ls180.v:6515.50-6515.309"
-  cell $or $or$ls180.v:6515$2231
+  attribute \src "ls180.v:6617.50-6617.309"
+  cell $or $or$ls180.v:6617$2300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2230_Y
+    connect \A $or$ls180.v:6617$2299_Y
     connect \B \builder_interface6_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2231_Y
+    connect \Y $or$ls180.v:6617$2300_Y
   end
-  attribute \src "ls180.v:6515.49-6515.346"
-  cell $or $or$ls180.v:6515$2232
+  attribute \src "ls180.v:6617.49-6617.346"
+  cell $or $or$ls180.v:6617$2301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2231_Y
+    connect \A $or$ls180.v:6617$2300_Y
     connect \B \builder_interface7_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2232_Y
+    connect \Y $or$ls180.v:6617$2301_Y
   end
-  attribute \src "ls180.v:6515.48-6515.383"
-  cell $or $or$ls180.v:6515$2233
+  attribute \src "ls180.v:6617.48-6617.383"
+  cell $or $or$ls180.v:6617$2302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2232_Y
+    connect \A $or$ls180.v:6617$2301_Y
     connect \B \builder_interface8_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2233_Y
+    connect \Y $or$ls180.v:6617$2302_Y
   end
-  attribute \src "ls180.v:6515.47-6515.420"
-  cell $or $or$ls180.v:6515$2234
+  attribute \src "ls180.v:6617.47-6617.420"
+  cell $or $or$ls180.v:6617$2303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2233_Y
+    connect \A $or$ls180.v:6617$2302_Y
     connect \B \builder_interface9_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2234_Y
+    connect \Y $or$ls180.v:6617$2303_Y
   end
-  attribute \src "ls180.v:6515.46-6515.458"
-  cell $or $or$ls180.v:6515$2235
+  attribute \src "ls180.v:6617.46-6617.458"
+  cell $or $or$ls180.v:6617$2304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2234_Y
+    connect \A $or$ls180.v:6617$2303_Y
     connect \B \builder_interface10_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2235_Y
+    connect \Y $or$ls180.v:6617$2304_Y
   end
-  attribute \src "ls180.v:6515.45-6515.496"
-  cell $or $or$ls180.v:6515$2236
+  attribute \src "ls180.v:6617.45-6617.496"
+  cell $or $or$ls180.v:6617$2305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2235_Y
+    connect \A $or$ls180.v:6617$2304_Y
     connect \B \builder_interface11_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2236_Y
+    connect \Y $or$ls180.v:6617$2305_Y
   end
-  attribute \src "ls180.v:6515.44-6515.534"
-  cell $or $or$ls180.v:6515$2237
+  attribute \src "ls180.v:6617.44-6617.534"
+  cell $or $or$ls180.v:6617$2306
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2236_Y
+    connect \A $or$ls180.v:6617$2305_Y
     connect \B \builder_interface12_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2237_Y
+    connect \Y $or$ls180.v:6617$2306_Y
   end
-  attribute \src "ls180.v:6515.43-6515.572"
-  cell $or $or$ls180.v:6515$2238
+  attribute \src "ls180.v:6617.43-6617.572"
+  cell $or $or$ls180.v:6617$2307
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2237_Y
+    connect \A $or$ls180.v:6617$2306_Y
     connect \B \builder_interface13_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2238_Y
+    connect \Y $or$ls180.v:6617$2307_Y
   end
-  attribute \src "ls180.v:6515.42-6515.610"
-  cell $or $or$ls180.v:6515$2239
+  attribute \src "ls180.v:6617.42-6617.610"
+  cell $or $or$ls180.v:6617$2308
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:6515$2238_Y
+    connect \A $or$ls180.v:6617$2307_Y
     connect \B \builder_interface14_bank_bus_dat_r
-    connect \Y $or$ls180.v:6515$2239_Y
+    connect \Y $or$ls180.v:6617$2308_Y
   end
-  attribute \src "ls180.v:6842.90-6842.179"
-  cell $or $or$ls180.v:6842$2264
+  attribute \src "ls180.v:6944.90-6944.179"
+  cell $or $or$ls180.v:6944$2333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked0
-    connect \B $and$ls180.v:6842$2263_Y
-    connect \Y $or$ls180.v:6842$2264_Y
+    connect \B $and$ls180.v:6944$2332_Y
+    connect \Y $or$ls180.v:6944$2333_Y
   end
-  attribute \src "ls180.v:6842.89-6842.254"
-  cell $or $or$ls180.v:6842$2267
+  attribute \src "ls180.v:6944.89-6944.254"
+  cell $or $or$ls180.v:6944$2336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6842$2264_Y
-    connect \B $and$ls180.v:6842$2266_Y
-    connect \Y $or$ls180.v:6842$2267_Y
+    connect \A $or$ls180.v:6944$2333_Y
+    connect \B $and$ls180.v:6944$2335_Y
+    connect \Y $or$ls180.v:6944$2336_Y
   end
-  attribute \src "ls180.v:6842.88-6842.329"
-  cell $or $or$ls180.v:6842$2270
+  attribute \src "ls180.v:6944.88-6944.329"
+  cell $or $or$ls180.v:6944$2339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6842$2267_Y
-    connect \B $and$ls180.v:6842$2269_Y
-    connect \Y $or$ls180.v:6842$2270_Y
+    connect \A $or$ls180.v:6944$2336_Y
+    connect \B $and$ls180.v:6944$2338_Y
+    connect \Y $or$ls180.v:6944$2339_Y
   end
-  attribute \src "ls180.v:6866.90-6866.179"
-  cell $or $or$ls180.v:6866$2280
+  attribute \src "ls180.v:6968.90-6968.179"
+  cell $or $or$ls180.v:6968$2349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked1
-    connect \B $and$ls180.v:6866$2279_Y
-    connect \Y $or$ls180.v:6866$2280_Y
+    connect \B $and$ls180.v:6968$2348_Y
+    connect \Y $or$ls180.v:6968$2349_Y
   end
-  attribute \src "ls180.v:6866.89-6866.254"
-  cell $or $or$ls180.v:6866$2283
+  attribute \src "ls180.v:6968.89-6968.254"
+  cell $or $or$ls180.v:6968$2352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6866$2280_Y
-    connect \B $and$ls180.v:6866$2282_Y
-    connect \Y $or$ls180.v:6866$2283_Y
+    connect \A $or$ls180.v:6968$2349_Y
+    connect \B $and$ls180.v:6968$2351_Y
+    connect \Y $or$ls180.v:6968$2352_Y
   end
-  attribute \src "ls180.v:6866.88-6866.329"
-  cell $or $or$ls180.v:6866$2286
+  attribute \src "ls180.v:6968.88-6968.329"
+  cell $or $or$ls180.v:6968$2355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6866$2283_Y
-    connect \B $and$ls180.v:6866$2285_Y
-    connect \Y $or$ls180.v:6866$2286_Y
+    connect \A $or$ls180.v:6968$2352_Y
+    connect \B $and$ls180.v:6968$2354_Y
+    connect \Y $or$ls180.v:6968$2355_Y
   end
-  attribute \src "ls180.v:6890.90-6890.179"
-  cell $or $or$ls180.v:6890$2296
+  attribute \src "ls180.v:6992.90-6992.179"
+  cell $or $or$ls180.v:6992$2365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked2
-    connect \B $and$ls180.v:6890$2295_Y
-    connect \Y $or$ls180.v:6890$2296_Y
+    connect \B $and$ls180.v:6992$2364_Y
+    connect \Y $or$ls180.v:6992$2365_Y
   end
-  attribute \src "ls180.v:6890.89-6890.254"
-  cell $or $or$ls180.v:6890$2299
+  attribute \src "ls180.v:6992.89-6992.254"
+  cell $or $or$ls180.v:6992$2368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6890$2296_Y
-    connect \B $and$ls180.v:6890$2298_Y
-    connect \Y $or$ls180.v:6890$2299_Y
+    connect \A $or$ls180.v:6992$2365_Y
+    connect \B $and$ls180.v:6992$2367_Y
+    connect \Y $or$ls180.v:6992$2368_Y
   end
-  attribute \src "ls180.v:6890.88-6890.329"
-  cell $or $or$ls180.v:6890$2302
+  attribute \src "ls180.v:6992.88-6992.329"
+  cell $or $or$ls180.v:6992$2371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6890$2299_Y
-    connect \B $and$ls180.v:6890$2301_Y
-    connect \Y $or$ls180.v:6890$2302_Y
+    connect \A $or$ls180.v:6992$2368_Y
+    connect \B $and$ls180.v:6992$2370_Y
+    connect \Y $or$ls180.v:6992$2371_Y
   end
-  attribute \src "ls180.v:6914.90-6914.179"
-  cell $or $or$ls180.v:6914$2312
+  attribute \src "ls180.v:7016.90-7016.179"
+  cell $or $or$ls180.v:7016$2381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_locked3
-    connect \B $and$ls180.v:6914$2311_Y
-    connect \Y $or$ls180.v:6914$2312_Y
+    connect \B $and$ls180.v:7016$2380_Y
+    connect \Y $or$ls180.v:7016$2381_Y
   end
-  attribute \src "ls180.v:6914.89-6914.254"
-  cell $or $or$ls180.v:6914$2315
+  attribute \src "ls180.v:7016.89-7016.254"
+  cell $or $or$ls180.v:7016$2384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6914$2312_Y
-    connect \B $and$ls180.v:6914$2314_Y
-    connect \Y $or$ls180.v:6914$2315_Y
+    connect \A $or$ls180.v:7016$2381_Y
+    connect \B $and$ls180.v:7016$2383_Y
+    connect \Y $or$ls180.v:7016$2384_Y
   end
-  attribute \src "ls180.v:6914.88-6914.329"
-  cell $or $or$ls180.v:6914$2318
+  attribute \src "ls180.v:7016.88-7016.329"
+  cell $or $or$ls180.v:7016$2387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:6914$2315_Y
-    connect \B $and$ls180.v:6914$2317_Y
-    connect \Y $or$ls180.v:6914$2318_Y
+    connect \A $or$ls180.v:7016$2384_Y
+    connect \B $and$ls180.v:7016$2386_Y
+    connect \Y $or$ls180.v:7016$2387_Y
   end
-  attribute \src "ls180.v:7428.20-7428.71"
-  cell $or $or$ls180.v:7428$2375
+  attribute \src "ls180.v:7530.20-7530.71"
+  cell $or $or$ls180.v:7530$2444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258825,10 +260118,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [0]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7428$2375_Y
+    connect \Y $or$ls180.v:7530$2444_Y
   end
-  attribute \src "ls180.v:7429.20-7429.71"
-  cell $or $or$ls180.v:7429$2376
+  attribute \src "ls180.v:7531.20-7531.71"
+  cell $or $or$ls180.v:7531$2445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258836,10 +260129,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [1]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7429$2376_Y
+    connect \Y $or$ls180.v:7531$2445_Y
   end
-  attribute \src "ls180.v:7430.20-7430.71"
-  cell $or $or$ls180.v:7430$2377
+  attribute \src "ls180.v:7532.20-7532.71"
+  cell $or $or$ls180.v:7532$2446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258847,10 +260140,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [2]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7430$2377_Y
+    connect \Y $or$ls180.v:7532$2446_Y
   end
-  attribute \src "ls180.v:7431.20-7431.71"
-  cell $or $or$ls180.v:7431$2378
+  attribute \src "ls180.v:7533.20-7533.71"
+  cell $or $or$ls180.v:7533$2447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258858,10 +260151,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [3]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7431$2378_Y
+    connect \Y $or$ls180.v:7533$2447_Y
   end
-  attribute \src "ls180.v:7432.20-7432.71"
-  cell $or $or$ls180.v:7432$2379
+  attribute \src "ls180.v:7534.20-7534.71"
+  cell $or $or$ls180.v:7534$2448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258869,10 +260162,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [4]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7432$2379_Y
+    connect \Y $or$ls180.v:7534$2448_Y
   end
-  attribute \src "ls180.v:7433.20-7433.71"
-  cell $or $or$ls180.v:7433$2380
+  attribute \src "ls180.v:7535.20-7535.71"
+  cell $or $or$ls180.v:7535$2449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258880,10 +260173,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [5]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7433$2380_Y
+    connect \Y $or$ls180.v:7535$2449_Y
   end
-  attribute \src "ls180.v:7434.20-7434.71"
-  cell $or $or$ls180.v:7434$2381
+  attribute \src "ls180.v:7536.20-7536.71"
+  cell $or $or$ls180.v:7536$2450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258891,10 +260184,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [6]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7434$2381_Y
+    connect \Y $or$ls180.v:7536$2450_Y
   end
-  attribute \src "ls180.v:7435.20-7435.71"
-  cell $or $or$ls180.v:7435$2382
+  attribute \src "ls180.v:7537.20-7537.71"
+  cell $or $or$ls180.v:7537$2451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258902,10 +260195,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [7]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7435$2382_Y
+    connect \Y $or$ls180.v:7537$2451_Y
   end
-  attribute \src "ls180.v:7436.20-7436.71"
-  cell $or $or$ls180.v:7436$2383
+  attribute \src "ls180.v:7538.20-7538.71"
+  cell $or $or$ls180.v:7538$2452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258913,10 +260206,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [8]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7436$2383_Y
+    connect \Y $or$ls180.v:7538$2452_Y
   end
-  attribute \src "ls180.v:7437.20-7437.71"
-  cell $or $or$ls180.v:7437$2384
+  attribute \src "ls180.v:7539.20-7539.71"
+  cell $or $or$ls180.v:7539$2453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258924,10 +260217,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [9]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7437$2384_Y
+    connect \Y $or$ls180.v:7539$2453_Y
   end
-  attribute \src "ls180.v:7438.21-7438.73"
-  cell $or $or$ls180.v:7438$2385
+  attribute \src "ls180.v:7540.21-7540.73"
+  cell $or $or$ls180.v:7540$2454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258935,10 +260228,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [10]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7438$2385_Y
+    connect \Y $or$ls180.v:7540$2454_Y
   end
-  attribute \src "ls180.v:7439.21-7439.73"
-  cell $or $or$ls180.v:7439$2386
+  attribute \src "ls180.v:7541.21-7541.73"
+  cell $or $or$ls180.v:7541$2455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258946,10 +260239,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [11]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7439$2386_Y
+    connect \Y $or$ls180.v:7541$2455_Y
   end
-  attribute \src "ls180.v:7440.21-7440.73"
-  cell $or $or$ls180.v:7440$2387
+  attribute \src "ls180.v:7542.21-7542.73"
+  cell $or $or$ls180.v:7542$2456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258957,10 +260250,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [12]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7440$2387_Y
+    connect \Y $or$ls180.v:7542$2456_Y
   end
-  attribute \src "ls180.v:7441.21-7441.73"
-  cell $or $or$ls180.v:7441$2388
+  attribute \src "ls180.v:7543.21-7543.73"
+  cell $or $or$ls180.v:7543$2457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258968,10 +260261,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [13]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7441$2388_Y
+    connect \Y $or$ls180.v:7543$2457_Y
   end
-  attribute \src "ls180.v:7442.21-7442.73"
-  cell $or $or$ls180.v:7442$2389
+  attribute \src "ls180.v:7544.21-7544.73"
+  cell $or $or$ls180.v:7544$2458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258979,10 +260272,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [14]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7442$2389_Y
+    connect \Y $or$ls180.v:7544$2458_Y
   end
-  attribute \src "ls180.v:7443.21-7443.73"
-  cell $or $or$ls180.v:7443$2390
+  attribute \src "ls180.v:7545.21-7545.73"
+  cell $or $or$ls180.v:7545$2459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258990,10 +260283,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [15]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7443$2390_Y
+    connect \Y $or$ls180.v:7545$2459_Y
   end
-  attribute \src "ls180.v:7444.21-7444.73"
-  cell $or $or$ls180.v:7444$2391
+  attribute \src "ls180.v:7546.21-7546.73"
+  cell $or $or$ls180.v:7546$2460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259001,10 +260294,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [16]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7444$2391_Y
+    connect \Y $or$ls180.v:7546$2460_Y
   end
-  attribute \src "ls180.v:7445.21-7445.73"
-  cell $or $or$ls180.v:7445$2392
+  attribute \src "ls180.v:7547.21-7547.73"
+  cell $or $or$ls180.v:7547$2461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259012,10 +260305,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [17]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7445$2392_Y
+    connect \Y $or$ls180.v:7547$2461_Y
   end
-  attribute \src "ls180.v:7446.21-7446.73"
-  cell $or $or$ls180.v:7446$2393
+  attribute \src "ls180.v:7548.21-7548.73"
+  cell $or $or$ls180.v:7548$2462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259023,10 +260316,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [18]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7446$2393_Y
+    connect \Y $or$ls180.v:7548$2462_Y
   end
-  attribute \src "ls180.v:7447.21-7447.73"
-  cell $or $or$ls180.v:7447$2394
+  attribute \src "ls180.v:7549.21-7549.73"
+  cell $or $or$ls180.v:7549$2463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259034,10 +260327,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [19]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7447$2394_Y
+    connect \Y $or$ls180.v:7549$2463_Y
   end
-  attribute \src "ls180.v:7448.21-7448.73"
-  cell $or $or$ls180.v:7448$2395
+  attribute \src "ls180.v:7550.21-7550.73"
+  cell $or $or$ls180.v:7550$2464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259045,10 +260338,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [20]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7448$2395_Y
+    connect \Y $or$ls180.v:7550$2464_Y
   end
-  attribute \src "ls180.v:7449.21-7449.73"
-  cell $or $or$ls180.v:7449$2396
+  attribute \src "ls180.v:7551.21-7551.73"
+  cell $or $or$ls180.v:7551$2465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259056,10 +260349,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [21]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7449$2396_Y
+    connect \Y $or$ls180.v:7551$2465_Y
   end
-  attribute \src "ls180.v:7450.21-7450.73"
-  cell $or $or$ls180.v:7450$2397
+  attribute \src "ls180.v:7552.21-7552.73"
+  cell $or $or$ls180.v:7552$2466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259067,10 +260360,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [22]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7450$2397_Y
+    connect \Y $or$ls180.v:7552$2466_Y
   end
-  attribute \src "ls180.v:7451.21-7451.73"
-  cell $or $or$ls180.v:7451$2398
+  attribute \src "ls180.v:7553.21-7553.73"
+  cell $or $or$ls180.v:7553$2467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259078,10 +260371,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_nc [23]
     connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7451$2398_Y
+    connect \Y $or$ls180.v:7553$2467_Y
   end
-  attribute \src "ls180.v:7452.7-7452.93"
-  cell $or $or$ls180.v:7452$2399
+  attribute \src "ls180.v:7554.7-7554.93"
+  cell $or $or$ls180.v:7554$2468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259089,10 +260382,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface0_converted_interface_ack
     connect \B \main_libresocsim_converter0_skip
-    connect \Y $or$ls180.v:7452$2399_Y
+    connect \Y $or$ls180.v:7554$2468_Y
   end
-  attribute \src "ls180.v:7463.7-7463.93"
-  cell $or $or$ls180.v:7463$2400
+  attribute \src "ls180.v:7565.7-7565.93"
+  cell $or $or$ls180.v:7565$2469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259100,10 +260393,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface1_converted_interface_ack
     connect \B \main_libresocsim_converter1_skip
-    connect \Y $or$ls180.v:7463$2400_Y
+    connect \Y $or$ls180.v:7565$2469_Y
   end
-  attribute \src "ls180.v:7474.7-7474.93"
-  cell $or $or$ls180.v:7474$2401
+  attribute \src "ls180.v:7576.7-7576.93"
+  cell $or $or$ls180.v:7576$2470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259111,142 +260404,142 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface2_converted_interface_ack
     connect \B \main_libresocsim_converter2_skip
-    connect \Y $or$ls180.v:7474$2401_Y
+    connect \Y $or$ls180.v:7576$2470_Y
   end
-  attribute \src "ls180.v:7603.7-7603.107"
-  cell $or $or$ls180.v:7603$2437
+  attribute \src "ls180.v:7717.7-7717.107"
+  cell $or $or$ls180.v:7717$2515
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7603$2436_Y
+    connect \A $not$ls180.v:7717$2514_Y
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7603$2437_Y
+    connect \Y $or$ls180.v:7717$2515_Y
   end
-  attribute \src "ls180.v:7649.7-7649.107"
-  cell $or $or$ls180.v:7649$2453
+  attribute \src "ls180.v:7763.7-7763.107"
+  cell $or $or$ls180.v:7763$2531
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7649$2452_Y
+    connect \A $not$ls180.v:7763$2530_Y
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7649$2453_Y
+    connect \Y $or$ls180.v:7763$2531_Y
   end
-  attribute \src "ls180.v:7695.7-7695.107"
-  cell $or $or$ls180.v:7695$2469
+  attribute \src "ls180.v:7809.7-7809.107"
+  cell $or $or$ls180.v:7809$2547
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7695$2468_Y
+    connect \A $not$ls180.v:7809$2546_Y
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7695$2469_Y
+    connect \Y $or$ls180.v:7809$2547_Y
   end
-  attribute \src "ls180.v:7741.7-7741.107"
-  cell $or $or$ls180.v:7741$2485
+  attribute \src "ls180.v:7855.7-7855.107"
+  cell $or $or$ls180.v:7855$2563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7741$2484_Y
+    connect \A $not$ls180.v:7855$2562_Y
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7741$2485_Y
+    connect \Y $or$ls180.v:7855$2563_Y
   end
-  attribute \src "ls180.v:7929.40-7929.125"
-  cell $or $or$ls180.v:7929$2506
+  attribute \src "ls180.v:8043.40-8043.125"
+  cell $or $or$ls180.v:8043$2584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:7929$2505_Y
-    connect \Y $or$ls180.v:7929$2506_Y
+    connect \B $and$ls180.v:8043$2583_Y
+    connect \Y $or$ls180.v:8043$2584_Y
   end
-  attribute \src "ls180.v:7929.39-7929.207"
-  cell $or $or$ls180.v:7929$2509
+  attribute \src "ls180.v:8043.39-8043.207"
+  cell $or $or$ls180.v:8043$2587
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7929$2506_Y
-    connect \B $and$ls180.v:7929$2508_Y
-    connect \Y $or$ls180.v:7929$2509_Y
+    connect \A $or$ls180.v:8043$2584_Y
+    connect \B $and$ls180.v:8043$2586_Y
+    connect \Y $or$ls180.v:8043$2587_Y
   end
-  attribute \src "ls180.v:7929.38-7929.289"
-  cell $or $or$ls180.v:7929$2512
+  attribute \src "ls180.v:8043.38-8043.289"
+  cell $or $or$ls180.v:8043$2590
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7929$2509_Y
-    connect \B $and$ls180.v:7929$2511_Y
-    connect \Y $or$ls180.v:7929$2512_Y
+    connect \A $or$ls180.v:8043$2587_Y
+    connect \B $and$ls180.v:8043$2589_Y
+    connect \Y $or$ls180.v:8043$2590_Y
   end
-  attribute \src "ls180.v:7929.37-7929.371"
-  cell $or $or$ls180.v:7929$2515
+  attribute \src "ls180.v:8043.37-8043.371"
+  cell $or $or$ls180.v:8043$2593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7929$2512_Y
-    connect \B $and$ls180.v:7929$2514_Y
-    connect \Y $or$ls180.v:7929$2515_Y
+    connect \A $or$ls180.v:8043$2590_Y
+    connect \B $and$ls180.v:8043$2592_Y
+    connect \Y $or$ls180.v:8043$2593_Y
   end
-  attribute \src "ls180.v:7930.41-7930.126"
-  cell $or $or$ls180.v:7930$2518
+  attribute \src "ls180.v:8044.41-8044.126"
+  cell $or $or$ls180.v:8044$2596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:7930$2517_Y
-    connect \Y $or$ls180.v:7930$2518_Y
+    connect \B $and$ls180.v:8044$2595_Y
+    connect \Y $or$ls180.v:8044$2596_Y
   end
-  attribute \src "ls180.v:7930.40-7930.208"
-  cell $or $or$ls180.v:7930$2521
+  attribute \src "ls180.v:8044.40-8044.208"
+  cell $or $or$ls180.v:8044$2599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7930$2518_Y
-    connect \B $and$ls180.v:7930$2520_Y
-    connect \Y $or$ls180.v:7930$2521_Y
+    connect \A $or$ls180.v:8044$2596_Y
+    connect \B $and$ls180.v:8044$2598_Y
+    connect \Y $or$ls180.v:8044$2599_Y
   end
-  attribute \src "ls180.v:7930.39-7930.290"
-  cell $or $or$ls180.v:7930$2524
+  attribute \src "ls180.v:8044.39-8044.290"
+  cell $or $or$ls180.v:8044$2602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7930$2521_Y
-    connect \B $and$ls180.v:7930$2523_Y
-    connect \Y $or$ls180.v:7930$2524_Y
+    connect \A $or$ls180.v:8044$2599_Y
+    connect \B $and$ls180.v:8044$2601_Y
+    connect \Y $or$ls180.v:8044$2602_Y
   end
-  attribute \src "ls180.v:7930.38-7930.372"
-  cell $or $or$ls180.v:7930$2527
+  attribute \src "ls180.v:8044.38-8044.372"
+  cell $or $or$ls180.v:8044$2605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7930$2524_Y
-    connect \B $and$ls180.v:7930$2526_Y
-    connect \Y $or$ls180.v:7930$2527_Y
+    connect \A $or$ls180.v:8044$2602_Y
+    connect \B $and$ls180.v:8044$2604_Y
+    connect \Y $or$ls180.v:8044$2605_Y
   end
-  attribute \src "ls180.v:7934.7-7934.49"
-  cell $or $or$ls180.v:7934$2528
+  attribute \src "ls180.v:8048.7-8048.49"
+  cell $or $or$ls180.v:8048$2606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259254,32 +260547,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_ack
     connect \B \main_converter_skip
-    connect \Y $or$ls180.v:7934$2528_Y
+    connect \Y $or$ls180.v:8048$2606_Y
   end
-  attribute \src "ls180.v:8097.21-8097.74"
-  cell $or $or$ls180.v:8097$2576
+  attribute \src "ls180.v:8211.21-8211.74"
+  cell $or $or$ls180.v:8211$2654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8097$2574_Y
-    connect \B $not$ls180.v:8097$2575_Y
-    connect \Y $or$ls180.v:8097$2576_Y
+    connect \A $not$ls180.v:8211$2652_Y
+    connect \B $not$ls180.v:8211$2653_Y
+    connect \Y $or$ls180.v:8211$2654_Y
   end
-  attribute \src "ls180.v:8132.21-8132.71"
-  cell $or $or$ls180.v:8132$2581
+  attribute \src "ls180.v:8246.21-8246.71"
+  cell $or $or$ls180.v:8246$2659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8132$2579_Y
-    connect \B $not$ls180.v:8132$2580_Y
-    connect \Y $or$ls180.v:8132$2581_Y
+    connect \A $not$ls180.v:8246$2657_Y
+    connect \B $not$ls180.v:8246$2658_Y
+    connect \Y $or$ls180.v:8246$2659_Y
   end
-  attribute \src "ls180.v:8200.32-8200.85"
-  cell $or $or$ls180.v:8200$2593
+  attribute \src "ls180.v:8314.32-8314.85"
+  cell $or $or$ls180.v:8314$2671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259287,21 +260580,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_start
     connect \B \main_sdphy_cmdr_cmdr_run
-    connect \Y $or$ls180.v:8200$2593_Y
+    connect \Y $or$ls180.v:8314$2671_Y
   end
-  attribute \src "ls180.v:8206.8-8206.97"
-  cell $or $or$ls180.v:8206$2595
+  attribute \src "ls180.v:8320.8-8320.97"
+  cell $or $or$ls180.v:8320$2673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8206$2594_Y
+    connect \A $eq$ls180.v:8320$2672_Y
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_last
-    connect \Y $or$ls180.v:8206$2595_Y
+    connect \Y $or$ls180.v:8320$2673_Y
   end
-  attribute \src "ls180.v:8223.52-8223.139"
-  cell $or $or$ls180.v:8223$2600
+  attribute \src "ls180.v:8337.52-8337.139"
+  cell $or $or$ls180.v:8337$2678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259309,10 +260602,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_first
     connect \B \main_sdphy_cmdr_cmdr_converter_source_first
-    connect \Y $or$ls180.v:8223$2600_Y
+    connect \Y $or$ls180.v:8337$2678_Y
   end
-  attribute \src "ls180.v:8224.51-8224.136"
-  cell $or $or$ls180.v:8224$2601
+  attribute \src "ls180.v:8338.51-8338.136"
+  cell $or $or$ls180.v:8338$2679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259320,21 +260613,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_last
     connect \B \main_sdphy_cmdr_cmdr_converter_source_last
-    connect \Y $or$ls180.v:8224$2601_Y
+    connect \Y $or$ls180.v:8338$2679_Y
   end
-  attribute \src "ls180.v:8258.7-8258.87"
-  cell $or $or$ls180.v:8258$2604
+  attribute \src "ls180.v:8372.7-8372.87"
+  cell $or $or$ls180.v:8372$2682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8258$2603_Y
+    connect \A $not$ls180.v:8372$2681_Y
     connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
-    connect \Y $or$ls180.v:8258$2604_Y
+    connect \Y $or$ls180.v:8372$2682_Y
   end
-  attribute \src "ls180.v:8281.33-8281.88"
-  cell $or $or$ls180.v:8281$2605
+  attribute \src "ls180.v:8395.33-8395.88"
+  cell $or $or$ls180.v:8395$2683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259342,21 +260635,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_start
     connect \B \main_sdphy_dataw_crcr_run
-    connect \Y $or$ls180.v:8281$2605_Y
+    connect \Y $or$ls180.v:8395$2683_Y
   end
-  attribute \src "ls180.v:8287.8-8287.99"
-  cell $or $or$ls180.v:8287$2607
+  attribute \src "ls180.v:8401.8-8401.99"
+  cell $or $or$ls180.v:8401$2685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8287$2606_Y
+    connect \A $eq$ls180.v:8401$2684_Y
     connect \B \main_sdphy_dataw_crcr_converter_sink_last
-    connect \Y $or$ls180.v:8287$2607_Y
+    connect \Y $or$ls180.v:8401$2685_Y
   end
-  attribute \src "ls180.v:8304.53-8304.142"
-  cell $or $or$ls180.v:8304$2612
+  attribute \src "ls180.v:8418.53-8418.142"
+  cell $or $or$ls180.v:8418$2690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259364,10 +260657,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_first
     connect \B \main_sdphy_dataw_crcr_converter_source_first
-    connect \Y $or$ls180.v:8304$2612_Y
+    connect \Y $or$ls180.v:8418$2690_Y
   end
-  attribute \src "ls180.v:8305.52-8305.139"
-  cell $or $or$ls180.v:8305$2613
+  attribute \src "ls180.v:8419.52-8419.139"
+  cell $or $or$ls180.v:8419$2691
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259375,21 +260668,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_last
     connect \B \main_sdphy_dataw_crcr_converter_source_last
-    connect \Y $or$ls180.v:8305$2613_Y
+    connect \Y $or$ls180.v:8419$2691_Y
   end
-  attribute \src "ls180.v:8339.7-8339.89"
-  cell $or $or$ls180.v:8339$2616
+  attribute \src "ls180.v:8453.7-8453.89"
+  cell $or $or$ls180.v:8453$2694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8339$2615_Y
+    connect \A $not$ls180.v:8453$2693_Y
     connect \B \main_sdphy_dataw_crcr_buf_source_ready
-    connect \Y $or$ls180.v:8339$2616_Y
+    connect \Y $or$ls180.v:8453$2694_Y
   end
-  attribute \src "ls180.v:8360.34-8360.91"
-  cell $or $or$ls180.v:8360$2617
+  attribute \src "ls180.v:8474.34-8474.91"
+  cell $or $or$ls180.v:8474$2695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259397,21 +260690,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_start
     connect \B \main_sdphy_datar_datar_run
-    connect \Y $or$ls180.v:8360$2617_Y
+    connect \Y $or$ls180.v:8474$2695_Y
   end
-  attribute \src "ls180.v:8366.8-8366.101"
-  cell $or $or$ls180.v:8366$2619
+  attribute \src "ls180.v:8480.8-8480.101"
+  cell $or $or$ls180.v:8480$2697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8366$2618_Y
+    connect \A $eq$ls180.v:8480$2696_Y
     connect \B \main_sdphy_datar_datar_converter_sink_last
-    connect \Y $or$ls180.v:8366$2619_Y
+    connect \Y $or$ls180.v:8480$2697_Y
   end
-  attribute \src "ls180.v:8383.54-8383.145"
-  cell $or $or$ls180.v:8383$2624
+  attribute \src "ls180.v:8497.54-8497.145"
+  cell $or $or$ls180.v:8497$2702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259419,10 +260712,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_first
     connect \B \main_sdphy_datar_datar_converter_source_first
-    connect \Y $or$ls180.v:8383$2624_Y
+    connect \Y $or$ls180.v:8497$2702_Y
   end
-  attribute \src "ls180.v:8384.53-8384.142"
-  cell $or $or$ls180.v:8384$2625
+  attribute \src "ls180.v:8498.53-8498.142"
+  cell $or $or$ls180.v:8498$2703
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259430,32 +260723,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_last
     connect \B \main_sdphy_datar_datar_converter_source_last
-    connect \Y $or$ls180.v:8384$2625_Y
+    connect \Y $or$ls180.v:8498$2703_Y
   end
-  attribute \src "ls180.v:8400.7-8400.91"
-  cell $or $or$ls180.v:8400$2628
+  attribute \src "ls180.v:8514.7-8514.91"
+  cell $or $or$ls180.v:8514$2706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8400$2627_Y
+    connect \A $not$ls180.v:8514$2705_Y
     connect \B \main_sdphy_datar_datar_buf_source_ready
-    connect \Y $or$ls180.v:8400$2628_Y
+    connect \Y $or$ls180.v:8514$2706_Y
   end
-  attribute \src "ls180.v:8589.8-8589.89"
-  cell $or $or$ls180.v:8589$2652
+  attribute \src "ls180.v:8703.8-8703.89"
+  cell $or $or$ls180.v:8703$2730
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8589$2651_Y
+    connect \A $eq$ls180.v:8703$2729_Y
     connect \B \main_sdblock2mem_converter_sink_last
-    connect \Y $or$ls180.v:8589$2652_Y
+    connect \Y $or$ls180.v:8703$2730_Y
   end
-  attribute \src "ls180.v:8606.48-8606.127"
-  cell $or $or$ls180.v:8606$2657
+  attribute \src "ls180.v:8720.48-8720.127"
+  cell $or $or$ls180.v:8720$2735
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259463,10 +260756,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_first
     connect \B \main_sdblock2mem_converter_source_first
-    connect \Y $or$ls180.v:8606$2657_Y
+    connect \Y $or$ls180.v:8720$2735_Y
   end
-  attribute \src "ls180.v:8607.47-8607.124"
-  cell $or $or$ls180.v:8607$2658
+  attribute \src "ls180.v:8721.47-8721.124"
+  cell $or $or$ls180.v:8721$2736
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259474,10 +260767,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_last
     connect \B \main_sdblock2mem_converter_source_last
-    connect \Y $or$ls180.v:8607$2658_Y
+    connect \Y $or$ls180.v:8721$2736_Y
   end
-  attribute \src "ls180.v:3178.46-3178.94"
-  cell $sshl $sshl$ls180.v:3178$83
+  attribute \src "ls180.v:3253.46-3253.94"
+  cell $sshl $sshl$ls180.v:3253$134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259485,10 +260778,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \main_sdram_bankmachine0_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:3178$83_Y
+    connect \Y $sshl$ls180.v:3253$134_Y
   end
-  attribute \src "ls180.v:3335.46-3335.94"
-  cell $sshl $sshl$ls180.v:3335$113
+  attribute \src "ls180.v:3410.46-3410.94"
+  cell $sshl $sshl$ls180.v:3410$164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259496,10 +260789,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \main_sdram_bankmachine1_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:3335$113_Y
+    connect \Y $sshl$ls180.v:3410$164_Y
   end
-  attribute \src "ls180.v:3492.46-3492.94"
-  cell $sshl $sshl$ls180.v:3492$143
+  attribute \src "ls180.v:3567.46-3567.94"
+  cell $sshl $sshl$ls180.v:3567$194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259507,10 +260800,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \main_sdram_bankmachine2_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:3492$143_Y
+    connect \Y $sshl$ls180.v:3567$194_Y
   end
-  attribute \src "ls180.v:3649.46-3649.94"
-  cell $sshl $sshl$ls180.v:3649$173
+  attribute \src "ls180.v:3724.46-3724.94"
+  cell $sshl $sshl$ls180.v:3724$224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259518,10 +260811,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \main_sdram_bankmachine3_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:3649$173_Y
+    connect \Y $sshl$ls180.v:3724$224_Y
   end
-  attribute \src "ls180.v:3209.63-3209.122"
-  cell $sub $sub$ls180.v:3209$96
+  attribute \src "ls180.v:3284.63-3284.122"
+  cell $sub $sub$ls180.v:3284$147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259529,10 +260822,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:3209$96_Y
+    connect \Y $sub$ls180.v:3284$147_Y
   end
-  attribute \src "ls180.v:3366.63-3366.122"
-  cell $sub $sub$ls180.v:3366$126
+  attribute \src "ls180.v:3441.63-3441.122"
+  cell $sub $sub$ls180.v:3441$177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259540,10 +260833,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:3366$126_Y
+    connect \Y $sub$ls180.v:3441$177_Y
   end
-  attribute \src "ls180.v:3523.63-3523.122"
-  cell $sub $sub$ls180.v:3523$156
+  attribute \src "ls180.v:3598.63-3598.122"
+  cell $sub $sub$ls180.v:3598$207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259551,10 +260844,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:3523$156_Y
+    connect \Y $sub$ls180.v:3598$207_Y
   end
-  attribute \src "ls180.v:3680.63-3680.122"
-  cell $sub $sub$ls180.v:3680$186
+  attribute \src "ls180.v:3755.63-3755.122"
+  cell $sub $sub$ls180.v:3755$237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259562,10 +260855,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:3680$186_Y
+    connect \Y $sub$ls180.v:3755$237_Y
   end
-  attribute \src "ls180.v:4086.38-4086.75"
-  cell $sub $sub$ls180.v:4086$540
+  attribute \src "ls180.v:4161.38-4161.75"
+  cell $sub $sub$ls180.v:4161$591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 30
     parameter \B_SIGNED 0
@@ -259573,10 +260866,10 @@ module \ls180
     parameter \Y_WIDTH 31
     connect \A \main_litedram_wb_adr
     connect \B 31'1001000000000000000000000000000
-    connect \Y $sub$ls180.v:4086$540_Y
+    connect \Y $sub$ls180.v:4161$591_Y
   end
-  attribute \src "ls180.v:4172.36-4172.68"
-  cell $sub $sub$ls180.v:4172$585
+  attribute \src "ls180.v:4247.36-4247.68"
+  cell $sub $sub$ls180.v:4247$636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259584,10 +260877,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_tx_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:4172$585_Y
+    connect \Y $sub$ls180.v:4247$636_Y
   end
-  attribute \src "ls180.v:4202.36-4202.68"
-  cell $sub $sub$ls180.v:4202$596
+  attribute \src "ls180.v:4277.36-4277.68"
+  cell $sub $sub$ls180.v:4277$647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259595,10 +260888,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_rx_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:4202$596_Y
+    connect \Y $sub$ls180.v:4277$647_Y
   end
-  attribute \src "ls180.v:4227.70-4227.110"
-  cell $sub $sub$ls180.v:4227$602
+  attribute \src "ls180.v:4302.70-4302.110"
+  cell $sub $sub$ls180.v:4302$653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 15
     parameter \B_SIGNED 0
@@ -259606,10 +260899,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spimaster8_clk_divider [15:1]
     connect \B 1'1
-    connect \Y $sub$ls180.v:4227$602_Y
+    connect \Y $sub$ls180.v:4302$653_Y
   end
-  attribute \src "ls180.v:4228.70-4228.104"
-  cell $sub $sub$ls180.v:4228$604
+  attribute \src "ls180.v:4303.70-4303.104"
+  cell $sub $sub$ls180.v:4303$655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -259617,10 +260910,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spimaster8_clk_divider
     connect \B 1'1
-    connect \Y $sub$ls180.v:4228$604_Y
+    connect \Y $sub$ls180.v:4303$655_Y
   end
-  attribute \src "ls180.v:4255.37-4255.66"
-  cell $sub $sub$ls180.v:4255$608
+  attribute \src "ls180.v:4330.37-4330.66"
+  cell $sub $sub$ls180.v:4330$659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -259628,10 +260921,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_spimaster1_length
     connect \B 1'1
-    connect \Y $sub$ls180.v:4255$608_Y
+    connect \Y $sub$ls180.v:4330$659_Y
   end
-  attribute \src "ls180.v:4285.67-4285.107"
-  cell $sub $sub$ls180.v:4285$610
+  attribute \src "ls180.v:4360.67-4360.107"
+  cell $sub $sub$ls180.v:4360$661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 15
     parameter \B_SIGNED 0
@@ -259639,10 +260932,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spisdcard_clk_divider0 [15:1]
     connect \B 1'1
-    connect \Y $sub$ls180.v:4285$610_Y
+    connect \Y $sub$ls180.v:4360$661_Y
   end
-  attribute \src "ls180.v:4286.67-4286.101"
-  cell $sub $sub$ls180.v:4286$612
+  attribute \src "ls180.v:4361.67-4361.101"
+  cell $sub $sub$ls180.v:4361$663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -259650,10 +260943,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spisdcard_clk_divider0
     connect \B 1'1
-    connect \Y $sub$ls180.v:4286$612_Y
+    connect \Y $sub$ls180.v:4361$663_Y
   end
-  attribute \src "ls180.v:4314.35-4314.64"
-  cell $sub $sub$ls180.v:4314$616
+  attribute \src "ls180.v:4389.35-4389.64"
+  cell $sub $sub$ls180.v:4389$667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -259661,10 +260954,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_spisdcard_length0
     connect \B 1'1
-    connect \Y $sub$ls180.v:4314$616_Y
+    connect \Y $sub$ls180.v:4389$667_Y
   end
-  attribute \src "ls180.v:4568.60-4568.90"
-  cell $sub $sub$ls180.v:4568$660
+  attribute \src "ls180.v:4643.60-4643.90"
+  cell $sub $sub$ls180.v:4643$711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259672,10 +260965,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdphy_cmdr_timeout
     connect \B 1'1
-    connect \Y $sub$ls180.v:4568$660_Y
+    connect \Y $sub$ls180.v:4643$711_Y
   end
-  attribute \src "ls180.v:4579.62-4579.104"
-  cell $sub $sub$ls180.v:4579$662
+  attribute \src "ls180.v:4654.62-4654.104"
+  cell $sub $sub$ls180.v:4654$713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -259683,10 +260976,10 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \main_sdphy_cmdr_sink_payload_length
     connect \B 1'1
-    connect \Y $sub$ls180.v:4579$662_Y
+    connect \Y $sub$ls180.v:4654$713_Y
   end
-  attribute \src "ls180.v:4596.60-4596.90"
-  cell $sub $sub$ls180.v:4596$666
+  attribute \src "ls180.v:4671.60-4671.90"
+  cell $sub $sub$ls180.v:4671$717
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259694,10 +260987,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdphy_cmdr_timeout
     connect \B 1'1
-    connect \Y $sub$ls180.v:4596$666_Y
+    connect \Y $sub$ls180.v:4671$717_Y
   end
-  attribute \src "ls180.v:4825.62-4825.93"
-  cell $sub $sub$ls180.v:4825$696
+  attribute \src "ls180.v:4900.62-4900.93"
+  cell $sub $sub$ls180.v:4900$747
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259705,10 +260998,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdphy_datar_timeout
     connect \B 1'1
-    connect \Y $sub$ls180.v:4825$696_Y
+    connect \Y $sub$ls180.v:4900$747_Y
   end
-  attribute \src "ls180.v:4830.62-4830.93"
-  cell $sub $sub$ls180.v:4830$697
+  attribute \src "ls180.v:4905.62-4905.93"
+  cell $sub $sub$ls180.v:4905$748
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259716,21 +261009,21 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdphy_datar_timeout
     connect \B 1'1
-    connect \Y $sub$ls180.v:4830$697_Y
+    connect \Y $sub$ls180.v:4905$748_Y
   end
-  attribute \src "ls180.v:4841.64-4841.122"
-  cell $sub $sub$ls180.v:4841$700
+  attribute \src "ls180.v:4916.64-4916.122"
+  cell $sub $sub$ls180.v:4916$751
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 10
-    connect \A $add$ls180.v:4841$699_Y
+    connect \A $add$ls180.v:4916$750_Y
     connect \B 1'1
-    connect \Y $sub$ls180.v:4841$700_Y
+    connect \Y $sub$ls180.v:4916$751_Y
   end
-  attribute \src "ls180.v:4862.62-4862.93"
-  cell $sub $sub$ls180.v:4862$703
+  attribute \src "ls180.v:4937.62-4937.93"
+  cell $sub $sub$ls180.v:4937$754
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259738,10 +261031,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdphy_datar_timeout
     connect \B 1'1
-    connect \Y $sub$ls180.v:4862$703_Y
+    connect \Y $sub$ls180.v:4937$754_Y
   end
-  attribute \src "ls180.v:5324.37-5324.75"
-  cell $sub $sub$ls180.v:5324$976
+  attribute \src "ls180.v:5399.37-5399.75"
+  cell $sub $sub$ls180.v:5399$1027
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259749,10 +261042,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdcore_block_count_storage
     connect \B 1'1
-    connect \Y $sub$ls180.v:5324$976_Y
+    connect \Y $sub$ls180.v:5399$1027_Y
   end
-  attribute \src "ls180.v:5339.62-5339.100"
-  cell $sub $sub$ls180.v:5339$979
+  attribute \src "ls180.v:5414.62-5414.100"
+  cell $sub $sub$ls180.v:5414$1030
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259760,10 +261053,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdcore_block_count_storage
     connect \B 1'1
-    connect \Y $sub$ls180.v:5339$979_Y
+    connect \Y $sub$ls180.v:5414$1030_Y
   end
-  attribute \src "ls180.v:5350.39-5350.77"
-  cell $sub $sub$ls180.v:5350$984
+  attribute \src "ls180.v:5425.39-5425.77"
+  cell $sub $sub$ls180.v:5425$1035
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259771,10 +261064,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdcore_block_count_storage
     connect \B 1'1
-    connect \Y $sub$ls180.v:5350$984_Y
+    connect \Y $sub$ls180.v:5425$1035_Y
   end
-  attribute \src "ls180.v:5425.40-5425.76"
-  cell $sub $sub$ls180.v:5425$988
+  attribute \src "ls180.v:5500.40-5500.76"
+  cell $sub $sub$ls180.v:5500$1039
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -259782,10 +261075,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdblock2mem_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:5425$988_Y
+    connect \Y $sub$ls180.v:5500$1039_Y
   end
-  attribute \src "ls180.v:5474.56-5474.104"
-  cell $sub $sub$ls180.v:5474$1002
+  attribute \src "ls180.v:5549.56-5549.104"
+  cell $sub $sub$ls180.v:5549$1053
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259793,10 +261086,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdblock2mem_wishbonedmawriter_length
     connect \B 1'1
-    connect \Y $sub$ls180.v:5474$1002_Y
+    connect \Y $sub$ls180.v:5549$1053_Y
   end
-  attribute \src "ls180.v:5564.71-5564.105"
-  cell $sub $sub$ls180.v:5564$1008
+  attribute \src "ls180.v:5639.71-5639.105"
+  cell $sub $sub$ls180.v:5639$1059
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259804,10 +261097,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_sdmem2block_dma_length
     connect \B 1'1
-    connect \Y $sub$ls180.v:5564$1008_Y
+    connect \Y $sub$ls180.v:5639$1059_Y
   end
-  attribute \src "ls180.v:5633.40-5633.76"
-  cell $sub $sub$ls180.v:5633$1019
+  attribute \src "ls180.v:5708.40-5708.76"
+  cell $sub $sub$ls180.v:5708$1070
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -259815,10 +261108,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdmem2block_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:5633$1019_Y
+    connect \Y $sub$ls180.v:5708$1070_Y
   end
-  attribute \src "ls180.v:7498.31-7498.60"
-  cell $sub $sub$ls180.v:7498$2408
+  attribute \src "ls180.v:7600.31-7600.60"
+  cell $sub $sub$ls180.v:7600$2477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -259826,10 +261119,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_libresocsim_value
     connect \B 1'1
-    connect \Y $sub$ls180.v:7498$2408_Y
+    connect \Y $sub$ls180.v:7600$2477_Y
   end
-  attribute \src "ls180.v:7519.31-7519.61"
-  cell $sub $sub$ls180.v:7519$2413
+  attribute \src "ls180.v:7633.31-7633.61"
+  cell $sub $sub$ls180.v:7633$2491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -259837,10 +261130,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \main_sdram_timer_count1
     connect \B 1'1
-    connect \Y $sub$ls180.v:7519$2413_Y
+    connect \Y $sub$ls180.v:7633$2491_Y
   end
-  attribute \src "ls180.v:7525.34-7525.67"
-  cell $sub $sub$ls180.v:7525$2414
+  attribute \src "ls180.v:7639.34-7639.67"
+  cell $sub $sub$ls180.v:7639$2492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259848,10 +261141,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_postponer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7525$2414_Y
+    connect \Y $sub$ls180.v:7639$2492_Y
   end
-  attribute \src "ls180.v:7536.36-7536.69"
-  cell $sub $sub$ls180.v:7536$2417
+  attribute \src "ls180.v:7650.36-7650.69"
+  cell $sub $sub$ls180.v:7650$2495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259859,10 +261152,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7536$2417_Y
+    connect \Y $sub$ls180.v:7650$2495_Y
   end
-  attribute \src "ls180.v:7600.59-7600.116"
-  cell $sub $sub$ls180.v:7600$2435
+  attribute \src "ls180.v:7714.59-7714.116"
+  cell $sub $sub$ls180.v:7714$2513
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259870,10 +261163,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7600$2435_Y
+    connect \Y $sub$ls180.v:7714$2513_Y
   end
-  attribute \src "ls180.v:7619.46-7619.90"
-  cell $sub $sub$ls180.v:7619$2439
+  attribute \src "ls180.v:7733.46-7733.90"
+  cell $sub $sub$ls180.v:7733$2517
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259881,10 +261174,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7619$2439_Y
+    connect \Y $sub$ls180.v:7733$2517_Y
   end
-  attribute \src "ls180.v:7646.59-7646.116"
-  cell $sub $sub$ls180.v:7646$2451
+  attribute \src "ls180.v:7760.59-7760.116"
+  cell $sub $sub$ls180.v:7760$2529
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259892,10 +261185,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7646$2451_Y
+    connect \Y $sub$ls180.v:7760$2529_Y
   end
-  attribute \src "ls180.v:7665.46-7665.90"
-  cell $sub $sub$ls180.v:7665$2455
+  attribute \src "ls180.v:7779.46-7779.90"
+  cell $sub $sub$ls180.v:7779$2533
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259903,10 +261196,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7665$2455_Y
+    connect \Y $sub$ls180.v:7779$2533_Y
   end
-  attribute \src "ls180.v:7692.59-7692.116"
-  cell $sub $sub$ls180.v:7692$2467
+  attribute \src "ls180.v:7806.59-7806.116"
+  cell $sub $sub$ls180.v:7806$2545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259914,10 +261207,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7692$2467_Y
+    connect \Y $sub$ls180.v:7806$2545_Y
   end
-  attribute \src "ls180.v:7711.46-7711.90"
-  cell $sub $sub$ls180.v:7711$2471
+  attribute \src "ls180.v:7825.46-7825.90"
+  cell $sub $sub$ls180.v:7825$2549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259925,10 +261218,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7711$2471_Y
+    connect \Y $sub$ls180.v:7825$2549_Y
   end
-  attribute \src "ls180.v:7738.59-7738.116"
-  cell $sub $sub$ls180.v:7738$2483
+  attribute \src "ls180.v:7852.59-7852.116"
+  cell $sub $sub$ls180.v:7852$2561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259936,10 +261229,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7738$2483_Y
+    connect \Y $sub$ls180.v:7852$2561_Y
   end
-  attribute \src "ls180.v:7757.46-7757.90"
-  cell $sub $sub$ls180.v:7757$2487
+  attribute \src "ls180.v:7871.46-7871.90"
+  cell $sub $sub$ls180.v:7871$2565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259947,10 +261240,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7757$2487_Y
+    connect \Y $sub$ls180.v:7871$2565_Y
   end
-  attribute \src "ls180.v:7768.25-7768.48"
-  cell $sub $sub$ls180.v:7768$2491
+  attribute \src "ls180.v:7882.25-7882.48"
+  cell $sub $sub$ls180.v:7882$2569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -259958,10 +261251,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdram_time0
     connect \B 1'1
-    connect \Y $sub$ls180.v:7768$2491_Y
+    connect \Y $sub$ls180.v:7882$2569_Y
   end
-  attribute \src "ls180.v:7775.25-7775.48"
-  cell $sub $sub$ls180.v:7775$2494
+  attribute \src "ls180.v:7889.25-7889.48"
+  cell $sub $sub$ls180.v:7889$2572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -259969,10 +261262,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_time1
     connect \B 1'1
-    connect \Y $sub$ls180.v:7775$2494_Y
+    connect \Y $sub$ls180.v:7889$2572_Y
   end
-  attribute \src "ls180.v:7907.33-7907.64"
-  cell $sub $sub$ls180.v:7907$2499
+  attribute \src "ls180.v:8021.33-8021.64"
+  cell $sub $sub$ls180.v:8021$2577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259980,10 +261273,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7907$2499_Y
+    connect \Y $sub$ls180.v:8021$2577_Y
   end
-  attribute \src "ls180.v:7922.33-7922.64"
-  cell $sub $sub$ls180.v:7922$2502
+  attribute \src "ls180.v:8036.33-8036.64"
+  cell $sub $sub$ls180.v:8036$2580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -259991,10 +261284,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7922$2502_Y
+    connect \Y $sub$ls180.v:8036$2580_Y
   end
-  attribute \src "ls180.v:8049.33-8049.64"
-  cell $sub $sub$ls180.v:8049$2561
+  attribute \src "ls180.v:8163.33-8163.64"
+  cell $sub $sub$ls180.v:8163$2639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -260002,10 +261295,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_tx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:8049$2561_Y
+    connect \Y $sub$ls180.v:8163$2639_Y
   end
-  attribute \src "ls180.v:8071.33-8071.64"
-  cell $sub $sub$ls180.v:8071$2572
+  attribute \src "ls180.v:8185.33-8185.64"
+  cell $sub $sub$ls180.v:8185$2650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -260013,10 +261306,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_rx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:8071$2572_Y
+    connect \Y $sub$ls180.v:8185$2650_Y
   end
-  attribute \src "ls180.v:8106.34-8106.66"
-  cell $sub $sub$ls180.v:8106$2577
+  attribute \src "ls180.v:8220.34-8220.66"
+  cell $sub $sub$ls180.v:8220$2655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260024,10 +261317,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spimaster34_mosi_sel
     connect \B 1'1
-    connect \Y $sub$ls180.v:8106$2577_Y
+    connect \Y $sub$ls180.v:8220$2655_Y
   end
-  attribute \src "ls180.v:8141.32-8141.62"
-  cell $sub $sub$ls180.v:8141$2582
+  attribute \src "ls180.v:8255.32-8255.62"
+  cell $sub $sub$ls180.v:8255$2660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260035,10 +261328,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spisdcard_mosi_sel
     connect \B 1'1
-    connect \Y $sub$ls180.v:8141$2582_Y
+    connect \Y $sub$ls180.v:8255$2660_Y
   end
-  attribute \src "ls180.v:8165.30-8165.53"
-  cell $sub $sub$ls180.v:8165$2585
+  attribute \src "ls180.v:8279.30-8279.53"
+  cell $sub $sub$ls180.v:8279$2663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -260046,10 +261339,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm0_period
     connect \B 1'1
-    connect \Y $sub$ls180.v:8165$2585_Y
+    connect \Y $sub$ls180.v:8279$2663_Y
   end
-  attribute \src "ls180.v:8179.30-8179.53"
-  cell $sub $sub$ls180.v:8179$2589
+  attribute \src "ls180.v:8293.30-8293.53"
+  cell $sub $sub$ls180.v:8293$2667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -260057,10 +261350,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm1_period
     connect \B 1'1
-    connect \Y $sub$ls180.v:8179$2589_Y
+    connect \Y $sub$ls180.v:8293$2667_Y
   end
-  attribute \src "ls180.v:8582.36-8582.70"
-  cell $sub $sub$ls180.v:8582$2650
+  attribute \src "ls180.v:8696.36-8696.70"
+  cell $sub $sub$ls180.v:8696$2728
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -260068,10 +261361,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdblock2mem_fifo_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:8582$2650_Y
+    connect \Y $sub$ls180.v:8696$2728_Y
   end
-  attribute \src "ls180.v:8668.36-8668.70"
-  cell $sub $sub$ls180.v:8668$2672
+  attribute \src "ls180.v:8782.36-8782.70"
+  cell $sub $sub$ls180.v:8782$2750
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -260079,10 +261372,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdmem2block_fifo_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:8668$2672_Y
+    connect \Y $sub$ls180.v:8782$2750_Y
   end
-  attribute \src "ls180.v:8781.22-8781.42"
-  cell $sub $sub$ls180.v:8781$2679
+  attribute \src "ls180.v:8895.22-8895.42"
+  cell $sub $sub$ls180.v:8895$2757
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -260090,10 +261383,10 @@ module \ls180
     parameter \Y_WIDTH 20
     connect \A \builder_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:8781$2679_Y
+    connect \Y $sub$ls180.v:8895$2757_Y
   end
-  attribute \src "ls180.v:4922.353-4922.425"
-  cell $xor $xor$ls180.v:4922$710
+  attribute \src "ls180.v:4997.353-4997.425"
+  cell $xor $xor$ls180.v:4997$761
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260101,10 +261394,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [39]
     connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
-    connect \Y $xor$ls180.v:4922$710_Y
+    connect \Y $xor$ls180.v:4997$761_Y
   end
-  attribute \src "ls180.v:4922.200-4922.272"
-  cell $xor $xor$ls180.v:4922$711
+  attribute \src "ls180.v:4997.200-4997.272"
+  cell $xor $xor$ls180.v:4997$762
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260112,21 +261405,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [39]
     connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
-    connect \Y $xor$ls180.v:4922$711_Y
+    connect \Y $xor$ls180.v:4997$762_Y
   end
-  attribute \src "ls180.v:4922.160-4922.273"
-  cell $xor $xor$ls180.v:4922$712
+  attribute \src "ls180.v:4997.160-4997.273"
+  cell $xor $xor$ls180.v:4997$763
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg0 [2]
-    connect \B $xor$ls180.v:4922$711_Y
-    connect \Y $xor$ls180.v:4922$712_Y
+    connect \B $xor$ls180.v:4997$762_Y
+    connect \Y $xor$ls180.v:4997$763_Y
   end
-  attribute \src "ls180.v:4923.353-4923.425"
-  cell $xor $xor$ls180.v:4923$713
+  attribute \src "ls180.v:4998.353-4998.425"
+  cell $xor $xor$ls180.v:4998$764
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260134,10 +261427,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [38]
     connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
-    connect \Y $xor$ls180.v:4923$713_Y
+    connect \Y $xor$ls180.v:4998$764_Y
   end
-  attribute \src "ls180.v:4923.200-4923.272"
-  cell $xor $xor$ls180.v:4923$714
+  attribute \src "ls180.v:4998.200-4998.272"
+  cell $xor $xor$ls180.v:4998$765
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260145,21 +261438,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [38]
     connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
-    connect \Y $xor$ls180.v:4923$714_Y
+    connect \Y $xor$ls180.v:4998$765_Y
   end
-  attribute \src "ls180.v:4923.160-4923.273"
-  cell $xor $xor$ls180.v:4923$715
+  attribute \src "ls180.v:4998.160-4998.273"
+  cell $xor $xor$ls180.v:4998$766
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg1 [2]
-    connect \B $xor$ls180.v:4923$714_Y
-    connect \Y $xor$ls180.v:4923$715_Y
+    connect \B $xor$ls180.v:4998$765_Y
+    connect \Y $xor$ls180.v:4998$766_Y
   end
-  attribute \src "ls180.v:4924.353-4924.425"
-  cell $xor $xor$ls180.v:4924$716
+  attribute \src "ls180.v:4999.353-4999.425"
+  cell $xor $xor$ls180.v:4999$767
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260167,10 +261460,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [37]
     connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
-    connect \Y $xor$ls180.v:4924$716_Y
+    connect \Y $xor$ls180.v:4999$767_Y
   end
-  attribute \src "ls180.v:4924.200-4924.272"
-  cell $xor $xor$ls180.v:4924$717
+  attribute \src "ls180.v:4999.200-4999.272"
+  cell $xor $xor$ls180.v:4999$768
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260178,21 +261471,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [37]
     connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
-    connect \Y $xor$ls180.v:4924$717_Y
+    connect \Y $xor$ls180.v:4999$768_Y
   end
-  attribute \src "ls180.v:4924.160-4924.273"
-  cell $xor $xor$ls180.v:4924$718
+  attribute \src "ls180.v:4999.160-4999.273"
+  cell $xor $xor$ls180.v:4999$769
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg2 [2]
-    connect \B $xor$ls180.v:4924$717_Y
-    connect \Y $xor$ls180.v:4924$718_Y
+    connect \B $xor$ls180.v:4999$768_Y
+    connect \Y $xor$ls180.v:4999$769_Y
   end
-  attribute \src "ls180.v:4925.353-4925.425"
-  cell $xor $xor$ls180.v:4925$719
+  attribute \src "ls180.v:5000.353-5000.425"
+  cell $xor $xor$ls180.v:5000$770
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260200,10 +261493,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [36]
     connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
-    connect \Y $xor$ls180.v:4925$719_Y
+    connect \Y $xor$ls180.v:5000$770_Y
   end
-  attribute \src "ls180.v:4925.200-4925.272"
-  cell $xor $xor$ls180.v:4925$720
+  attribute \src "ls180.v:5000.200-5000.272"
+  cell $xor $xor$ls180.v:5000$771
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260211,21 +261504,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [36]
     connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
-    connect \Y $xor$ls180.v:4925$720_Y
+    connect \Y $xor$ls180.v:5000$771_Y
   end
-  attribute \src "ls180.v:4925.160-4925.273"
-  cell $xor $xor$ls180.v:4925$721
+  attribute \src "ls180.v:5000.160-5000.273"
+  cell $xor $xor$ls180.v:5000$772
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg3 [2]
-    connect \B $xor$ls180.v:4925$720_Y
-    connect \Y $xor$ls180.v:4925$721_Y
+    connect \B $xor$ls180.v:5000$771_Y
+    connect \Y $xor$ls180.v:5000$772_Y
   end
-  attribute \src "ls180.v:4926.353-4926.425"
-  cell $xor $xor$ls180.v:4926$722
+  attribute \src "ls180.v:5001.353-5001.425"
+  cell $xor $xor$ls180.v:5001$773
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260233,10 +261526,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [35]
     connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
-    connect \Y $xor$ls180.v:4926$722_Y
+    connect \Y $xor$ls180.v:5001$773_Y
   end
-  attribute \src "ls180.v:4926.200-4926.272"
-  cell $xor $xor$ls180.v:4926$723
+  attribute \src "ls180.v:5001.200-5001.272"
+  cell $xor $xor$ls180.v:5001$774
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260244,21 +261537,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [35]
     connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
-    connect \Y $xor$ls180.v:4926$723_Y
+    connect \Y $xor$ls180.v:5001$774_Y
   end
-  attribute \src "ls180.v:4926.160-4926.273"
-  cell $xor $xor$ls180.v:4926$724
+  attribute \src "ls180.v:5001.160-5001.273"
+  cell $xor $xor$ls180.v:5001$775
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg4 [2]
-    connect \B $xor$ls180.v:4926$723_Y
-    connect \Y $xor$ls180.v:4926$724_Y
+    connect \B $xor$ls180.v:5001$774_Y
+    connect \Y $xor$ls180.v:5001$775_Y
   end
-  attribute \src "ls180.v:4927.353-4927.425"
-  cell $xor $xor$ls180.v:4927$725
+  attribute \src "ls180.v:5002.353-5002.425"
+  cell $xor $xor$ls180.v:5002$776
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260266,10 +261559,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [34]
     connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
-    connect \Y $xor$ls180.v:4927$725_Y
+    connect \Y $xor$ls180.v:5002$776_Y
   end
-  attribute \src "ls180.v:4927.200-4927.272"
-  cell $xor $xor$ls180.v:4927$726
+  attribute \src "ls180.v:5002.200-5002.272"
+  cell $xor $xor$ls180.v:5002$777
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260277,21 +261570,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [34]
     connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
-    connect \Y $xor$ls180.v:4927$726_Y
+    connect \Y $xor$ls180.v:5002$777_Y
   end
-  attribute \src "ls180.v:4927.160-4927.273"
-  cell $xor $xor$ls180.v:4927$727
+  attribute \src "ls180.v:5002.160-5002.273"
+  cell $xor $xor$ls180.v:5002$778
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg5 [2]
-    connect \B $xor$ls180.v:4927$726_Y
-    connect \Y $xor$ls180.v:4927$727_Y
+    connect \B $xor$ls180.v:5002$777_Y
+    connect \Y $xor$ls180.v:5002$778_Y
   end
-  attribute \src "ls180.v:4928.353-4928.425"
-  cell $xor $xor$ls180.v:4928$728
+  attribute \src "ls180.v:5003.353-5003.425"
+  cell $xor $xor$ls180.v:5003$779
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260299,10 +261592,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [33]
     connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
-    connect \Y $xor$ls180.v:4928$728_Y
+    connect \Y $xor$ls180.v:5003$779_Y
   end
-  attribute \src "ls180.v:4928.200-4928.272"
-  cell $xor $xor$ls180.v:4928$729
+  attribute \src "ls180.v:5003.200-5003.272"
+  cell $xor $xor$ls180.v:5003$780
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260310,21 +261603,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [33]
     connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
-    connect \Y $xor$ls180.v:4928$729_Y
+    connect \Y $xor$ls180.v:5003$780_Y
   end
-  attribute \src "ls180.v:4928.160-4928.273"
-  cell $xor $xor$ls180.v:4928$730
+  attribute \src "ls180.v:5003.160-5003.273"
+  cell $xor $xor$ls180.v:5003$781
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg6 [2]
-    connect \B $xor$ls180.v:4928$729_Y
-    connect \Y $xor$ls180.v:4928$730_Y
+    connect \B $xor$ls180.v:5003$780_Y
+    connect \Y $xor$ls180.v:5003$781_Y
   end
-  attribute \src "ls180.v:4929.353-4929.425"
-  cell $xor $xor$ls180.v:4929$731
+  attribute \src "ls180.v:5004.353-5004.425"
+  cell $xor $xor$ls180.v:5004$782
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260332,10 +261625,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [32]
     connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
-    connect \Y $xor$ls180.v:4929$731_Y
+    connect \Y $xor$ls180.v:5004$782_Y
   end
-  attribute \src "ls180.v:4929.200-4929.272"
-  cell $xor $xor$ls180.v:4929$732
+  attribute \src "ls180.v:5004.200-5004.272"
+  cell $xor $xor$ls180.v:5004$783
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260343,21 +261636,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [32]
     connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
-    connect \Y $xor$ls180.v:4929$732_Y
+    connect \Y $xor$ls180.v:5004$783_Y
   end
-  attribute \src "ls180.v:4929.160-4929.273"
-  cell $xor $xor$ls180.v:4929$733
+  attribute \src "ls180.v:5004.160-5004.273"
+  cell $xor $xor$ls180.v:5004$784
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg7 [2]
-    connect \B $xor$ls180.v:4929$732_Y
-    connect \Y $xor$ls180.v:4929$733_Y
+    connect \B $xor$ls180.v:5004$783_Y
+    connect \Y $xor$ls180.v:5004$784_Y
   end
-  attribute \src "ls180.v:4930.353-4930.425"
-  cell $xor $xor$ls180.v:4930$734
+  attribute \src "ls180.v:5005.353-5005.425"
+  cell $xor $xor$ls180.v:5005$785
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260365,10 +261658,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [31]
     connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
-    connect \Y $xor$ls180.v:4930$734_Y
+    connect \Y $xor$ls180.v:5005$785_Y
   end
-  attribute \src "ls180.v:4930.200-4930.272"
-  cell $xor $xor$ls180.v:4930$735
+  attribute \src "ls180.v:5005.200-5005.272"
+  cell $xor $xor$ls180.v:5005$786
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260376,21 +261669,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [31]
     connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
-    connect \Y $xor$ls180.v:4930$735_Y
+    connect \Y $xor$ls180.v:5005$786_Y
   end
-  attribute \src "ls180.v:4930.160-4930.273"
-  cell $xor $xor$ls180.v:4930$736
+  attribute \src "ls180.v:5005.160-5005.273"
+  cell $xor $xor$ls180.v:5005$787
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg8 [2]
-    connect \B $xor$ls180.v:4930$735_Y
-    connect \Y $xor$ls180.v:4930$736_Y
+    connect \B $xor$ls180.v:5005$786_Y
+    connect \Y $xor$ls180.v:5005$787_Y
   end
-  attribute \src "ls180.v:4931.354-4931.426"
-  cell $xor $xor$ls180.v:4931$737
+  attribute \src "ls180.v:5006.354-5006.426"
+  cell $xor $xor$ls180.v:5006$788
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260398,10 +261691,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [30]
     connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
-    connect \Y $xor$ls180.v:4931$737_Y
+    connect \Y $xor$ls180.v:5006$788_Y
   end
-  attribute \src "ls180.v:4931.201-4931.273"
-  cell $xor $xor$ls180.v:4931$738
+  attribute \src "ls180.v:5006.201-5006.273"
+  cell $xor $xor$ls180.v:5006$789
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260409,21 +261702,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [30]
     connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
-    connect \Y $xor$ls180.v:4931$738_Y
+    connect \Y $xor$ls180.v:5006$789_Y
   end
-  attribute \src "ls180.v:4931.161-4931.274"
-  cell $xor $xor$ls180.v:4931$739
+  attribute \src "ls180.v:5006.161-5006.274"
+  cell $xor $xor$ls180.v:5006$790
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg9 [2]
-    connect \B $xor$ls180.v:4931$738_Y
-    connect \Y $xor$ls180.v:4931$739_Y
+    connect \B $xor$ls180.v:5006$789_Y
+    connect \Y $xor$ls180.v:5006$790_Y
   end
-  attribute \src "ls180.v:4932.361-4932.434"
-  cell $xor $xor$ls180.v:4932$740
+  attribute \src "ls180.v:5007.361-5007.434"
+  cell $xor $xor$ls180.v:5007$791
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260431,10 +261724,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [29]
     connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
-    connect \Y $xor$ls180.v:4932$740_Y
+    connect \Y $xor$ls180.v:5007$791_Y
   end
-  attribute \src "ls180.v:4932.205-4932.278"
-  cell $xor $xor$ls180.v:4932$741
+  attribute \src "ls180.v:5007.205-5007.278"
+  cell $xor $xor$ls180.v:5007$792
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260442,21 +261735,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [29]
     connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
-    connect \Y $xor$ls180.v:4932$741_Y
+    connect \Y $xor$ls180.v:5007$792_Y
   end
-  attribute \src "ls180.v:4932.164-4932.279"
-  cell $xor $xor$ls180.v:4932$742
+  attribute \src "ls180.v:5007.164-5007.279"
+  cell $xor $xor$ls180.v:5007$793
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg10 [2]
-    connect \B $xor$ls180.v:4932$741_Y
-    connect \Y $xor$ls180.v:4932$742_Y
+    connect \B $xor$ls180.v:5007$792_Y
+    connect \Y $xor$ls180.v:5007$793_Y
   end
-  attribute \src "ls180.v:4933.361-4933.434"
-  cell $xor $xor$ls180.v:4933$743
+  attribute \src "ls180.v:5008.361-5008.434"
+  cell $xor $xor$ls180.v:5008$794
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260464,10 +261757,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [28]
     connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
-    connect \Y $xor$ls180.v:4933$743_Y
+    connect \Y $xor$ls180.v:5008$794_Y
   end
-  attribute \src "ls180.v:4933.205-4933.278"
-  cell $xor $xor$ls180.v:4933$744
+  attribute \src "ls180.v:5008.205-5008.278"
+  cell $xor $xor$ls180.v:5008$795
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260475,21 +261768,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [28]
     connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
-    connect \Y $xor$ls180.v:4933$744_Y
+    connect \Y $xor$ls180.v:5008$795_Y
   end
-  attribute \src "ls180.v:4933.164-4933.279"
-  cell $xor $xor$ls180.v:4933$745
+  attribute \src "ls180.v:5008.164-5008.279"
+  cell $xor $xor$ls180.v:5008$796
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg11 [2]
-    connect \B $xor$ls180.v:4933$744_Y
-    connect \Y $xor$ls180.v:4933$745_Y
+    connect \B $xor$ls180.v:5008$795_Y
+    connect \Y $xor$ls180.v:5008$796_Y
   end
-  attribute \src "ls180.v:4934.361-4934.434"
-  cell $xor $xor$ls180.v:4934$746
+  attribute \src "ls180.v:5009.361-5009.434"
+  cell $xor $xor$ls180.v:5009$797
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260497,10 +261790,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [27]
     connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
-    connect \Y $xor$ls180.v:4934$746_Y
+    connect \Y $xor$ls180.v:5009$797_Y
   end
-  attribute \src "ls180.v:4934.205-4934.278"
-  cell $xor $xor$ls180.v:4934$747
+  attribute \src "ls180.v:5009.205-5009.278"
+  cell $xor $xor$ls180.v:5009$798
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260508,21 +261801,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [27]
     connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
-    connect \Y $xor$ls180.v:4934$747_Y
+    connect \Y $xor$ls180.v:5009$798_Y
   end
-  attribute \src "ls180.v:4934.164-4934.279"
-  cell $xor $xor$ls180.v:4934$748
+  attribute \src "ls180.v:5009.164-5009.279"
+  cell $xor $xor$ls180.v:5009$799
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg12 [2]
-    connect \B $xor$ls180.v:4934$747_Y
-    connect \Y $xor$ls180.v:4934$748_Y
+    connect \B $xor$ls180.v:5009$798_Y
+    connect \Y $xor$ls180.v:5009$799_Y
   end
-  attribute \src "ls180.v:4935.361-4935.434"
-  cell $xor $xor$ls180.v:4935$749
+  attribute \src "ls180.v:5010.361-5010.434"
+  cell $xor $xor$ls180.v:5010$800
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260530,10 +261823,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [26]
     connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
-    connect \Y $xor$ls180.v:4935$749_Y
+    connect \Y $xor$ls180.v:5010$800_Y
   end
-  attribute \src "ls180.v:4935.205-4935.278"
-  cell $xor $xor$ls180.v:4935$750
+  attribute \src "ls180.v:5010.205-5010.278"
+  cell $xor $xor$ls180.v:5010$801
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260541,21 +261834,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [26]
     connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
-    connect \Y $xor$ls180.v:4935$750_Y
+    connect \Y $xor$ls180.v:5010$801_Y
   end
-  attribute \src "ls180.v:4935.164-4935.279"
-  cell $xor $xor$ls180.v:4935$751
+  attribute \src "ls180.v:5010.164-5010.279"
+  cell $xor $xor$ls180.v:5010$802
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg13 [2]
-    connect \B $xor$ls180.v:4935$750_Y
-    connect \Y $xor$ls180.v:4935$751_Y
+    connect \B $xor$ls180.v:5010$801_Y
+    connect \Y $xor$ls180.v:5010$802_Y
   end
-  attribute \src "ls180.v:4936.361-4936.434"
-  cell $xor $xor$ls180.v:4936$752
+  attribute \src "ls180.v:5011.361-5011.434"
+  cell $xor $xor$ls180.v:5011$803
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260563,10 +261856,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [25]
     connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
-    connect \Y $xor$ls180.v:4936$752_Y
+    connect \Y $xor$ls180.v:5011$803_Y
   end
-  attribute \src "ls180.v:4936.205-4936.278"
-  cell $xor $xor$ls180.v:4936$753
+  attribute \src "ls180.v:5011.205-5011.278"
+  cell $xor $xor$ls180.v:5011$804
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260574,21 +261867,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [25]
     connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
-    connect \Y $xor$ls180.v:4936$753_Y
+    connect \Y $xor$ls180.v:5011$804_Y
   end
-  attribute \src "ls180.v:4936.164-4936.279"
-  cell $xor $xor$ls180.v:4936$754
+  attribute \src "ls180.v:5011.164-5011.279"
+  cell $xor $xor$ls180.v:5011$805
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg14 [2]
-    connect \B $xor$ls180.v:4936$753_Y
-    connect \Y $xor$ls180.v:4936$754_Y
+    connect \B $xor$ls180.v:5011$804_Y
+    connect \Y $xor$ls180.v:5011$805_Y
   end
-  attribute \src "ls180.v:4937.361-4937.434"
-  cell $xor $xor$ls180.v:4937$755
+  attribute \src "ls180.v:5012.361-5012.434"
+  cell $xor $xor$ls180.v:5012$806
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260596,10 +261889,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [24]
     connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
-    connect \Y $xor$ls180.v:4937$755_Y
+    connect \Y $xor$ls180.v:5012$806_Y
   end
-  attribute \src "ls180.v:4937.205-4937.278"
-  cell $xor $xor$ls180.v:4937$756
+  attribute \src "ls180.v:5012.205-5012.278"
+  cell $xor $xor$ls180.v:5012$807
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260607,21 +261900,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [24]
     connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
-    connect \Y $xor$ls180.v:4937$756_Y
+    connect \Y $xor$ls180.v:5012$807_Y
   end
-  attribute \src "ls180.v:4937.164-4937.279"
-  cell $xor $xor$ls180.v:4937$757
+  attribute \src "ls180.v:5012.164-5012.279"
+  cell $xor $xor$ls180.v:5012$808
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg15 [2]
-    connect \B $xor$ls180.v:4937$756_Y
-    connect \Y $xor$ls180.v:4937$757_Y
+    connect \B $xor$ls180.v:5012$807_Y
+    connect \Y $xor$ls180.v:5012$808_Y
   end
-  attribute \src "ls180.v:4938.361-4938.434"
-  cell $xor $xor$ls180.v:4938$758
+  attribute \src "ls180.v:5013.361-5013.434"
+  cell $xor $xor$ls180.v:5013$809
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260629,10 +261922,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [23]
     connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
-    connect \Y $xor$ls180.v:4938$758_Y
+    connect \Y $xor$ls180.v:5013$809_Y
   end
-  attribute \src "ls180.v:4938.205-4938.278"
-  cell $xor $xor$ls180.v:4938$759
+  attribute \src "ls180.v:5013.205-5013.278"
+  cell $xor $xor$ls180.v:5013$810
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260640,21 +261933,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [23]
     connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
-    connect \Y $xor$ls180.v:4938$759_Y
+    connect \Y $xor$ls180.v:5013$810_Y
   end
-  attribute \src "ls180.v:4938.164-4938.279"
-  cell $xor $xor$ls180.v:4938$760
+  attribute \src "ls180.v:5013.164-5013.279"
+  cell $xor $xor$ls180.v:5013$811
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg16 [2]
-    connect \B $xor$ls180.v:4938$759_Y
-    connect \Y $xor$ls180.v:4938$760_Y
+    connect \B $xor$ls180.v:5013$810_Y
+    connect \Y $xor$ls180.v:5013$811_Y
   end
-  attribute \src "ls180.v:4939.361-4939.434"
-  cell $xor $xor$ls180.v:4939$761
+  attribute \src "ls180.v:5014.361-5014.434"
+  cell $xor $xor$ls180.v:5014$812
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260662,10 +261955,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [22]
     connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
-    connect \Y $xor$ls180.v:4939$761_Y
+    connect \Y $xor$ls180.v:5014$812_Y
   end
-  attribute \src "ls180.v:4939.205-4939.278"
-  cell $xor $xor$ls180.v:4939$762
+  attribute \src "ls180.v:5014.205-5014.278"
+  cell $xor $xor$ls180.v:5014$813
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260673,21 +261966,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [22]
     connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
-    connect \Y $xor$ls180.v:4939$762_Y
+    connect \Y $xor$ls180.v:5014$813_Y
   end
-  attribute \src "ls180.v:4939.164-4939.279"
-  cell $xor $xor$ls180.v:4939$763
+  attribute \src "ls180.v:5014.164-5014.279"
+  cell $xor $xor$ls180.v:5014$814
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg17 [2]
-    connect \B $xor$ls180.v:4939$762_Y
-    connect \Y $xor$ls180.v:4939$763_Y
+    connect \B $xor$ls180.v:5014$813_Y
+    connect \Y $xor$ls180.v:5014$814_Y
   end
-  attribute \src "ls180.v:4940.361-4940.434"
-  cell $xor $xor$ls180.v:4940$764
+  attribute \src "ls180.v:5015.361-5015.434"
+  cell $xor $xor$ls180.v:5015$815
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260695,10 +261988,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [21]
     connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
-    connect \Y $xor$ls180.v:4940$764_Y
+    connect \Y $xor$ls180.v:5015$815_Y
   end
-  attribute \src "ls180.v:4940.205-4940.278"
-  cell $xor $xor$ls180.v:4940$765
+  attribute \src "ls180.v:5015.205-5015.278"
+  cell $xor $xor$ls180.v:5015$816
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260706,21 +261999,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [21]
     connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
-    connect \Y $xor$ls180.v:4940$765_Y
+    connect \Y $xor$ls180.v:5015$816_Y
   end
-  attribute \src "ls180.v:4940.164-4940.279"
-  cell $xor $xor$ls180.v:4940$766
+  attribute \src "ls180.v:5015.164-5015.279"
+  cell $xor $xor$ls180.v:5015$817
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg18 [2]
-    connect \B $xor$ls180.v:4940$765_Y
-    connect \Y $xor$ls180.v:4940$766_Y
+    connect \B $xor$ls180.v:5015$816_Y
+    connect \Y $xor$ls180.v:5015$817_Y
   end
-  attribute \src "ls180.v:4941.361-4941.434"
-  cell $xor $xor$ls180.v:4941$767
+  attribute \src "ls180.v:5016.361-5016.434"
+  cell $xor $xor$ls180.v:5016$818
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260728,10 +262021,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [20]
     connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
-    connect \Y $xor$ls180.v:4941$767_Y
+    connect \Y $xor$ls180.v:5016$818_Y
   end
-  attribute \src "ls180.v:4941.205-4941.278"
-  cell $xor $xor$ls180.v:4941$768
+  attribute \src "ls180.v:5016.205-5016.278"
+  cell $xor $xor$ls180.v:5016$819
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260739,21 +262032,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [20]
     connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
-    connect \Y $xor$ls180.v:4941$768_Y
+    connect \Y $xor$ls180.v:5016$819_Y
   end
-  attribute \src "ls180.v:4941.164-4941.279"
-  cell $xor $xor$ls180.v:4941$769
+  attribute \src "ls180.v:5016.164-5016.279"
+  cell $xor $xor$ls180.v:5016$820
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg19 [2]
-    connect \B $xor$ls180.v:4941$768_Y
-    connect \Y $xor$ls180.v:4941$769_Y
+    connect \B $xor$ls180.v:5016$819_Y
+    connect \Y $xor$ls180.v:5016$820_Y
   end
-  attribute \src "ls180.v:4942.361-4942.434"
-  cell $xor $xor$ls180.v:4942$770
+  attribute \src "ls180.v:5017.361-5017.434"
+  cell $xor $xor$ls180.v:5017$821
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260761,10 +262054,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [19]
     connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
-    connect \Y $xor$ls180.v:4942$770_Y
+    connect \Y $xor$ls180.v:5017$821_Y
   end
-  attribute \src "ls180.v:4942.205-4942.278"
-  cell $xor $xor$ls180.v:4942$771
+  attribute \src "ls180.v:5017.205-5017.278"
+  cell $xor $xor$ls180.v:5017$822
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260772,21 +262065,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [19]
     connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
-    connect \Y $xor$ls180.v:4942$771_Y
+    connect \Y $xor$ls180.v:5017$822_Y
   end
-  attribute \src "ls180.v:4942.164-4942.279"
-  cell $xor $xor$ls180.v:4942$772
+  attribute \src "ls180.v:5017.164-5017.279"
+  cell $xor $xor$ls180.v:5017$823
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg20 [2]
-    connect \B $xor$ls180.v:4942$771_Y
-    connect \Y $xor$ls180.v:4942$772_Y
+    connect \B $xor$ls180.v:5017$822_Y
+    connect \Y $xor$ls180.v:5017$823_Y
   end
-  attribute \src "ls180.v:4943.361-4943.434"
-  cell $xor $xor$ls180.v:4943$773
+  attribute \src "ls180.v:5018.361-5018.434"
+  cell $xor $xor$ls180.v:5018$824
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260794,10 +262087,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [18]
     connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
-    connect \Y $xor$ls180.v:4943$773_Y
+    connect \Y $xor$ls180.v:5018$824_Y
   end
-  attribute \src "ls180.v:4943.205-4943.278"
-  cell $xor $xor$ls180.v:4943$774
+  attribute \src "ls180.v:5018.205-5018.278"
+  cell $xor $xor$ls180.v:5018$825
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260805,21 +262098,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [18]
     connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
-    connect \Y $xor$ls180.v:4943$774_Y
+    connect \Y $xor$ls180.v:5018$825_Y
   end
-  attribute \src "ls180.v:4943.164-4943.279"
-  cell $xor $xor$ls180.v:4943$775
+  attribute \src "ls180.v:5018.164-5018.279"
+  cell $xor $xor$ls180.v:5018$826
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg21 [2]
-    connect \B $xor$ls180.v:4943$774_Y
-    connect \Y $xor$ls180.v:4943$775_Y
+    connect \B $xor$ls180.v:5018$825_Y
+    connect \Y $xor$ls180.v:5018$826_Y
   end
-  attribute \src "ls180.v:4944.361-4944.434"
-  cell $xor $xor$ls180.v:4944$776
+  attribute \src "ls180.v:5019.361-5019.434"
+  cell $xor $xor$ls180.v:5019$827
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260827,10 +262120,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [17]
     connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
-    connect \Y $xor$ls180.v:4944$776_Y
+    connect \Y $xor$ls180.v:5019$827_Y
   end
-  attribute \src "ls180.v:4944.205-4944.278"
-  cell $xor $xor$ls180.v:4944$777
+  attribute \src "ls180.v:5019.205-5019.278"
+  cell $xor $xor$ls180.v:5019$828
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260838,21 +262131,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [17]
     connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
-    connect \Y $xor$ls180.v:4944$777_Y
+    connect \Y $xor$ls180.v:5019$828_Y
   end
-  attribute \src "ls180.v:4944.164-4944.279"
-  cell $xor $xor$ls180.v:4944$778
+  attribute \src "ls180.v:5019.164-5019.279"
+  cell $xor $xor$ls180.v:5019$829
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg22 [2]
-    connect \B $xor$ls180.v:4944$777_Y
-    connect \Y $xor$ls180.v:4944$778_Y
+    connect \B $xor$ls180.v:5019$828_Y
+    connect \Y $xor$ls180.v:5019$829_Y
   end
-  attribute \src "ls180.v:4945.361-4945.434"
-  cell $xor $xor$ls180.v:4945$779
+  attribute \src "ls180.v:5020.361-5020.434"
+  cell $xor $xor$ls180.v:5020$830
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260860,10 +262153,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [16]
     connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
-    connect \Y $xor$ls180.v:4945$779_Y
+    connect \Y $xor$ls180.v:5020$830_Y
   end
-  attribute \src "ls180.v:4945.205-4945.278"
-  cell $xor $xor$ls180.v:4945$780
+  attribute \src "ls180.v:5020.205-5020.278"
+  cell $xor $xor$ls180.v:5020$831
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260871,21 +262164,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [16]
     connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
-    connect \Y $xor$ls180.v:4945$780_Y
+    connect \Y $xor$ls180.v:5020$831_Y
   end
-  attribute \src "ls180.v:4945.164-4945.279"
-  cell $xor $xor$ls180.v:4945$781
+  attribute \src "ls180.v:5020.164-5020.279"
+  cell $xor $xor$ls180.v:5020$832
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg23 [2]
-    connect \B $xor$ls180.v:4945$780_Y
-    connect \Y $xor$ls180.v:4945$781_Y
+    connect \B $xor$ls180.v:5020$831_Y
+    connect \Y $xor$ls180.v:5020$832_Y
   end
-  attribute \src "ls180.v:4946.361-4946.434"
-  cell $xor $xor$ls180.v:4946$782
+  attribute \src "ls180.v:5021.361-5021.434"
+  cell $xor $xor$ls180.v:5021$833
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260893,10 +262186,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [15]
     connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
-    connect \Y $xor$ls180.v:4946$782_Y
+    connect \Y $xor$ls180.v:5021$833_Y
   end
-  attribute \src "ls180.v:4946.205-4946.278"
-  cell $xor $xor$ls180.v:4946$783
+  attribute \src "ls180.v:5021.205-5021.278"
+  cell $xor $xor$ls180.v:5021$834
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260904,21 +262197,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [15]
     connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
-    connect \Y $xor$ls180.v:4946$783_Y
+    connect \Y $xor$ls180.v:5021$834_Y
   end
-  attribute \src "ls180.v:4946.164-4946.279"
-  cell $xor $xor$ls180.v:4946$784
+  attribute \src "ls180.v:5021.164-5021.279"
+  cell $xor $xor$ls180.v:5021$835
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg24 [2]
-    connect \B $xor$ls180.v:4946$783_Y
-    connect \Y $xor$ls180.v:4946$784_Y
+    connect \B $xor$ls180.v:5021$834_Y
+    connect \Y $xor$ls180.v:5021$835_Y
   end
-  attribute \src "ls180.v:4947.361-4947.434"
-  cell $xor $xor$ls180.v:4947$785
+  attribute \src "ls180.v:5022.361-5022.434"
+  cell $xor $xor$ls180.v:5022$836
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260926,10 +262219,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [14]
     connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
-    connect \Y $xor$ls180.v:4947$785_Y
+    connect \Y $xor$ls180.v:5022$836_Y
   end
-  attribute \src "ls180.v:4947.205-4947.278"
-  cell $xor $xor$ls180.v:4947$786
+  attribute \src "ls180.v:5022.205-5022.278"
+  cell $xor $xor$ls180.v:5022$837
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260937,21 +262230,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [14]
     connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
-    connect \Y $xor$ls180.v:4947$786_Y
+    connect \Y $xor$ls180.v:5022$837_Y
   end
-  attribute \src "ls180.v:4947.164-4947.279"
-  cell $xor $xor$ls180.v:4947$787
+  attribute \src "ls180.v:5022.164-5022.279"
+  cell $xor $xor$ls180.v:5022$838
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg25 [2]
-    connect \B $xor$ls180.v:4947$786_Y
-    connect \Y $xor$ls180.v:4947$787_Y
+    connect \B $xor$ls180.v:5022$837_Y
+    connect \Y $xor$ls180.v:5022$838_Y
   end
-  attribute \src "ls180.v:4948.361-4948.434"
-  cell $xor $xor$ls180.v:4948$788
+  attribute \src "ls180.v:5023.361-5023.434"
+  cell $xor $xor$ls180.v:5023$839
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260959,10 +262252,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [13]
     connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
-    connect \Y $xor$ls180.v:4948$788_Y
+    connect \Y $xor$ls180.v:5023$839_Y
   end
-  attribute \src "ls180.v:4948.205-4948.278"
-  cell $xor $xor$ls180.v:4948$789
+  attribute \src "ls180.v:5023.205-5023.278"
+  cell $xor $xor$ls180.v:5023$840
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260970,21 +262263,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [13]
     connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
-    connect \Y $xor$ls180.v:4948$789_Y
+    connect \Y $xor$ls180.v:5023$840_Y
   end
-  attribute \src "ls180.v:4948.164-4948.279"
-  cell $xor $xor$ls180.v:4948$790
+  attribute \src "ls180.v:5023.164-5023.279"
+  cell $xor $xor$ls180.v:5023$841
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg26 [2]
-    connect \B $xor$ls180.v:4948$789_Y
-    connect \Y $xor$ls180.v:4948$790_Y
+    connect \B $xor$ls180.v:5023$840_Y
+    connect \Y $xor$ls180.v:5023$841_Y
   end
-  attribute \src "ls180.v:4949.361-4949.434"
-  cell $xor $xor$ls180.v:4949$791
+  attribute \src "ls180.v:5024.361-5024.434"
+  cell $xor $xor$ls180.v:5024$842
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260992,10 +262285,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [12]
     connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
-    connect \Y $xor$ls180.v:4949$791_Y
+    connect \Y $xor$ls180.v:5024$842_Y
   end
-  attribute \src "ls180.v:4949.205-4949.278"
-  cell $xor $xor$ls180.v:4949$792
+  attribute \src "ls180.v:5024.205-5024.278"
+  cell $xor $xor$ls180.v:5024$843
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261003,21 +262296,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [12]
     connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
-    connect \Y $xor$ls180.v:4949$792_Y
+    connect \Y $xor$ls180.v:5024$843_Y
   end
-  attribute \src "ls180.v:4949.164-4949.279"
-  cell $xor $xor$ls180.v:4949$793
+  attribute \src "ls180.v:5024.164-5024.279"
+  cell $xor $xor$ls180.v:5024$844
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg27 [2]
-    connect \B $xor$ls180.v:4949$792_Y
-    connect \Y $xor$ls180.v:4949$793_Y
+    connect \B $xor$ls180.v:5024$843_Y
+    connect \Y $xor$ls180.v:5024$844_Y
   end
-  attribute \src "ls180.v:4950.361-4950.434"
-  cell $xor $xor$ls180.v:4950$794
+  attribute \src "ls180.v:5025.361-5025.434"
+  cell $xor $xor$ls180.v:5025$845
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261025,10 +262318,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [11]
     connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
-    connect \Y $xor$ls180.v:4950$794_Y
+    connect \Y $xor$ls180.v:5025$845_Y
   end
-  attribute \src "ls180.v:4950.205-4950.278"
-  cell $xor $xor$ls180.v:4950$795
+  attribute \src "ls180.v:5025.205-5025.278"
+  cell $xor $xor$ls180.v:5025$846
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261036,21 +262329,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [11]
     connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
-    connect \Y $xor$ls180.v:4950$795_Y
+    connect \Y $xor$ls180.v:5025$846_Y
   end
-  attribute \src "ls180.v:4950.164-4950.279"
-  cell $xor $xor$ls180.v:4950$796
+  attribute \src "ls180.v:5025.164-5025.279"
+  cell $xor $xor$ls180.v:5025$847
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg28 [2]
-    connect \B $xor$ls180.v:4950$795_Y
-    connect \Y $xor$ls180.v:4950$796_Y
+    connect \B $xor$ls180.v:5025$846_Y
+    connect \Y $xor$ls180.v:5025$847_Y
   end
-  attribute \src "ls180.v:4951.361-4951.434"
-  cell $xor $xor$ls180.v:4951$797
+  attribute \src "ls180.v:5026.361-5026.434"
+  cell $xor $xor$ls180.v:5026$848
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261058,10 +262351,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [10]
     connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
-    connect \Y $xor$ls180.v:4951$797_Y
+    connect \Y $xor$ls180.v:5026$848_Y
   end
-  attribute \src "ls180.v:4951.205-4951.278"
-  cell $xor $xor$ls180.v:4951$798
+  attribute \src "ls180.v:5026.205-5026.278"
+  cell $xor $xor$ls180.v:5026$849
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261069,21 +262362,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [10]
     connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
-    connect \Y $xor$ls180.v:4951$798_Y
+    connect \Y $xor$ls180.v:5026$849_Y
   end
-  attribute \src "ls180.v:4951.164-4951.279"
-  cell $xor $xor$ls180.v:4951$799
+  attribute \src "ls180.v:5026.164-5026.279"
+  cell $xor $xor$ls180.v:5026$850
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg29 [2]
-    connect \B $xor$ls180.v:4951$798_Y
-    connect \Y $xor$ls180.v:4951$799_Y
+    connect \B $xor$ls180.v:5026$849_Y
+    connect \Y $xor$ls180.v:5026$850_Y
   end
-  attribute \src "ls180.v:4952.360-4952.432"
-  cell $xor $xor$ls180.v:4952$800
+  attribute \src "ls180.v:5027.360-5027.432"
+  cell $xor $xor$ls180.v:5027$851
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261091,10 +262384,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [9]
     connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
-    connect \Y $xor$ls180.v:4952$800_Y
+    connect \Y $xor$ls180.v:5027$851_Y
   end
-  attribute \src "ls180.v:4952.205-4952.277"
-  cell $xor $xor$ls180.v:4952$801
+  attribute \src "ls180.v:5027.205-5027.277"
+  cell $xor $xor$ls180.v:5027$852
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261102,21 +262395,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [9]
     connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
-    connect \Y $xor$ls180.v:4952$801_Y
+    connect \Y $xor$ls180.v:5027$852_Y
   end
-  attribute \src "ls180.v:4952.164-4952.278"
-  cell $xor $xor$ls180.v:4952$802
+  attribute \src "ls180.v:5027.164-5027.278"
+  cell $xor $xor$ls180.v:5027$853
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg30 [2]
-    connect \B $xor$ls180.v:4952$801_Y
-    connect \Y $xor$ls180.v:4952$802_Y
+    connect \B $xor$ls180.v:5027$852_Y
+    connect \Y $xor$ls180.v:5027$853_Y
   end
-  attribute \src "ls180.v:4953.360-4953.432"
-  cell $xor $xor$ls180.v:4953$803
+  attribute \src "ls180.v:5028.360-5028.432"
+  cell $xor $xor$ls180.v:5028$854
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261124,10 +262417,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [8]
     connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
-    connect \Y $xor$ls180.v:4953$803_Y
+    connect \Y $xor$ls180.v:5028$854_Y
   end
-  attribute \src "ls180.v:4953.205-4953.277"
-  cell $xor $xor$ls180.v:4953$804
+  attribute \src "ls180.v:5028.205-5028.277"
+  cell $xor $xor$ls180.v:5028$855
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261135,21 +262428,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [8]
     connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
-    connect \Y $xor$ls180.v:4953$804_Y
+    connect \Y $xor$ls180.v:5028$855_Y
   end
-  attribute \src "ls180.v:4953.164-4953.278"
-  cell $xor $xor$ls180.v:4953$805
+  attribute \src "ls180.v:5028.164-5028.278"
+  cell $xor $xor$ls180.v:5028$856
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg31 [2]
-    connect \B $xor$ls180.v:4953$804_Y
-    connect \Y $xor$ls180.v:4953$805_Y
+    connect \B $xor$ls180.v:5028$855_Y
+    connect \Y $xor$ls180.v:5028$856_Y
   end
-  attribute \src "ls180.v:4954.360-4954.432"
-  cell $xor $xor$ls180.v:4954$806
+  attribute \src "ls180.v:5029.360-5029.432"
+  cell $xor $xor$ls180.v:5029$857
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261157,10 +262450,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [7]
     connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
-    connect \Y $xor$ls180.v:4954$806_Y
+    connect \Y $xor$ls180.v:5029$857_Y
   end
-  attribute \src "ls180.v:4954.205-4954.277"
-  cell $xor $xor$ls180.v:4954$807
+  attribute \src "ls180.v:5029.205-5029.277"
+  cell $xor $xor$ls180.v:5029$858
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261168,21 +262461,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [7]
     connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
-    connect \Y $xor$ls180.v:4954$807_Y
+    connect \Y $xor$ls180.v:5029$858_Y
   end
-  attribute \src "ls180.v:4954.164-4954.278"
-  cell $xor $xor$ls180.v:4954$808
+  attribute \src "ls180.v:5029.164-5029.278"
+  cell $xor $xor$ls180.v:5029$859
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg32 [2]
-    connect \B $xor$ls180.v:4954$807_Y
-    connect \Y $xor$ls180.v:4954$808_Y
+    connect \B $xor$ls180.v:5029$858_Y
+    connect \Y $xor$ls180.v:5029$859_Y
   end
-  attribute \src "ls180.v:4955.360-4955.432"
-  cell $xor $xor$ls180.v:4955$809
+  attribute \src "ls180.v:5030.360-5030.432"
+  cell $xor $xor$ls180.v:5030$860
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261190,10 +262483,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [6]
     connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
-    connect \Y $xor$ls180.v:4955$809_Y
+    connect \Y $xor$ls180.v:5030$860_Y
   end
-  attribute \src "ls180.v:4955.205-4955.277"
-  cell $xor $xor$ls180.v:4955$810
+  attribute \src "ls180.v:5030.205-5030.277"
+  cell $xor $xor$ls180.v:5030$861
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261201,21 +262494,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [6]
     connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
-    connect \Y $xor$ls180.v:4955$810_Y
+    connect \Y $xor$ls180.v:5030$861_Y
   end
-  attribute \src "ls180.v:4955.164-4955.278"
-  cell $xor $xor$ls180.v:4955$811
+  attribute \src "ls180.v:5030.164-5030.278"
+  cell $xor $xor$ls180.v:5030$862
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg33 [2]
-    connect \B $xor$ls180.v:4955$810_Y
-    connect \Y $xor$ls180.v:4955$811_Y
+    connect \B $xor$ls180.v:5030$861_Y
+    connect \Y $xor$ls180.v:5030$862_Y
   end
-  attribute \src "ls180.v:4956.360-4956.432"
-  cell $xor $xor$ls180.v:4956$812
+  attribute \src "ls180.v:5031.360-5031.432"
+  cell $xor $xor$ls180.v:5031$863
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261223,10 +262516,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [5]
     connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
-    connect \Y $xor$ls180.v:4956$812_Y
+    connect \Y $xor$ls180.v:5031$863_Y
   end
-  attribute \src "ls180.v:4956.205-4956.277"
-  cell $xor $xor$ls180.v:4956$813
+  attribute \src "ls180.v:5031.205-5031.277"
+  cell $xor $xor$ls180.v:5031$864
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261234,21 +262527,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [5]
     connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
-    connect \Y $xor$ls180.v:4956$813_Y
+    connect \Y $xor$ls180.v:5031$864_Y
   end
-  attribute \src "ls180.v:4956.164-4956.278"
-  cell $xor $xor$ls180.v:4956$814
+  attribute \src "ls180.v:5031.164-5031.278"
+  cell $xor $xor$ls180.v:5031$865
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg34 [2]
-    connect \B $xor$ls180.v:4956$813_Y
-    connect \Y $xor$ls180.v:4956$814_Y
+    connect \B $xor$ls180.v:5031$864_Y
+    connect \Y $xor$ls180.v:5031$865_Y
   end
-  attribute \src "ls180.v:4957.360-4957.432"
-  cell $xor $xor$ls180.v:4957$815
+  attribute \src "ls180.v:5032.360-5032.432"
+  cell $xor $xor$ls180.v:5032$866
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261256,10 +262549,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [4]
     connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
-    connect \Y $xor$ls180.v:4957$815_Y
+    connect \Y $xor$ls180.v:5032$866_Y
   end
-  attribute \src "ls180.v:4957.205-4957.277"
-  cell $xor $xor$ls180.v:4957$816
+  attribute \src "ls180.v:5032.205-5032.277"
+  cell $xor $xor$ls180.v:5032$867
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261267,21 +262560,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [4]
     connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
-    connect \Y $xor$ls180.v:4957$816_Y
+    connect \Y $xor$ls180.v:5032$867_Y
   end
-  attribute \src "ls180.v:4957.164-4957.278"
-  cell $xor $xor$ls180.v:4957$817
+  attribute \src "ls180.v:5032.164-5032.278"
+  cell $xor $xor$ls180.v:5032$868
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg35 [2]
-    connect \B $xor$ls180.v:4957$816_Y
-    connect \Y $xor$ls180.v:4957$817_Y
+    connect \B $xor$ls180.v:5032$867_Y
+    connect \Y $xor$ls180.v:5032$868_Y
   end
-  attribute \src "ls180.v:4958.360-4958.432"
-  cell $xor $xor$ls180.v:4958$818
+  attribute \src "ls180.v:5033.360-5033.432"
+  cell $xor $xor$ls180.v:5033$869
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261289,10 +262582,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [3]
     connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
-    connect \Y $xor$ls180.v:4958$818_Y
+    connect \Y $xor$ls180.v:5033$869_Y
   end
-  attribute \src "ls180.v:4958.205-4958.277"
-  cell $xor $xor$ls180.v:4958$819
+  attribute \src "ls180.v:5033.205-5033.277"
+  cell $xor $xor$ls180.v:5033$870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261300,21 +262593,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [3]
     connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
-    connect \Y $xor$ls180.v:4958$819_Y
+    connect \Y $xor$ls180.v:5033$870_Y
   end
-  attribute \src "ls180.v:4958.164-4958.278"
-  cell $xor $xor$ls180.v:4958$820
+  attribute \src "ls180.v:5033.164-5033.278"
+  cell $xor $xor$ls180.v:5033$871
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg36 [2]
-    connect \B $xor$ls180.v:4958$819_Y
-    connect \Y $xor$ls180.v:4958$820_Y
+    connect \B $xor$ls180.v:5033$870_Y
+    connect \Y $xor$ls180.v:5033$871_Y
   end
-  attribute \src "ls180.v:4959.360-4959.432"
-  cell $xor $xor$ls180.v:4959$821
+  attribute \src "ls180.v:5034.360-5034.432"
+  cell $xor $xor$ls180.v:5034$872
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261322,10 +262615,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [2]
     connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
-    connect \Y $xor$ls180.v:4959$821_Y
+    connect \Y $xor$ls180.v:5034$872_Y
   end
-  attribute \src "ls180.v:4959.205-4959.277"
-  cell $xor $xor$ls180.v:4959$822
+  attribute \src "ls180.v:5034.205-5034.277"
+  cell $xor $xor$ls180.v:5034$873
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261333,21 +262626,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [2]
     connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
-    connect \Y $xor$ls180.v:4959$822_Y
+    connect \Y $xor$ls180.v:5034$873_Y
   end
-  attribute \src "ls180.v:4959.164-4959.278"
-  cell $xor $xor$ls180.v:4959$823
+  attribute \src "ls180.v:5034.164-5034.278"
+  cell $xor $xor$ls180.v:5034$874
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg37 [2]
-    connect \B $xor$ls180.v:4959$822_Y
-    connect \Y $xor$ls180.v:4959$823_Y
+    connect \B $xor$ls180.v:5034$873_Y
+    connect \Y $xor$ls180.v:5034$874_Y
   end
-  attribute \src "ls180.v:4960.360-4960.432"
-  cell $xor $xor$ls180.v:4960$824
+  attribute \src "ls180.v:5035.360-5035.432"
+  cell $xor $xor$ls180.v:5035$875
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261355,10 +262648,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [1]
     connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
-    connect \Y $xor$ls180.v:4960$824_Y
+    connect \Y $xor$ls180.v:5035$875_Y
   end
-  attribute \src "ls180.v:4960.205-4960.277"
-  cell $xor $xor$ls180.v:4960$825
+  attribute \src "ls180.v:5035.205-5035.277"
+  cell $xor $xor$ls180.v:5035$876
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261366,21 +262659,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [1]
     connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
-    connect \Y $xor$ls180.v:4960$825_Y
+    connect \Y $xor$ls180.v:5035$876_Y
   end
-  attribute \src "ls180.v:4960.164-4960.278"
-  cell $xor $xor$ls180.v:4960$826
+  attribute \src "ls180.v:5035.164-5035.278"
+  cell $xor $xor$ls180.v:5035$877
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg38 [2]
-    connect \B $xor$ls180.v:4960$825_Y
-    connect \Y $xor$ls180.v:4960$826_Y
+    connect \B $xor$ls180.v:5035$876_Y
+    connect \Y $xor$ls180.v:5035$877_Y
   end
-  attribute \src "ls180.v:4961.360-4961.432"
-  cell $xor $xor$ls180.v:4961$827
+  attribute \src "ls180.v:5036.360-5036.432"
+  cell $xor $xor$ls180.v:5036$878
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261388,10 +262681,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [0]
     connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
-    connect \Y $xor$ls180.v:4961$827_Y
+    connect \Y $xor$ls180.v:5036$878_Y
   end
-  attribute \src "ls180.v:4961.205-4961.277"
-  cell $xor $xor$ls180.v:4961$828
+  attribute \src "ls180.v:5036.205-5036.277"
+  cell $xor $xor$ls180.v:5036$879
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261399,21 +262692,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_val [0]
     connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
-    connect \Y $xor$ls180.v:4961$828_Y
+    connect \Y $xor$ls180.v:5036$879_Y
   end
-  attribute \src "ls180.v:4961.164-4961.278"
-  cell $xor $xor$ls180.v:4961$829
+  attribute \src "ls180.v:5036.164-5036.278"
+  cell $xor $xor$ls180.v:5036$880
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc7_inserter_crcreg39 [2]
-    connect \B $xor$ls180.v:4961$828_Y
-    connect \Y $xor$ls180.v:4961$829_Y
+    connect \B $xor$ls180.v:5036$879_Y
+    connect \Y $xor$ls180.v:5036$880_Y
   end
-  attribute \src "ls180.v:4982.899-4982.983"
-  cell $xor $xor$ls180.v:4982$843
+  attribute \src "ls180.v:5057.899-5057.983"
+  cell $xor $xor$ls180.v:5057$894
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261421,10 +262714,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:4982$843_Y
+    connect \Y $xor$ls180.v:5057$894_Y
   end
-  attribute \src "ls180.v:4982.634-4982.718"
-  cell $xor $xor$ls180.v:4982$844
+  attribute \src "ls180.v:5057.634-5057.718"
+  cell $xor $xor$ls180.v:5057$895
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261432,21 +262725,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:4982$844_Y
+    connect \Y $xor$ls180.v:5057$895_Y
   end
-  attribute \src "ls180.v:4982.588-4982.719"
-  cell $xor $xor$ls180.v:4982$845
+  attribute \src "ls180.v:5057.588-5057.719"
+  cell $xor $xor$ls180.v:5057$896
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4]
-    connect \B $xor$ls180.v:4982$844_Y
-    connect \Y $xor$ls180.v:4982$845_Y
+    connect \B $xor$ls180.v:5057$895_Y
+    connect \Y $xor$ls180.v:5057$896_Y
   end
-  attribute \src "ls180.v:4982.234-4982.318"
-  cell $xor $xor$ls180.v:4982$846
+  attribute \src "ls180.v:5057.234-5057.318"
+  cell $xor $xor$ls180.v:5057$897
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261454,21 +262747,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:4982$846_Y
+    connect \Y $xor$ls180.v:5057$897_Y
   end
-  attribute \src "ls180.v:4982.187-4982.319"
-  cell $xor $xor$ls180.v:4982$847
+  attribute \src "ls180.v:5057.187-5057.319"
+  cell $xor $xor$ls180.v:5057$898
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11]
-    connect \B $xor$ls180.v:4982$846_Y
-    connect \Y $xor$ls180.v:4982$847_Y
+    connect \B $xor$ls180.v:5057$897_Y
+    connect \Y $xor$ls180.v:5057$898_Y
   end
-  attribute \src "ls180.v:4983.899-4983.983"
-  cell $xor $xor$ls180.v:4983$848
+  attribute \src "ls180.v:5058.899-5058.983"
+  cell $xor $xor$ls180.v:5058$899
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261476,10 +262769,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:4983$848_Y
+    connect \Y $xor$ls180.v:5058$899_Y
   end
-  attribute \src "ls180.v:4983.634-4983.718"
-  cell $xor $xor$ls180.v:4983$849
+  attribute \src "ls180.v:5058.634-5058.718"
+  cell $xor $xor$ls180.v:5058$900
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261487,21 +262780,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:4983$849_Y
+    connect \Y $xor$ls180.v:5058$900_Y
   end
-  attribute \src "ls180.v:4983.588-4983.719"
-  cell $xor $xor$ls180.v:4983$850
+  attribute \src "ls180.v:5058.588-5058.719"
+  cell $xor $xor$ls180.v:5058$901
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4]
-    connect \B $xor$ls180.v:4983$849_Y
-    connect \Y $xor$ls180.v:4983$850_Y
+    connect \B $xor$ls180.v:5058$900_Y
+    connect \Y $xor$ls180.v:5058$901_Y
   end
-  attribute \src "ls180.v:4983.234-4983.318"
-  cell $xor $xor$ls180.v:4983$851
+  attribute \src "ls180.v:5058.234-5058.318"
+  cell $xor $xor$ls180.v:5058$902
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261509,21 +262802,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:4983$851_Y
+    connect \Y $xor$ls180.v:5058$902_Y
   end
-  attribute \src "ls180.v:4983.187-4983.319"
-  cell $xor $xor$ls180.v:4983$852
+  attribute \src "ls180.v:5058.187-5058.319"
+  cell $xor $xor$ls180.v:5058$903
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11]
-    connect \B $xor$ls180.v:4983$851_Y
-    connect \Y $xor$ls180.v:4983$852_Y
+    connect \B $xor$ls180.v:5058$902_Y
+    connect \Y $xor$ls180.v:5058$903_Y
   end
-  attribute \src "ls180.v:4992.899-4992.983"
-  cell $xor $xor$ls180.v:4992$854
+  attribute \src "ls180.v:5067.899-5067.983"
+  cell $xor $xor$ls180.v:5067$905
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261531,10 +262824,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:4992$854_Y
+    connect \Y $xor$ls180.v:5067$905_Y
   end
-  attribute \src "ls180.v:4992.634-4992.718"
-  cell $xor $xor$ls180.v:4992$855
+  attribute \src "ls180.v:5067.634-5067.718"
+  cell $xor $xor$ls180.v:5067$906
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261542,21 +262835,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:4992$855_Y
+    connect \Y $xor$ls180.v:5067$906_Y
   end
-  attribute \src "ls180.v:4992.588-4992.719"
-  cell $xor $xor$ls180.v:4992$856
+  attribute \src "ls180.v:5067.588-5067.719"
+  cell $xor $xor$ls180.v:5067$907
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4]
-    connect \B $xor$ls180.v:4992$855_Y
-    connect \Y $xor$ls180.v:4992$856_Y
+    connect \B $xor$ls180.v:5067$906_Y
+    connect \Y $xor$ls180.v:5067$907_Y
   end
-  attribute \src "ls180.v:4992.234-4992.318"
-  cell $xor $xor$ls180.v:4992$857
+  attribute \src "ls180.v:5067.234-5067.318"
+  cell $xor $xor$ls180.v:5067$908
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261564,21 +262857,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:4992$857_Y
+    connect \Y $xor$ls180.v:5067$908_Y
   end
-  attribute \src "ls180.v:4992.187-4992.319"
-  cell $xor $xor$ls180.v:4992$858
+  attribute \src "ls180.v:5067.187-5067.319"
+  cell $xor $xor$ls180.v:5067$909
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11]
-    connect \B $xor$ls180.v:4992$857_Y
-    connect \Y $xor$ls180.v:4992$858_Y
+    connect \B $xor$ls180.v:5067$908_Y
+    connect \Y $xor$ls180.v:5067$909_Y
   end
-  attribute \src "ls180.v:4993.899-4993.983"
-  cell $xor $xor$ls180.v:4993$859
+  attribute \src "ls180.v:5068.899-5068.983"
+  cell $xor $xor$ls180.v:5068$910
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261586,10 +262879,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:4993$859_Y
+    connect \Y $xor$ls180.v:5068$910_Y
   end
-  attribute \src "ls180.v:4993.634-4993.718"
-  cell $xor $xor$ls180.v:4993$860
+  attribute \src "ls180.v:5068.634-5068.718"
+  cell $xor $xor$ls180.v:5068$911
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261597,21 +262890,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:4993$860_Y
+    connect \Y $xor$ls180.v:5068$911_Y
   end
-  attribute \src "ls180.v:4993.588-4993.719"
-  cell $xor $xor$ls180.v:4993$861
+  attribute \src "ls180.v:5068.588-5068.719"
+  cell $xor $xor$ls180.v:5068$912
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4]
-    connect \B $xor$ls180.v:4993$860_Y
-    connect \Y $xor$ls180.v:4993$861_Y
+    connect \B $xor$ls180.v:5068$911_Y
+    connect \Y $xor$ls180.v:5068$912_Y
   end
-  attribute \src "ls180.v:4993.234-4993.318"
-  cell $xor $xor$ls180.v:4993$862
+  attribute \src "ls180.v:5068.234-5068.318"
+  cell $xor $xor$ls180.v:5068$913
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261619,21 +262912,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:4993$862_Y
+    connect \Y $xor$ls180.v:5068$913_Y
   end
-  attribute \src "ls180.v:4993.187-4993.319"
-  cell $xor $xor$ls180.v:4993$863
+  attribute \src "ls180.v:5068.187-5068.319"
+  cell $xor $xor$ls180.v:5068$914
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11]
-    connect \B $xor$ls180.v:4993$862_Y
-    connect \Y $xor$ls180.v:4993$863_Y
+    connect \B $xor$ls180.v:5068$913_Y
+    connect \Y $xor$ls180.v:5068$914_Y
   end
-  attribute \src "ls180.v:5002.899-5002.983"
-  cell $xor $xor$ls180.v:5002$865
+  attribute \src "ls180.v:5077.899-5077.983"
+  cell $xor $xor$ls180.v:5077$916
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261641,10 +262934,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5002$865_Y
+    connect \Y $xor$ls180.v:5077$916_Y
   end
-  attribute \src "ls180.v:5002.634-5002.718"
-  cell $xor $xor$ls180.v:5002$866
+  attribute \src "ls180.v:5077.634-5077.718"
+  cell $xor $xor$ls180.v:5077$917
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261652,21 +262945,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5002$866_Y
+    connect \Y $xor$ls180.v:5077$917_Y
   end
-  attribute \src "ls180.v:5002.588-5002.719"
-  cell $xor $xor$ls180.v:5002$867
+  attribute \src "ls180.v:5077.588-5077.719"
+  cell $xor $xor$ls180.v:5077$918
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4]
-    connect \B $xor$ls180.v:5002$866_Y
-    connect \Y $xor$ls180.v:5002$867_Y
+    connect \B $xor$ls180.v:5077$917_Y
+    connect \Y $xor$ls180.v:5077$918_Y
   end
-  attribute \src "ls180.v:5002.234-5002.318"
-  cell $xor $xor$ls180.v:5002$868
+  attribute \src "ls180.v:5077.234-5077.318"
+  cell $xor $xor$ls180.v:5077$919
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261674,21 +262967,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5002$868_Y
+    connect \Y $xor$ls180.v:5077$919_Y
   end
-  attribute \src "ls180.v:5002.187-5002.319"
-  cell $xor $xor$ls180.v:5002$869
+  attribute \src "ls180.v:5077.187-5077.319"
+  cell $xor $xor$ls180.v:5077$920
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11]
-    connect \B $xor$ls180.v:5002$868_Y
-    connect \Y $xor$ls180.v:5002$869_Y
+    connect \B $xor$ls180.v:5077$919_Y
+    connect \Y $xor$ls180.v:5077$920_Y
   end
-  attribute \src "ls180.v:5003.899-5003.983"
-  cell $xor $xor$ls180.v:5003$870
+  attribute \src "ls180.v:5078.899-5078.983"
+  cell $xor $xor$ls180.v:5078$921
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261696,10 +262989,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5003$870_Y
+    connect \Y $xor$ls180.v:5078$921_Y
   end
-  attribute \src "ls180.v:5003.634-5003.718"
-  cell $xor $xor$ls180.v:5003$871
+  attribute \src "ls180.v:5078.634-5078.718"
+  cell $xor $xor$ls180.v:5078$922
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261707,21 +263000,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5003$871_Y
+    connect \Y $xor$ls180.v:5078$922_Y
   end
-  attribute \src "ls180.v:5003.588-5003.719"
-  cell $xor $xor$ls180.v:5003$872
+  attribute \src "ls180.v:5078.588-5078.719"
+  cell $xor $xor$ls180.v:5078$923
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4]
-    connect \B $xor$ls180.v:5003$871_Y
-    connect \Y $xor$ls180.v:5003$872_Y
+    connect \B $xor$ls180.v:5078$922_Y
+    connect \Y $xor$ls180.v:5078$923_Y
   end
-  attribute \src "ls180.v:5003.234-5003.318"
-  cell $xor $xor$ls180.v:5003$873
+  attribute \src "ls180.v:5078.234-5078.318"
+  cell $xor $xor$ls180.v:5078$924
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261729,21 +263022,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5003$873_Y
+    connect \Y $xor$ls180.v:5078$924_Y
   end
-  attribute \src "ls180.v:5003.187-5003.319"
-  cell $xor $xor$ls180.v:5003$874
+  attribute \src "ls180.v:5078.187-5078.319"
+  cell $xor $xor$ls180.v:5078$925
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11]
-    connect \B $xor$ls180.v:5003$873_Y
-    connect \Y $xor$ls180.v:5003$874_Y
+    connect \B $xor$ls180.v:5078$924_Y
+    connect \Y $xor$ls180.v:5078$925_Y
   end
-  attribute \src "ls180.v:5012.899-5012.983"
-  cell $xor $xor$ls180.v:5012$876
+  attribute \src "ls180.v:5087.899-5087.983"
+  cell $xor $xor$ls180.v:5087$927
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261751,10 +263044,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5012$876_Y
+    connect \Y $xor$ls180.v:5087$927_Y
   end
-  attribute \src "ls180.v:5012.634-5012.718"
-  cell $xor $xor$ls180.v:5012$877
+  attribute \src "ls180.v:5087.634-5087.718"
+  cell $xor $xor$ls180.v:5087$928
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261762,21 +263055,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5012$877_Y
+    connect \Y $xor$ls180.v:5087$928_Y
   end
-  attribute \src "ls180.v:5012.588-5012.719"
-  cell $xor $xor$ls180.v:5012$878
+  attribute \src "ls180.v:5087.588-5087.719"
+  cell $xor $xor$ls180.v:5087$929
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4]
-    connect \B $xor$ls180.v:5012$877_Y
-    connect \Y $xor$ls180.v:5012$878_Y
+    connect \B $xor$ls180.v:5087$928_Y
+    connect \Y $xor$ls180.v:5087$929_Y
   end
-  attribute \src "ls180.v:5012.234-5012.318"
-  cell $xor $xor$ls180.v:5012$879
+  attribute \src "ls180.v:5087.234-5087.318"
+  cell $xor $xor$ls180.v:5087$930
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261784,21 +263077,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5012$879_Y
+    connect \Y $xor$ls180.v:5087$930_Y
   end
-  attribute \src "ls180.v:5012.187-5012.319"
-  cell $xor $xor$ls180.v:5012$880
+  attribute \src "ls180.v:5087.187-5087.319"
+  cell $xor $xor$ls180.v:5087$931
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11]
-    connect \B $xor$ls180.v:5012$879_Y
-    connect \Y $xor$ls180.v:5012$880_Y
+    connect \B $xor$ls180.v:5087$930_Y
+    connect \Y $xor$ls180.v:5087$931_Y
   end
-  attribute \src "ls180.v:5013.899-5013.983"
-  cell $xor $xor$ls180.v:5013$881
+  attribute \src "ls180.v:5088.899-5088.983"
+  cell $xor $xor$ls180.v:5088$932
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261806,10 +263099,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5013$881_Y
+    connect \Y $xor$ls180.v:5088$932_Y
   end
-  attribute \src "ls180.v:5013.634-5013.718"
-  cell $xor $xor$ls180.v:5013$882
+  attribute \src "ls180.v:5088.634-5088.718"
+  cell $xor $xor$ls180.v:5088$933
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261817,21 +263110,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5013$882_Y
+    connect \Y $xor$ls180.v:5088$933_Y
   end
-  attribute \src "ls180.v:5013.588-5013.719"
-  cell $xor $xor$ls180.v:5013$883
+  attribute \src "ls180.v:5088.588-5088.719"
+  cell $xor $xor$ls180.v:5088$934
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4]
-    connect \B $xor$ls180.v:5013$882_Y
-    connect \Y $xor$ls180.v:5013$883_Y
+    connect \B $xor$ls180.v:5088$933_Y
+    connect \Y $xor$ls180.v:5088$934_Y
   end
-  attribute \src "ls180.v:5013.234-5013.318"
-  cell $xor $xor$ls180.v:5013$884
+  attribute \src "ls180.v:5088.234-5088.318"
+  cell $xor $xor$ls180.v:5088$935
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261839,21 +263132,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5013$884_Y
+    connect \Y $xor$ls180.v:5088$935_Y
   end
-  attribute \src "ls180.v:5013.187-5013.319"
-  cell $xor $xor$ls180.v:5013$885
+  attribute \src "ls180.v:5088.187-5088.319"
+  cell $xor $xor$ls180.v:5088$936
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11]
-    connect \B $xor$ls180.v:5013$884_Y
-    connect \Y $xor$ls180.v:5013$885_Y
+    connect \B $xor$ls180.v:5088$935_Y
+    connect \Y $xor$ls180.v:5088$936_Y
   end
-  attribute \src "ls180.v:5164.879-5164.961"
-  cell $xor $xor$ls180.v:5164$918
+  attribute \src "ls180.v:5239.879-5239.961"
+  cell $xor $xor$ls180.v:5239$969
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261861,10 +263154,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [1]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:5164$918_Y
+    connect \Y $xor$ls180.v:5239$969_Y
   end
-  attribute \src "ls180.v:5164.620-5164.702"
-  cell $xor $xor$ls180.v:5164$919
+  attribute \src "ls180.v:5239.620-5239.702"
+  cell $xor $xor$ls180.v:5239$970
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261872,21 +263165,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [1]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:5164$919_Y
+    connect \Y $xor$ls180.v:5239$970_Y
   end
-  attribute \src "ls180.v:5164.575-5164.703"
-  cell $xor $xor$ls180.v:5164$920
+  attribute \src "ls180.v:5239.575-5239.703"
+  cell $xor $xor$ls180.v:5239$971
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4]
-    connect \B $xor$ls180.v:5164$919_Y
-    connect \Y $xor$ls180.v:5164$920_Y
+    connect \B $xor$ls180.v:5239$970_Y
+    connect \Y $xor$ls180.v:5239$971_Y
   end
-  attribute \src "ls180.v:5164.229-5164.311"
-  cell $xor $xor$ls180.v:5164$921
+  attribute \src "ls180.v:5239.229-5239.311"
+  cell $xor $xor$ls180.v:5239$972
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261894,21 +263187,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [1]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
-    connect \Y $xor$ls180.v:5164$921_Y
+    connect \Y $xor$ls180.v:5239$972_Y
   end
-  attribute \src "ls180.v:5164.183-5164.312"
-  cell $xor $xor$ls180.v:5164$922
+  attribute \src "ls180.v:5239.183-5239.312"
+  cell $xor $xor$ls180.v:5239$973
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11]
-    connect \B $xor$ls180.v:5164$921_Y
-    connect \Y $xor$ls180.v:5164$922_Y
+    connect \B $xor$ls180.v:5239$972_Y
+    connect \Y $xor$ls180.v:5239$973_Y
   end
-  attribute \src "ls180.v:5165.879-5165.961"
-  cell $xor $xor$ls180.v:5165$923
+  attribute \src "ls180.v:5240.879-5240.961"
+  cell $xor $xor$ls180.v:5240$974
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261916,10 +263209,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [0]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:5165$923_Y
+    connect \Y $xor$ls180.v:5240$974_Y
   end
-  attribute \src "ls180.v:5165.620-5165.702"
-  cell $xor $xor$ls180.v:5165$924
+  attribute \src "ls180.v:5240.620-5240.702"
+  cell $xor $xor$ls180.v:5240$975
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261927,21 +263220,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [0]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:5165$924_Y
+    connect \Y $xor$ls180.v:5240$975_Y
   end
-  attribute \src "ls180.v:5165.575-5165.703"
-  cell $xor $xor$ls180.v:5165$925
+  attribute \src "ls180.v:5240.575-5240.703"
+  cell $xor $xor$ls180.v:5240$976
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4]
-    connect \B $xor$ls180.v:5165$924_Y
-    connect \Y $xor$ls180.v:5165$925_Y
+    connect \B $xor$ls180.v:5240$975_Y
+    connect \Y $xor$ls180.v:5240$976_Y
   end
-  attribute \src "ls180.v:5165.229-5165.311"
-  cell $xor $xor$ls180.v:5165$926
+  attribute \src "ls180.v:5240.229-5240.311"
+  cell $xor $xor$ls180.v:5240$977
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261949,21 +263242,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_val [0]
     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
-    connect \Y $xor$ls180.v:5165$926_Y
+    connect \Y $xor$ls180.v:5240$977_Y
   end
-  attribute \src "ls180.v:5165.183-5165.312"
-  cell $xor $xor$ls180.v:5165$927
+  attribute \src "ls180.v:5240.183-5240.312"
+  cell $xor $xor$ls180.v:5240$978
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11]
-    connect \B $xor$ls180.v:5165$926_Y
-    connect \Y $xor$ls180.v:5165$927_Y
+    connect \B $xor$ls180.v:5240$977_Y
+    connect \Y $xor$ls180.v:5240$978_Y
   end
-  attribute \src "ls180.v:5174.879-5174.961"
-  cell $xor $xor$ls180.v:5174$929
+  attribute \src "ls180.v:5249.879-5249.961"
+  cell $xor $xor$ls180.v:5249$980
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261971,10 +263264,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [1]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:5174$929_Y
+    connect \Y $xor$ls180.v:5249$980_Y
   end
-  attribute \src "ls180.v:5174.620-5174.702"
-  cell $xor $xor$ls180.v:5174$930
+  attribute \src "ls180.v:5249.620-5249.702"
+  cell $xor $xor$ls180.v:5249$981
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261982,21 +263275,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [1]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:5174$930_Y
+    connect \Y $xor$ls180.v:5249$981_Y
   end
-  attribute \src "ls180.v:5174.575-5174.703"
-  cell $xor $xor$ls180.v:5174$931
+  attribute \src "ls180.v:5249.575-5249.703"
+  cell $xor $xor$ls180.v:5249$982
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4]
-    connect \B $xor$ls180.v:5174$930_Y
-    connect \Y $xor$ls180.v:5174$931_Y
+    connect \B $xor$ls180.v:5249$981_Y
+    connect \Y $xor$ls180.v:5249$982_Y
   end
-  attribute \src "ls180.v:5174.229-5174.311"
-  cell $xor $xor$ls180.v:5174$932
+  attribute \src "ls180.v:5249.229-5249.311"
+  cell $xor $xor$ls180.v:5249$983
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262004,21 +263297,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [1]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
-    connect \Y $xor$ls180.v:5174$932_Y
+    connect \Y $xor$ls180.v:5249$983_Y
   end
-  attribute \src "ls180.v:5174.183-5174.312"
-  cell $xor $xor$ls180.v:5174$933
+  attribute \src "ls180.v:5249.183-5249.312"
+  cell $xor $xor$ls180.v:5249$984
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11]
-    connect \B $xor$ls180.v:5174$932_Y
-    connect \Y $xor$ls180.v:5174$933_Y
+    connect \B $xor$ls180.v:5249$983_Y
+    connect \Y $xor$ls180.v:5249$984_Y
   end
-  attribute \src "ls180.v:5175.879-5175.961"
-  cell $xor $xor$ls180.v:5175$934
+  attribute \src "ls180.v:5250.879-5250.961"
+  cell $xor $xor$ls180.v:5250$985
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262026,10 +263319,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [0]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:5175$934_Y
+    connect \Y $xor$ls180.v:5250$985_Y
   end
-  attribute \src "ls180.v:5175.620-5175.702"
-  cell $xor $xor$ls180.v:5175$935
+  attribute \src "ls180.v:5250.620-5250.702"
+  cell $xor $xor$ls180.v:5250$986
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262037,21 +263330,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [0]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:5175$935_Y
+    connect \Y $xor$ls180.v:5250$986_Y
   end
-  attribute \src "ls180.v:5175.575-5175.703"
-  cell $xor $xor$ls180.v:5175$936
+  attribute \src "ls180.v:5250.575-5250.703"
+  cell $xor $xor$ls180.v:5250$987
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4]
-    connect \B $xor$ls180.v:5175$935_Y
-    connect \Y $xor$ls180.v:5175$936_Y
+    connect \B $xor$ls180.v:5250$986_Y
+    connect \Y $xor$ls180.v:5250$987_Y
   end
-  attribute \src "ls180.v:5175.229-5175.311"
-  cell $xor $xor$ls180.v:5175$937
+  attribute \src "ls180.v:5250.229-5250.311"
+  cell $xor $xor$ls180.v:5250$988
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262059,21 +263352,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_val [0]
     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
-    connect \Y $xor$ls180.v:5175$937_Y
+    connect \Y $xor$ls180.v:5250$988_Y
   end
-  attribute \src "ls180.v:5175.183-5175.312"
-  cell $xor $xor$ls180.v:5175$938
+  attribute \src "ls180.v:5250.183-5250.312"
+  cell $xor $xor$ls180.v:5250$989
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11]
-    connect \B $xor$ls180.v:5175$937_Y
-    connect \Y $xor$ls180.v:5175$938_Y
+    connect \B $xor$ls180.v:5250$988_Y
+    connect \Y $xor$ls180.v:5250$989_Y
   end
-  attribute \src "ls180.v:5184.879-5184.961"
-  cell $xor $xor$ls180.v:5184$940
+  attribute \src "ls180.v:5259.879-5259.961"
+  cell $xor $xor$ls180.v:5259$991
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262081,10 +263374,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_val [1]
     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5184$940_Y
+    connect \Y $xor$ls180.v:5259$991_Y
   end
-  attribute \src "ls180.v:5184.620-5184.702"
-  cell $xor $xor$ls180.v:5184$941
+  attribute \src "ls180.v:5259.620-5259.702"
+  cell $xor $xor$ls180.v:5259$992
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262092,21 +263385,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_val [1]
     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5184$941_Y
+    connect \Y $xor$ls180.v:5259$992_Y
   end
-  attribute \src "ls180.v:5184.575-5184.703"
-  cell $xor $xor$ls180.v:5184$942
+  attribute \src "ls180.v:5259.575-5259.703"
+  cell $xor $xor$ls180.v:5259$993
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4]
-    connect \B $xor$ls180.v:5184$941_Y
-    connect \Y $xor$ls180.v:5184$942_Y
+    connect \B $xor$ls180.v:5259$992_Y
+    connect \Y $xor$ls180.v:5259$993_Y
   end
-  attribute \src "ls180.v:5184.229-5184.311"
-  cell $xor $xor$ls180.v:5184$943
+  attribute \src "ls180.v:5259.229-5259.311"
+  cell $xor $xor$ls180.v:5259$994
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262114,32 +263407,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_val [1]
     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
-    connect \Y $xor$ls180.v:5184$943_Y
+    connect \Y $xor$ls180.v:5259$994_Y
   end
-  attribute \src "ls180.v:5184.183-5184.312"
-  cell $xor $xor$ls180.v:5184$944
+  attribute \src "ls180.v:5259.183-5259.312"
+  cell $xor $xor$ls180.v:5259$995
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11]
-    connect \B $xor$ls180.v:5184$943_Y
-    connect \Y $xor$ls180.v:5184$944_Y
+    connect \B $xor$ls180.v:5259$994_Y
+    connect \Y $xor$ls180.v:5259$995_Y
   end
-  attribute \src "ls180.v:5185.879-5185.961"
-  cell $xor $xor$ls180.v:5185$945
+  attribute \src "ls180.v:5260.183-5260.312"
+  cell $xor $xor$ls180.v:5260$1000
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \main_sdcore_crc16_checker_crc2_val [0]
-    connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5185$945_Y
+    connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11]
+    connect \B $xor$ls180.v:5260$999_Y
+    connect \Y $xor$ls180.v:5260$1000_Y
   end
-  attribute \src "ls180.v:5185.620-5185.702"
-  cell $xor $xor$ls180.v:5185$946
+  attribute \src "ls180.v:5260.879-5260.961"
+  cell $xor $xor$ls180.v:5260$996
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262147,43 +263440,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc2_val [0]
     connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5185$946_Y
+    connect \Y $xor$ls180.v:5260$996_Y
   end
-  attribute \src "ls180.v:5185.575-5185.703"
-  cell $xor $xor$ls180.v:5185$947
+  attribute \src "ls180.v:5260.620-5260.702"
+  cell $xor $xor$ls180.v:5260$997
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4]
-    connect \B $xor$ls180.v:5185$946_Y
-    connect \Y $xor$ls180.v:5185$947_Y
+    connect \A \main_sdcore_crc16_checker_crc2_val [0]
+    connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
+    connect \Y $xor$ls180.v:5260$997_Y
   end
-  attribute \src "ls180.v:5185.229-5185.311"
-  cell $xor $xor$ls180.v:5185$948
+  attribute \src "ls180.v:5260.575-5260.703"
+  cell $xor $xor$ls180.v:5260$998
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \main_sdcore_crc16_checker_crc2_val [0]
-    connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
-    connect \Y $xor$ls180.v:5185$948_Y
+    connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4]
+    connect \B $xor$ls180.v:5260$997_Y
+    connect \Y $xor$ls180.v:5260$998_Y
   end
-  attribute \src "ls180.v:5185.183-5185.312"
-  cell $xor $xor$ls180.v:5185$949
+  attribute \src "ls180.v:5260.229-5260.311"
+  cell $xor $xor$ls180.v:5260$999
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11]
-    connect \B $xor$ls180.v:5185$948_Y
-    connect \Y $xor$ls180.v:5185$949_Y
+    connect \A \main_sdcore_crc16_checker_crc2_val [0]
+    connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
+    connect \Y $xor$ls180.v:5260$999_Y
   end
-  attribute \src "ls180.v:5194.879-5194.961"
-  cell $xor $xor$ls180.v:5194$951
+  attribute \src "ls180.v:5269.879-5269.961"
+  cell $xor $xor$ls180.v:5269$1002
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262191,10 +263484,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [1]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5194$951_Y
+    connect \Y $xor$ls180.v:5269$1002_Y
   end
-  attribute \src "ls180.v:5194.620-5194.702"
-  cell $xor $xor$ls180.v:5194$952
+  attribute \src "ls180.v:5269.620-5269.702"
+  cell $xor $xor$ls180.v:5269$1003
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262202,21 +263495,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [1]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5194$952_Y
+    connect \Y $xor$ls180.v:5269$1003_Y
   end
-  attribute \src "ls180.v:5194.575-5194.703"
-  cell $xor $xor$ls180.v:5194$953
+  attribute \src "ls180.v:5269.575-5269.703"
+  cell $xor $xor$ls180.v:5269$1004
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4]
-    connect \B $xor$ls180.v:5194$952_Y
-    connect \Y $xor$ls180.v:5194$953_Y
+    connect \B $xor$ls180.v:5269$1003_Y
+    connect \Y $xor$ls180.v:5269$1004_Y
   end
-  attribute \src "ls180.v:5194.229-5194.311"
-  cell $xor $xor$ls180.v:5194$954
+  attribute \src "ls180.v:5269.229-5269.311"
+  cell $xor $xor$ls180.v:5269$1005
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262224,21 +263517,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [1]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
-    connect \Y $xor$ls180.v:5194$954_Y
+    connect \Y $xor$ls180.v:5269$1005_Y
   end
-  attribute \src "ls180.v:5194.183-5194.312"
-  cell $xor $xor$ls180.v:5194$955
+  attribute \src "ls180.v:5269.183-5269.312"
+  cell $xor $xor$ls180.v:5269$1006
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11]
-    connect \B $xor$ls180.v:5194$954_Y
-    connect \Y $xor$ls180.v:5194$955_Y
+    connect \B $xor$ls180.v:5269$1005_Y
+    connect \Y $xor$ls180.v:5269$1006_Y
   end
-  attribute \src "ls180.v:5195.879-5195.961"
-  cell $xor $xor$ls180.v:5195$956
+  attribute \src "ls180.v:5270.879-5270.961"
+  cell $xor $xor$ls180.v:5270$1007
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262246,10 +263539,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [0]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5195$956_Y
+    connect \Y $xor$ls180.v:5270$1007_Y
   end
-  attribute \src "ls180.v:5195.620-5195.702"
-  cell $xor $xor$ls180.v:5195$957
+  attribute \src "ls180.v:5270.620-5270.702"
+  cell $xor $xor$ls180.v:5270$1008
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262257,21 +263550,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [0]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5195$957_Y
+    connect \Y $xor$ls180.v:5270$1008_Y
   end
-  attribute \src "ls180.v:5195.575-5195.703"
-  cell $xor $xor$ls180.v:5195$958
+  attribute \src "ls180.v:5270.575-5270.703"
+  cell $xor $xor$ls180.v:5270$1009
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4]
-    connect \B $xor$ls180.v:5195$957_Y
-    connect \Y $xor$ls180.v:5195$958_Y
+    connect \B $xor$ls180.v:5270$1008_Y
+    connect \Y $xor$ls180.v:5270$1009_Y
   end
-  attribute \src "ls180.v:5195.229-5195.311"
-  cell $xor $xor$ls180.v:5195$959
+  attribute \src "ls180.v:5270.229-5270.311"
+  cell $xor $xor$ls180.v:5270$1010
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -262279,21 +263572,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_val [0]
     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
-    connect \Y $xor$ls180.v:5195$959_Y
+    connect \Y $xor$ls180.v:5270$1010_Y
   end
-  attribute \src "ls180.v:5195.183-5195.312"
-  cell $xor $xor$ls180.v:5195$960
+  attribute \src "ls180.v:5270.183-5270.312"
+  cell $xor $xor$ls180.v:5270$1011
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11]
-    connect \B $xor$ls180.v:5195$959_Y
-    connect \Y $xor$ls180.v:5195$960_Y
+    connect \B $xor$ls180.v:5270$1010_Y
+    connect \Y $xor$ls180.v:5270$1011_Y
   end
   attribute \module_not_derived 1
-  attribute \src "ls180.v:10179.13-10553.2"
+  attribute \src "ls180.v:10356.13-10730.2"
   cell \test_issuer \test_issuer
     connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
     connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
@@ -262489,7 +263782,7 @@ module \ls180
     connect \pwm_0__pad__o \pwm_1 [0]
     connect \pwm_1__core__o \pwm [1]
     connect \pwm_1__pad__o \pwm_1 [1]
-    connect \rst $or$ls180.v:10279$2750_Y
+    connect \rst $or$ls180.v:10456$2870_Y
     connect \sd0_clk__core__o \sdcard_clk
     connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
     connect \sd0_cmd__core__i \sdcard_cmd_i
@@ -262670,28 +263963,67 @@ module \ls180
     connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
   end
   attribute \src "ls180.v:0.0-0.0"
-  process $proc$ls180.v:0$3701
+  process $proc$ls180.v:0$3842
     sync always
     sync init
   end
-  attribute \src "ls180.v:1000.5-1000.31"
-  process $proc$ls180.v:1000$3130
-    assign { } { }
-    assign $1\main_spimaster12_re[0:0] 1'0
+  attribute \src "ls180.v:0.0-0.0"
+  process $proc$ls180.v:0$3843
+    sync always
+    sync init
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  process $proc$ls180.v:0$3844
+    sync always
+    sync init
+  end
+  attribute \src "ls180.v:0.0-0.0"
+  process $proc$ls180.v:0$3845
     sync always
     sync init
-      update \main_spimaster12_re $1\main_spimaster12_re[0:0]
   end
   attribute \src "ls180.v:1004.11-1004.42"
-  process $proc$ls180.v:1004$3131
+  process $proc$ls180.v:1004$3254
     assign { } { }
-    assign $1\main_spimaster16_storage[7:0] 8'00000000
+    assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
     sync always
     sync init
-      update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
+      update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
+  end
+  attribute \src "ls180.v:1005.5-1005.37"
+  process $proc$ls180.v:1005$3255
+    assign { } { }
+    assign $0\main_uart_rx_fifo_replace[0:0] 1'0
+    sync always
+      update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:1006.11-1006.43"
+  process $proc$ls180.v:1006$3256
+    assign { } { }
+    assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
+    sync always
+    sync init
+      update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
+  end
+  attribute \src "ls180.v:1007.11-1007.43"
+  process $proc$ls180.v:1007$3257
+    assign { } { }
+    assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
+    sync always
+    sync init
+      update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
+  end
+  attribute \src "ls180.v:1008.11-1008.46"
+  process $proc$ls180.v:1008$3258
+    assign { } { }
+    assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
+    sync always
+    sync init
+      update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:10043.1-10053.4"
-  process $proc$ls180.v:10043$2680
+  attribute \src "ls180.v:10160.1-10170.4"
+  process $proc$ls180.v:10160$2758
     assign { } { }
     assign { } { }
     assign { } { }
@@ -262705,4290 +264037,4631 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 0
-    assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 0
-    assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 0
-    assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 0
+    assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 0
+    assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 0
+    assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 0
+    assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 0
     assign $0\memadr[6:0] \main_libresocsim_adr
-    attribute \src "ls180.v:10044.2-10045.65"
+    attribute \src "ls180.v:10161.2-10162.65"
     switch \main_libresocsim_we [0]
-      attribute \src "ls180.v:10044.6-10044.28"
+      attribute \src "ls180.v:10161.6-10161.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
-        assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 255
+        assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
+        assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 255
       case 
     end
-    attribute \src "ls180.v:10046.2-10047.67"
+    attribute \src "ls180.v:10163.2-10164.67"
     switch \main_libresocsim_we [1]
-      attribute \src "ls180.v:10046.6-10046.28"
+      attribute \src "ls180.v:10163.6-10163.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 65280
+        assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 65280
       case 
     end
-    attribute \src "ls180.v:10048.2-10049.69"
+    attribute \src "ls180.v:10165.2-10166.69"
     switch \main_libresocsim_we [2]
-      attribute \src "ls180.v:10048.6-10048.28"
+      attribute \src "ls180.v:10165.6-10165.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 16711680
+        assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 16711680
       case 
     end
-    attribute \src "ls180.v:10050.2-10051.69"
+    attribute \src "ls180.v:10167.2-10168.69"
     switch \main_libresocsim_we [3]
-      attribute \src "ls180.v:10050.6-10050.28"
+      attribute \src "ls180.v:10167.6-10167.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 32'11111111000000000000000000000000
+        assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 32'11111111000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
       update \memadr $0\memadr[6:0]
-      update $memwr$\mem$ls180.v:10045$1_ADDR $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681
-      update $memwr$\mem$ls180.v:10045$1_DATA $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682
-      update $memwr$\mem$ls180.v:10045$1_EN $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683
-      update $memwr$\mem$ls180.v:10047$2_ADDR $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684
-      update $memwr$\mem$ls180.v:10047$2_DATA $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685
-      update $memwr$\mem$ls180.v:10047$2_EN $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686
-      update $memwr$\mem$ls180.v:10049$3_ADDR $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687
-      update $memwr$\mem$ls180.v:10049$3_DATA $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688
-      update $memwr$\mem$ls180.v:10049$3_EN $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689
-      update $memwr$\mem$ls180.v:10051$4_ADDR $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690
-      update $memwr$\mem$ls180.v:10051$4_DATA $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691
-      update $memwr$\mem$ls180.v:10051$4_EN $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692
-  end
-  attribute \src "ls180.v:1005.5-1005.31"
-  process $proc$ls180.v:1005$3132
+      update $memwr$\mem$ls180.v:10162$1_ADDR $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759
+      update $memwr$\mem$ls180.v:10162$1_DATA $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760
+      update $memwr$\mem$ls180.v:10162$1_EN $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761
+      update $memwr$\mem$ls180.v:10164$2_ADDR $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762
+      update $memwr$\mem$ls180.v:10164$2_DATA $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763
+      update $memwr$\mem$ls180.v:10164$2_EN $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764
+      update $memwr$\mem$ls180.v:10166$3_ADDR $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765
+      update $memwr$\mem$ls180.v:10166$3_DATA $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766
+      update $memwr$\mem$ls180.v:10166$3_EN $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767
+      update $memwr$\mem$ls180.v:10168$4_ADDR $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768
+      update $memwr$\mem$ls180.v:10168$4_DATA $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769
+      update $memwr$\mem$ls180.v:10168$4_EN $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770
+  end
+  attribute \src "ls180.v:10180.1-10190.4"
+  process $proc$ls180.v:10180$2772
     assign { } { }
-    assign $1\main_spimaster17_re[0:0] 1'0
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 7'xxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 0
+    assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 7'xxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 0
+    assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 7'xxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 0
+    assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 7'xxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 0
+    assign $0\memadr_1[6:0] \main_sram0_adr
+    attribute \src "ls180.v:10181.2-10182.55"
+    switch \main_sram0_we [0]
+      attribute \src "ls180.v:10181.6-10181.22"
+      case 1'1
+        assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 { 24'000000000000000000000000 \main_sram0_dat_w [7:0] }
+        assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 255
+      case 
+    end
+    attribute \src "ls180.v:10183.2-10184.57"
+    switch \main_sram0_we [1]
+      attribute \src "ls180.v:10183.6-10183.22"
+      case 1'1
+        assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 { 16'0000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx }
+        assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 65280
+      case 
+    end
+    attribute \src "ls180.v:10185.2-10186.59"
+    switch \main_sram0_we [2]
+      attribute \src "ls180.v:10185.6-10185.22"
+      case 1'1
+        assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 { 8'00000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 16711680
+      case 
+    end
+    attribute \src "ls180.v:10187.2-10188.59"
+    switch \main_sram0_we [3]
+      attribute \src "ls180.v:10187.6-10187.22"
+      case 1'1
+        assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 { \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 32'11111111000000000000000000000000
+      case 
+    end
+    sync posedge \sys_clk_1
+      update \memadr_1 $0\memadr_1[6:0]
+      update $memwr$\mem_1$ls180.v:10182$5_ADDR $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773
+      update $memwr$\mem_1$ls180.v:10182$5_DATA $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774
+      update $memwr$\mem_1$ls180.v:10182$5_EN $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775
+      update $memwr$\mem_1$ls180.v:10184$6_ADDR $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776
+      update $memwr$\mem_1$ls180.v:10184$6_DATA $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777
+      update $memwr$\mem_1$ls180.v:10184$6_EN $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778
+      update $memwr$\mem_1$ls180.v:10186$7_ADDR $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779
+      update $memwr$\mem_1$ls180.v:10186$7_DATA $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780
+      update $memwr$\mem_1$ls180.v:10186$7_EN $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781
+      update $memwr$\mem_1$ls180.v:10188$8_ADDR $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782
+      update $memwr$\mem_1$ls180.v:10188$8_DATA $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783
+      update $memwr$\mem_1$ls180.v:10188$8_EN $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784
+  end
+  attribute \src "ls180.v:10200.1-10210.4"
+  process $proc$ls180.v:10200$2786
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 7'xxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 0
+    assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 7'xxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 0
+    assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 7'xxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 0
+    assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 7'xxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 0
+    assign $0\memadr_2[6:0] \main_sram1_adr
+    attribute \src "ls180.v:10201.2-10202.55"
+    switch \main_sram1_we [0]
+      attribute \src "ls180.v:10201.6-10201.22"
+      case 1'1
+        assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 { 24'000000000000000000000000 \main_sram1_dat_w [7:0] }
+        assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 255
+      case 
+    end
+    attribute \src "ls180.v:10203.2-10204.57"
+    switch \main_sram1_we [1]
+      attribute \src "ls180.v:10203.6-10203.22"
+      case 1'1
+        assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 { 16'0000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx }
+        assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 65280
+      case 
+    end
+    attribute \src "ls180.v:10205.2-10206.59"
+    switch \main_sram1_we [2]
+      attribute \src "ls180.v:10205.6-10205.22"
+      case 1'1
+        assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 { 8'00000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 16711680
+      case 
+    end
+    attribute \src "ls180.v:10207.2-10208.59"
+    switch \main_sram1_we [3]
+      attribute \src "ls180.v:10207.6-10207.22"
+      case 1'1
+        assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 { \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 32'11111111000000000000000000000000
+      case 
+    end
+    sync posedge \sys_clk_1
+      update \memadr_2 $0\memadr_2[6:0]
+      update $memwr$\mem_2$ls180.v:10202$9_ADDR $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787
+      update $memwr$\mem_2$ls180.v:10202$9_DATA $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788
+      update $memwr$\mem_2$ls180.v:10202$9_EN $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789
+      update $memwr$\mem_2$ls180.v:10204$10_ADDR $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790
+      update $memwr$\mem_2$ls180.v:10204$10_DATA $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791
+      update $memwr$\mem_2$ls180.v:10204$10_EN $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792
+      update $memwr$\mem_2$ls180.v:10206$11_ADDR $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793
+      update $memwr$\mem_2$ls180.v:10206$11_DATA $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794
+      update $memwr$\mem_2$ls180.v:10206$11_EN $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795
+      update $memwr$\mem_2$ls180.v:10208$12_ADDR $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796
+      update $memwr$\mem_2$ls180.v:10208$12_DATA $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797
+      update $memwr$\mem_2$ls180.v:10208$12_EN $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798
+  end
+  attribute \src "ls180.v:10220.1-10230.4"
+  process $proc$ls180.v:10220$2800
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 7'xxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 0
+    assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 7'xxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 0
+    assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 7'xxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 0
+    assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 7'xxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 0
+    assign $0\memadr_3[6:0] \main_sram2_adr
+    attribute \src "ls180.v:10221.2-10222.55"
+    switch \main_sram2_we [0]
+      attribute \src "ls180.v:10221.6-10221.22"
+      case 1'1
+        assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 { 24'000000000000000000000000 \main_sram2_dat_w [7:0] }
+        assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 255
+      case 
+    end
+    attribute \src "ls180.v:10223.2-10224.57"
+    switch \main_sram2_we [1]
+      attribute \src "ls180.v:10223.6-10223.22"
+      case 1'1
+        assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 { 16'0000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx }
+        assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 65280
+      case 
+    end
+    attribute \src "ls180.v:10225.2-10226.59"
+    switch \main_sram2_we [2]
+      attribute \src "ls180.v:10225.6-10225.22"
+      case 1'1
+        assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 { 8'00000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 16711680
+      case 
+    end
+    attribute \src "ls180.v:10227.2-10228.59"
+    switch \main_sram2_we [3]
+      attribute \src "ls180.v:10227.6-10227.22"
+      case 1'1
+        assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 { \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 32'11111111000000000000000000000000
+      case 
+    end
+    sync posedge \sys_clk_1
+      update \memadr_3 $0\memadr_3[6:0]
+      update $memwr$\mem_3$ls180.v:10222$13_ADDR $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801
+      update $memwr$\mem_3$ls180.v:10222$13_DATA $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802
+      update $memwr$\mem_3$ls180.v:10222$13_EN $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803
+      update $memwr$\mem_3$ls180.v:10224$14_ADDR $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804
+      update $memwr$\mem_3$ls180.v:10224$14_DATA $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805
+      update $memwr$\mem_3$ls180.v:10224$14_EN $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806
+      update $memwr$\mem_3$ls180.v:10226$15_ADDR $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807
+      update $memwr$\mem_3$ls180.v:10226$15_DATA $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808
+      update $memwr$\mem_3$ls180.v:10226$15_EN $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809
+      update $memwr$\mem_3$ls180.v:10228$16_ADDR $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810
+      update $memwr$\mem_3$ls180.v:10228$16_DATA $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811
+      update $memwr$\mem_3$ls180.v:10228$16_EN $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812
+  end
+  attribute \src "ls180.v:1023.5-1023.27"
+  process $proc$ls180.v:1023$3259
+    assign { } { }
+    assign $0\main_uart_reset[0:0] 1'0
     sync always
+      update \main_uart_reset $0\main_uart_reset[0:0]
     sync init
-      update \main_spimaster17_re $1\main_spimaster17_re[0:0]
   end
-  attribute \src "ls180.v:10063.1-10067.4"
-  process $proc$ls180.v:10063$2694
+  attribute \src "ls180.v:1024.12-1024.40"
+  process $proc$ls180.v:1024$3260
+    assign { } { }
+    assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
+  end
+  attribute \src "ls180.v:10240.1-10244.4"
+  process $proc$ls180.v:10240$2814
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 3'xxx
-    assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'0000000000000000000000000
-    assign $0\memdat[24:0] $memrd$\storage$ls180.v:10066$2698_DATA
-    attribute \src "ls180.v:10064.2-10065.129"
+    assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 3'xxx
+    assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'0000000000000000000000000
+    assign $0\memdat[24:0] $memrd$\storage$ls180.v:10243$2818_DATA
+    attribute \src "ls180.v:10241.2-10242.129"
     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10064.6-10064.60"
+      attribute \src "ls180.v:10241.6-10241.60"
       case 1'1
-        assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'1111111111111111111111111
+        assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat $0\memdat[24:0]
-      update $memwr$\storage$ls180.v:10065$5_ADDR $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695
-      update $memwr$\storage$ls180.v:10065$5_DATA $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696
-      update $memwr$\storage$ls180.v:10065$5_EN $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697
+      update $memwr$\storage$ls180.v:10242$17_ADDR $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815
+      update $memwr$\storage$ls180.v:10242$17_DATA $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816
+      update $memwr$\storage$ls180.v:10242$17_EN $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817
   end
-  attribute \src "ls180.v:10069.1-10070.4"
-  process $proc$ls180.v:10069$2699
+  attribute \src "ls180.v:10246.1-10247.4"
+  process $proc$ls180.v:10246$2819
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:10077.1-10081.4"
-  process $proc$ls180.v:10077$2701
+  attribute \src "ls180.v:1025.5-1025.27"
+  process $proc$ls180.v:1025$3261
+    assign { } { }
+    assign $1\main_gpio_oe_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
+  end
+  attribute \src "ls180.v:10254.1-10258.4"
+  process $proc$ls180.v:10254$2821
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 3'xxx
-    assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'0000000000000000000000000
-    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10080$2705_DATA
-    attribute \src "ls180.v:10078.2-10079.131"
+    assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 3'xxx
+    assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'0000000000000000000000000
+    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10257$2825_DATA
+    attribute \src "ls180.v:10255.2-10256.131"
     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10078.6-10078.60"
+      attribute \src "ls180.v:10255.6-10255.60"
       case 1'1
-        assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'1111111111111111111111111
+        assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_1 $0\memdat_1[24:0]
-      update $memwr$\storage_1$ls180.v:10079$6_ADDR $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702
-      update $memwr$\storage_1$ls180.v:10079$6_DATA $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703
-      update $memwr$\storage_1$ls180.v:10079$6_EN $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704
+      update $memwr$\storage_1$ls180.v:10256$18_ADDR $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822
+      update $memwr$\storage_1$ls180.v:10256$18_DATA $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823
+      update $memwr$\storage_1$ls180.v:10256$18_EN $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824
   end
-  attribute \src "ls180.v:10083.1-10084.4"
-  process $proc$ls180.v:10083$2706
-    sync posedge \sys_clk_1
-  end
-  attribute \src "ls180.v:1009.5-1009.36"
-  process $proc$ls180.v:1009$3133
+  attribute \src "ls180.v:1026.12-1026.36"
+  process $proc$ls180.v:1026$3262
     assign { } { }
-    assign $1\main_spimaster21_storage[0:0] 1'1
+    assign $1\main_gpio_status[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
+      update \main_gpio_status $1\main_gpio_status[15:0]
+  end
+  attribute \src "ls180.v:10260.1-10261.4"
+  process $proc$ls180.v:10260$2826
+    sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:10091.1-10095.4"
-  process $proc$ls180.v:10091$2708
+  attribute \src "ls180.v:10268.1-10272.4"
+  process $proc$ls180.v:10268$2828
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 3'xxx
-    assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'0000000000000000000000000
-    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10094$2712_DATA
-    attribute \src "ls180.v:10092.2-10093.131"
+    assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 3'xxx
+    assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'0000000000000000000000000
+    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10271$2832_DATA
+    attribute \src "ls180.v:10269.2-10270.131"
     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10092.6-10092.60"
+      attribute \src "ls180.v:10269.6-10269.60"
       case 1'1
-        assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'1111111111111111111111111
+        assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_2 $0\memdat_2[24:0]
-      update $memwr$\storage_2$ls180.v:10093$7_ADDR $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709
-      update $memwr$\storage_2$ls180.v:10093$7_DATA $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710
-      update $memwr$\storage_2$ls180.v:10093$7_EN $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711
+      update $memwr$\storage_2$ls180.v:10270$19_ADDR $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829
+      update $memwr$\storage_2$ls180.v:10270$19_DATA $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830
+      update $memwr$\storage_2$ls180.v:10270$19_EN $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831
   end
-  attribute \src "ls180.v:10097.1-10098.4"
-  process $proc$ls180.v:10097$2713
+  attribute \src "ls180.v:10274.1-10275.4"
+  process $proc$ls180.v:10274$2833
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1010.5-1010.31"
-  process $proc$ls180.v:1010$3134
+  attribute \src "ls180.v:1028.12-1028.41"
+  process $proc$ls180.v:1028$3263
     assign { } { }
-    assign $1\main_spimaster22_re[0:0] 1'0
+    assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_spimaster22_re $1\main_spimaster22_re[0:0]
+      update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
   end
-  attribute \src "ls180.v:10105.1-10109.4"
-  process $proc$ls180.v:10105$2715
+  attribute \src "ls180.v:10282.1-10286.4"
+  process $proc$ls180.v:10282$2835
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 3'xxx
-    assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'0000000000000000000000000
-    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10108$2719_DATA
-    attribute \src "ls180.v:10106.2-10107.131"
+    assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 3'xxx
+    assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'0000000000000000000000000
+    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10285$2839_DATA
+    attribute \src "ls180.v:10283.2-10284.131"
     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10106.6-10106.60"
+      attribute \src "ls180.v:10283.6-10283.60"
       case 1'1
-        assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'1111111111111111111111111
+        assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_3 $0\memdat_3[24:0]
-      update $memwr$\storage_3$ls180.v:10107$8_ADDR $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716
-      update $memwr$\storage_3$ls180.v:10107$8_DATA $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717
-      update $memwr$\storage_3$ls180.v:10107$8_EN $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718
-  end
-  attribute \src "ls180.v:1011.5-1011.36"
-  process $proc$ls180.v:1011$3135
-    assign { } { }
-    assign $1\main_spimaster23_storage[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
+      update $memwr$\storage_3$ls180.v:10284$20_ADDR $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836
+      update $memwr$\storage_3$ls180.v:10284$20_DATA $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837
+      update $memwr$\storage_3$ls180.v:10284$20_EN $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838
   end
-  attribute \src "ls180.v:10111.1-10112.4"
-  process $proc$ls180.v:10111$2720
+  attribute \src "ls180.v:10288.1-10289.4"
+  process $proc$ls180.v:10288$2840
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1012.5-1012.31"
-  process $proc$ls180.v:1012$3136
+  attribute \src "ls180.v:1029.5-1029.28"
+  process $proc$ls180.v:1029$3264
     assign { } { }
-    assign $1\main_spimaster24_re[0:0] 1'0
+    assign $1\main_gpio_out_re[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster24_re $1\main_spimaster24_re[0:0]
+      update \main_gpio_out_re $1\main_gpio_out_re[0:0]
   end
-  attribute \src "ls180.v:10120.1-10124.4"
-  process $proc$ls180.v:10120$2722
+  attribute \src "ls180.v:10297.1-10301.4"
+  process $proc$ls180.v:10297$2842
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 4'xxxx
-    assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 10'xxxxxxxxxx
-    assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'0000000000
-    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10123$2726_DATA
-    attribute \src "ls180.v:10121.2-10122.77"
+    assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 4'xxxx
+    assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 10'xxxxxxxxxx
+    assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'0000000000
+    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10300$2846_DATA
+    attribute \src "ls180.v:10298.2-10299.77"
     switch \main_uart_tx_fifo_wrport_we
-      attribute \src "ls180.v:10121.6-10121.33"
+      attribute \src "ls180.v:10298.6-10298.33"
       case 1'1
-        assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr
-        assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w
-        assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'1111111111
+        assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 \main_uart_tx_fifo_wrport_adr
+        assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 \main_uart_tx_fifo_wrport_dat_w
+        assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_4 $0\memdat_4[9:0]
-      update $memwr$\storage_4$ls180.v:10122$9_ADDR $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723
-      update $memwr$\storage_4$ls180.v:10122$9_DATA $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724
-      update $memwr$\storage_4$ls180.v:10122$9_EN $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725
+      update $memwr$\storage_4$ls180.v:10299$21_ADDR $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843
+      update $memwr$\storage_4$ls180.v:10299$21_DATA $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844
+      update $memwr$\storage_4$ls180.v:10299$21_EN $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845
   end
-  attribute \src "ls180.v:10126.1-10129.4"
-  process $proc$ls180.v:10126$2727
+  attribute \src "ls180.v:10303.1-10306.4"
+  process $proc$ls180.v:10303$2847
     assign $0\memdat_5[9:0] \memdat_5
-    attribute \src "ls180.v:10127.2-10128.55"
+    attribute \src "ls180.v:10304.2-10305.55"
     switch \main_uart_tx_fifo_rdport_re
-      attribute \src "ls180.v:10127.6-10127.33"
+      attribute \src "ls180.v:10304.6-10304.33"
       case 1'1
-        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10128$2728_DATA
+        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10305$2848_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_5 $0\memdat_5[9:0]
   end
-  attribute \src "ls180.v:1013.5-1013.39"
-  process $proc$ls180.v:1013$3137
-    assign { } { }
-    assign $1\main_spimaster25_clk_enable[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
-  end
-  attribute \src "ls180.v:10137.1-10141.4"
-  process $proc$ls180.v:10137$2729
+  attribute \src "ls180.v:10314.1-10318.4"
+  process $proc$ls180.v:10314$2849
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 4'xxxx
-    assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 10'xxxxxxxxxx
-    assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'0000000000
-    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10140$2733_DATA
-    attribute \src "ls180.v:10138.2-10139.77"
+    assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 4'xxxx
+    assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 10'xxxxxxxxxx
+    assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'0000000000
+    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10317$2853_DATA
+    attribute \src "ls180.v:10315.2-10316.77"
     switch \main_uart_rx_fifo_wrport_we
-      attribute \src "ls180.v:10138.6-10138.33"
+      attribute \src "ls180.v:10315.6-10315.33"
       case 1'1
-        assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr
-        assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w
-        assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'1111111111
+        assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 \main_uart_rx_fifo_wrport_adr
+        assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 \main_uart_rx_fifo_wrport_dat_w
+        assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_6 $0\memdat_6[9:0]
-      update $memwr$\storage_5$ls180.v:10139$10_ADDR $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730
-      update $memwr$\storage_5$ls180.v:10139$10_DATA $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731
-      update $memwr$\storage_5$ls180.v:10139$10_EN $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732
-  end
-  attribute \src "ls180.v:1014.5-1014.38"
-  process $proc$ls180.v:1014$3138
-    assign { } { }
-    assign $1\main_spimaster26_cs_enable[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
+      update $memwr$\storage_5$ls180.v:10316$22_ADDR $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850
+      update $memwr$\storage_5$ls180.v:10316$22_DATA $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851
+      update $memwr$\storage_5$ls180.v:10316$22_EN $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852
   end
-  attribute \src "ls180.v:10143.1-10146.4"
-  process $proc$ls180.v:10143$2734
+  attribute \src "ls180.v:10320.1-10323.4"
+  process $proc$ls180.v:10320$2854
     assign $0\memdat_7[9:0] \memdat_7
-    attribute \src "ls180.v:10144.2-10145.55"
+    attribute \src "ls180.v:10321.2-10322.55"
     switch \main_uart_rx_fifo_rdport_re
-      attribute \src "ls180.v:10144.6-10144.33"
+      attribute \src "ls180.v:10321.6-10321.33"
       case 1'1
-        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10145$2735_DATA
+        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10322$2855_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_7 $0\memdat_7[9:0]
   end
-  attribute \src "ls180.v:1015.11-1015.40"
-  process $proc$ls180.v:1015$3139
-    assign { } { }
-    assign $1\main_spimaster27_count[2:0] 3'000
-    sync always
-    sync init
-      update \main_spimaster27_count $1\main_spimaster27_count[2:0]
-  end
-  attribute \src "ls180.v:10153.1-10157.4"
-  process $proc$ls180.v:10153$2736
+  attribute \src "ls180.v:10330.1-10334.4"
+  process $proc$ls180.v:10330$2856
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 5'xxxxx
-    assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 10'xxxxxxxxxx
-    assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'0000000000
-    assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10156$2740_DATA
-    attribute \src "ls180.v:10154.2-10155.85"
+    assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 5'xxxxx
+    assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 10'xxxxxxxxxx
+    assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'0000000000
+    assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10333$2860_DATA
+    attribute \src "ls180.v:10331.2-10332.85"
     switch \main_sdblock2mem_fifo_wrport_we
-      attribute \src "ls180.v:10154.6-10154.37"
+      attribute \src "ls180.v:10331.6-10331.37"
       case 1'1
-        assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr
-        assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w
-        assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'1111111111
+        assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 \main_sdblock2mem_fifo_wrport_adr
+        assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 \main_sdblock2mem_fifo_wrport_dat_w
+        assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_8 $0\memdat_8[9:0]
-      update $memwr$\storage_6$ls180.v:10155$11_ADDR $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737
-      update $memwr$\storage_6$ls180.v:10155$11_DATA $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738
-      update $memwr$\storage_6$ls180.v:10155$11_EN $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739
+      update $memwr$\storage_6$ls180.v:10332$23_ADDR $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857
+      update $memwr$\storage_6$ls180.v:10332$23_DATA $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858
+      update $memwr$\storage_6$ls180.v:10332$23_EN $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859
   end
-  attribute \src "ls180.v:10159.1-10160.4"
-  process $proc$ls180.v:10159$2741
+  attribute \src "ls180.v:10336.1-10337.4"
+  process $proc$ls180.v:10336$2861
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1016.5-1016.39"
-  process $proc$ls180.v:1016$3140
-    assign { } { }
-    assign $1\main_spimaster28_mosi_latch[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
-  end
-  attribute \src "ls180.v:10167.1-10171.4"
-  process $proc$ls180.v:10167$2743
+  attribute \src "ls180.v:10344.1-10348.4"
+  process $proc$ls180.v:10344$2863
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 5'xxxxx
-    assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 10'xxxxxxxxxx
-    assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'0000000000
-    assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10170$2747_DATA
-    attribute \src "ls180.v:10168.2-10169.85"
+    assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 5'xxxxx
+    assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 10'xxxxxxxxxx
+    assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'0000000000
+    assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10347$2867_DATA
+    attribute \src "ls180.v:10345.2-10346.85"
     switch \main_sdmem2block_fifo_wrport_we
-      attribute \src "ls180.v:10168.6-10168.37"
+      attribute \src "ls180.v:10345.6-10345.37"
       case 1'1
-        assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr
-        assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w
-        assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'1111111111
+        assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 \main_sdmem2block_fifo_wrport_adr
+        assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 \main_sdmem2block_fifo_wrport_dat_w
+        assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_9 $0\memdat_9[9:0]
-      update $memwr$\storage_7$ls180.v:10169$12_ADDR $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744
-      update $memwr$\storage_7$ls180.v:10169$12_DATA $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745
-      update $memwr$\storage_7$ls180.v:10169$12_EN $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746
+      update $memwr$\storage_7$ls180.v:10346$24_ADDR $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864
+      update $memwr$\storage_7$ls180.v:10346$24_DATA $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865
+      update $memwr$\storage_7$ls180.v:10346$24_EN $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866
   end
-  attribute \src "ls180.v:1017.5-1017.39"
-  process $proc$ls180.v:1017$3141
+  attribute \src "ls180.v:1035.5-1035.32"
+  process $proc$ls180.v:1035$3265
     assign { } { }
-    assign $1\main_spimaster29_miso_latch[0:0] 1'0
+    assign $1\main_spimaster2_done[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
+      update \main_spimaster2_done $1\main_spimaster2_done[0:0]
   end
-  attribute \src "ls180.v:10173.1-10174.4"
-  process $proc$ls180.v:10173$2748
+  attribute \src "ls180.v:10350.1-10351.4"
+  process $proc$ls180.v:10350$2868
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1018.12-1018.48"
-  process $proc$ls180.v:1018$3142
+  attribute \src "ls180.v:1036.5-1036.31"
+  process $proc$ls180.v:1036$3266
+    assign { } { }
+    assign $1\main_spimaster3_irq[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
+  end
+  attribute \src "ls180.v:1038.11-1038.38"
+  process $proc$ls180.v:1038$3267
+    assign { } { }
+    assign $1\main_spimaster5_miso[7:0] 8'00000000
+    sync always
+    sync init
+      update \main_spimaster5_miso $1\main_spimaster5_miso[7:0]
+  end
+  attribute \src "ls180.v:1041.12-1041.47"
+  process $proc$ls180.v:1041$3268
+    assign { } { }
+    assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
+    sync always
+      update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0]
+    sync init
+  end
+  attribute \src "ls180.v:1042.5-1042.33"
+  process $proc$ls180.v:1042$3269
+    assign { } { }
+    assign $1\main_spimaster9_start[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster9_start $1\main_spimaster9_start[0:0]
+  end
+  attribute \src "ls180.v:1044.12-1044.44"
+  process $proc$ls180.v:1044$3270
+    assign { } { }
+    assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
+  end
+  attribute \src "ls180.v:1045.5-1045.31"
+  process $proc$ls180.v:1045$3271
+    assign { } { }
+    assign $1\main_spimaster12_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster12_re $1\main_spimaster12_re[0:0]
+  end
+  attribute \src "ls180.v:1049.11-1049.42"
+  process $proc$ls180.v:1049$3272
+    assign { } { }
+    assign $1\main_spimaster16_storage[7:0] 8'00000000
+    sync always
+    sync init
+      update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
+  end
+  attribute \src "ls180.v:1050.5-1050.31"
+  process $proc$ls180.v:1050$3273
+    assign { } { }
+    assign $1\main_spimaster17_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster17_re $1\main_spimaster17_re[0:0]
+  end
+  attribute \src "ls180.v:1054.5-1054.36"
+  process $proc$ls180.v:1054$3274
+    assign { } { }
+    assign $1\main_spimaster21_storage[0:0] 1'1
+    sync always
+    sync init
+      update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
+  end
+  attribute \src "ls180.v:1055.5-1055.31"
+  process $proc$ls180.v:1055$3275
+    assign { } { }
+    assign $1\main_spimaster22_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster22_re $1\main_spimaster22_re[0:0]
+  end
+  attribute \src "ls180.v:1056.5-1056.36"
+  process $proc$ls180.v:1056$3276
+    assign { } { }
+    assign $1\main_spimaster23_storage[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
+  end
+  attribute \src "ls180.v:1057.5-1057.31"
+  process $proc$ls180.v:1057$3277
+    assign { } { }
+    assign $1\main_spimaster24_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster24_re $1\main_spimaster24_re[0:0]
+  end
+  attribute \src "ls180.v:1058.5-1058.39"
+  process $proc$ls180.v:1058$3278
+    assign { } { }
+    assign $1\main_spimaster25_clk_enable[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
+  end
+  attribute \src "ls180.v:1059.5-1059.38"
+  process $proc$ls180.v:1059$3279
+    assign { } { }
+    assign $1\main_spimaster26_cs_enable[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
+  end
+  attribute \src "ls180.v:1060.11-1060.40"
+  process $proc$ls180.v:1060$3280
+    assign { } { }
+    assign $1\main_spimaster27_count[2:0] 3'000
+    sync always
+    sync init
+      update \main_spimaster27_count $1\main_spimaster27_count[2:0]
+  end
+  attribute \src "ls180.v:1061.5-1061.39"
+  process $proc$ls180.v:1061$3281
+    assign { } { }
+    assign $1\main_spimaster28_mosi_latch[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
+  end
+  attribute \src "ls180.v:1062.5-1062.39"
+  process $proc$ls180.v:1062$3282
+    assign { } { }
+    assign $1\main_spimaster29_miso_latch[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
+  end
+  attribute \src "ls180.v:1063.12-1063.48"
+  process $proc$ls180.v:1063$3283
     assign { } { }
     assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
   end
-  attribute \src "ls180.v:1021.11-1021.44"
-  process $proc$ls180.v:1021$3143
+  attribute \src "ls180.v:1066.11-1066.44"
+  process $proc$ls180.v:1066$3284
     assign { } { }
     assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
     sync always
     sync init
       update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
   end
-  attribute \src "ls180.v:1022.11-1022.43"
-  process $proc$ls180.v:1022$3144
+  attribute \src "ls180.v:1067.11-1067.43"
+  process $proc$ls180.v:1067$3285
     assign { } { }
     assign $1\main_spimaster34_mosi_sel[2:0] 3'000
     sync always
     sync init
       update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
   end
-  attribute \src "ls180.v:1023.11-1023.44"
-  process $proc$ls180.v:1023$3145
+  attribute \src "ls180.v:1068.11-1068.44"
+  process $proc$ls180.v:1068$3286
     assign { } { }
     assign $1\main_spimaster35_miso_data[7:0] 8'00000000
     sync always
     sync init
       update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
   end
-  attribute \src "ls180.v:1026.5-1026.32"
-  process $proc$ls180.v:1026$3146
+  attribute \src "ls180.v:1071.5-1071.32"
+  process $proc$ls180.v:1071$3287
     assign { } { }
     assign $1\main_spisdcard_done0[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
   end
-  attribute \src "ls180.v:1027.5-1027.30"
-  process $proc$ls180.v:1027$3147
+  attribute \src "ls180.v:1072.5-1072.30"
+  process $proc$ls180.v:1072$3288
     assign { } { }
     assign $1\main_spisdcard_irq[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
   end
-  attribute \src "ls180.v:1029.11-1029.37"
-  process $proc$ls180.v:1029$3148
+  attribute \src "ls180.v:1074.11-1074.37"
+  process $proc$ls180.v:1074$3289
     assign { } { }
     assign $1\main_spisdcard_miso[7:0] 8'00000000
     sync always
     sync init
       update \main_spisdcard_miso $1\main_spisdcard_miso[7:0]
   end
-  attribute \src "ls180.v:1033.5-1033.33"
-  process $proc$ls180.v:1033$3149
+  attribute \src "ls180.v:1078.5-1078.33"
+  process $proc$ls180.v:1078$3290
     assign { } { }
     assign $1\main_spisdcard_start1[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
   end
-  attribute \src "ls180.v:1035.12-1035.50"
-  process $proc$ls180.v:1035$3150
+  attribute \src "ls180.v:1080.12-1080.50"
+  process $proc$ls180.v:1080$3291
     assign { } { }
     assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
   end
-  attribute \src "ls180.v:1036.5-1036.37"
-  process $proc$ls180.v:1036$3151
+  attribute \src "ls180.v:1081.5-1081.37"
+  process $proc$ls180.v:1081$3292
     assign { } { }
     assign $1\main_spisdcard_control_re[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
   end
-  attribute \src "ls180.v:1040.11-1040.45"
-  process $proc$ls180.v:1040$3152
+  attribute \src "ls180.v:1085.11-1085.45"
+  process $proc$ls180.v:1085$3293
     assign { } { }
     assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
     sync always
     sync init
       update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0]
   end
-  attribute \src "ls180.v:1041.5-1041.34"
-  process $proc$ls180.v:1041$3153
+  attribute \src "ls180.v:1086.5-1086.34"
+  process $proc$ls180.v:1086$3294
     assign { } { }
     assign $1\main_spisdcard_mosi_re[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
   end
-  attribute \src "ls180.v:1045.5-1045.37"
-  process $proc$ls180.v:1045$3154
+  attribute \src "ls180.v:1090.5-1090.37"
+  process $proc$ls180.v:1090$3295
     assign { } { }
     assign $1\main_spisdcard_cs_storage[0:0] 1'1
     sync always
     sync init
       update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
   end
-  attribute \src "ls180.v:1046.5-1046.32"
-  process $proc$ls180.v:1046$3155
+  attribute \src "ls180.v:1091.5-1091.32"
+  process $proc$ls180.v:1091$3296
     assign { } { }
     assign $1\main_spisdcard_cs_re[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
   end
-  attribute \src "ls180.v:1047.5-1047.43"
-  process $proc$ls180.v:1047$3156
+  attribute \src "ls180.v:1092.5-1092.43"
+  process $proc$ls180.v:1092$3297
     assign { } { }
     assign $1\main_spisdcard_loopback_storage[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
   end
-  attribute \src "ls180.v:1048.5-1048.38"
-  process $proc$ls180.v:1048$3157
+  attribute \src "ls180.v:1093.5-1093.38"
+  process $proc$ls180.v:1093$3298
     assign { } { }
     assign $1\main_spisdcard_loopback_re[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
   end
-  attribute \src "ls180.v:1049.5-1049.37"
-  process $proc$ls180.v:1049$3158
+  attribute \src "ls180.v:1094.5-1094.37"
+  process $proc$ls180.v:1094$3299
     assign { } { }
     assign $1\main_spisdcard_clk_enable[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
   end
-  attribute \src "ls180.v:1050.5-1050.36"
-  process $proc$ls180.v:1050$3159
+  attribute \src "ls180.v:1095.5-1095.36"
+  process $proc$ls180.v:1095$3300
     assign { } { }
     assign $1\main_spisdcard_cs_enable[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
   end
-  attribute \src "ls180.v:1051.11-1051.38"
-  process $proc$ls180.v:1051$3160
+  attribute \src "ls180.v:1096.11-1096.38"
+  process $proc$ls180.v:1096$3301
     assign { } { }
     assign $1\main_spisdcard_count[2:0] 3'000
     sync always
     sync init
       update \main_spisdcard_count $1\main_spisdcard_count[2:0]
   end
-  attribute \src "ls180.v:1052.5-1052.37"
-  process $proc$ls180.v:1052$3161
+  attribute \src "ls180.v:1097.5-1097.37"
+  process $proc$ls180.v:1097$3302
     assign { } { }
     assign $1\main_spisdcard_mosi_latch[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
   end
-  attribute \src "ls180.v:1053.5-1053.37"
-  process $proc$ls180.v:1053$3162
+  attribute \src "ls180.v:1098.5-1098.37"
+  process $proc$ls180.v:1098$3303
     assign { } { }
     assign $1\main_spisdcard_miso_latch[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
   end
-  attribute \src "ls180.v:1054.12-1054.47"
-  process $proc$ls180.v:1054$3163
+  attribute \src "ls180.v:1099.12-1099.47"
+  process $proc$ls180.v:1099$3304
     assign { } { }
     assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
   end
-  attribute \src "ls180.v:1057.11-1057.42"
-  process $proc$ls180.v:1057$3164
+  attribute \src "ls180.v:1102.11-1102.42"
+  process $proc$ls180.v:1102$3305
     assign { } { }
     assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
     sync always
     sync init
       update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
   end
-  attribute \src "ls180.v:1058.11-1058.41"
-  process $proc$ls180.v:1058$3165
+  attribute \src "ls180.v:1103.11-1103.41"
+  process $proc$ls180.v:1103$3306
     assign { } { }
     assign $1\main_spisdcard_mosi_sel[2:0] 3'000
     sync always
     sync init
       update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
   end
-  attribute \src "ls180.v:1059.11-1059.42"
-  process $proc$ls180.v:1059$3166
+  attribute \src "ls180.v:1104.11-1104.42"
+  process $proc$ls180.v:1104$3307
     assign { } { }
     assign $1\main_spisdcard_miso_data[7:0] 8'00000000
     sync always
     sync init
       update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
   end
-  attribute \src "ls180.v:1060.12-1060.45"
-  process $proc$ls180.v:1060$3167
+  attribute \src "ls180.v:1105.12-1105.45"
+  process $proc$ls180.v:1105$3308
     assign { } { }
     assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
     sync always
     sync init
       update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
   end
-  attribute \src "ls180.v:1061.5-1061.30"
-  process $proc$ls180.v:1061$3168
+  attribute \src "ls180.v:1106.5-1106.30"
+  process $proc$ls180.v:1106$3309
     assign { } { }
     assign $1\main_spimaster1_re[0:0] 1'0
     sync always
     sync init
       update \main_spimaster1_re $1\main_spimaster1_re[0:0]
   end
-  attribute \src "ls180.v:1063.12-1063.30"
-  process $proc$ls180.v:1063$3169
+  attribute \src "ls180.v:1108.12-1108.30"
+  process $proc$ls180.v:1108$3310
     assign { } { }
     assign $1\main_dummy[23:0] 24'000000000000000000000000
     sync always
     sync init
       update \main_dummy $1\main_dummy[23:0]
   end
-  attribute \src "ls180.v:1067.12-1067.37"
-  process $proc$ls180.v:1067$3170
+  attribute \src "ls180.v:1112.12-1112.37"
+  process $proc$ls180.v:1112$3311
     assign { } { }
     assign $1\main_pwm0_counter[31:0] 0
     sync always
     sync init
       update \main_pwm0_counter $1\main_pwm0_counter[31:0]
   end
-  attribute \src "ls180.v:1068.5-1068.36"
-  process $proc$ls180.v:1068$3171
+  attribute \src "ls180.v:1113.5-1113.36"
+  process $proc$ls180.v:1113$3312
     assign { } { }
     assign $1\main_pwm0_enable_storage[0:0] 1'0
     sync always
     sync init
       update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
   end
-  attribute \src "ls180.v:1069.5-1069.31"
-  process $proc$ls180.v:1069$3172
+  attribute \src "ls180.v:1114.5-1114.31"
+  process $proc$ls180.v:1114$3313
     assign { } { }
     assign $1\main_pwm0_enable_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
   end
-  attribute \src "ls180.v:1070.12-1070.43"
-  process $proc$ls180.v:1070$3173
+  attribute \src "ls180.v:1115.12-1115.43"
+  process $proc$ls180.v:1115$3314
     assign { } { }
     assign $1\main_pwm0_width_storage[31:0] 0
     sync always
     sync init
       update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
   end
-  attribute \src "ls180.v:1071.5-1071.30"
-  process $proc$ls180.v:1071$3174
+  attribute \src "ls180.v:1116.5-1116.30"
+  process $proc$ls180.v:1116$3315
     assign { } { }
     assign $1\main_pwm0_width_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
   end
-  attribute \src "ls180.v:1072.12-1072.44"
-  process $proc$ls180.v:1072$3175
+  attribute \src "ls180.v:1117.12-1117.44"
+  process $proc$ls180.v:1117$3316
     assign { } { }
     assign $1\main_pwm0_period_storage[31:0] 0
     sync always
     sync init
       update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
   end
-  attribute \src "ls180.v:1073.5-1073.31"
-  process $proc$ls180.v:1073$3176
+  attribute \src "ls180.v:1118.5-1118.31"
+  process $proc$ls180.v:1118$3317
     assign { } { }
     assign $1\main_pwm0_period_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
   end
-  attribute \src "ls180.v:1077.12-1077.37"
-  process $proc$ls180.v:1077$3177
+  attribute \src "ls180.v:112.5-112.49"
+  process $proc$ls180.v:112$2905
+    assign { } { }
+    assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
+  end
+  attribute \src "ls180.v:1122.12-1122.37"
+  process $proc$ls180.v:1122$3318
     assign { } { }
     assign $1\main_pwm1_counter[31:0] 0
     sync always
     sync init
       update \main_pwm1_counter $1\main_pwm1_counter[31:0]
   end
-  attribute \src "ls180.v:1078.5-1078.36"
-  process $proc$ls180.v:1078$3178
+  attribute \src "ls180.v:1123.5-1123.36"
+  process $proc$ls180.v:1123$3319
     assign { } { }
     assign $1\main_pwm1_enable_storage[0:0] 1'0
     sync always
     sync init
       update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
   end
-  attribute \src "ls180.v:1079.5-1079.31"
-  process $proc$ls180.v:1079$3179
+  attribute \src "ls180.v:1124.5-1124.31"
+  process $proc$ls180.v:1124$3320
     assign { } { }
     assign $1\main_pwm1_enable_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
   end
-  attribute \src "ls180.v:1080.12-1080.43"
-  process $proc$ls180.v:1080$3180
+  attribute \src "ls180.v:1125.12-1125.43"
+  process $proc$ls180.v:1125$3321
     assign { } { }
     assign $1\main_pwm1_width_storage[31:0] 0
     sync always
     sync init
       update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
   end
-  attribute \src "ls180.v:1081.5-1081.30"
-  process $proc$ls180.v:1081$3181
+  attribute \src "ls180.v:1126.5-1126.30"
+  process $proc$ls180.v:1126$3322
     assign { } { }
     assign $1\main_pwm1_width_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
   end
-  attribute \src "ls180.v:1082.12-1082.44"
-  process $proc$ls180.v:1082$3182
+  attribute \src "ls180.v:1127.12-1127.44"
+  process $proc$ls180.v:1127$3323
     assign { } { }
     assign $1\main_pwm1_period_storage[31:0] 0
     sync always
     sync init
       update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
   end
-  attribute \src "ls180.v:1083.5-1083.31"
-  process $proc$ls180.v:1083$3183
+  attribute \src "ls180.v:1128.5-1128.31"
+  process $proc$ls180.v:1128$3324
     assign { } { }
     assign $1\main_pwm1_period_re[0:0] 1'0
     sync always
     sync init
       update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
   end
-  attribute \src "ls180.v:1087.11-1087.34"
-  process $proc$ls180.v:1087$3184
+  attribute \src "ls180.v:1132.11-1132.34"
+  process $proc$ls180.v:1132$3325
     assign { } { }
     assign $1\main_i2c_storage[2:0] 3'000
     sync always
     sync init
       update \main_i2c_storage $1\main_i2c_storage[2:0]
   end
-  attribute \src "ls180.v:1088.5-1088.23"
-  process $proc$ls180.v:1088$3185
+  attribute \src "ls180.v:1133.5-1133.23"
+  process $proc$ls180.v:1133$3326
     assign { } { }
     assign $1\main_i2c_re[0:0] 1'0
     sync always
     sync init
       update \main_i2c_re $1\main_i2c_re[0:0]
   end
-  attribute \src "ls180.v:1094.11-1094.46"
-  process $proc$ls180.v:1094$3186
+  attribute \src "ls180.v:1139.11-1139.46"
+  process $proc$ls180.v:1139$3327
     assign { } { }
     assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
     sync always
     sync init
       update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
   end
-  attribute \src "ls180.v:1095.5-1095.33"
-  process $proc$ls180.v:1095$3187
+  attribute \src "ls180.v:114.5-114.49"
+  process $proc$ls180.v:114$2906
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:1140.5-1140.33"
+  process $proc$ls180.v:1140$3328
     assign { } { }
     assign $1\main_sdphy_clocker_re[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
   end
-  attribute \src "ls180.v:1097.5-1097.35"
-  process $proc$ls180.v:1097$3188
+  attribute \src "ls180.v:1142.5-1142.35"
+  process $proc$ls180.v:1142$3329
     assign { } { }
     assign $1\main_sdphy_clocker_clk0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
   end
-  attribute \src "ls180.v:1099.11-1099.41"
-  process $proc$ls180.v:1099$3189
+  attribute \src "ls180.v:1144.11-1144.41"
+  process $proc$ls180.v:1144$3330
     assign { } { }
     assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
     sync always
     sync init
       update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
   end
-  attribute \src "ls180.v:1100.5-1100.35"
-  process $proc$ls180.v:1100$3190
+  attribute \src "ls180.v:1145.5-1145.35"
+  process $proc$ls180.v:1145$3331
     assign { } { }
     assign $1\main_sdphy_clocker_clk1[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
   end
-  attribute \src "ls180.v:1101.5-1101.36"
-  process $proc$ls180.v:1101$3191
+  attribute \src "ls180.v:1146.5-1146.36"
+  process $proc$ls180.v:1146$3332
     assign { } { }
     assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
   end
-  attribute \src "ls180.v:1105.5-1105.40"
-  process $proc$ls180.v:1105$3192
+  attribute \src "ls180.v:1150.5-1150.40"
+  process $proc$ls180.v:1150$3333
     assign { } { }
     assign $0\main_sdphy_init_initialize_w[0:0] 1'0
     sync always
       update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0]
     sync init
   end
-  attribute \src "ls180.v:1110.5-1110.48"
-  process $proc$ls180.v:1110$3193
+  attribute \src "ls180.v:1155.5-1155.48"
+  process $proc$ls180.v:1155$3334
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
   end
-  attribute \src "ls180.v:1111.5-1111.50"
-  process $proc$ls180.v:1111$3194
+  attribute \src "ls180.v:1156.5-1156.50"
+  process $proc$ls180.v:1156$3335
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
   end
-  attribute \src "ls180.v:1112.5-1112.51"
-  process $proc$ls180.v:1112$3195
+  attribute \src "ls180.v:1157.5-1157.51"
+  process $proc$ls180.v:1157$3336
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
   end
-  attribute \src "ls180.v:1113.11-1113.57"
-  process $proc$ls180.v:1113$3196
+  attribute \src "ls180.v:1158.11-1158.57"
+  process $proc$ls180.v:1158$3337
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
     sync always
     sync init
       update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
   end
-  attribute \src "ls180.v:1114.5-1114.52"
-  process $proc$ls180.v:1114$3197
+  attribute \src "ls180.v:1159.5-1159.52"
+  process $proc$ls180.v:1159$3338
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
   end
-  attribute \src "ls180.v:1115.11-1115.39"
-  process $proc$ls180.v:1115$3198
+  attribute \src "ls180.v:1160.11-1160.39"
+  process $proc$ls180.v:1160$3339
     assign { } { }
     assign $1\main_sdphy_init_count[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
   end
-  attribute \src "ls180.v:112.5-112.49"
-  process $proc$ls180.v:112$2773
-    assign { } { }
-    assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
-  end
-  attribute \src "ls180.v:1120.5-1120.48"
-  process $proc$ls180.v:1120$3199
+  attribute \src "ls180.v:1165.5-1165.48"
+  process $proc$ls180.v:1165$3340
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
   end
-  attribute \src "ls180.v:1121.5-1121.50"
-  process $proc$ls180.v:1121$3200
+  attribute \src "ls180.v:1166.5-1166.50"
+  process $proc$ls180.v:1166$3341
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
   end
-  attribute \src "ls180.v:1122.5-1122.51"
-  process $proc$ls180.v:1122$3201
+  attribute \src "ls180.v:1167.5-1167.51"
+  process $proc$ls180.v:1167$3342
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
   end
-  attribute \src "ls180.v:1123.11-1123.57"
-  process $proc$ls180.v:1123$3202
+  attribute \src "ls180.v:1168.11-1168.57"
+  process $proc$ls180.v:1168$3343
     assign { } { }
     assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1124.5-1124.52"
-  process $proc$ls180.v:1124$3203
+  attribute \src "ls180.v:1169.5-1169.52"
+  process $proc$ls180.v:1169$3344
     assign { } { }
     assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1125.5-1125.38"
-  process $proc$ls180.v:1125$3204
+  attribute \src "ls180.v:1170.5-1170.38"
+  process $proc$ls180.v:1170$3345
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1126.5-1126.38"
-  process $proc$ls180.v:1126$3205
+  attribute \src "ls180.v:1171.5-1171.38"
+  process $proc$ls180.v:1171$3346
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1127.5-1127.37"
-  process $proc$ls180.v:1127$3206
+  attribute \src "ls180.v:1172.5-1172.37"
+  process $proc$ls180.v:1172$3347
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
   end
-  attribute \src "ls180.v:1128.11-1128.51"
-  process $proc$ls180.v:1128$3207
+  attribute \src "ls180.v:1173.11-1173.51"
+  process $proc$ls180.v:1173$3348
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
   end
-  attribute \src "ls180.v:1129.5-1129.32"
-  process $proc$ls180.v:1129$3208
+  attribute \src "ls180.v:1174.5-1174.32"
+  process $proc$ls180.v:1174$3349
     assign { } { }
     assign $1\main_sdphy_cmdw_done[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
   end
-  attribute \src "ls180.v:1130.11-1130.39"
-  process $proc$ls180.v:1130$3209
+  attribute \src "ls180.v:1175.11-1175.39"
+  process $proc$ls180.v:1175$3350
     assign { } { }
     assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
   end
-  attribute \src "ls180.v:1133.5-1133.49"
-  process $proc$ls180.v:1133$3210
+  attribute \src "ls180.v:1178.5-1178.49"
+  process $proc$ls180.v:1178$3351
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1134.5-1134.48"
-  process $proc$ls180.v:1134$3211
+  attribute \src "ls180.v:1179.5-1179.48"
+  process $proc$ls180.v:1179$3352
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1135.5-1135.55"
-  process $proc$ls180.v:1135$3212
+  attribute \src "ls180.v:1180.5-1180.55"
+  process $proc$ls180.v:1180$3353
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
     sync init
   end
-  attribute \src "ls180.v:1137.5-1137.57"
-  process $proc$ls180.v:1137$3213
+  attribute \src "ls180.v:1182.5-1182.57"
+  process $proc$ls180.v:1182$3354
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
     sync init
   end
-  attribute \src "ls180.v:1138.5-1138.58"
-  process $proc$ls180.v:1138$3214
+  attribute \src "ls180.v:1183.5-1183.58"
+  process $proc$ls180.v:1183$3355
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:114.5-114.49"
-  process $proc$ls180.v:114$2774
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1140.11-1140.64"
-  process $proc$ls180.v:1140$3215
+  attribute \src "ls180.v:1185.11-1185.64"
+  process $proc$ls180.v:1185$3356
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1141.5-1141.59"
-  process $proc$ls180.v:1141$3216
+  attribute \src "ls180.v:1186.5-1186.59"
+  process $proc$ls180.v:1186$3357
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1143.5-1143.48"
-  process $proc$ls180.v:1143$3217
+  attribute \src "ls180.v:1188.5-1188.48"
+  process $proc$ls180.v:1188$3358
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
   end
-  attribute \src "ls180.v:1144.5-1144.50"
-  process $proc$ls180.v:1144$3218
+  attribute \src "ls180.v:1189.5-1189.50"
+  process $proc$ls180.v:1189$3359
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
   end
-  attribute \src "ls180.v:1145.5-1145.51"
-  process $proc$ls180.v:1145$3219
+  attribute \src "ls180.v:1190.5-1190.51"
+  process $proc$ls180.v:1190$3360
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
   end
-  attribute \src "ls180.v:1146.11-1146.57"
-  process $proc$ls180.v:1146$3220
+  attribute \src "ls180.v:1191.11-1191.57"
+  process $proc$ls180.v:1191$3361
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1147.5-1147.52"
-  process $proc$ls180.v:1147$3221
+  attribute \src "ls180.v:1192.5-1192.52"
+  process $proc$ls180.v:1192$3362
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1148.5-1148.38"
-  process $proc$ls180.v:1148$3222
+  attribute \src "ls180.v:1193.5-1193.38"
+  process $proc$ls180.v:1193$3363
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1149.5-1149.38"
-  process $proc$ls180.v:1149$3223
+  attribute \src "ls180.v:1194.5-1194.38"
+  process $proc$ls180.v:1194$3364
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1150.5-1150.37"
-  process $proc$ls180.v:1150$3224
+  attribute \src "ls180.v:1195.5-1195.37"
+  process $proc$ls180.v:1195$3365
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
   end
-  attribute \src "ls180.v:1151.11-1151.53"
-  process $proc$ls180.v:1151$3225
+  attribute \src "ls180.v:1196.11-1196.53"
+  process $proc$ls180.v:1196$3366
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
   end
-  attribute \src "ls180.v:1152.5-1152.40"
-  process $proc$ls180.v:1152$3226
+  attribute \src "ls180.v:1197.5-1197.40"
+  process $proc$ls180.v:1197$3367
     assign { } { }
     assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
   end
-  attribute \src "ls180.v:1153.5-1153.40"
-  process $proc$ls180.v:1153$3227
+  attribute \src "ls180.v:1198.5-1198.40"
+  process $proc$ls180.v:1198$3368
     assign { } { }
     assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
   end
-  attribute \src "ls180.v:1154.5-1154.39"
-  process $proc$ls180.v:1154$3228
+  attribute \src "ls180.v:1199.5-1199.39"
+  process $proc$ls180.v:1199$3369
     assign { } { }
     assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
   end
-  attribute \src "ls180.v:1155.11-1155.53"
-  process $proc$ls180.v:1155$3229
+  attribute \src "ls180.v:1200.11-1200.53"
+  process $proc$ls180.v:1200$3370
     assign { } { }
     assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1156.11-1156.55"
-  process $proc$ls180.v:1156$3230
+  attribute \src "ls180.v:1201.11-1201.55"
+  process $proc$ls180.v:1201$3371
     assign { } { }
     assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
     sync always
     sync init
       update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
   end
-  attribute \src "ls180.v:1157.12-1157.48"
-  process $proc$ls180.v:1157$3231
+  attribute \src "ls180.v:1202.12-1202.48"
+  process $proc$ls180.v:1202$3372
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout[31:0] 500000
     sync always
     sync init
       update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
   end
-  attribute \src "ls180.v:1158.11-1158.39"
-  process $proc$ls180.v:1158$3232
+  attribute \src "ls180.v:1203.11-1203.39"
+  process $proc$ls180.v:1203$3373
     assign { } { }
     assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
   end
-  attribute \src "ls180.v:1160.5-1160.46"
-  process $proc$ls180.v:1160$3233
+  attribute \src "ls180.v:1205.5-1205.46"
+  process $proc$ls180.v:1205$3374
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:1171.5-1171.53"
-  process $proc$ls180.v:1171$3234
+  attribute \src "ls180.v:1216.5-1216.53"
+  process $proc$ls180.v:1216$3375
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
   end
-  attribute \src "ls180.v:1176.5-1176.36"
-  process $proc$ls180.v:1176$3235
+  attribute \src "ls180.v:1221.5-1221.36"
+  process $proc$ls180.v:1221$3376
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
   end
-  attribute \src "ls180.v:1179.5-1179.53"
-  process $proc$ls180.v:1179$3236
+  attribute \src "ls180.v:1224.5-1224.53"
+  process $proc$ls180.v:1224$3377
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1180.5-1180.52"
-  process $proc$ls180.v:1180$3237
+  attribute \src "ls180.v:1225.5-1225.52"
+  process $proc$ls180.v:1225$3378
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
     sync always
       update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1184.5-1184.55"
-  process $proc$ls180.v:1184$3238
+  attribute \src "ls180.v:1229.5-1229.55"
+  process $proc$ls180.v:1229$3379
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
   end
-  attribute \src "ls180.v:1185.5-1185.54"
-  process $proc$ls180.v:1185$3239
+  attribute \src "ls180.v:1230.5-1230.54"
+  process $proc$ls180.v:1230$3380
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
   end
-  attribute \src "ls180.v:1186.11-1186.68"
-  process $proc$ls180.v:1186$3240
+  attribute \src "ls180.v:1231.11-1231.68"
+  process $proc$ls180.v:1231$3381
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1187.11-1187.81"
-  process $proc$ls180.v:1187$3241
+  attribute \src "ls180.v:1232.11-1232.81"
+  process $proc$ls180.v:1232$3382
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
   end
-  attribute \src "ls180.v:1188.11-1188.54"
-  process $proc$ls180.v:1188$3242
+  attribute \src "ls180.v:1233.11-1233.54"
+  process $proc$ls180.v:1233$3383
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
   end
-  attribute \src "ls180.v:1190.5-1190.53"
-  process $proc$ls180.v:1190$3243
+  attribute \src "ls180.v:1235.5-1235.53"
+  process $proc$ls180.v:1235$3384
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
   end
-  attribute \src "ls180.v:1201.5-1201.49"
-  process $proc$ls180.v:1201$3244
+  attribute \src "ls180.v:1246.5-1246.49"
+  process $proc$ls180.v:1246$3385
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
   end
-  attribute \src "ls180.v:1203.5-1203.49"
-  process $proc$ls180.v:1203$3245
+  attribute \src "ls180.v:1248.5-1248.49"
+  process $proc$ls180.v:1248$3386
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
   end
-  attribute \src "ls180.v:1204.5-1204.48"
-  process $proc$ls180.v:1204$3246
+  attribute \src "ls180.v:1249.5-1249.48"
+  process $proc$ls180.v:1249$3387
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
   end
-  attribute \src "ls180.v:1205.11-1205.62"
-  process $proc$ls180.v:1205$3247
+  attribute \src "ls180.v:1250.11-1250.62"
+  process $proc$ls180.v:1250$3388
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1206.5-1206.38"
-  process $proc$ls180.v:1206$3248
+  attribute \src "ls180.v:1251.5-1251.38"
+  process $proc$ls180.v:1251$3389
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
   end
-  attribute \src "ls180.v:1211.5-1211.49"
-  process $proc$ls180.v:1211$3249
+  attribute \src "ls180.v:1256.5-1256.49"
+  process $proc$ls180.v:1256$3390
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
   end
-  attribute \src "ls180.v:1212.5-1212.51"
-  process $proc$ls180.v:1212$3250
+  attribute \src "ls180.v:1257.5-1257.51"
+  process $proc$ls180.v:1257$3391
     assign { } { }
     assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
     sync init
   end
-  attribute \src "ls180.v:1213.5-1213.52"
-  process $proc$ls180.v:1213$3251
+  attribute \src "ls180.v:1258.5-1258.52"
+  process $proc$ls180.v:1258$3392
     assign { } { }
     assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1214.11-1214.58"
-  process $proc$ls180.v:1214$3252
+  attribute \src "ls180.v:1259.11-1259.58"
+  process $proc$ls180.v:1259$3393
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
     sync always
     sync init
       update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
   end
-  attribute \src "ls180.v:1215.5-1215.53"
-  process $proc$ls180.v:1215$3253
+  attribute \src "ls180.v:1260.5-1260.53"
+  process $proc$ls180.v:1260$3394
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
   end
-  attribute \src "ls180.v:1216.5-1216.39"
-  process $proc$ls180.v:1216$3254
+  attribute \src "ls180.v:1261.5-1261.39"
+  process $proc$ls180.v:1261$3395
     assign { } { }
     assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1217.5-1217.39"
-  process $proc$ls180.v:1217$3255
+  attribute \src "ls180.v:1262.5-1262.39"
+  process $proc$ls180.v:1262$3396
     assign { } { }
     assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1218.5-1218.39"
-  process $proc$ls180.v:1218$3256
+  attribute \src "ls180.v:1263.5-1263.39"
+  process $proc$ls180.v:1263$3397
     assign { } { }
     assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
   end
-  attribute \src "ls180.v:1219.5-1219.38"
-  process $proc$ls180.v:1219$3257
+  attribute \src "ls180.v:1264.5-1264.38"
+  process $proc$ls180.v:1264$3398
     assign { } { }
     assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
   end
-  attribute \src "ls180.v:1220.11-1220.52"
-  process $proc$ls180.v:1220$3258
+  attribute \src "ls180.v:1265.11-1265.52"
+  process $proc$ls180.v:1265$3399
     assign { } { }
     assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
   end
-  attribute \src "ls180.v:1221.5-1221.33"
-  process $proc$ls180.v:1221$3259
+  attribute \src "ls180.v:1266.5-1266.33"
+  process $proc$ls180.v:1266$3400
     assign { } { }
     assign $1\main_sdphy_dataw_stop[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
   end
-  attribute \src "ls180.v:1222.11-1222.40"
-  process $proc$ls180.v:1222$3260
+  attribute \src "ls180.v:1267.11-1267.40"
+  process $proc$ls180.v:1267$3401
     assign { } { }
     assign $1\main_sdphy_dataw_count[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
   end
-  attribute \src "ls180.v:1223.5-1223.50"
-  process $proc$ls180.v:1223$3261
+  attribute \src "ls180.v:1268.5-1268.50"
+  process $proc$ls180.v:1268$3402
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
     sync init
   end
-  attribute \src "ls180.v:1225.5-1225.50"
-  process $proc$ls180.v:1225$3262
+  attribute \src "ls180.v:1270.5-1270.50"
+  process $proc$ls180.v:1270$3403
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1226.5-1226.49"
-  process $proc$ls180.v:1226$3263
+  attribute \src "ls180.v:1271.5-1271.49"
+  process $proc$ls180.v:1271$3404
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1227.5-1227.56"
-  process $proc$ls180.v:1227$3264
+  attribute \src "ls180.v:1272.5-1272.56"
+  process $proc$ls180.v:1272$3405
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
     sync init
   end
-  attribute \src "ls180.v:1228.5-1228.58"
-  process $proc$ls180.v:1228$3265
+  attribute \src "ls180.v:1273.5-1273.58"
+  process $proc$ls180.v:1273$3406
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
     sync init
   end
-  attribute \src "ls180.v:1229.5-1229.58"
-  process $proc$ls180.v:1229$3266
+  attribute \src "ls180.v:1274.5-1274.58"
+  process $proc$ls180.v:1274$3407
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
     sync init
   end
-  attribute \src "ls180.v:1230.5-1230.59"
-  process $proc$ls180.v:1230$3267
+  attribute \src "ls180.v:1275.5-1275.59"
+  process $proc$ls180.v:1275$3408
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1231.11-1231.65"
-  process $proc$ls180.v:1231$3268
+  attribute \src "ls180.v:1276.11-1276.65"
+  process $proc$ls180.v:1276$3409
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
     sync init
   end
-  attribute \src "ls180.v:1232.11-1232.65"
-  process $proc$ls180.v:1232$3269
+  attribute \src "ls180.v:1277.11-1277.65"
+  process $proc$ls180.v:1277$3410
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1233.5-1233.60"
-  process $proc$ls180.v:1233$3270
+  attribute \src "ls180.v:1278.5-1278.60"
+  process $proc$ls180.v:1278$3411
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1234.5-1234.34"
-  process $proc$ls180.v:1234$3271
+  attribute \src "ls180.v:1279.5-1279.34"
+  process $proc$ls180.v:1279$3412
     assign { } { }
     assign $1\main_sdphy_dataw_start[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
   end
-  attribute \src "ls180.v:1235.5-1235.34"
-  process $proc$ls180.v:1235$3272
+  attribute \src "ls180.v:1280.5-1280.34"
+  process $proc$ls180.v:1280$3413
     assign { } { }
     assign $1\main_sdphy_dataw_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
   end
-  attribute \src "ls180.v:1236.5-1236.34"
-  process $proc$ls180.v:1236$3273
+  attribute \src "ls180.v:1281.5-1281.34"
+  process $proc$ls180.v:1281$3414
     assign { } { }
     assign $1\main_sdphy_dataw_error[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
   end
-  attribute \src "ls180.v:1238.5-1238.47"
-  process $proc$ls180.v:1238$3274
+  attribute \src "ls180.v:1283.5-1283.47"
+  process $proc$ls180.v:1283$3415
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
     sync always
       update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:1249.5-1249.54"
-  process $proc$ls180.v:1249$3275
+  attribute \src "ls180.v:1294.5-1294.54"
+  process $proc$ls180.v:1294$3416
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
   end
-  attribute \src "ls180.v:1254.5-1254.37"
-  process $proc$ls180.v:1254$3276
+  attribute \src "ls180.v:1299.5-1299.37"
+  process $proc$ls180.v:1299$3417
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
   end
-  attribute \src "ls180.v:1257.5-1257.54"
-  process $proc$ls180.v:1257$3277
+  attribute \src "ls180.v:1302.5-1302.54"
+  process $proc$ls180.v:1302$3418
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
     sync always
       update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1258.5-1258.53"
-  process $proc$ls180.v:1258$3278
+  attribute \src "ls180.v:1303.5-1303.53"
+  process $proc$ls180.v:1303$3419
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
     sync always
       update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1262.5-1262.56"
-  process $proc$ls180.v:1262$3279
+  attribute \src "ls180.v:1307.5-1307.56"
+  process $proc$ls180.v:1307$3420
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
   end
-  attribute \src "ls180.v:1263.5-1263.55"
-  process $proc$ls180.v:1263$3280
+  attribute \src "ls180.v:1308.5-1308.55"
+  process $proc$ls180.v:1308$3421
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
   end
-  attribute \src "ls180.v:1264.11-1264.69"
-  process $proc$ls180.v:1264$3281
+  attribute \src "ls180.v:1309.11-1309.69"
+  process $proc$ls180.v:1309$3422
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1265.11-1265.82"
-  process $proc$ls180.v:1265$3282
+  attribute \src "ls180.v:1310.11-1310.82"
+  process $proc$ls180.v:1310$3423
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
   end
-  attribute \src "ls180.v:1266.11-1266.55"
-  process $proc$ls180.v:1266$3283
+  attribute \src "ls180.v:1311.11-1311.55"
+  process $proc$ls180.v:1311$3424
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
   end
-  attribute \src "ls180.v:1268.5-1268.54"
-  process $proc$ls180.v:1268$3284
+  attribute \src "ls180.v:1313.5-1313.54"
+  process $proc$ls180.v:1313$3425
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
   end
-  attribute \src "ls180.v:1279.5-1279.50"
-  process $proc$ls180.v:1279$3285
+  attribute \src "ls180.v:1324.5-1324.50"
+  process $proc$ls180.v:1324$3426
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
   end
-  attribute \src "ls180.v:1281.5-1281.50"
-  process $proc$ls180.v:1281$3286
+  attribute \src "ls180.v:1326.5-1326.50"
+  process $proc$ls180.v:1326$3427
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
   end
-  attribute \src "ls180.v:1282.5-1282.49"
-  process $proc$ls180.v:1282$3287
+  attribute \src "ls180.v:1327.5-1327.49"
+  process $proc$ls180.v:1327$3428
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
   end
-  attribute \src "ls180.v:1283.11-1283.63"
-  process $proc$ls180.v:1283$3288
+  attribute \src "ls180.v:1328.11-1328.63"
+  process $proc$ls180.v:1328$3429
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1284.5-1284.39"
-  process $proc$ls180.v:1284$3289
+  attribute \src "ls180.v:1329.5-1329.39"
+  process $proc$ls180.v:1329$3430
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
   end
-  attribute \src "ls180.v:1287.5-1287.50"
-  process $proc$ls180.v:1287$3290
+  attribute \src "ls180.v:1332.5-1332.50"
+  process $proc$ls180.v:1332$3431
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1288.5-1288.49"
-  process $proc$ls180.v:1288$3291
+  attribute \src "ls180.v:1333.5-1333.49"
+  process $proc$ls180.v:1333$3432
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1289.5-1289.56"
-  process $proc$ls180.v:1289$3292
+  attribute \src "ls180.v:1334.5-1334.56"
+  process $proc$ls180.v:1334$3433
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
     sync init
   end
-  attribute \src "ls180.v:1291.5-1291.58"
-  process $proc$ls180.v:1291$3293
+  attribute \src "ls180.v:1336.5-1336.58"
+  process $proc$ls180.v:1336$3434
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
     sync init
   end
-  attribute \src "ls180.v:1292.5-1292.59"
-  process $proc$ls180.v:1292$3294
+  attribute \src "ls180.v:1337.5-1337.59"
+  process $proc$ls180.v:1337$3435
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1294.11-1294.65"
-  process $proc$ls180.v:1294$3295
+  attribute \src "ls180.v:1339.11-1339.65"
+  process $proc$ls180.v:1339$3436
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1295.5-1295.60"
-  process $proc$ls180.v:1295$3296
+  attribute \src "ls180.v:1340.5-1340.60"
+  process $proc$ls180.v:1340$3437
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1297.5-1297.49"
-  process $proc$ls180.v:1297$3297
+  attribute \src "ls180.v:1342.5-1342.49"
+  process $proc$ls180.v:1342$3438
     assign { } { }
     assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
   end
-  attribute \src "ls180.v:1298.5-1298.51"
-  process $proc$ls180.v:1298$3298
+  attribute \src "ls180.v:1343.5-1343.51"
+  process $proc$ls180.v:1343$3439
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
     sync init
   end
-  attribute \src "ls180.v:1299.5-1299.52"
-  process $proc$ls180.v:1299$3299
+  attribute \src "ls180.v:1344.5-1344.52"
+  process $proc$ls180.v:1344$3440
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1300.11-1300.58"
-  process $proc$ls180.v:1300$3300
+  attribute \src "ls180.v:1345.11-1345.58"
+  process $proc$ls180.v:1345$3441
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
     sync always
       update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
     sync init
   end
-  attribute \src "ls180.v:1301.5-1301.53"
-  process $proc$ls180.v:1301$3301
+  attribute \src "ls180.v:1346.5-1346.53"
+  process $proc$ls180.v:1346$3442
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:1302.5-1302.39"
-  process $proc$ls180.v:1302$3302
+  attribute \src "ls180.v:1347.5-1347.39"
+  process $proc$ls180.v:1347$3443
     assign { } { }
     assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1303.5-1303.39"
-  process $proc$ls180.v:1303$3303
+  attribute \src "ls180.v:1348.5-1348.39"
+  process $proc$ls180.v:1348$3444
     assign { } { }
     assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1304.5-1304.38"
-  process $proc$ls180.v:1304$3304
+  attribute \src "ls180.v:1349.5-1349.38"
+  process $proc$ls180.v:1349$3445
     assign { } { }
     assign $1\main_sdphy_datar_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
   end
-  attribute \src "ls180.v:1305.11-1305.61"
-  process $proc$ls180.v:1305$3305
+  attribute \src "ls180.v:1350.11-1350.61"
+  process $proc$ls180.v:1350$3446
     assign { } { }
     assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
     sync always
     sync init
       update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
   end
-  attribute \src "ls180.v:1306.5-1306.41"
-  process $proc$ls180.v:1306$3306
+  attribute \src "ls180.v:1351.5-1351.41"
+  process $proc$ls180.v:1351$3447
     assign { } { }
     assign $1\main_sdphy_datar_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
   end
-  attribute \src "ls180.v:1307.5-1307.41"
-  process $proc$ls180.v:1307$3307
+  attribute \src "ls180.v:1352.5-1352.41"
+  process $proc$ls180.v:1352$3448
     assign { } { }
     assign $1\main_sdphy_datar_source_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
   end
-  attribute \src "ls180.v:1308.5-1308.41"
-  process $proc$ls180.v:1308$3308
+  attribute \src "ls180.v:1353.5-1353.41"
+  process $proc$ls180.v:1353$3449
     assign { } { }
     assign $0\main_sdphy_datar_source_first[0:0] 1'0
     sync always
       update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1309.5-1309.40"
-  process $proc$ls180.v:1309$3309
+  attribute \src "ls180.v:1354.5-1354.40"
+  process $proc$ls180.v:1354$3450
     assign { } { }
     assign $1\main_sdphy_datar_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
   end
-  attribute \src "ls180.v:1310.11-1310.54"
-  process $proc$ls180.v:1310$3310
+  attribute \src "ls180.v:1355.11-1355.54"
+  process $proc$ls180.v:1355$3451
     assign { } { }
     assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1311.11-1311.56"
-  process $proc$ls180.v:1311$3311
+  attribute \src "ls180.v:1356.11-1356.56"
+  process $proc$ls180.v:1356$3452
     assign { } { }
     assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
     sync always
     sync init
       update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
   end
-  attribute \src "ls180.v:1312.5-1312.33"
-  process $proc$ls180.v:1312$3312
+  attribute \src "ls180.v:1357.5-1357.33"
+  process $proc$ls180.v:1357$3453
     assign { } { }
     assign $1\main_sdphy_datar_stop[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
   end
-  attribute \src "ls180.v:1313.12-1313.49"
-  process $proc$ls180.v:1313$3313
+  attribute \src "ls180.v:1358.12-1358.49"
+  process $proc$ls180.v:1358$3454
     assign { } { }
     assign $1\main_sdphy_datar_timeout[31:0] 500000
     sync always
     sync init
       update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
   end
-  attribute \src "ls180.v:1314.11-1314.41"
-  process $proc$ls180.v:1314$3314
+  attribute \src "ls180.v:1359.11-1359.41"
+  process $proc$ls180.v:1359$3455
     assign { } { }
     assign $1\main_sdphy_datar_count[9:0] 10'0000000000
     sync always
     sync init
       update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
   end
-  attribute \src "ls180.v:1316.5-1316.48"
-  process $proc$ls180.v:1316$3315
+  attribute \src "ls180.v:1361.5-1361.48"
+  process $proc$ls180.v:1361$3456
     assign { } { }
     assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
     sync always
       update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:1327.5-1327.55"
-  process $proc$ls180.v:1327$3316
+  attribute \src "ls180.v:1372.5-1372.55"
+  process $proc$ls180.v:1372$3457
     assign { } { }
     assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
   end
-  attribute \src "ls180.v:1332.5-1332.38"
-  process $proc$ls180.v:1332$3317
+  attribute \src "ls180.v:1377.5-1377.38"
+  process $proc$ls180.v:1377$3458
     assign { } { }
     assign $1\main_sdphy_datar_datar_run[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
   end
-  attribute \src "ls180.v:1335.5-1335.55"
-  process $proc$ls180.v:1335$3318
+  attribute \src "ls180.v:1380.5-1380.55"
+  process $proc$ls180.v:1380$3459
     assign { } { }
     assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
     sync always
       update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1336.5-1336.54"
-  process $proc$ls180.v:1336$3319
+  attribute \src "ls180.v:1381.5-1381.54"
+  process $proc$ls180.v:1381$3460
     assign { } { }
     assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
     sync always
       update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:1340.5-1340.57"
-  process $proc$ls180.v:1340$3320
+  attribute \src "ls180.v:1385.5-1385.57"
+  process $proc$ls180.v:1385$3461
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
   end
-  attribute \src "ls180.v:1341.5-1341.56"
-  process $proc$ls180.v:1341$3321
+  attribute \src "ls180.v:1386.5-1386.56"
+  process $proc$ls180.v:1386$3462
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
   end
-  attribute \src "ls180.v:1342.11-1342.70"
-  process $proc$ls180.v:1342$3322
+  attribute \src "ls180.v:1387.11-1387.70"
+  process $proc$ls180.v:1387$3463
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1343.11-1343.83"
-  process $proc$ls180.v:1343$3323
+  attribute \src "ls180.v:1388.11-1388.83"
+  process $proc$ls180.v:1388$3464
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
   end
-  attribute \src "ls180.v:1344.5-1344.50"
-  process $proc$ls180.v:1344$3324
+  attribute \src "ls180.v:1389.5-1389.50"
+  process $proc$ls180.v:1389$3465
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
   end
-  attribute \src "ls180.v:1346.5-1346.55"
-  process $proc$ls180.v:1346$3325
+  attribute \src "ls180.v:1391.5-1391.55"
+  process $proc$ls180.v:1391$3466
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
   end
-  attribute \src "ls180.v:1357.5-1357.51"
-  process $proc$ls180.v:1357$3326
+  attribute \src "ls180.v:1402.5-1402.51"
+  process $proc$ls180.v:1402$3467
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
   end
-  attribute \src "ls180.v:1359.5-1359.51"
-  process $proc$ls180.v:1359$3327
+  attribute \src "ls180.v:1404.5-1404.51"
+  process $proc$ls180.v:1404$3468
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
   end
-  attribute \src "ls180.v:1360.5-1360.50"
-  process $proc$ls180.v:1360$3328
+  attribute \src "ls180.v:1405.5-1405.50"
+  process $proc$ls180.v:1405$3469
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
   end
-  attribute \src "ls180.v:1361.11-1361.64"
-  process $proc$ls180.v:1361$3329
+  attribute \src "ls180.v:1406.11-1406.64"
+  process $proc$ls180.v:1406$3470
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1362.5-1362.40"
-  process $proc$ls180.v:1362$3330
+  attribute \src "ls180.v:1407.5-1407.40"
+  process $proc$ls180.v:1407$3471
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
   end
-  attribute \src "ls180.v:1364.5-1364.35"
-  process $proc$ls180.v:1364$3331
+  attribute \src "ls180.v:1409.5-1409.35"
+  process $proc$ls180.v:1409$3472
     assign { } { }
     assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
   end
-  attribute \src "ls180.v:1367.11-1367.42"
-  process $proc$ls180.v:1367$3332
+  attribute \src "ls180.v:1412.11-1412.42"
+  process $proc$ls180.v:1412$3473
     assign { } { }
     assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
     sync always
     sync init
       update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
   end
-  attribute \src "ls180.v:1380.12-1380.52"
-  process $proc$ls180.v:1380$3333
+  attribute \src "ls180.v:1425.12-1425.52"
+  process $proc$ls180.v:1425$3474
     assign { } { }
     assign $1\main_sdcore_cmd_argument_storage[31:0] 0
     sync always
     sync init
       update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
   end
-  attribute \src "ls180.v:1381.5-1381.39"
-  process $proc$ls180.v:1381$3334
+  attribute \src "ls180.v:1426.5-1426.39"
+  process $proc$ls180.v:1426$3475
     assign { } { }
     assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
   end
-  attribute \src "ls180.v:1382.12-1382.51"
-  process $proc$ls180.v:1382$3335
+  attribute \src "ls180.v:1427.12-1427.51"
+  process $proc$ls180.v:1427$3476
     assign { } { }
     assign $1\main_sdcore_cmd_command_storage[31:0] 0
     sync always
     sync init
       update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
   end
-  attribute \src "ls180.v:1383.5-1383.38"
-  process $proc$ls180.v:1383$3336
+  attribute \src "ls180.v:1428.5-1428.38"
+  process $proc$ls180.v:1428$3477
     assign { } { }
     assign $1\main_sdcore_cmd_command_re[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
   end
-  attribute \src "ls180.v:1387.5-1387.34"
-  process $proc$ls180.v:1387$3337
+  attribute \src "ls180.v:1432.5-1432.34"
+  process $proc$ls180.v:1432$3478
     assign { } { }
     assign $0\main_sdcore_cmd_send_w[0:0] 1'0
     sync always
       update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0]
     sync init
   end
-  attribute \src "ls180.v:1388.13-1388.53"
-  process $proc$ls180.v:1388$3338
+  attribute \src "ls180.v:1433.13-1433.53"
+  process $proc$ls180.v:1433$3479
     assign { } { }
     assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
   end
-  attribute \src "ls180.v:1394.11-1394.51"
-  process $proc$ls180.v:1394$3339
+  attribute \src "ls180.v:1439.11-1439.51"
+  process $proc$ls180.v:1439$3480
     assign { } { }
     assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
     sync always
     sync init
       update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
   end
-  attribute \src "ls180.v:1395.5-1395.39"
-  process $proc$ls180.v:1395$3340
+  attribute \src "ls180.v:1440.5-1440.39"
+  process $proc$ls180.v:1440$3481
     assign { } { }
     assign $1\main_sdcore_block_length_re[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
   end
-  attribute \src "ls180.v:1396.12-1396.51"
-  process $proc$ls180.v:1396$3341
+  attribute \src "ls180.v:1441.12-1441.51"
+  process $proc$ls180.v:1441$3482
     assign { } { }
     assign $1\main_sdcore_block_count_storage[31:0] 0
     sync always
     sync init
       update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
   end
-  attribute \src "ls180.v:1397.5-1397.38"
-  process $proc$ls180.v:1397$3342
+  attribute \src "ls180.v:1442.5-1442.38"
+  process $proc$ls180.v:1442$3483
     assign { } { }
     assign $1\main_sdcore_block_count_re[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
   end
-  attribute \src "ls180.v:1398.11-1398.51"
-  process $proc$ls180.v:1398$3343
+  attribute \src "ls180.v:1443.11-1443.51"
+  process $proc$ls180.v:1443$3484
     assign { } { }
     assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
     sync always
     sync init
       update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
   end
-  attribute \src "ls180.v:1440.11-1440.47"
-  process $proc$ls180.v:1440$3344
+  attribute \src "ls180.v:1485.11-1485.47"
+  process $proc$ls180.v:1485$3485
     assign { } { }
     assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
     sync always
     sync init
       update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
   end
-  attribute \src "ls180.v:1444.5-1444.49"
-  process $proc$ls180.v:1444$3345
+  attribute \src "ls180.v:1489.5-1489.49"
+  process $proc$ls180.v:1489$3486
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1448.5-1448.51"
-  process $proc$ls180.v:1448$3346
+  attribute \src "ls180.v:1493.5-1493.51"
+  process $proc$ls180.v:1493$3487
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
   end
-  attribute \src "ls180.v:1449.5-1449.51"
-  process $proc$ls180.v:1449$3347
+  attribute \src "ls180.v:1494.5-1494.51"
+  process $proc$ls180.v:1494$3488
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
   end
-  attribute \src "ls180.v:1450.5-1450.51"
-  process $proc$ls180.v:1450$3348
+  attribute \src "ls180.v:1495.5-1495.51"
+  process $proc$ls180.v:1495$3489
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
     sync always
       update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1451.5-1451.50"
-  process $proc$ls180.v:1451$3349
+  attribute \src "ls180.v:1496.5-1496.50"
+  process $proc$ls180.v:1496$3490
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
   end
-  attribute \src "ls180.v:1452.11-1452.64"
-  process $proc$ls180.v:1452$3350
+  attribute \src "ls180.v:1497.11-1497.64"
+  process $proc$ls180.v:1497$3491
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:1453.11-1453.48"
-  process $proc$ls180.v:1453$3351
+  attribute \src "ls180.v:1498.11-1498.48"
+  process $proc$ls180.v:1498$3492
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
   end
-  attribute \src "ls180.v:1454.12-1454.59"
-  process $proc$ls180.v:1454$3352
+  attribute \src "ls180.v:1499.12-1499.59"
+  process $proc$ls180.v:1499$3493
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1458.12-1458.55"
-  process $proc$ls180.v:1458$3353
+  attribute \src "ls180.v:1503.12-1503.55"
+  process $proc$ls180.v:1503$3494
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
   end
-  attribute \src "ls180.v:1461.12-1461.59"
-  process $proc$ls180.v:1461$3354
+  attribute \src "ls180.v:1506.12-1506.59"
+  process $proc$ls180.v:1506$3495
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1465.12-1465.55"
-  process $proc$ls180.v:1465$3355
+  attribute \src "ls180.v:1510.12-1510.55"
+  process $proc$ls180.v:1510$3496
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
   end
-  attribute \src "ls180.v:1468.12-1468.59"
-  process $proc$ls180.v:1468$3356
+  attribute \src "ls180.v:1513.12-1513.59"
+  process $proc$ls180.v:1513$3497
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1472.12-1472.55"
-  process $proc$ls180.v:1472$3357
+  attribute \src "ls180.v:1517.12-1517.55"
+  process $proc$ls180.v:1517$3498
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
   end
-  attribute \src "ls180.v:1475.12-1475.59"
-  process $proc$ls180.v:1475$3358
+  attribute \src "ls180.v:1520.12-1520.59"
+  process $proc$ls180.v:1520$3499
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1479.12-1479.55"
-  process $proc$ls180.v:1479$3359
+  attribute \src "ls180.v:1524.12-1524.55"
+  process $proc$ls180.v:1524$3500
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
   end
-  attribute \src "ls180.v:1482.12-1482.54"
-  process $proc$ls180.v:1482$3360
+  attribute \src "ls180.v:1527.12-1527.54"
+  process $proc$ls180.v:1527$3501
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
   end
-  attribute \src "ls180.v:1483.12-1483.54"
-  process $proc$ls180.v:1483$3361
+  attribute \src "ls180.v:1528.12-1528.54"
+  process $proc$ls180.v:1528$3502
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
   end
-  attribute \src "ls180.v:1484.12-1484.54"
-  process $proc$ls180.v:1484$3362
+  attribute \src "ls180.v:1529.12-1529.54"
+  process $proc$ls180.v:1529$3503
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
   end
-  attribute \src "ls180.v:1485.12-1485.54"
-  process $proc$ls180.v:1485$3363
+  attribute \src "ls180.v:1530.12-1530.54"
+  process $proc$ls180.v:1530$3504
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
   end
-  attribute \src "ls180.v:1486.5-1486.48"
-  process $proc$ls180.v:1486$3364
+  attribute \src "ls180.v:1531.5-1531.48"
+  process $proc$ls180.v:1531$3505
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1487.5-1487.48"
-  process $proc$ls180.v:1487$3365
+  attribute \src "ls180.v:1532.5-1532.48"
+  process $proc$ls180.v:1532$3506
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1488.5-1488.48"
-  process $proc$ls180.v:1488$3366
+  attribute \src "ls180.v:1533.5-1533.48"
+  process $proc$ls180.v:1533$3507
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
   end
-  attribute \src "ls180.v:1489.5-1489.47"
-  process $proc$ls180.v:1489$3367
+  attribute \src "ls180.v:1534.5-1534.47"
+  process $proc$ls180.v:1534$3508
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
   end
-  attribute \src "ls180.v:1490.11-1490.61"
-  process $proc$ls180.v:1490$3368
+  attribute \src "ls180.v:1535.11-1535.61"
+  process $proc$ls180.v:1535$3509
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
   end
-  attribute \src "ls180.v:1491.5-1491.50"
-  process $proc$ls180.v:1491$3369
+  attribute \src "ls180.v:1536.5-1536.50"
+  process $proc$ls180.v:1536$3510
     assign { } { }
     assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
   end
-  attribute \src "ls180.v:1493.5-1493.50"
-  process $proc$ls180.v:1493$3370
+  attribute \src "ls180.v:1538.5-1538.50"
+  process $proc$ls180.v:1538$3511
     assign { } { }
     assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
     sync always
       update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1496.11-1496.47"
-  process $proc$ls180.v:1496$3371
+  attribute \src "ls180.v:1541.11-1541.47"
+  process $proc$ls180.v:1541$3512
     assign { } { }
     assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
   end
-  attribute \src "ls180.v:1497.11-1497.47"
-  process $proc$ls180.v:1497$3372
+  attribute \src "ls180.v:1542.11-1542.47"
+  process $proc$ls180.v:1542$3513
     assign { } { }
     assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
     sync always
     sync init
       update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
   end
-  attribute \src "ls180.v:1498.12-1498.58"
-  process $proc$ls180.v:1498$3373
+  attribute \src "ls180.v:1543.12-1543.58"
+  process $proc$ls180.v:1543$3514
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1502.12-1502.54"
-  process $proc$ls180.v:1502$3374
+  attribute \src "ls180.v:1547.12-1547.54"
+  process $proc$ls180.v:1547$3515
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
   end
-  attribute \src "ls180.v:1503.5-1503.46"
-  process $proc$ls180.v:1503$3375
+  attribute \src "ls180.v:1548.5-1548.46"
+  process $proc$ls180.v:1548$3516
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
   end
-  attribute \src "ls180.v:1505.12-1505.58"
-  process $proc$ls180.v:1505$3376
+  attribute \src "ls180.v:1550.12-1550.58"
+  process $proc$ls180.v:1550$3517
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1509.12-1509.54"
-  process $proc$ls180.v:1509$3377
+  attribute \src "ls180.v:1554.12-1554.54"
+  process $proc$ls180.v:1554$3518
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
   end
-  attribute \src "ls180.v:1510.5-1510.46"
-  process $proc$ls180.v:1510$3378
+  attribute \src "ls180.v:1555.5-1555.46"
+  process $proc$ls180.v:1555$3519
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
   end
-  attribute \src "ls180.v:1512.12-1512.58"
-  process $proc$ls180.v:1512$3379
+  attribute \src "ls180.v:1557.12-1557.58"
+  process $proc$ls180.v:1557$3520
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1516.12-1516.54"
-  process $proc$ls180.v:1516$3380
+  attribute \src "ls180.v:1561.12-1561.54"
+  process $proc$ls180.v:1561$3521
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
   end
-  attribute \src "ls180.v:1517.5-1517.46"
-  process $proc$ls180.v:1517$3381
+  attribute \src "ls180.v:1562.5-1562.46"
+  process $proc$ls180.v:1562$3522
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
   end
-  attribute \src "ls180.v:1519.12-1519.58"
-  process $proc$ls180.v:1519$3382
+  attribute \src "ls180.v:1564.12-1564.58"
+  process $proc$ls180.v:1564$3523
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
   end
-  attribute \src "ls180.v:1523.12-1523.54"
-  process $proc$ls180.v:1523$3383
+  attribute \src "ls180.v:1568.12-1568.54"
+  process $proc$ls180.v:1568$3524
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
   end
-  attribute \src "ls180.v:1524.5-1524.46"
-  process $proc$ls180.v:1524$3384
+  attribute \src "ls180.v:1569.5-1569.46"
+  process $proc$ls180.v:1569$3525
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
   end
-  attribute \src "ls180.v:1526.12-1526.53"
-  process $proc$ls180.v:1526$3385
+  attribute \src "ls180.v:1571.12-1571.53"
+  process $proc$ls180.v:1571$3526
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
   end
-  attribute \src "ls180.v:1527.12-1527.53"
-  process $proc$ls180.v:1527$3386
+  attribute \src "ls180.v:1572.12-1572.53"
+  process $proc$ls180.v:1572$3527
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
   end
-  attribute \src "ls180.v:1528.12-1528.53"
-  process $proc$ls180.v:1528$3387
+  attribute \src "ls180.v:1573.12-1573.53"
+  process $proc$ls180.v:1573$3528
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
   end
-  attribute \src "ls180.v:1529.12-1529.53"
-  process $proc$ls180.v:1529$3388
+  attribute \src "ls180.v:1574.12-1574.53"
+  process $proc$ls180.v:1574$3529
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
   end
-  attribute \src "ls180.v:1530.5-1530.43"
-  process $proc$ls180.v:1530$3389
+  attribute \src "ls180.v:1575.5-1575.43"
+  process $proc$ls180.v:1575$3530
     assign { } { }
     assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
   end
-  attribute \src "ls180.v:1531.12-1531.51"
-  process $proc$ls180.v:1531$3390
+  attribute \src "ls180.v:1576.12-1576.51"
+  process $proc$ls180.v:1576$3531
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
   end
-  attribute \src "ls180.v:1532.12-1532.51"
-  process $proc$ls180.v:1532$3391
+  attribute \src "ls180.v:1577.12-1577.51"
+  process $proc$ls180.v:1577$3532
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
   end
-  attribute \src "ls180.v:1533.12-1533.51"
-  process $proc$ls180.v:1533$3392
+  attribute \src "ls180.v:1578.12-1578.51"
+  process $proc$ls180.v:1578$3533
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
   end
-  attribute \src "ls180.v:1534.12-1534.51"
-  process $proc$ls180.v:1534$3393
+  attribute \src "ls180.v:1579.12-1579.51"
+  process $proc$ls180.v:1579$3534
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
   end
-  attribute \src "ls180.v:1536.11-1536.39"
-  process $proc$ls180.v:1536$3394
+  attribute \src "ls180.v:158.12-158.71"
+  process $proc$ls180.v:158$2907
+    assign { } { }
+    assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    sync always
+    sync init
+      update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
+  end
+  attribute \src "ls180.v:1581.11-1581.39"
+  process $proc$ls180.v:1581$3535
     assign { } { }
     assign $1\main_sdcore_cmd_count[2:0] 3'000
     sync always
     sync init
       update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
   end
-  attribute \src "ls180.v:1537.5-1537.32"
-  process $proc$ls180.v:1537$3395
+  attribute \src "ls180.v:1582.5-1582.32"
+  process $proc$ls180.v:1582$3536
     assign { } { }
     assign $1\main_sdcore_cmd_done[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
   end
-  attribute \src "ls180.v:1538.5-1538.33"
-  process $proc$ls180.v:1538$3396
+  attribute \src "ls180.v:1583.5-1583.33"
+  process $proc$ls180.v:1583$3537
     assign { } { }
     assign $1\main_sdcore_cmd_error[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
   end
-  attribute \src "ls180.v:1539.5-1539.35"
-  process $proc$ls180.v:1539$3397
+  attribute \src "ls180.v:1584.5-1584.35"
+  process $proc$ls180.v:1584$3538
     assign { } { }
     assign $1\main_sdcore_cmd_timeout[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
   end
-  attribute \src "ls180.v:1541.12-1541.42"
-  process $proc$ls180.v:1541$3398
+  attribute \src "ls180.v:1586.12-1586.42"
+  process $proc$ls180.v:1586$3539
     assign { } { }
     assign $1\main_sdcore_data_count[31:0] 0
     sync always
     sync init
       update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
   end
-  attribute \src "ls180.v:1542.5-1542.33"
-  process $proc$ls180.v:1542$3399
+  attribute \src "ls180.v:1587.5-1587.33"
+  process $proc$ls180.v:1587$3540
     assign { } { }
     assign $1\main_sdcore_data_done[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
   end
-  attribute \src "ls180.v:1543.5-1543.34"
-  process $proc$ls180.v:1543$3400
+  attribute \src "ls180.v:1588.5-1588.34"
+  process $proc$ls180.v:1588$3541
     assign { } { }
     assign $1\main_sdcore_data_error[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
   end
-  attribute \src "ls180.v:1544.5-1544.36"
-  process $proc$ls180.v:1544$3401
+  attribute \src "ls180.v:1589.5-1589.36"
+  process $proc$ls180.v:1589$3542
     assign { } { }
     assign $1\main_sdcore_data_timeout[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
   end
-  attribute \src "ls180.v:1553.11-1553.41"
-  process $proc$ls180.v:1553$3402
+  attribute \src "ls180.v:159.12-159.73"
+  process $proc$ls180.v:159$2908
+    assign { } { }
+    assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
+    sync always
+    sync init
+      update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
+  end
+  attribute \src "ls180.v:1598.11-1598.41"
+  process $proc$ls180.v:1598$3543
     assign { } { }
     assign $0\main_interface0_bus_cti[2:0] 3'000
     sync always
       update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0]
     sync init
   end
-  attribute \src "ls180.v:1554.11-1554.41"
-  process $proc$ls180.v:1554$3403
+  attribute \src "ls180.v:1599.11-1599.41"
+  process $proc$ls180.v:1599$3544
     assign { } { }
     assign $0\main_interface0_bus_bte[1:0] 2'00
     sync always
       update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0]
     sync init
   end
-  attribute \src "ls180.v:1577.11-1577.45"
-  process $proc$ls180.v:1577$3404
+  attribute \src "ls180.v:161.11-161.69"
+  process $proc$ls180.v:161$2909
+    assign { } { }
+    assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
+    sync always
+    sync init
+      update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
+  end
+  attribute \src "ls180.v:162.5-162.63"
+  process $proc$ls180.v:162$2910
+    assign { } { }
+    assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
+  end
+  attribute \src "ls180.v:1622.11-1622.45"
+  process $proc$ls180.v:1622$3545
     assign { } { }
     assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
     sync always
     sync init
       update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
   end
-  attribute \src "ls180.v:1578.5-1578.41"
-  process $proc$ls180.v:1578$3405
+  attribute \src "ls180.v:1623.5-1623.41"
+  process $proc$ls180.v:1623$3546
     assign { } { }
     assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
     sync always
       update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:1579.11-1579.47"
-  process $proc$ls180.v:1579$3406
+  attribute \src "ls180.v:1624.11-1624.47"
+  process $proc$ls180.v:1624$3547
     assign { } { }
     assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
     sync always
     sync init
       update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
   end
-  attribute \src "ls180.v:158.12-158.71"
-  process $proc$ls180.v:158$2775
-    assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
-    sync always
-    sync init
-      update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
-  end
-  attribute \src "ls180.v:1580.11-1580.47"
-  process $proc$ls180.v:1580$3407
+  attribute \src "ls180.v:1625.11-1625.47"
+  process $proc$ls180.v:1625$3548
     assign { } { }
     assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
     sync always
     sync init
       update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
   end
-  attribute \src "ls180.v:1581.11-1581.50"
-  process $proc$ls180.v:1581$3408
+  attribute \src "ls180.v:1626.11-1626.50"
+  process $proc$ls180.v:1626$3549
     assign { } { }
     assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
     sync always
     sync init
       update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
   end
-  attribute \src "ls180.v:159.12-159.73"
-  process $proc$ls180.v:159$2776
+  attribute \src "ls180.v:163.5-163.63"
+  process $proc$ls180.v:163$2911
     assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
+    assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
+      update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
   end
-  attribute \src "ls180.v:1601.5-1601.51"
-  process $proc$ls180.v:1601$3409
+  attribute \src "ls180.v:1646.5-1646.51"
+  process $proc$ls180.v:1646$3550
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
   end
-  attribute \src "ls180.v:1602.5-1602.50"
-  process $proc$ls180.v:1602$3410
+  attribute \src "ls180.v:1647.5-1647.50"
+  process $proc$ls180.v:1647$3551
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
   end
-  attribute \src "ls180.v:1603.12-1603.66"
-  process $proc$ls180.v:1603$3411
+  attribute \src "ls180.v:1648.12-1648.66"
+  process $proc$ls180.v:1648$3552
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
   end
-  attribute \src "ls180.v:1604.11-1604.77"
-  process $proc$ls180.v:1604$3412
+  attribute \src "ls180.v:1649.11-1649.77"
+  process $proc$ls180.v:1649$3553
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
     sync always
     sync init
       update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
   end
-  attribute \src "ls180.v:1605.11-1605.50"
-  process $proc$ls180.v:1605$3413
+  attribute \src "ls180.v:165.5-165.62"
+  process $proc$ls180.v:165$2912
+    assign { } { }
+    assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
+  end
+  attribute \src "ls180.v:1650.11-1650.50"
+  process $proc$ls180.v:1650$3554
     assign { } { }
     assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
     sync always
     sync init
       update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
   end
-  attribute \src "ls180.v:1607.5-1607.49"
-  process $proc$ls180.v:1607$3414
+  attribute \src "ls180.v:1652.5-1652.49"
+  process $proc$ls180.v:1652$3555
     assign { } { }
     assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
   end
-  attribute \src "ls180.v:161.11-161.69"
-  process $proc$ls180.v:161$2777
+  attribute \src "ls180.v:1658.5-1658.45"
+  process $proc$ls180.v:1658$3556
     assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
+    assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
+      update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
   end
-  attribute \src "ls180.v:1613.5-1613.45"
-  process $proc$ls180.v:1613$3415
+  attribute \src "ls180.v:166.11-166.69"
+  process $proc$ls180.v:166$2913
     assign { } { }
-    assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
+    assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
     sync always
+      update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
     sync init
-      update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
   end
-  attribute \src "ls180.v:1615.12-1615.62"
-  process $proc$ls180.v:1615$3416
+  attribute \src "ls180.v:1660.12-1660.62"
+  process $proc$ls180.v:1660$3557
     assign { } { }
     assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
   end
-  attribute \src "ls180.v:1616.12-1616.60"
-  process $proc$ls180.v:1616$3417
+  attribute \src "ls180.v:1661.12-1661.60"
+  process $proc$ls180.v:1661$3558
     assign { } { }
     assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
   end
-  attribute \src "ls180.v:1618.5-1618.57"
-  process $proc$ls180.v:1618$3418
+  attribute \src "ls180.v:1663.5-1663.57"
+  process $proc$ls180.v:1663$3559
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
   end
-  attribute \src "ls180.v:162.5-162.63"
-  process $proc$ls180.v:162$2778
-    assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
-  end
-  attribute \src "ls180.v:1622.12-1622.67"
-  process $proc$ls180.v:1622$3419
+  attribute \src "ls180.v:1667.12-1667.67"
+  process $proc$ls180.v:1667$3560
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
   end
-  attribute \src "ls180.v:1623.5-1623.54"
-  process $proc$ls180.v:1623$3420
+  attribute \src "ls180.v:1668.5-1668.54"
+  process $proc$ls180.v:1668$3561
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
   end
-  attribute \src "ls180.v:1624.12-1624.69"
-  process $proc$ls180.v:1624$3421
+  attribute \src "ls180.v:1669.12-1669.69"
+  process $proc$ls180.v:1669$3562
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
   end
-  attribute \src "ls180.v:1625.5-1625.56"
-  process $proc$ls180.v:1625$3422
+  attribute \src "ls180.v:167.11-167.69"
+  process $proc$ls180.v:167$2914
+    assign { } { }
+    assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
+    sync always
+      update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
+    sync init
+  end
+  attribute \src "ls180.v:1670.5-1670.56"
+  process $proc$ls180.v:1670$3563
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
   end
-  attribute \src "ls180.v:1626.5-1626.61"
-  process $proc$ls180.v:1626$3423
+  attribute \src "ls180.v:1671.5-1671.61"
+  process $proc$ls180.v:1671$3564
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
   end
-  attribute \src "ls180.v:1627.5-1627.56"
-  process $proc$ls180.v:1627$3424
+  attribute \src "ls180.v:1672.5-1672.56"
+  process $proc$ls180.v:1672$3565
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
   end
-  attribute \src "ls180.v:1628.5-1628.53"
-  process $proc$ls180.v:1628$3425
+  attribute \src "ls180.v:1673.5-1673.53"
+  process $proc$ls180.v:1673$3566
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
   end
-  attribute \src "ls180.v:163.5-163.63"
-  process $proc$ls180.v:163$2779
-    assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
-  end
-  attribute \src "ls180.v:1630.5-1630.59"
-  process $proc$ls180.v:1630$3426
+  attribute \src "ls180.v:1675.5-1675.59"
+  process $proc$ls180.v:1675$3567
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
   end
-  attribute \src "ls180.v:1631.5-1631.54"
-  process $proc$ls180.v:1631$3427
+  attribute \src "ls180.v:1676.5-1676.54"
+  process $proc$ls180.v:1676$3568
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
   end
-  attribute \src "ls180.v:1633.12-1633.61"
-  process $proc$ls180.v:1633$3428
+  attribute \src "ls180.v:1678.12-1678.61"
+  process $proc$ls180.v:1678$3569
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
   end
-  attribute \src "ls180.v:1636.12-1636.43"
-  process $proc$ls180.v:1636$3429
+  attribute \src "ls180.v:1681.12-1681.43"
+  process $proc$ls180.v:1681$3570
     assign { } { }
     assign $1\main_interface1_bus_adr[31:0] 0
     sync always
     sync init
       update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
   end
-  attribute \src "ls180.v:1637.12-1637.45"
-  process $proc$ls180.v:1637$3430
+  attribute \src "ls180.v:1682.12-1682.45"
+  process $proc$ls180.v:1682$3571
     assign { } { }
     assign $0\main_interface1_bus_dat_w[31:0] 0
     sync always
       update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0]
     sync init
   end
-  attribute \src "ls180.v:1639.11-1639.41"
-  process $proc$ls180.v:1639$3431
+  attribute \src "ls180.v:1684.11-1684.41"
+  process $proc$ls180.v:1684$3572
     assign { } { }
     assign $1\main_interface1_bus_sel[3:0] 4'0000
     sync always
     sync init
       update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
   end
-  attribute \src "ls180.v:1640.5-1640.35"
-  process $proc$ls180.v:1640$3432
+  attribute \src "ls180.v:1685.5-1685.35"
+  process $proc$ls180.v:1685$3573
     assign { } { }
     assign $1\main_interface1_bus_cyc[0:0] 1'0
     sync always
     sync init
       update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
   end
-  attribute \src "ls180.v:1641.5-1641.35"
-  process $proc$ls180.v:1641$3433
+  attribute \src "ls180.v:1686.5-1686.35"
+  process $proc$ls180.v:1686$3574
     assign { } { }
     assign $1\main_interface1_bus_stb[0:0] 1'0
     sync always
     sync init
       update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
   end
-  attribute \src "ls180.v:1643.5-1643.34"
-  process $proc$ls180.v:1643$3434
+  attribute \src "ls180.v:1688.5-1688.34"
+  process $proc$ls180.v:1688$3575
     assign { } { }
     assign $1\main_interface1_bus_we[0:0] 1'0
     sync always
     sync init
       update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
   end
-  attribute \src "ls180.v:1644.11-1644.41"
-  process $proc$ls180.v:1644$3435
+  attribute \src "ls180.v:1689.11-1689.41"
+  process $proc$ls180.v:1689$3576
     assign { } { }
     assign $0\main_interface1_bus_cti[2:0] 3'000
     sync always
       update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0]
     sync init
   end
-  attribute \src "ls180.v:1645.11-1645.41"
-  process $proc$ls180.v:1645$3436
+  attribute \src "ls180.v:169.5-169.44"
+  process $proc$ls180.v:169$2915
     assign { } { }
-    assign $0\main_interface1_bus_bte[1:0] 2'00
+    assign $1\main_libresocsim_converter0_skip[0:0] 1'0
     sync always
-      update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
     sync init
+      update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
   end
-  attribute \src "ls180.v:165.5-165.62"
-  process $proc$ls180.v:165$2780
+  attribute \src "ls180.v:1690.11-1690.41"
+  process $proc$ls180.v:1690$3577
     assign { } { }
-    assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+    assign $0\main_interface1_bus_bte[1:0] 2'00
     sync always
+      update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
     sync init
-      update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
   end
-  attribute \src "ls180.v:1652.5-1652.43"
-  process $proc$ls180.v:1652$3437
+  attribute \src "ls180.v:1697.5-1697.43"
+  process $proc$ls180.v:1697$3578
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
   end
-  attribute \src "ls180.v:1653.5-1653.43"
-  process $proc$ls180.v:1653$3438
+  attribute \src "ls180.v:1698.5-1698.43"
+  process $proc$ls180.v:1698$3579
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
   end
-  attribute \src "ls180.v:1654.5-1654.42"
-  process $proc$ls180.v:1654$3439
+  attribute \src "ls180.v:1699.5-1699.42"
+  process $proc$ls180.v:1699$3580
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
   end
-  attribute \src "ls180.v:1655.12-1655.61"
-  process $proc$ls180.v:1655$3440
+  attribute \src "ls180.v:170.5-170.47"
+  process $proc$ls180.v:170$2916
+    assign { } { }
+    assign $1\main_libresocsim_converter0_counter[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
+  end
+  attribute \src "ls180.v:1700.12-1700.61"
+  process $proc$ls180.v:1700$3581
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
   end
-  attribute \src "ls180.v:1656.5-1656.45"
-  process $proc$ls180.v:1656$3441
+  attribute \src "ls180.v:1701.5-1701.45"
+  process $proc$ls180.v:1701$3582
     assign { } { }
     assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
   end
-  attribute \src "ls180.v:1658.5-1658.45"
-  process $proc$ls180.v:1658$3442
+  attribute \src "ls180.v:1703.5-1703.45"
+  process $proc$ls180.v:1703$3583
     assign { } { }
     assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
     sync always
       update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:1659.5-1659.44"
-  process $proc$ls180.v:1659$3443
+  attribute \src "ls180.v:1704.5-1704.44"
+  process $proc$ls180.v:1704$3584
     assign { } { }
     assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
   end
-  attribute \src "ls180.v:166.11-166.69"
-  process $proc$ls180.v:166$2781
-    assign { } { }
-    assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
-    sync always
-      update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
-    sync init
-  end
-  attribute \src "ls180.v:1660.12-1660.60"
-  process $proc$ls180.v:1660$3444
+  attribute \src "ls180.v:1705.12-1705.60"
+  process $proc$ls180.v:1705$3585
     assign { } { }
     assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
   end
-  attribute \src "ls180.v:1661.12-1661.45"
-  process $proc$ls180.v:1661$3445
+  attribute \src "ls180.v:1706.12-1706.45"
+  process $proc$ls180.v:1706$3586
     assign { } { }
     assign $1\main_sdmem2block_dma_data[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
   end
-  attribute \src "ls180.v:1662.12-1662.53"
-  process $proc$ls180.v:1662$3446
+  attribute \src "ls180.v:1707.12-1707.53"
+  process $proc$ls180.v:1707$3587
     assign { } { }
     assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
   end
-  attribute \src "ls180.v:1663.5-1663.40"
-  process $proc$ls180.v:1663$3447
+  attribute \src "ls180.v:1708.5-1708.40"
+  process $proc$ls180.v:1708$3588
     assign { } { }
     assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
   end
-  attribute \src "ls180.v:1664.12-1664.55"
-  process $proc$ls180.v:1664$3448
+  attribute \src "ls180.v:1709.12-1709.55"
+  process $proc$ls180.v:1709$3589
     assign { } { }
     assign $1\main_sdmem2block_dma_length_storage[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
   end
-  attribute \src "ls180.v:1665.5-1665.42"
-  process $proc$ls180.v:1665$3449
+  attribute \src "ls180.v:1710.5-1710.42"
+  process $proc$ls180.v:1710$3590
     assign { } { }
     assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
   end
-  attribute \src "ls180.v:1666.5-1666.47"
-  process $proc$ls180.v:1666$3450
+  attribute \src "ls180.v:1711.5-1711.47"
+  process $proc$ls180.v:1711$3591
     assign { } { }
     assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
   end
-  attribute \src "ls180.v:1667.5-1667.42"
-  process $proc$ls180.v:1667$3451
+  attribute \src "ls180.v:1712.5-1712.42"
+  process $proc$ls180.v:1712$3592
     assign { } { }
     assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
   end
-  attribute \src "ls180.v:1668.5-1668.44"
-  process $proc$ls180.v:1668$3452
+  attribute \src "ls180.v:1713.5-1713.44"
+  process $proc$ls180.v:1713$3593
     assign { } { }
     assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
   end
-  attribute \src "ls180.v:167.11-167.69"
-  process $proc$ls180.v:167$2782
-    assign { } { }
-    assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
-    sync always
-      update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
-    sync init
-  end
-  attribute \src "ls180.v:1670.5-1670.45"
-  process $proc$ls180.v:1670$3453
+  attribute \src "ls180.v:1715.5-1715.45"
+  process $proc$ls180.v:1715$3594
     assign { } { }
     assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
   end
-  attribute \src "ls180.v:1671.5-1671.40"
-  process $proc$ls180.v:1671$3454
+  attribute \src "ls180.v:1716.5-1716.40"
+  process $proc$ls180.v:1716$3595
     assign { } { }
     assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
   end
-  attribute \src "ls180.v:1675.12-1675.47"
-  process $proc$ls180.v:1675$3455
+  attribute \src "ls180.v:172.12-172.53"
+  process $proc$ls180.v:172$2917
+    assign { } { }
+    assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync always
+    sync init
+      update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
+  end
+  attribute \src "ls180.v:1720.12-1720.47"
+  process $proc$ls180.v:1720$3596
     assign { } { }
     assign $1\main_sdmem2block_dma_offset[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
   end
-  attribute \src "ls180.v:1687.11-1687.64"
-  process $proc$ls180.v:1687$3456
+  attribute \src "ls180.v:173.12-173.71"
+  process $proc$ls180.v:173$2918
     assign { } { }
-    assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
+    assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
     sync init
-      update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
+      update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
   end
-  attribute \src "ls180.v:1689.11-1689.48"
-  process $proc$ls180.v:1689$3457
+  attribute \src "ls180.v:1732.11-1732.64"
+  process $proc$ls180.v:1732$3597
     assign { } { }
-    assign $1\main_sdmem2block_converter_mux[1:0] 2'00
+    assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
     sync always
     sync init
-      update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
+      update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:169.5-169.44"
-  process $proc$ls180.v:169$2783
+  attribute \src "ls180.v:1734.11-1734.48"
+  process $proc$ls180.v:1734$3598
     assign { } { }
-    assign $1\main_libresocsim_converter0_skip[0:0] 1'0
+    assign $1\main_sdmem2block_converter_mux[1:0] 2'00
     sync always
     sync init
-      update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
+      update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
   end
-  attribute \src "ls180.v:170.5-170.47"
-  process $proc$ls180.v:170$2784
+  attribute \src "ls180.v:174.12-174.73"
+  process $proc$ls180.v:174$2919
     assign { } { }
-    assign $1\main_libresocsim_converter0_counter[0:0] 1'0
+    assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
     sync always
     sync init
-      update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
+      update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:1713.11-1713.45"
-  process $proc$ls180.v:1713$3458
+  attribute \src "ls180.v:1758.11-1758.45"
+  process $proc$ls180.v:1758$3599
     assign { } { }
     assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
     sync always
     sync init
       update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
   end
-  attribute \src "ls180.v:1714.5-1714.41"
-  process $proc$ls180.v:1714$3459
+  attribute \src "ls180.v:1759.5-1759.41"
+  process $proc$ls180.v:1759$3600
     assign { } { }
     assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
     sync always
       update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:1715.11-1715.47"
-  process $proc$ls180.v:1715$3460
+  attribute \src "ls180.v:176.11-176.69"
+  process $proc$ls180.v:176$2920
+    assign { } { }
+    assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
+    sync always
+    sync init
+      update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
+  end
+  attribute \src "ls180.v:1760.11-1760.47"
+  process $proc$ls180.v:1760$3601
     assign { } { }
     assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
     sync always
     sync init
       update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
   end
-  attribute \src "ls180.v:1716.11-1716.47"
-  process $proc$ls180.v:1716$3461
+  attribute \src "ls180.v:1761.11-1761.47"
+  process $proc$ls180.v:1761$3602
     assign { } { }
     assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
     sync always
     sync init
       update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
   end
-  attribute \src "ls180.v:1717.11-1717.50"
-  process $proc$ls180.v:1717$3462
+  attribute \src "ls180.v:1762.11-1762.50"
+  process $proc$ls180.v:1762$3603
     assign { } { }
     assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
     sync always
     sync init
       update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
   end
-  attribute \src "ls180.v:172.12-172.53"
-  process $proc$ls180.v:172$2785
-    assign { } { }
-    assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync always
-    sync init
-      update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
-  end
-  attribute \src "ls180.v:173.12-173.71"
-  process $proc$ls180.v:173$2786
+  attribute \src "ls180.v:177.5-177.63"
+  process $proc$ls180.v:177$2921
     assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
+      update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
   end
-  attribute \src "ls180.v:1730.5-1730.36"
-  process $proc$ls180.v:1730$3463
+  attribute \src "ls180.v:1775.5-1775.36"
+  process $proc$ls180.v:1775$3604
     assign { } { }
     assign $1\builder_converter0_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter0_state $1\builder_converter0_state[0:0]
   end
-  attribute \src "ls180.v:1731.5-1731.41"
-  process $proc$ls180.v:1731$3464
+  attribute \src "ls180.v:1776.5-1776.41"
+  process $proc$ls180.v:1776$3605
     assign { } { }
     assign $1\builder_converter0_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
   end
-  attribute \src "ls180.v:1732.5-1732.69"
-  process $proc$ls180.v:1732$3465
+  attribute \src "ls180.v:1777.5-1777.69"
+  process $proc$ls180.v:1777$3606
     assign { } { }
     assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
   end
-  attribute \src "ls180.v:1733.5-1733.72"
-  process $proc$ls180.v:1733$3466
+  attribute \src "ls180.v:1778.5-1778.72"
+  process $proc$ls180.v:1778$3607
     assign { } { }
     assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1734.5-1734.36"
-  process $proc$ls180.v:1734$3467
+  attribute \src "ls180.v:1779.5-1779.36"
+  process $proc$ls180.v:1779$3608
     assign { } { }
     assign $1\builder_converter1_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter1_state $1\builder_converter1_state[0:0]
   end
-  attribute \src "ls180.v:1735.5-1735.41"
-  process $proc$ls180.v:1735$3468
+  attribute \src "ls180.v:178.5-178.63"
+  process $proc$ls180.v:178$2922
+    assign { } { }
+    assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
+  end
+  attribute \src "ls180.v:1780.5-1780.41"
+  process $proc$ls180.v:1780$3609
     assign { } { }
     assign $1\builder_converter1_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
   end
-  attribute \src "ls180.v:1736.5-1736.69"
-  process $proc$ls180.v:1736$3469
+  attribute \src "ls180.v:1781.5-1781.69"
+  process $proc$ls180.v:1781$3610
     assign { } { }
     assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
   end
-  attribute \src "ls180.v:1737.5-1737.72"
-  process $proc$ls180.v:1737$3470
+  attribute \src "ls180.v:1782.5-1782.72"
+  process $proc$ls180.v:1782$3611
     assign { } { }
     assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1738.5-1738.36"
-  process $proc$ls180.v:1738$3471
+  attribute \src "ls180.v:1783.5-1783.36"
+  process $proc$ls180.v:1783$3612
     assign { } { }
     assign $1\builder_converter2_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter2_state $1\builder_converter2_state[0:0]
   end
-  attribute \src "ls180.v:1739.5-1739.41"
-  process $proc$ls180.v:1739$3472
+  attribute \src "ls180.v:1784.5-1784.41"
+  process $proc$ls180.v:1784$3613
     assign { } { }
     assign $1\builder_converter2_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
   end
-  attribute \src "ls180.v:174.12-174.73"
-  process $proc$ls180.v:174$2787
-    assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
-    sync always
-    sync init
-      update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
-  end
-  attribute \src "ls180.v:1740.5-1740.69"
-  process $proc$ls180.v:1740$3473
+  attribute \src "ls180.v:1785.5-1785.69"
+  process $proc$ls180.v:1785$3614
     assign { } { }
     assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
   end
-  attribute \src "ls180.v:1741.5-1741.72"
-  process $proc$ls180.v:1741$3474
+  attribute \src "ls180.v:1786.5-1786.72"
+  process $proc$ls180.v:1786$3615
     assign { } { }
     assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1742.11-1742.41"
-  process $proc$ls180.v:1742$3475
+  attribute \src "ls180.v:1787.11-1787.41"
+  process $proc$ls180.v:1787$3616
     assign { } { }
     assign $1\builder_refresher_state[1:0] 2'00
     sync always
     sync init
       update \builder_refresher_state $1\builder_refresher_state[1:0]
   end
-  attribute \src "ls180.v:1743.11-1743.46"
-  process $proc$ls180.v:1743$3476
+  attribute \src "ls180.v:1788.11-1788.46"
+  process $proc$ls180.v:1788$3617
     assign { } { }
     assign $1\builder_refresher_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
   end
-  attribute \src "ls180.v:1744.11-1744.44"
-  process $proc$ls180.v:1744$3477
+  attribute \src "ls180.v:1789.11-1789.44"
+  process $proc$ls180.v:1789$3618
     assign { } { }
     assign $1\builder_bankmachine0_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
   end
-  attribute \src "ls180.v:1745.11-1745.49"
-  process $proc$ls180.v:1745$3478
+  attribute \src "ls180.v:1790.11-1790.49"
+  process $proc$ls180.v:1790$3619
     assign { } { }
     assign $1\builder_bankmachine0_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
   end
-  attribute \src "ls180.v:1746.11-1746.44"
-  process $proc$ls180.v:1746$3479
+  attribute \src "ls180.v:1791.11-1791.44"
+  process $proc$ls180.v:1791$3620
     assign { } { }
     assign $1\builder_bankmachine1_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
   end
-  attribute \src "ls180.v:1747.11-1747.49"
-  process $proc$ls180.v:1747$3480
+  attribute \src "ls180.v:1792.11-1792.49"
+  process $proc$ls180.v:1792$3621
     assign { } { }
     assign $1\builder_bankmachine1_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
   end
-  attribute \src "ls180.v:1748.11-1748.44"
-  process $proc$ls180.v:1748$3481
+  attribute \src "ls180.v:1793.11-1793.44"
+  process $proc$ls180.v:1793$3622
     assign { } { }
     assign $1\builder_bankmachine2_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
   end
-  attribute \src "ls180.v:1749.11-1749.49"
-  process $proc$ls180.v:1749$3482
+  attribute \src "ls180.v:1794.11-1794.49"
+  process $proc$ls180.v:1794$3623
     assign { } { }
     assign $1\builder_bankmachine2_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
   end
-  attribute \src "ls180.v:1750.11-1750.44"
-  process $proc$ls180.v:1750$3483
+  attribute \src "ls180.v:1795.11-1795.44"
+  process $proc$ls180.v:1795$3624
     assign { } { }
     assign $1\builder_bankmachine3_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
   end
-  attribute \src "ls180.v:1751.11-1751.49"
-  process $proc$ls180.v:1751$3484
+  attribute \src "ls180.v:1796.11-1796.49"
+  process $proc$ls180.v:1796$3625
     assign { } { }
     assign $1\builder_bankmachine3_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
   end
-  attribute \src "ls180.v:1752.11-1752.43"
-  process $proc$ls180.v:1752$3485
+  attribute \src "ls180.v:1797.11-1797.43"
+  process $proc$ls180.v:1797$3626
     assign { } { }
     assign $1\builder_multiplexer_state[2:0] 3'000
     sync always
     sync init
       update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
   end
-  attribute \src "ls180.v:1753.11-1753.48"
-  process $proc$ls180.v:1753$3486
+  attribute \src "ls180.v:1798.11-1798.48"
+  process $proc$ls180.v:1798$3627
     assign { } { }
     assign $1\builder_multiplexer_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
   end
-  attribute \src "ls180.v:176.11-176.69"
-  process $proc$ls180.v:176$2788
+  attribute \src "ls180.v:180.5-180.62"
+  process $proc$ls180.v:180$2923
     assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
+    assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
+      update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
   end
-  attribute \src "ls180.v:1766.5-1766.27"
-  process $proc$ls180.v:1766$3487
+  attribute \src "ls180.v:181.11-181.69"
+  process $proc$ls180.v:181$2924
+    assign { } { }
+    assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
+    sync always
+      update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
+    sync init
+  end
+  attribute \src "ls180.v:1811.5-1811.27"
+  process $proc$ls180.v:1811$3628
     assign { } { }
     assign $0\builder_locked0[0:0] 1'0
     sync always
       update \builder_locked0 $0\builder_locked0[0:0]
     sync init
   end
-  attribute \src "ls180.v:1767.5-1767.27"
-  process $proc$ls180.v:1767$3488
+  attribute \src "ls180.v:1812.5-1812.27"
+  process $proc$ls180.v:1812$3629
     assign { } { }
     assign $0\builder_locked1[0:0] 1'0
     sync always
       update \builder_locked1 $0\builder_locked1[0:0]
     sync init
   end
-  attribute \src "ls180.v:1768.5-1768.27"
-  process $proc$ls180.v:1768$3489
+  attribute \src "ls180.v:1813.5-1813.27"
+  process $proc$ls180.v:1813$3630
     assign { } { }
     assign $0\builder_locked2[0:0] 1'0
     sync always
       update \builder_locked2 $0\builder_locked2[0:0]
     sync init
   end
-  attribute \src "ls180.v:1769.5-1769.27"
-  process $proc$ls180.v:1769$3490
+  attribute \src "ls180.v:1814.5-1814.27"
+  process $proc$ls180.v:1814$3631
     assign { } { }
     assign $0\builder_locked3[0:0] 1'0
     sync always
       update \builder_locked3 $0\builder_locked3[0:0]
     sync init
   end
-  attribute \src "ls180.v:177.5-177.63"
-  process $proc$ls180.v:177$2789
-    assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
-  end
-  attribute \src "ls180.v:1770.5-1770.42"
-  process $proc$ls180.v:1770$3491
+  attribute \src "ls180.v:1815.5-1815.42"
+  process $proc$ls180.v:1815$3632
     assign { } { }
     assign $1\builder_new_master_wdata_ready[0:0] 1'0
     sync always
     sync init
       update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:1771.5-1771.43"
-  process $proc$ls180.v:1771$3492
+  attribute \src "ls180.v:1816.5-1816.43"
+  process $proc$ls180.v:1816$3633
     assign { } { }
     assign $1\builder_new_master_rdata_valid0[0:0] 1'0
     sync always
     sync init
       update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
   end
-  attribute \src "ls180.v:1772.5-1772.43"
-  process $proc$ls180.v:1772$3493
+  attribute \src "ls180.v:1817.5-1817.43"
+  process $proc$ls180.v:1817$3634
     assign { } { }
     assign $1\builder_new_master_rdata_valid1[0:0] 1'0
     sync always
     sync init
       update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
   end
-  attribute \src "ls180.v:1773.5-1773.43"
-  process $proc$ls180.v:1773$3494
+  attribute \src "ls180.v:1818.5-1818.43"
+  process $proc$ls180.v:1818$3635
     assign { } { }
     assign $1\builder_new_master_rdata_valid2[0:0] 1'0
     sync always
     sync init
       update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
   end
-  attribute \src "ls180.v:1774.5-1774.43"
-  process $proc$ls180.v:1774$3495
+  attribute \src "ls180.v:1819.5-1819.43"
+  process $proc$ls180.v:1819$3636
     assign { } { }
     assign $1\builder_new_master_rdata_valid3[0:0] 1'0
     sync always
     sync init
       update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
   end
-  attribute \src "ls180.v:1775.5-1775.35"
-  process $proc$ls180.v:1775$3496
+  attribute \src "ls180.v:182.11-182.69"
+  process $proc$ls180.v:182$2925
+    assign { } { }
+    assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
+    sync always
+      update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
+    sync init
+  end
+  attribute \src "ls180.v:1820.5-1820.35"
+  process $proc$ls180.v:1820$3637
     assign { } { }
     assign $1\builder_converter_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter_state $1\builder_converter_state[0:0]
   end
-  attribute \src "ls180.v:1776.5-1776.40"
-  process $proc$ls180.v:1776$3497
+  attribute \src "ls180.v:1821.5-1821.40"
+  process $proc$ls180.v:1821$3638
     assign { } { }
     assign $1\builder_converter_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_converter_next_state $1\builder_converter_next_state[0:0]
   end
-  attribute \src "ls180.v:1777.5-1777.55"
-  process $proc$ls180.v:1777$3498
+  attribute \src "ls180.v:1822.5-1822.55"
+  process $proc$ls180.v:1822$3639
     assign { } { }
     assign $1\main_converter_counter_converter_next_value[0:0] 1'0
     sync always
     sync init
       update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
   end
-  attribute \src "ls180.v:1778.5-1778.58"
-  process $proc$ls180.v:1778$3499
+  attribute \src "ls180.v:1823.5-1823.58"
+  process $proc$ls180.v:1823$3640
     assign { } { }
     assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1779.11-1779.42"
-  process $proc$ls180.v:1779$3500
+  attribute \src "ls180.v:1824.11-1824.42"
+  process $proc$ls180.v:1824$3641
     assign { } { }
     assign $1\builder_spimaster0_state[1:0] 2'00
     sync always
     sync init
       update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
   end
-  attribute \src "ls180.v:178.5-178.63"
-  process $proc$ls180.v:178$2790
-    assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
-  end
-  attribute \src "ls180.v:1780.11-1780.47"
-  process $proc$ls180.v:1780$3501
+  attribute \src "ls180.v:1825.11-1825.47"
+  process $proc$ls180.v:1825$3642
     assign { } { }
     assign $1\builder_spimaster0_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
   end
-  attribute \src "ls180.v:1781.11-1781.62"
-  process $proc$ls180.v:1781$3502
+  attribute \src "ls180.v:1826.11-1826.62"
+  process $proc$ls180.v:1826$3643
     assign { } { }
     assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
     sync always
     sync init
       update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
   end
-  attribute \src "ls180.v:1782.5-1782.59"
-  process $proc$ls180.v:1782$3503
+  attribute \src "ls180.v:1827.5-1827.59"
+  process $proc$ls180.v:1827$3644
     assign { } { }
     assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1783.11-1783.42"
-  process $proc$ls180.v:1783$3504
+  attribute \src "ls180.v:1828.11-1828.42"
+  process $proc$ls180.v:1828$3645
     assign { } { }
     assign $1\builder_spimaster1_state[1:0] 2'00
     sync always
     sync init
       update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
   end
-  attribute \src "ls180.v:1784.11-1784.47"
-  process $proc$ls180.v:1784$3505
+  attribute \src "ls180.v:1829.11-1829.47"
+  process $proc$ls180.v:1829$3646
     assign { } { }
     assign $1\builder_spimaster1_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
   end
-  attribute \src "ls180.v:1785.11-1785.60"
-  process $proc$ls180.v:1785$3506
+  attribute \src "ls180.v:1830.11-1830.60"
+  process $proc$ls180.v:1830$3647
     assign { } { }
     assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
     sync always
     sync init
       update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
   end
-  attribute \src "ls180.v:1786.5-1786.57"
-  process $proc$ls180.v:1786$3507
+  attribute \src "ls180.v:1831.5-1831.57"
+  process $proc$ls180.v:1831$3648
     assign { } { }
     assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1787.5-1787.41"
-  process $proc$ls180.v:1787$3508
+  attribute \src "ls180.v:1832.5-1832.41"
+  process $proc$ls180.v:1832$3649
     assign { } { }
     assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
   end
-  attribute \src "ls180.v:1788.5-1788.46"
-  process $proc$ls180.v:1788$3509
+  attribute \src "ls180.v:1833.5-1833.46"
+  process $proc$ls180.v:1833$3650
     assign { } { }
     assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
   end
-  attribute \src "ls180.v:1789.11-1789.66"
-  process $proc$ls180.v:1789$3510
+  attribute \src "ls180.v:1834.11-1834.66"
+  process $proc$ls180.v:1834$3651
     assign { } { }
     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
   end
-  attribute \src "ls180.v:1790.5-1790.63"
-  process $proc$ls180.v:1790$3511
+  attribute \src "ls180.v:1835.5-1835.63"
+  process $proc$ls180.v:1835$3652
     assign { } { }
     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1791.11-1791.47"
-  process $proc$ls180.v:1791$3512
+  attribute \src "ls180.v:1836.11-1836.47"
+  process $proc$ls180.v:1836$3653
     assign { } { }
     assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
   end
-  attribute \src "ls180.v:1792.11-1792.52"
-  process $proc$ls180.v:1792$3513
+  attribute \src "ls180.v:1837.11-1837.52"
+  process $proc$ls180.v:1837$3654
     assign { } { }
     assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
   end
-  attribute \src "ls180.v:1793.11-1793.66"
-  process $proc$ls180.v:1793$3514
+  attribute \src "ls180.v:1838.11-1838.66"
+  process $proc$ls180.v:1838$3655
     assign { } { }
     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
   end
-  attribute \src "ls180.v:1794.5-1794.63"
-  process $proc$ls180.v:1794$3515
+  attribute \src "ls180.v:1839.5-1839.63"
+  process $proc$ls180.v:1839$3656
     assign { } { }
     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1795.11-1795.47"
-  process $proc$ls180.v:1795$3516
+  attribute \src "ls180.v:184.5-184.44"
+  process $proc$ls180.v:184$2926
+    assign { } { }
+    assign $1\main_libresocsim_converter1_skip[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
+  end
+  attribute \src "ls180.v:1840.11-1840.47"
+  process $proc$ls180.v:1840$3657
     assign { } { }
     assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
   end
-  attribute \src "ls180.v:1796.11-1796.52"
-  process $proc$ls180.v:1796$3517
+  attribute \src "ls180.v:1841.11-1841.52"
+  process $proc$ls180.v:1841$3658
     assign { } { }
     assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
   end
-  attribute \src "ls180.v:1797.11-1797.67"
-  process $proc$ls180.v:1797$3518
+  attribute \src "ls180.v:1842.11-1842.67"
+  process $proc$ls180.v:1842$3659
     assign { } { }
     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
   end
-  attribute \src "ls180.v:1798.5-1798.64"
-  process $proc$ls180.v:1798$3519
+  attribute \src "ls180.v:1843.5-1843.64"
+  process $proc$ls180.v:1843$3660
     assign { } { }
     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:1799.12-1799.71"
-  process $proc$ls180.v:1799$3520
+  attribute \src "ls180.v:1844.12-1844.71"
+  process $proc$ls180.v:1844$3661
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
     sync always
     sync init
       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
   end
-  attribute \src "ls180.v:180.5-180.62"
-  process $proc$ls180.v:180$2791
-    assign { } { }
-    assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
-  end
-  attribute \src "ls180.v:1800.5-1800.66"
-  process $proc$ls180.v:1800$3521
+  attribute \src "ls180.v:1845.5-1845.66"
+  process $proc$ls180.v:1845$3662
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:1801.5-1801.66"
-  process $proc$ls180.v:1801$3522
+  attribute \src "ls180.v:1846.5-1846.66"
+  process $proc$ls180.v:1846$3663
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
   end
-  attribute \src "ls180.v:1802.5-1802.69"
-  process $proc$ls180.v:1802$3523
+  attribute \src "ls180.v:1847.5-1847.69"
+  process $proc$ls180.v:1847$3664
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:1803.5-1803.41"
-  process $proc$ls180.v:1803$3524
+  attribute \src "ls180.v:1848.5-1848.41"
+  process $proc$ls180.v:1848$3665
     assign { } { }
     assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
   end
-  attribute \src "ls180.v:1804.5-1804.46"
-  process $proc$ls180.v:1804$3525
+  attribute \src "ls180.v:1849.5-1849.46"
+  process $proc$ls180.v:1849$3666
     assign { } { }
     assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
   end
-  attribute \src "ls180.v:1805.5-1805.66"
-  process $proc$ls180.v:1805$3526
+  attribute \src "ls180.v:185.5-185.47"
+  process $proc$ls180.v:185$2927
+    assign { } { }
+    assign $1\main_libresocsim_converter1_counter[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
+  end
+  attribute \src "ls180.v:1850.5-1850.66"
+  process $proc$ls180.v:1850$3667
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
   end
-  attribute \src "ls180.v:1806.5-1806.69"
-  process $proc$ls180.v:1806$3527
+  attribute \src "ls180.v:1851.5-1851.69"
+  process $proc$ls180.v:1851$3668
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1807.11-1807.41"
-  process $proc$ls180.v:1807$3528
+  attribute \src "ls180.v:1852.11-1852.41"
+  process $proc$ls180.v:1852$3669
     assign { } { }
     assign $1\builder_sdphy_fsm_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
   end
-  attribute \src "ls180.v:1808.11-1808.46"
-  process $proc$ls180.v:1808$3529
+  attribute \src "ls180.v:1853.11-1853.46"
+  process $proc$ls180.v:1853$3670
     assign { } { }
     assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
   end
-  attribute \src "ls180.v:1809.11-1809.61"
-  process $proc$ls180.v:1809$3530
+  attribute \src "ls180.v:1854.11-1854.61"
+  process $proc$ls180.v:1854$3671
     assign { } { }
     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
     sync always
     sync init
       update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
   end
-  attribute \src "ls180.v:181.11-181.69"
-  process $proc$ls180.v:181$2792
-    assign { } { }
-    assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
-    sync always
-      update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
-    sync init
-  end
-  attribute \src "ls180.v:1810.5-1810.58"
-  process $proc$ls180.v:1810$3531
+  attribute \src "ls180.v:1855.5-1855.58"
+  process $proc$ls180.v:1855$3672
     assign { } { }
     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1811.11-1811.48"
-  process $proc$ls180.v:1811$3532
+  attribute \src "ls180.v:1856.11-1856.48"
+  process $proc$ls180.v:1856$3673
     assign { } { }
     assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
   end
-  attribute \src "ls180.v:1812.11-1812.53"
-  process $proc$ls180.v:1812$3533
+  attribute \src "ls180.v:1857.11-1857.53"
+  process $proc$ls180.v:1857$3674
     assign { } { }
     assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
   end
-  attribute \src "ls180.v:1813.11-1813.70"
-  process $proc$ls180.v:1813$3534
+  attribute \src "ls180.v:1858.11-1858.70"
+  process $proc$ls180.v:1858$3675
     assign { } { }
     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
     sync always
     sync init
       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
   end
-  attribute \src "ls180.v:1814.5-1814.66"
-  process $proc$ls180.v:1814$3535
+  attribute \src "ls180.v:1859.5-1859.66"
+  process $proc$ls180.v:1859$3676
     assign { } { }
     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:1815.12-1815.73"
-  process $proc$ls180.v:1815$3536
+  attribute \src "ls180.v:1860.12-1860.73"
+  process $proc$ls180.v:1860$3677
     assign { } { }
     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
     sync always
     sync init
       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
   end
-  attribute \src "ls180.v:1816.5-1816.68"
-  process $proc$ls180.v:1816$3537
+  attribute \src "ls180.v:1861.5-1861.68"
+  process $proc$ls180.v:1861$3678
     assign { } { }
     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:1817.5-1817.69"
-  process $proc$ls180.v:1817$3538
+  attribute \src "ls180.v:1862.5-1862.69"
+  process $proc$ls180.v:1862$3679
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
   end
-  attribute \src "ls180.v:1818.5-1818.72"
-  process $proc$ls180.v:1818$3539
+  attribute \src "ls180.v:1863.5-1863.72"
+  process $proc$ls180.v:1863$3680
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:1819.5-1819.52"
-  process $proc$ls180.v:1819$3540
+  attribute \src "ls180.v:1864.5-1864.52"
+  process $proc$ls180.v:1864$3681
     assign { } { }
     assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
   end
-  attribute \src "ls180.v:182.11-182.69"
-  process $proc$ls180.v:182$2793
-    assign { } { }
-    assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
-    sync always
-      update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
-    sync init
-  end
-  attribute \src "ls180.v:1820.5-1820.57"
-  process $proc$ls180.v:1820$3541
+  attribute \src "ls180.v:1865.5-1865.57"
+  process $proc$ls180.v:1865$3682
     assign { } { }
     assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
   end
-  attribute \src "ls180.v:1821.12-1821.93"
-  process $proc$ls180.v:1821$3542
+  attribute \src "ls180.v:1866.12-1866.93"
+  process $proc$ls180.v:1866$3683
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
   end
-  attribute \src "ls180.v:1822.5-1822.88"
-  process $proc$ls180.v:1822$3543
+  attribute \src "ls180.v:1867.5-1867.88"
+  process $proc$ls180.v:1867$3684
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:1823.12-1823.93"
-  process $proc$ls180.v:1823$3544
+  attribute \src "ls180.v:1868.12-1868.93"
+  process $proc$ls180.v:1868$3685
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
   end
-  attribute \src "ls180.v:1824.5-1824.88"
-  process $proc$ls180.v:1824$3545
+  attribute \src "ls180.v:1869.5-1869.88"
+  process $proc$ls180.v:1869$3686
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:1825.12-1825.93"
-  process $proc$ls180.v:1825$3546
+  attribute \src "ls180.v:187.12-187.53"
+  process $proc$ls180.v:187$2928
+    assign { } { }
+    assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync always
+    sync init
+      update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
+  end
+  attribute \src "ls180.v:1870.12-1870.93"
+  process $proc$ls180.v:1870$3687
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
   end
-  attribute \src "ls180.v:1826.5-1826.88"
-  process $proc$ls180.v:1826$3547
+  attribute \src "ls180.v:1871.5-1871.88"
+  process $proc$ls180.v:1871$3688
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:1827.12-1827.93"
-  process $proc$ls180.v:1827$3548
+  attribute \src "ls180.v:1872.12-1872.93"
+  process $proc$ls180.v:1872$3689
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
   end
-  attribute \src "ls180.v:1828.5-1828.88"
-  process $proc$ls180.v:1828$3549
+  attribute \src "ls180.v:1873.5-1873.88"
+  process $proc$ls180.v:1873$3690
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
   end
-  attribute \src "ls180.v:1829.11-1829.87"
-  process $proc$ls180.v:1829$3550
+  attribute \src "ls180.v:1874.11-1874.87"
+  process $proc$ls180.v:1874$3691
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
   end
-  attribute \src "ls180.v:1830.5-1830.84"
-  process $proc$ls180.v:1830$3551
+  attribute \src "ls180.v:1875.5-1875.84"
+  process $proc$ls180.v:1875$3692
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
   end
-  attribute \src "ls180.v:1831.11-1831.42"
-  process $proc$ls180.v:1831$3552
+  attribute \src "ls180.v:1876.11-1876.42"
+  process $proc$ls180.v:1876$3693
     assign { } { }
     assign $1\builder_sdcore_fsm_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
   end
-  attribute \src "ls180.v:1832.11-1832.47"
-  process $proc$ls180.v:1832$3553
+  attribute \src "ls180.v:1877.11-1877.47"
+  process $proc$ls180.v:1877$3694
     assign { } { }
     assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
     sync always
     sync init
       update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
   end
-  attribute \src "ls180.v:1833.5-1833.55"
-  process $proc$ls180.v:1833$3554
+  attribute \src "ls180.v:1878.5-1878.55"
+  process $proc$ls180.v:1878$3695
     assign { } { }
     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
   end
-  attribute \src "ls180.v:1834.5-1834.58"
-  process $proc$ls180.v:1834$3555
+  attribute \src "ls180.v:1879.5-1879.58"
+  process $proc$ls180.v:1879$3696
     assign { } { }
     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:1835.5-1835.56"
-  process $proc$ls180.v:1835$3556
+  attribute \src "ls180.v:188.12-188.71"
+  process $proc$ls180.v:188$2929
+    assign { } { }
+    assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    sync always
+    sync init
+      update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
+  end
+  attribute \src "ls180.v:1880.5-1880.56"
+  process $proc$ls180.v:1880$3697
     assign { } { }
     assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
   end
-  attribute \src "ls180.v:1836.5-1836.59"
-  process $proc$ls180.v:1836$3557
+  attribute \src "ls180.v:1881.5-1881.59"
+  process $proc$ls180.v:1881$3698
     assign { } { }
     assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:1837.11-1837.62"
-  process $proc$ls180.v:1837$3558
+  attribute \src "ls180.v:1882.11-1882.62"
+  process $proc$ls180.v:1882$3699
     assign { } { }
     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
     sync always
     sync init
       update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
   end
-  attribute \src "ls180.v:1838.5-1838.59"
-  process $proc$ls180.v:1838$3559
+  attribute \src "ls180.v:1883.5-1883.59"
+  process $proc$ls180.v:1883$3700
     assign { } { }
     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:1839.12-1839.65"
-  process $proc$ls180.v:1839$3560
+  attribute \src "ls180.v:1884.12-1884.65"
+  process $proc$ls180.v:1884$3701
     assign { } { }
     assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
     sync always
     sync init
       update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
   end
-  attribute \src "ls180.v:184.5-184.44"
-  process $proc$ls180.v:184$2794
-    assign { } { }
-    assign $1\main_libresocsim_converter1_skip[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
-  end
-  attribute \src "ls180.v:1840.5-1840.60"
-  process $proc$ls180.v:1840$3561
+  attribute \src "ls180.v:1885.5-1885.60"
+  process $proc$ls180.v:1885$3702
     assign { } { }
     assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
   end
-  attribute \src "ls180.v:1841.5-1841.56"
-  process $proc$ls180.v:1841$3562
+  attribute \src "ls180.v:1886.5-1886.56"
+  process $proc$ls180.v:1886$3703
     assign { } { }
     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
   end
-  attribute \src "ls180.v:1842.5-1842.59"
-  process $proc$ls180.v:1842$3563
+  attribute \src "ls180.v:1887.5-1887.59"
+  process $proc$ls180.v:1887$3704
     assign { } { }
     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
   end
-  attribute \src "ls180.v:1843.5-1843.58"
-  process $proc$ls180.v:1843$3564
+  attribute \src "ls180.v:1888.5-1888.58"
+  process $proc$ls180.v:1888$3705
     assign { } { }
     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
   end
-  attribute \src "ls180.v:1844.5-1844.61"
-  process $proc$ls180.v:1844$3565
+  attribute \src "ls180.v:1889.5-1889.61"
+  process $proc$ls180.v:1889$3706
     assign { } { }
     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
   end
-  attribute \src "ls180.v:1845.5-1845.57"
-  process $proc$ls180.v:1845$3566
+  attribute \src "ls180.v:189.12-189.73"
+  process $proc$ls180.v:189$2930
+    assign { } { }
+    assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
+    sync always
+    sync init
+      update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
+  end
+  attribute \src "ls180.v:1890.5-1890.57"
+  process $proc$ls180.v:1890$3707
     assign { } { }
     assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
   end
-  attribute \src "ls180.v:1846.5-1846.60"
-  process $proc$ls180.v:1846$3567
+  attribute \src "ls180.v:1891.5-1891.60"
+  process $proc$ls180.v:1891$3708
     assign { } { }
     assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
   end
-  attribute \src "ls180.v:1847.5-1847.59"
-  process $proc$ls180.v:1847$3568
+  attribute \src "ls180.v:1892.5-1892.59"
+  process $proc$ls180.v:1892$3709
     assign { } { }
     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
   end
-  attribute \src "ls180.v:1848.5-1848.62"
-  process $proc$ls180.v:1848$3569
+  attribute \src "ls180.v:1893.5-1893.62"
+  process $proc$ls180.v:1893$3710
     assign { } { }
     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
   end
-  attribute \src "ls180.v:1849.13-1849.76"
-  process $proc$ls180.v:1849$3570
+  attribute \src "ls180.v:1894.13-1894.76"
+  process $proc$ls180.v:1894$3711
     assign { } { }
     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
   end
-  attribute \src "ls180.v:185.5-185.47"
-  process $proc$ls180.v:185$2795
-    assign { } { }
-    assign $1\main_libresocsim_converter1_counter[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
-  end
-  attribute \src "ls180.v:1850.5-1850.69"
-  process $proc$ls180.v:1850$3571
+  attribute \src "ls180.v:1895.5-1895.69"
+  process $proc$ls180.v:1895$3712
     assign { } { }
     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
   end
-  attribute \src "ls180.v:1851.11-1851.46"
-  process $proc$ls180.v:1851$3572
+  attribute \src "ls180.v:1896.11-1896.46"
+  process $proc$ls180.v:1896$3713
     assign { } { }
     assign $1\builder_sdblock2memdma_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
   end
-  attribute \src "ls180.v:1852.11-1852.51"
-  process $proc$ls180.v:1852$3573
+  attribute \src "ls180.v:1897.11-1897.51"
+  process $proc$ls180.v:1897$3714
     assign { } { }
     assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
   end
-  attribute \src "ls180.v:1853.12-1853.87"
-  process $proc$ls180.v:1853$3574
+  attribute \src "ls180.v:1898.12-1898.87"
+  process $proc$ls180.v:1898$3715
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
   end
-  attribute \src "ls180.v:1854.5-1854.82"
-  process $proc$ls180.v:1854$3575
+  attribute \src "ls180.v:1899.5-1899.82"
+  process $proc$ls180.v:1899$3716
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1855.5-1855.44"
-  process $proc$ls180.v:1855$3576
+  attribute \src "ls180.v:1900.5-1900.44"
+  process $proc$ls180.v:1900$3717
     assign { } { }
     assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
   end
-  attribute \src "ls180.v:1856.5-1856.49"
-  process $proc$ls180.v:1856$3577
+  attribute \src "ls180.v:1901.5-1901.49"
+  process $proc$ls180.v:1901$3718
     assign { } { }
     assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
     sync always
     sync init
       update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
   end
-  attribute \src "ls180.v:1857.12-1857.75"
-  process $proc$ls180.v:1857$3578
+  attribute \src "ls180.v:1902.12-1902.75"
+  process $proc$ls180.v:1902$3719
     assign { } { }
     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
   end
-  attribute \src "ls180.v:1858.5-1858.70"
-  process $proc$ls180.v:1858$3579
+  attribute \src "ls180.v:1903.5-1903.70"
+  process $proc$ls180.v:1903$3720
     assign { } { }
     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1859.11-1859.60"
-  process $proc$ls180.v:1859$3580
+  attribute \src "ls180.v:1904.11-1904.60"
+  process $proc$ls180.v:1904$3721
     assign { } { }
     assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
   end
-  attribute \src "ls180.v:1860.11-1860.65"
-  process $proc$ls180.v:1860$3581
+  attribute \src "ls180.v:1905.11-1905.65"
+  process $proc$ls180.v:1905$3722
     assign { } { }
     assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
   end
-  attribute \src "ls180.v:1861.12-1861.87"
-  process $proc$ls180.v:1861$3582
+  attribute \src "ls180.v:1906.12-1906.87"
+  process $proc$ls180.v:1906$3723
     assign { } { }
     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
     sync always
     sync init
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
   end
-  attribute \src "ls180.v:1862.5-1862.82"
-  process $proc$ls180.v:1862$3583
+  attribute \src "ls180.v:1907.5-1907.82"
+  process $proc$ls180.v:1907$3724
     assign { } { }
     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1863.12-1863.43"
-  process $proc$ls180.v:1863$3584
+  attribute \src "ls180.v:1908.12-1908.43"
+  process $proc$ls180.v:1908$3725
     assign { } { }
     assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
     sync always
     sync init
       update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
   end
-  attribute \src "ls180.v:1864.5-1864.34"
-  process $proc$ls180.v:1864$3585
+  attribute \src "ls180.v:1909.5-1909.34"
+  process $proc$ls180.v:1909$3726
     assign { } { }
     assign $1\builder_libresocsim_we[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
   end
-  attribute \src "ls180.v:1865.11-1865.43"
-  process $proc$ls180.v:1865$3586
+  attribute \src "ls180.v:191.11-191.69"
+  process $proc$ls180.v:191$2931
     assign { } { }
-    assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
+    assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
     sync always
     sync init
-      update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
+      update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
   end
-  attribute \src "ls180.v:1869.12-1869.54"
-  process $proc$ls180.v:1869$3587
+  attribute \src "ls180.v:1910.11-1910.43"
+  process $proc$ls180.v:1910$3727
     assign { } { }
-    assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
+    assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
     sync always
     sync init
-      update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
+      update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
   end
-  attribute \src "ls180.v:187.12-187.53"
-  process $proc$ls180.v:187$2796
+  attribute \src "ls180.v:1914.12-1914.54"
+  process $proc$ls180.v:1914$3728
     assign { } { }
-    assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
     sync always
     sync init
-      update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
+      update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
   end
-  attribute \src "ls180.v:1873.5-1873.44"
-  process $proc$ls180.v:1873$3588
+  attribute \src "ls180.v:1918.5-1918.44"
+  process $proc$ls180.v:1918$3729
     assign { } { }
     assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
   end
-  attribute \src "ls180.v:1877.5-1877.44"
-  process $proc$ls180.v:1877$3589
+  attribute \src "ls180.v:192.5-192.63"
+  process $proc$ls180.v:192$2932
     assign { } { }
-    assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
+    assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
     sync always
-      update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0]
     sync init
+      update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
   end
-  attribute \src "ls180.v:188.12-188.71"
-  process $proc$ls180.v:188$2797
+  attribute \src "ls180.v:1922.5-1922.44"
+  process $proc$ls180.v:1922$3730
     assign { } { }
-    assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
     sync always
+      update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0]
     sync init
-      update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
   end
-  attribute \src "ls180.v:1880.12-1880.40"
-  process $proc$ls180.v:1880$3590
+  attribute \src "ls180.v:1925.12-1925.40"
+  process $proc$ls180.v:1925$3731
     assign { } { }
     assign $1\builder_shared_dat_r[31:0] 0
     sync always
     sync init
       update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
   end
-  attribute \src "ls180.v:1884.5-1884.30"
-  process $proc$ls180.v:1884$3591
+  attribute \src "ls180.v:1929.5-1929.30"
+  process $proc$ls180.v:1929$3732
     assign { } { }
     assign $1\builder_shared_ack[0:0] 1'0
     sync always
     sync init
       update \builder_shared_ack $1\builder_shared_ack[0:0]
   end
-  attribute \src "ls180.v:189.12-189.73"
-  process $proc$ls180.v:189$2798
+  attribute \src "ls180.v:193.5-193.63"
+  process $proc$ls180.v:193$2933
     assign { } { }
-    assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
+    assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
+      update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
   end
-  attribute \src "ls180.v:1890.11-1890.31"
-  process $proc$ls180.v:1890$3592
+  attribute \src "ls180.v:1935.11-1935.31"
+  process $proc$ls180.v:1935$3733
     assign { } { }
     assign $1\builder_grant[2:0] 3'000
     sync always
     sync init
       update \builder_grant $1\builder_grant[2:0]
   end
-  attribute \src "ls180.v:1891.11-1891.35"
-  process $proc$ls180.v:1891$3593
+  attribute \src "ls180.v:1936.11-1936.35"
+  process $proc$ls180.v:1936$3734
     assign { } { }
-    assign $1\builder_slave_sel[4:0] 5'00000
+    assign $1\builder_slave_sel[7:0] 8'00000000
     sync always
     sync init
-      update \builder_slave_sel $1\builder_slave_sel[4:0]
+      update \builder_slave_sel $1\builder_slave_sel[7:0]
   end
-  attribute \src "ls180.v:1892.11-1892.37"
-  process $proc$ls180.v:1892$3594
+  attribute \src "ls180.v:1937.11-1937.37"
+  process $proc$ls180.v:1937$3735
     assign { } { }
-    assign $1\builder_slave_sel_r[4:0] 5'00000
+    assign $1\builder_slave_sel_r[7:0] 8'00000000
     sync always
     sync init
-      update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
+      update \builder_slave_sel_r $1\builder_slave_sel_r[7:0]
   end
-  attribute \src "ls180.v:1893.5-1893.25"
-  process $proc$ls180.v:1893$3595
+  attribute \src "ls180.v:1938.5-1938.25"
+  process $proc$ls180.v:1938$3736
     assign { } { }
     assign $1\builder_error[0:0] 1'0
     sync always
     sync init
       update \builder_error $1\builder_error[0:0]
   end
-  attribute \src "ls180.v:1896.12-1896.39"
-  process $proc$ls180.v:1896$3596
+  attribute \src "ls180.v:1941.12-1941.39"
+  process $proc$ls180.v:1941$3737
     assign { } { }
     assign $1\builder_count[19:0] 20'11110100001001000000
     sync always
     sync init
       update \builder_count $1\builder_count[19:0]
   end
-  attribute \src "ls180.v:1900.11-1900.51"
-  process $proc$ls180.v:1900$3597
+  attribute \src "ls180.v:1945.11-1945.51"
+  process $proc$ls180.v:1945$3738
     assign { } { }
     assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:191.11-191.69"
-  process $proc$ls180.v:191$2799
-    assign { } { }
-    assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
-    sync always
-    sync init
-      update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
-  end
-  attribute \src "ls180.v:192.5-192.63"
-  process $proc$ls180.v:192$2800
-    assign { } { }
-    assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
-  end
-  attribute \src "ls180.v:193.5-193.63"
-  process $proc$ls180.v:193$2801
-    assign { } { }
-    assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
-  end
-  attribute \src "ls180.v:1941.11-1941.51"
-  process $proc$ls180.v:1941$3598
-    assign { } { }
-    assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
-    sync always
-    sync init
-      update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
-  end
   attribute \src "ls180.v:195.5-195.62"
-  process $proc$ls180.v:195$2802
+  process $proc$ls180.v:195$2934
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
     sync always
@@ -266996,7 +268669,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
   end
   attribute \src "ls180.v:196.11-196.69"
-  process $proc$ls180.v:196$2803
+  process $proc$ls180.v:196$2935
     assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
     sync always
@@ -267004,31 +268677,23 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:197.11-197.69"
-  process $proc$ls180.v:197$2804
+  process $proc$ls180.v:197$2936
     assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
     sync always
       update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0]
     sync init
   end
-  attribute \src "ls180.v:1970.11-1970.51"
-  process $proc$ls180.v:1970$3599
-    assign { } { }
-    assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
-    sync always
-    sync init
-      update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
-  end
-  attribute \src "ls180.v:1983.11-1983.51"
-  process $proc$ls180.v:1983$3600
+  attribute \src "ls180.v:1986.11-1986.51"
+  process $proc$ls180.v:1986$3739
     assign { } { }
-    assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
+      update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:199.5-199.44"
-  process $proc$ls180.v:199$2805
+  process $proc$ls180.v:199$2937
     assign { } { }
     assign $1\main_libresocsim_converter2_skip[0:0] 1'0
     sync always
@@ -267036,71 +268701,87 @@ module \ls180
       update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
   end
   attribute \src "ls180.v:200.5-200.47"
-  process $proc$ls180.v:200$2806
+  process $proc$ls180.v:200$2938
     assign { } { }
     assign $1\main_libresocsim_converter2_counter[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
   end
+  attribute \src "ls180.v:2015.11-2015.51"
+  process $proc$ls180.v:2015$3740
+    assign { } { }
+    assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
+    sync always
+    sync init
+      update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
+  end
   attribute \src "ls180.v:202.12-202.53"
-  process $proc$ls180.v:202$2807
+  process $proc$ls180.v:202$2939
     assign { } { }
     assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
   end
-  attribute \src "ls180.v:2024.11-2024.51"
-  process $proc$ls180.v:2024$3601
+  attribute \src "ls180.v:2028.11-2028.51"
+  process $proc$ls180.v:2028$3741
     assign { } { }
-    assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
+      update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2065.11-2065.51"
-  process $proc$ls180.v:2065$3602
+  attribute \src "ls180.v:2069.11-2069.51"
+  process $proc$ls180.v:2069$3742
     assign { } { }
-    assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
+      update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:209.5-209.40"
-  process $proc$ls180.v:209$2808
+  process $proc$ls180.v:209$2940
     assign { } { }
     assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
   end
-  attribute \src "ls180.v:213.5-213.40"
-  process $proc$ls180.v:213$2809
+  attribute \src "ls180.v:2110.11-2110.51"
+  process $proc$ls180.v:2110$3743
     assign { } { }
-    assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
+    assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
     sync always
-      update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
     sync init
+      update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2130.11-2130.51"
-  process $proc$ls180.v:2130$3603
+  attribute \src "ls180.v:213.5-213.40"
+  process $proc$ls180.v:213$2941
     assign { } { }
-    assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
+    assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
     sync always
+      update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
     sync init
-      update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:216.11-216.37"
-  process $proc$ls180.v:216$2810
+  process $proc$ls180.v:216$2942
     assign { } { }
     assign $1\main_libresocsim_we[3:0] 4'0000
     sync always
     sync init
       update \main_libresocsim_we $1\main_libresocsim_we[3:0]
   end
+  attribute \src "ls180.v:2175.11-2175.51"
+  process $proc$ls180.v:2175$3744
+    assign { } { }
+    assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
+    sync always
+    sync init
+      update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
+  end
   attribute \src "ls180.v:218.12-218.49"
-  process $proc$ls180.v:218$2811
+  process $proc$ls180.v:218$2943
     assign { } { }
     assign $1\main_libresocsim_load_storage[31:0] 0
     sync always
@@ -267108,7 +268789,7 @@ module \ls180
       update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
   end
   attribute \src "ls180.v:219.5-219.36"
-  process $proc$ls180.v:219$2812
+  process $proc$ls180.v:219$2944
     assign { } { }
     assign $1\main_libresocsim_load_re[0:0] 1'0
     sync always
@@ -267116,7 +268797,7 @@ module \ls180
       update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
   end
   attribute \src "ls180.v:220.12-220.51"
-  process $proc$ls180.v:220$2813
+  process $proc$ls180.v:220$2945
     assign { } { }
     assign $1\main_libresocsim_reload_storage[31:0] 0
     sync always
@@ -267124,7 +268805,7 @@ module \ls180
       update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
   end
   attribute \src "ls180.v:221.5-221.38"
-  process $proc$ls180.v:221$2814
+  process $proc$ls180.v:221$2946
     assign { } { }
     assign $1\main_libresocsim_reload_re[0:0] 1'0
     sync always
@@ -267132,7 +268813,7 @@ module \ls180
       update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
   end
   attribute \src "ls180.v:222.5-222.39"
-  process $proc$ls180.v:222$2815
+  process $proc$ls180.v:222$2947
     assign { } { }
     assign $1\main_libresocsim_en_storage[0:0] 1'0
     sync always
@@ -267140,7 +268821,7 @@ module \ls180
       update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
   end
   attribute \src "ls180.v:223.5-223.34"
-  process $proc$ls180.v:223$2816
+  process $proc$ls180.v:223$2948
     assign { } { }
     assign $1\main_libresocsim_en_re[0:0] 1'0
     sync always
@@ -267148,7 +268829,7 @@ module \ls180
       update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
   end
   attribute \src "ls180.v:224.5-224.49"
-  process $proc$ls180.v:224$2817
+  process $proc$ls180.v:224$2949
     assign { } { }
     assign $1\main_libresocsim_update_value_storage[0:0] 1'0
     sync always
@@ -267156,7 +268837,7 @@ module \ls180
       update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
   end
   attribute \src "ls180.v:225.5-225.44"
-  process $proc$ls180.v:225$2818
+  process $proc$ls180.v:225$2950
     assign { } { }
     assign $1\main_libresocsim_update_value_re[0:0] 1'0
     sync always
@@ -267164,31 +268845,31 @@ module \ls180
       update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
   end
   attribute \src "ls180.v:226.12-226.49"
-  process $proc$ls180.v:226$2819
+  process $proc$ls180.v:226$2951
     assign { } { }
     assign $1\main_libresocsim_value_status[31:0] 0
     sync always
     sync init
       update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
   end
-  attribute \src "ls180.v:2263.11-2263.51"
-  process $proc$ls180.v:2263$3604
+  attribute \src "ls180.v:230.5-230.41"
+  process $proc$ls180.v:230$2952
     assign { } { }
-    assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\main_libresocsim_zero_pending[0:0] 1'0
     sync always
     sync init
-      update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
+      update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
   end
-  attribute \src "ls180.v:230.5-230.41"
-  process $proc$ls180.v:230$2820
+  attribute \src "ls180.v:2308.11-2308.51"
+  process $proc$ls180.v:2308$3745
     assign { } { }
-    assign $1\main_libresocsim_zero_pending[0:0] 1'0
+    assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
+      update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:232.5-232.39"
-  process $proc$ls180.v:232$2821
+  process $proc$ls180.v:232$2953
     assign { } { }
     assign $1\main_libresocsim_zero_clear[0:0] 1'0
     sync always
@@ -267196,39 +268877,31 @@ module \ls180
       update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
   end
   attribute \src "ls180.v:233.5-233.45"
-  process $proc$ls180.v:233$2822
+  process $proc$ls180.v:233$2954
     assign { } { }
     assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
   end
-  attribute \src "ls180.v:2344.11-2344.51"
-  process $proc$ls180.v:2344$3605
+  attribute \src "ls180.v:2389.11-2389.51"
+  process $proc$ls180.v:2389$3746
     assign { } { }
     assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2361.11-2361.51"
-  process $proc$ls180.v:2361$3606
+  attribute \src "ls180.v:2406.11-2406.51"
+  process $proc$ls180.v:2406$3747
     assign { } { }
     assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2402.11-2402.52"
-  process $proc$ls180.v:2402$3607
-    assign { } { }
-    assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
-    sync always
-    sync init
-      update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
-  end
   attribute \src "ls180.v:242.5-242.49"
-  process $proc$ls180.v:242$2823
+  process $proc$ls180.v:242$2955
     assign { } { }
     assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
     sync always
@@ -267236,839 +268909,831 @@ module \ls180
       update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
   end
   attribute \src "ls180.v:243.5-243.44"
-  process $proc$ls180.v:243$2824
+  process $proc$ls180.v:243$2956
     assign { } { }
     assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
     sync always
     sync init
       update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
   end
-  attribute \src "ls180.v:2435.11-2435.52"
-  process $proc$ls180.v:2435$3608
+  attribute \src "ls180.v:244.12-244.42"
+  process $proc$ls180.v:244$2957
+    assign { } { }
+    assign $1\main_libresocsim_value[31:0] 0
+    sync always
+    sync init
+      update \main_libresocsim_value $1\main_libresocsim_value[31:0]
+  end
+  attribute \src "ls180.v:2447.11-2447.52"
+  process $proc$ls180.v:2447$3748
+    assign { } { }
+    assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
+    sync always
+    sync init
+      update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
+  end
+  attribute \src "ls180.v:2480.11-2480.52"
+  process $proc$ls180.v:2480$3749
     assign { } { }
     assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:244.12-244.42"
-  process $proc$ls180.v:244$2825
+  attribute \src "ls180.v:251.5-251.39"
+  process $proc$ls180.v:251$2958
     assign { } { }
-    assign $1\main_libresocsim_value[31:0] 0
+    assign $1\main_interface0_ram_bus_ack[0:0] 1'0
     sync always
     sync init
-      update \main_libresocsim_value $1\main_libresocsim_value[31:0]
+      update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0]
   end
-  attribute \src "ls180.v:2476.11-2476.52"
-  process $proc$ls180.v:2476$3609
+  attribute \src "ls180.v:2521.11-2521.52"
+  process $proc$ls180.v:2521$3750
     assign { } { }
     assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:248.5-248.24"
-  process $proc$ls180.v:248$2826
+  attribute \src "ls180.v:255.5-255.39"
+  process $proc$ls180.v:255$2959
     assign { } { }
-    assign $1\main_int_rst[0:0] 1'1
+    assign $0\main_interface0_ram_bus_err[0:0] 1'0
     sync always
+      update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0]
     sync init
-      update \main_int_rst $1\main_int_rst[0:0]
   end
-  attribute \src "ls180.v:2541.11-2541.52"
-  process $proc$ls180.v:2541$3610
+  attribute \src "ls180.v:258.11-258.31"
+  process $proc$ls180.v:258$2960
+    assign { } { }
+    assign $1\main_sram0_we[3:0] 4'0000
+    sync always
+    sync init
+      update \main_sram0_we $1\main_sram0_we[3:0]
+  end
+  attribute \src "ls180.v:2586.11-2586.52"
+  process $proc$ls180.v:2586$3751
     assign { } { }
     assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2566.11-2566.52"
-  process $proc$ls180.v:2566$3611
+  attribute \src "ls180.v:2611.11-2611.52"
+  process $proc$ls180.v:2611$3752
     assign { } { }
     assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:2588.11-2588.31"
-  process $proc$ls180.v:2588$3612
+  attribute \src "ls180.v:2633.11-2633.31"
+  process $proc$ls180.v:2633$3753
     assign { } { }
     assign $1\builder_state[1:0] 2'00
     sync always
     sync init
       update \builder_state $1\builder_state[1:0]
   end
-  attribute \src "ls180.v:2589.11-2589.36"
-  process $proc$ls180.v:2589$3613
+  attribute \src "ls180.v:2634.11-2634.36"
+  process $proc$ls180.v:2634$3754
     assign { } { }
     assign $1\builder_next_state[1:0] 2'00
     sync always
     sync init
       update \builder_next_state $1\builder_next_state[1:0]
   end
-  attribute \src "ls180.v:2590.11-2590.55"
-  process $proc$ls180.v:2590$3614
+  attribute \src "ls180.v:2635.11-2635.55"
+  process $proc$ls180.v:2635$3755
     assign { } { }
     assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
     sync always
     sync init
       update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
   end
-  attribute \src "ls180.v:2591.5-2591.52"
-  process $proc$ls180.v:2591$3615
+  attribute \src "ls180.v:2636.5-2636.52"
+  process $proc$ls180.v:2636$3756
     assign { } { }
     assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:2592.12-2592.55"
-  process $proc$ls180.v:2592$3616
+  attribute \src "ls180.v:2637.12-2637.55"
+  process $proc$ls180.v:2637$3757
     assign { } { }
     assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
     sync always
     sync init
       update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
   end
-  attribute \src "ls180.v:2593.5-2593.50"
-  process $proc$ls180.v:2593$3617
+  attribute \src "ls180.v:2638.5-2638.50"
+  process $proc$ls180.v:2638$3758
     assign { } { }
     assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:2594.5-2594.46"
-  process $proc$ls180.v:2594$3618
+  attribute \src "ls180.v:2639.5-2639.46"
+  process $proc$ls180.v:2639$3759
     assign { } { }
     assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
   end
-  attribute \src "ls180.v:2595.5-2595.49"
-  process $proc$ls180.v:2595$3619
+  attribute \src "ls180.v:2640.5-2640.49"
+  process $proc$ls180.v:2640$3760
     assign { } { }
     assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:2596.5-2596.41"
-  process $proc$ls180.v:2596$3620
+  attribute \src "ls180.v:2641.5-2641.41"
+  process $proc$ls180.v:2641$3761
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:2597.12-2597.49"
-  process $proc$ls180.v:2597$3621
+  attribute \src "ls180.v:2642.12-2642.49"
+  process $proc$ls180.v:2642$3762
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:2598.11-2598.47"
-  process $proc$ls180.v:2598$3622
+  attribute \src "ls180.v:2643.11-2643.47"
+  process $proc$ls180.v:2643$3763
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
     sync always
     sync init
       update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
   end
-  attribute \src "ls180.v:2599.5-2599.41"
-  process $proc$ls180.v:2599$3623
+  attribute \src "ls180.v:2644.5-2644.41"
+  process $proc$ls180.v:2644$3764
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:2600.5-2600.41"
-  process $proc$ls180.v:2600$3624
+  attribute \src "ls180.v:2645.5-2645.41"
+  process $proc$ls180.v:2645$3765
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:2601.5-2601.41"
-  process $proc$ls180.v:2601$3625
+  attribute \src "ls180.v:2646.5-2646.41"
+  process $proc$ls180.v:2646$3766
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:2602.5-2602.39"
-  process $proc$ls180.v:2602$3626
+  attribute \src "ls180.v:2647.5-2647.39"
+  process $proc$ls180.v:2647$3767
     assign { } { }
     assign $1\builder_comb_t_array_muxed0[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:2603.5-2603.39"
-  process $proc$ls180.v:2603$3627
+  attribute \src "ls180.v:2648.5-2648.39"
+  process $proc$ls180.v:2648$3768
     assign { } { }
     assign $1\builder_comb_t_array_muxed1[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:2604.5-2604.39"
-  process $proc$ls180.v:2604$3628
+  attribute \src "ls180.v:2649.5-2649.39"
+  process $proc$ls180.v:2649$3769
     assign { } { }
     assign $1\builder_comb_t_array_muxed2[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:2605.5-2605.41"
-  process $proc$ls180.v:2605$3629
+  attribute \src "ls180.v:2650.5-2650.41"
+  process $proc$ls180.v:2650$3770
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:2606.12-2606.49"
-  process $proc$ls180.v:2606$3630
+  attribute \src "ls180.v:2651.12-2651.49"
+  process $proc$ls180.v:2651$3771
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
   end
-  attribute \src "ls180.v:2607.11-2607.47"
-  process $proc$ls180.v:2607$3631
+  attribute \src "ls180.v:2652.11-2652.47"
+  process $proc$ls180.v:2652$3772
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
     sync always
     sync init
       update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
   end
-  attribute \src "ls180.v:2608.5-2608.41"
-  process $proc$ls180.v:2608$3632
+  attribute \src "ls180.v:2653.5-2653.41"
+  process $proc$ls180.v:2653$3773
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
   end
-  attribute \src "ls180.v:2609.5-2609.42"
-  process $proc$ls180.v:2609$3633
+  attribute \src "ls180.v:2654.5-2654.42"
+  process $proc$ls180.v:2654$3774
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
   end
-  attribute \src "ls180.v:2610.5-2610.42"
-  process $proc$ls180.v:2610$3634
+  attribute \src "ls180.v:2655.5-2655.42"
+  process $proc$ls180.v:2655$3775
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
   end
-  attribute \src "ls180.v:2611.5-2611.39"
-  process $proc$ls180.v:2611$3635
+  attribute \src "ls180.v:2656.5-2656.39"
+  process $proc$ls180.v:2656$3776
     assign { } { }
     assign $1\builder_comb_t_array_muxed3[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:2612.5-2612.39"
-  process $proc$ls180.v:2612$3636
+  attribute \src "ls180.v:2657.5-2657.39"
+  process $proc$ls180.v:2657$3777
     assign { } { }
     assign $1\builder_comb_t_array_muxed4[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:2613.5-2613.39"
-  process $proc$ls180.v:2613$3637
+  attribute \src "ls180.v:2658.5-2658.39"
+  process $proc$ls180.v:2658$3778
     assign { } { }
     assign $1\builder_comb_t_array_muxed5[0:0] 1'0
     sync always
     sync init
       update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:2614.12-2614.50"
-  process $proc$ls180.v:2614$3638
+  attribute \src "ls180.v:2659.12-2659.50"
+  process $proc$ls180.v:2659$3779
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
   end
-  attribute \src "ls180.v:2615.5-2615.42"
-  process $proc$ls180.v:2615$3639
+  attribute \src "ls180.v:266.5-266.39"
+  process $proc$ls180.v:266$2961
+    assign { } { }
+    assign $1\main_interface1_ram_bus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0]
+  end
+  attribute \src "ls180.v:2660.5-2660.42"
+  process $proc$ls180.v:2660$3780
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
   end
-  attribute \src "ls180.v:2616.5-2616.42"
-  process $proc$ls180.v:2616$3640
+  attribute \src "ls180.v:2661.5-2661.42"
+  process $proc$ls180.v:2661$3781
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
   end
-  attribute \src "ls180.v:2617.12-2617.50"
-  process $proc$ls180.v:2617$3641
+  attribute \src "ls180.v:2662.12-2662.50"
+  process $proc$ls180.v:2662$3782
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
   end
-  attribute \src "ls180.v:2618.5-2618.42"
-  process $proc$ls180.v:2618$3642
+  attribute \src "ls180.v:2663.5-2663.42"
+  process $proc$ls180.v:2663$3783
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
   end
-  attribute \src "ls180.v:2619.5-2619.42"
-  process $proc$ls180.v:2619$3643
+  attribute \src "ls180.v:2664.5-2664.42"
+  process $proc$ls180.v:2664$3784
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
   end
-  attribute \src "ls180.v:2620.12-2620.50"
-  process $proc$ls180.v:2620$3644
+  attribute \src "ls180.v:2665.12-2665.50"
+  process $proc$ls180.v:2665$3785
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
   end
-  attribute \src "ls180.v:2621.5-2621.42"
-  process $proc$ls180.v:2621$3645
+  attribute \src "ls180.v:2666.5-2666.42"
+  process $proc$ls180.v:2666$3786
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
   end
-  attribute \src "ls180.v:2622.5-2622.42"
-  process $proc$ls180.v:2622$3646
+  attribute \src "ls180.v:2667.5-2667.42"
+  process $proc$ls180.v:2667$3787
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
   end
-  attribute \src "ls180.v:2623.12-2623.50"
-  process $proc$ls180.v:2623$3647
+  attribute \src "ls180.v:2668.12-2668.50"
+  process $proc$ls180.v:2668$3788
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
   end
-  attribute \src "ls180.v:2624.5-2624.42"
-  process $proc$ls180.v:2624$3648
+  attribute \src "ls180.v:2669.5-2669.42"
+  process $proc$ls180.v:2669$3789
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
   end
-  attribute \src "ls180.v:2625.5-2625.42"
-  process $proc$ls180.v:2625$3649
+  attribute \src "ls180.v:2670.5-2670.42"
+  process $proc$ls180.v:2670$3790
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
   end
-  attribute \src "ls180.v:2626.12-2626.50"
-  process $proc$ls180.v:2626$3650
+  attribute \src "ls180.v:2671.12-2671.50"
+  process $proc$ls180.v:2671$3791
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed24[31:0] 0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
   end
-  attribute \src "ls180.v:2627.12-2627.50"
-  process $proc$ls180.v:2627$3651
+  attribute \src "ls180.v:2672.12-2672.50"
+  process $proc$ls180.v:2672$3792
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed25[31:0] 0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
   end
-  attribute \src "ls180.v:2628.11-2628.48"
-  process $proc$ls180.v:2628$3652
+  attribute \src "ls180.v:2673.11-2673.48"
+  process $proc$ls180.v:2673$3793
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
   end
-  attribute \src "ls180.v:2629.5-2629.42"
-  process $proc$ls180.v:2629$3653
+  attribute \src "ls180.v:2674.5-2674.42"
+  process $proc$ls180.v:2674$3794
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
   end
-  attribute \src "ls180.v:263.12-263.38"
-  process $proc$ls180.v:263$2827
-    assign { } { }
-    assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
-  end
-  attribute \src "ls180.v:2630.5-2630.42"
-  process $proc$ls180.v:2630$3654
+  attribute \src "ls180.v:2675.5-2675.42"
+  process $proc$ls180.v:2675$3795
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
   end
-  attribute \src "ls180.v:2631.5-2631.42"
-  process $proc$ls180.v:2631$3655
+  attribute \src "ls180.v:2676.5-2676.42"
+  process $proc$ls180.v:2676$3796
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
     sync always
     sync init
       update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
   end
-  attribute \src "ls180.v:2632.11-2632.48"
-  process $proc$ls180.v:2632$3656
+  attribute \src "ls180.v:2677.11-2677.48"
+  process $proc$ls180.v:2677$3797
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
     sync always
     sync init
       update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
   end
-  attribute \src "ls180.v:2633.11-2633.48"
-  process $proc$ls180.v:2633$3657
+  attribute \src "ls180.v:2678.11-2678.48"
+  process $proc$ls180.v:2678$3798
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
     sync always
     sync init
       update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
   end
-  attribute \src "ls180.v:2634.11-2634.47"
-  process $proc$ls180.v:2634$3658
+  attribute \src "ls180.v:2679.11-2679.47"
+  process $proc$ls180.v:2679$3799
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
     sync always
     sync init
       update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
   end
-  attribute \src "ls180.v:2635.12-2635.49"
-  process $proc$ls180.v:2635$3659
+  attribute \src "ls180.v:2680.12-2680.49"
+  process $proc$ls180.v:2680$3800
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
     sync always
     sync init
       update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:2636.5-2636.41"
-  process $proc$ls180.v:2636$3660
+  attribute \src "ls180.v:2681.5-2681.41"
+  process $proc$ls180.v:2681$3801
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
     sync always
     sync init
       update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:2637.5-2637.41"
-  process $proc$ls180.v:2637$3661
+  attribute \src "ls180.v:2682.5-2682.41"
+  process $proc$ls180.v:2682$3802
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
     sync always
     sync init
       update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:2638.5-2638.41"
-  process $proc$ls180.v:2638$3662
+  attribute \src "ls180.v:2683.5-2683.41"
+  process $proc$ls180.v:2683$3803
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
     sync always
     sync init
       update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:2639.5-2639.41"
-  process $proc$ls180.v:2639$3663
+  attribute \src "ls180.v:2684.5-2684.41"
+  process $proc$ls180.v:2684$3804
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
     sync always
     sync init
       update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:264.5-264.36"
-  process $proc$ls180.v:264$2828
-    assign { } { }
-    assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:2640.5-2640.41"
-  process $proc$ls180.v:2640$3664
+  attribute \src "ls180.v:2685.5-2685.41"
+  process $proc$ls180.v:2685$3805
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
     sync always
     sync init
       update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:2641.5-2641.39"
-  process $proc$ls180.v:2641$3665
+  attribute \src "ls180.v:2686.5-2686.39"
+  process $proc$ls180.v:2686$3806
     assign { } { }
     assign $1\builder_sync_f_array_muxed0[0:0] 1'0
     sync always
     sync init
       update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:2642.5-2642.39"
-  process $proc$ls180.v:2642$3666
+  attribute \src "ls180.v:2687.5-2687.39"
+  process $proc$ls180.v:2687$3807
     assign { } { }
     assign $1\builder_sync_f_array_muxed1[0:0] 1'0
     sync always
     sync init
       update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:265.11-265.32"
-  process $proc$ls180.v:265$2829
-    assign { } { }
-    assign $1\main_rddata_en[2:0] 3'000
-    sync always
-    sync init
-      update \main_rddata_en $1\main_rddata_en[2:0]
-  end
-  attribute \src "ls180.v:268.5-268.36"
-  process $proc$ls180.v:268$2830
+  attribute \src "ls180.v:270.5-270.39"
+  process $proc$ls180.v:270$2962
     assign { } { }
-    assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
+    assign $0\main_interface1_ram_bus_err[0:0] 1'0
     sync always
+      update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0]
     sync init
-      update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
   end
-  attribute \src "ls180.v:269.5-269.35"
-  process $proc$ls180.v:269$2831
+  attribute \src "ls180.v:273.11-273.31"
+  process $proc$ls180.v:273$2963
     assign { } { }
-    assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
+    assign $1\main_sram1_we[3:0] 4'0000
     sync always
     sync init
-      update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
+      update \main_sram1_we $1\main_sram1_we[3:0]
   end
-  attribute \src "ls180.v:2699.32-2699.66"
-  process $proc$ls180.v:2699$3667
+  attribute \src "ls180.v:2744.32-2744.66"
+  process $proc$ls180.v:2744$3808
     assign { } { }
     assign $1\builder_multiregimpl0_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
   end
-  attribute \src "ls180.v:270.5-270.36"
-  process $proc$ls180.v:270$2832
-    assign { } { }
-    assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
-  end
-  attribute \src "ls180.v:2700.32-2700.66"
-  process $proc$ls180.v:2700$3668
+  attribute \src "ls180.v:2745.32-2745.66"
+  process $proc$ls180.v:2745$3809
     assign { } { }
     assign $1\builder_multiregimpl0_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
   end
-  attribute \src "ls180.v:2701.32-2701.66"
-  process $proc$ls180.v:2701$3669
+  attribute \src "ls180.v:2746.32-2746.66"
+  process $proc$ls180.v:2746$3810
     assign { } { }
     assign $1\builder_multiregimpl1_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
   end
-  attribute \src "ls180.v:2702.32-2702.66"
-  process $proc$ls180.v:2702$3670
+  attribute \src "ls180.v:2747.32-2747.66"
+  process $proc$ls180.v:2747$3811
     assign { } { }
     assign $1\builder_multiregimpl1_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
   end
-  attribute \src "ls180.v:2703.32-2703.66"
-  process $proc$ls180.v:2703$3671
+  attribute \src "ls180.v:2748.32-2748.66"
+  process $proc$ls180.v:2748$3812
     assign { } { }
     assign $1\builder_multiregimpl2_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
   end
-  attribute \src "ls180.v:2704.32-2704.66"
-  process $proc$ls180.v:2704$3672
+  attribute \src "ls180.v:2749.32-2749.66"
+  process $proc$ls180.v:2749$3813
     assign { } { }
     assign $1\builder_multiregimpl2_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
   end
-  attribute \src "ls180.v:2705.32-2705.66"
-  process $proc$ls180.v:2705$3673
+  attribute \src "ls180.v:2750.32-2750.66"
+  process $proc$ls180.v:2750$3814
     assign { } { }
     assign $1\builder_multiregimpl3_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
   end
-  attribute \src "ls180.v:2706.32-2706.66"
-  process $proc$ls180.v:2706$3674
+  attribute \src "ls180.v:2751.32-2751.66"
+  process $proc$ls180.v:2751$3815
     assign { } { }
     assign $1\builder_multiregimpl3_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
   end
-  attribute \src "ls180.v:2707.32-2707.66"
-  process $proc$ls180.v:2707$3675
+  attribute \src "ls180.v:2752.32-2752.66"
+  process $proc$ls180.v:2752$3816
     assign { } { }
     assign $1\builder_multiregimpl4_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
   end
-  attribute \src "ls180.v:2708.32-2708.66"
-  process $proc$ls180.v:2708$3676
+  attribute \src "ls180.v:2753.32-2753.66"
+  process $proc$ls180.v:2753$3817
     assign { } { }
     assign $1\builder_multiregimpl4_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
   end
-  attribute \src "ls180.v:2709.32-2709.66"
-  process $proc$ls180.v:2709$3677
+  attribute \src "ls180.v:2754.32-2754.66"
+  process $proc$ls180.v:2754$3818
     assign { } { }
     assign $1\builder_multiregimpl5_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
   end
-  attribute \src "ls180.v:271.5-271.35"
-  process $proc$ls180.v:271$2833
-    assign { } { }
-    assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
-  end
-  attribute \src "ls180.v:2710.32-2710.66"
-  process $proc$ls180.v:2710$3678
+  attribute \src "ls180.v:2755.32-2755.66"
+  process $proc$ls180.v:2755$3819
     assign { } { }
     assign $1\builder_multiregimpl5_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
   end
-  attribute \src "ls180.v:2711.32-2711.66"
-  process $proc$ls180.v:2711$3679
+  attribute \src "ls180.v:2756.32-2756.66"
+  process $proc$ls180.v:2756$3820
     assign { } { }
     assign $1\builder_multiregimpl6_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
   end
-  attribute \src "ls180.v:2712.32-2712.66"
-  process $proc$ls180.v:2712$3680
+  attribute \src "ls180.v:2757.32-2757.66"
+  process $proc$ls180.v:2757$3821
     assign { } { }
     assign $1\builder_multiregimpl6_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
   end
-  attribute \src "ls180.v:2713.32-2713.66"
-  process $proc$ls180.v:2713$3681
+  attribute \src "ls180.v:2758.32-2758.66"
+  process $proc$ls180.v:2758$3822
     assign { } { }
     assign $1\builder_multiregimpl7_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
   end
-  attribute \src "ls180.v:2714.32-2714.66"
-  process $proc$ls180.v:2714$3682
+  attribute \src "ls180.v:2759.32-2759.66"
+  process $proc$ls180.v:2759$3823
     assign { } { }
     assign $1\builder_multiregimpl7_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
   end
-  attribute \src "ls180.v:2715.32-2715.66"
-  process $proc$ls180.v:2715$3683
+  attribute \src "ls180.v:2760.32-2760.66"
+  process $proc$ls180.v:2760$3824
     assign { } { }
     assign $1\builder_multiregimpl8_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
   end
-  attribute \src "ls180.v:2716.32-2716.66"
-  process $proc$ls180.v:2716$3684
+  attribute \src "ls180.v:2761.32-2761.66"
+  process $proc$ls180.v:2761$3825
     assign { } { }
     assign $1\builder_multiregimpl8_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
   end
-  attribute \src "ls180.v:2717.32-2717.66"
-  process $proc$ls180.v:2717$3685
+  attribute \src "ls180.v:2762.32-2762.66"
+  process $proc$ls180.v:2762$3826
     assign { } { }
     assign $1\builder_multiregimpl9_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
   end
-  attribute \src "ls180.v:2718.32-2718.66"
-  process $proc$ls180.v:2718$3686
+  attribute \src "ls180.v:2763.32-2763.66"
+  process $proc$ls180.v:2763$3827
     assign { } { }
     assign $1\builder_multiregimpl9_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
   end
-  attribute \src "ls180.v:2719.32-2719.67"
-  process $proc$ls180.v:2719$3687
+  attribute \src "ls180.v:2764.32-2764.67"
+  process $proc$ls180.v:2764$3828
     assign { } { }
     assign $1\builder_multiregimpl10_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
   end
-  attribute \src "ls180.v:2720.32-2720.67"
-  process $proc$ls180.v:2720$3688
+  attribute \src "ls180.v:2765.32-2765.67"
+  process $proc$ls180.v:2765$3829
     assign { } { }
     assign $1\builder_multiregimpl10_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
   end
-  attribute \src "ls180.v:2721.32-2721.67"
-  process $proc$ls180.v:2721$3689
+  attribute \src "ls180.v:2766.32-2766.67"
+  process $proc$ls180.v:2766$3830
     assign { } { }
     assign $1\builder_multiregimpl11_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
   end
-  attribute \src "ls180.v:2722.32-2722.67"
-  process $proc$ls180.v:2722$3690
+  attribute \src "ls180.v:2767.32-2767.67"
+  process $proc$ls180.v:2767$3831
     assign { } { }
     assign $1\builder_multiregimpl11_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
   end
-  attribute \src "ls180.v:2723.32-2723.67"
-  process $proc$ls180.v:2723$3691
+  attribute \src "ls180.v:2768.32-2768.67"
+  process $proc$ls180.v:2768$3832
     assign { } { }
     assign $1\builder_multiregimpl12_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
   end
-  attribute \src "ls180.v:2724.32-2724.67"
-  process $proc$ls180.v:2724$3692
+  attribute \src "ls180.v:2769.32-2769.67"
+  process $proc$ls180.v:2769$3833
     assign { } { }
     assign $1\builder_multiregimpl12_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
   end
-  attribute \src "ls180.v:2725.32-2725.67"
-  process $proc$ls180.v:2725$3693
+  attribute \src "ls180.v:2770.32-2770.67"
+  process $proc$ls180.v:2770$3834
     assign { } { }
     assign $1\builder_multiregimpl13_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
   end
-  attribute \src "ls180.v:2726.32-2726.67"
-  process $proc$ls180.v:2726$3694
+  attribute \src "ls180.v:2771.32-2771.67"
+  process $proc$ls180.v:2771$3835
     assign { } { }
     assign $1\builder_multiregimpl13_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
   end
-  attribute \src "ls180.v:2727.32-2727.67"
-  process $proc$ls180.v:2727$3695
+  attribute \src "ls180.v:2772.32-2772.67"
+  process $proc$ls180.v:2772$3836
     assign { } { }
     assign $1\builder_multiregimpl14_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
   end
-  attribute \src "ls180.v:2728.32-2728.67"
-  process $proc$ls180.v:2728$3696
+  attribute \src "ls180.v:2773.32-2773.67"
+  process $proc$ls180.v:2773$3837
     assign { } { }
     assign $1\builder_multiregimpl14_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
   end
-  attribute \src "ls180.v:2729.32-2729.67"
-  process $proc$ls180.v:2729$3697
+  attribute \src "ls180.v:2774.32-2774.67"
+  process $proc$ls180.v:2774$3838
     assign { } { }
     assign $1\builder_multiregimpl15_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
   end
-  attribute \src "ls180.v:2730.32-2730.67"
-  process $proc$ls180.v:2730$3698
+  attribute \src "ls180.v:2775.32-2775.67"
+  process $proc$ls180.v:2775$3839
     assign { } { }
     assign $1\builder_multiregimpl15_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
   end
-  attribute \src "ls180.v:2731.32-2731.67"
-  process $proc$ls180.v:2731$3699
+  attribute \src "ls180.v:2776.32-2776.67"
+  process $proc$ls180.v:2776$3840
     assign { } { }
     assign $1\builder_multiregimpl16_regs0[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
   end
-  attribute \src "ls180.v:2732.32-2732.67"
-  process $proc$ls180.v:2732$3700
+  attribute \src "ls180.v:2777.32-2777.67"
+  process $proc$ls180.v:2777$3841
     assign { } { }
     assign $1\builder_multiregimpl16_regs1[0:0] 1'0
     sync always
     sync init
       update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
   end
-  attribute \src "ls180.v:275.5-275.36"
-  process $proc$ls180.v:275$2834
+  attribute \src "ls180.v:281.5-281.39"
+  process $proc$ls180.v:281$2964
     assign { } { }
-    assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
+    assign $1\main_interface2_ram_bus_ack[0:0] 1'0
     sync always
-      update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
     sync init
+      update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0]
   end
-  attribute \src "ls180.v:2767.1-2772.4"
-  process $proc$ls180.v:2767$13
+  attribute \src "ls180.v:2812.1-2817.4"
+  process $proc$ls180.v:2812$25
     assign { } { }
     assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000
     assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint }
@@ -268077,11 +269742,11 @@ module \ls180
     sync always
       update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0]
   end
-  attribute \src "ls180.v:2774.1-2784.4"
-  process $proc$ls180.v:2774$15
+  attribute \src "ls180.v:2819.1-2829.4"
+  process $proc$ls180.v:2819$27
     assign { } { }
     assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
-    attribute \src "ls180.v:2776.2-2783.9"
+    attribute \src "ls180.v:2821.2-2828.9"
     switch \main_libresocsim_converter0_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
@@ -268094,8 +269759,9 @@ module \ls180
     sync always
       update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:2786.1-2832.4"
-  process $proc$ls180.v:2786$16
+  attribute \src "ls180.v:2831.1-2877.4"
+  process $proc$ls180.v:2831$28
+    assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268107,22 +269773,21 @@ module \ls180
     assign { } { }
     assign { } { }
     assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+    assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
     assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
+    assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_converter0_skip[0:0] 1'0
-    assign { } { }
-    assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
-    assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
     assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
     assign $0\builder_converter0_next_state[0:0] \builder_converter0_state
-    attribute \src "ls180.v:2798.2-2831.9"
+    attribute \src "ls180.v:2843.2-2876.9"
     switch \builder_converter0_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter }
-        attribute \src "ls180.v:2801.4-2808.11"
+        attribute \src "ls180.v:2846.4-2853.11"
         switch \main_libresocsim_converter0_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -268132,23 +269797,23 @@ module \ls180
             assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:2809.4-2822.7"
-        switch $and$ls180.v:2809$17_Y
-          attribute \src "ls180.v:2809.8-2809.81"
+        attribute \src "ls180.v:2854.4-2867.7"
+        switch $and$ls180.v:2854$29_Y
+          attribute \src "ls180.v:2854.8-2854.81"
           case 1'1
-            assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2810$18_Y
+            assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2855$30_Y
             assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we
-            assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2812$19_Y
-            assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2813$20_Y
-            attribute \src "ls180.v:2814.5-2821.8"
-            switch $or$ls180.v:2814$21_Y
-              attribute \src "ls180.v:2814.9-2814.97"
+            assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2857$31_Y
+            assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2858$32_Y
+            attribute \src "ls180.v:2859.5-2866.8"
+            switch $or$ls180.v:2859$33_Y
+              attribute \src "ls180.v:2859.9-2859.97"
               case 1'1
-                assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2815$22_Y
+                assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2860$34_Y
                 assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:2817.6-2820.9"
-                switch $eq$ls180.v:2817$23_Y
-                  attribute \src "ls180.v:2817.10-2817.55"
+                attribute \src "ls180.v:2862.6-2865.9"
+                switch $eq$ls180.v:2862$35_Y
+                  attribute \src "ls180.v:2862.10-2862.55"
                   case 1'1
                     assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1
                     assign $0\builder_converter0_next_state[0:0] 1'0
@@ -268162,9 +269827,9 @@ module \ls180
       case 
         assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
         assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:2827.4-2829.7"
-        switch $and$ls180.v:2827$24_Y
-          attribute \src "ls180.v:2827.8-2827.81"
+        attribute \src "ls180.v:2872.4-2874.7"
+        switch $and$ls180.v:2872$36_Y
+          attribute \src "ls180.v:2872.8-2872.81"
           case 1'1
             assign $0\builder_converter0_next_state[0:0] 1'1
           case 
@@ -268182,27 +269847,19 @@ module \ls180
       update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
       update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:280.12-280.45"
-  process $proc$ls180.v:280$2835
+  attribute \src "ls180.v:285.5-285.39"
+  process $proc$ls180.v:285$2965
     assign { } { }
-    assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
+    assign $0\main_interface2_ram_bus_err[0:0] 1'0
     sync always
+      update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0]
     sync init
-      update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
   end
-  attribute \src "ls180.v:281.5-281.43"
-  process $proc$ls180.v:281$2836
-    assign { } { }
-    assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:2834.1-2844.4"
-  process $proc$ls180.v:2834$26
+  attribute \src "ls180.v:2879.1-2889.4"
+  process $proc$ls180.v:2879$38
     assign { } { }
     assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
-    attribute \src "ls180.v:2836.2-2843.9"
+    attribute \src "ls180.v:2881.2-2888.9"
     switch \main_libresocsim_converter1_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
@@ -268215,8 +269872,16 @@ module \ls180
     sync always
       update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:2846.1-2892.4"
-  process $proc$ls180.v:2846$27
+  attribute \src "ls180.v:288.11-288.31"
+  process $proc$ls180.v:288$2966
+    assign { } { }
+    assign $1\main_sram2_we[3:0] 4'0000
+    sync always
+    sync init
+      update \main_sram2_we $1\main_sram2_we[3:0]
+  end
+  attribute \src "ls180.v:2891.1-2937.4"
+  process $proc$ls180.v:2891$39
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268228,22 +269893,22 @@ module \ls180
     assign { } { }
     assign { } { }
     assign $0\main_libresocsim_converter1_skip[0:0] 1'0
+    assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
-    assign { } { }
-    assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
-    assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
     assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
+    assign { } { }
+    assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     assign $0\builder_converter1_next_state[0:0] \builder_converter1_state
-    attribute \src "ls180.v:2858.2-2891.9"
+    attribute \src "ls180.v:2903.2-2936.9"
     switch \builder_converter1_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter }
-        attribute \src "ls180.v:2861.4-2868.11"
+        attribute \src "ls180.v:2906.4-2913.11"
         switch \main_libresocsim_converter1_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -268253,23 +269918,23 @@ module \ls180
             assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:2869.4-2882.7"
-        switch $and$ls180.v:2869$28_Y
-          attribute \src "ls180.v:2869.8-2869.81"
+        attribute \src "ls180.v:2914.4-2927.7"
+        switch $and$ls180.v:2914$40_Y
+          attribute \src "ls180.v:2914.8-2914.81"
           case 1'1
-            assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2870$29_Y
+            assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2915$41_Y
             assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we
-            assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2872$30_Y
-            assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2873$31_Y
-            attribute \src "ls180.v:2874.5-2881.8"
-            switch $or$ls180.v:2874$32_Y
-              attribute \src "ls180.v:2874.9-2874.97"
+            assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2917$42_Y
+            assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2918$43_Y
+            attribute \src "ls180.v:2919.5-2926.8"
+            switch $or$ls180.v:2919$44_Y
+              attribute \src "ls180.v:2919.9-2919.97"
               case 1'1
-                assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2875$33_Y
+                assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2920$45_Y
                 assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:2877.6-2880.9"
-                switch $eq$ls180.v:2877$34_Y
-                  attribute \src "ls180.v:2877.10-2877.55"
+                attribute \src "ls180.v:2922.6-2925.9"
+                switch $eq$ls180.v:2922$46_Y
+                  attribute \src "ls180.v:2922.10-2922.55"
                   case 1'1
                     assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1
                     assign $0\builder_converter1_next_state[0:0] 1'0
@@ -268283,9 +269948,9 @@ module \ls180
       case 
         assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
         assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:2887.4-2889.7"
-        switch $and$ls180.v:2887$35_Y
-          attribute \src "ls180.v:2887.8-2887.81"
+        attribute \src "ls180.v:2932.4-2934.7"
+        switch $and$ls180.v:2932$47_Y
+          attribute \src "ls180.v:2932.8-2932.81"
           case 1'1
             assign $0\builder_converter1_next_state[0:0] 1'1
           case 
@@ -268303,11 +269968,19 @@ module \ls180
       update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
       update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:2894.1-2904.4"
-  process $proc$ls180.v:2894$37
+  attribute \src "ls180.v:293.5-293.24"
+  process $proc$ls180.v:293$2967
+    assign { } { }
+    assign $1\main_int_rst[0:0] 1'1
+    sync always
+    sync init
+      update \main_int_rst $1\main_int_rst[0:0]
+  end
+  attribute \src "ls180.v:2939.1-2949.4"
+  process $proc$ls180.v:2939$49
     assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
-    attribute \src "ls180.v:2896.2-2903.9"
+    attribute \src "ls180.v:2941.2-2948.9"
     switch \main_libresocsim_converter2_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
@@ -268320,8 +269993,8 @@ module \ls180
     sync always
       update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:2906.1-2952.4"
-  process $proc$ls180.v:2906$38
+  attribute \src "ls180.v:2951.1-2997.4"
+  process $proc$ls180.v:2951$50
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268335,20 +270008,20 @@ module \ls180
     assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
     assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
-    assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
-    assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
-    assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
     assign $0\main_libresocsim_converter2_skip[0:0] 1'0
+    assign { } { }
+    assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
+    assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     assign $0\builder_converter2_next_state[0:0] \builder_converter2_state
-    attribute \src "ls180.v:2918.2-2951.9"
+    attribute \src "ls180.v:2963.2-2996.9"
     switch \builder_converter2_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter }
-        attribute \src "ls180.v:2921.4-2928.11"
+        attribute \src "ls180.v:2966.4-2973.11"
         switch \main_libresocsim_converter2_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -268358,23 +270031,23 @@ module \ls180
             assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:2929.4-2942.7"
-        switch $and$ls180.v:2929$39_Y
-          attribute \src "ls180.v:2929.8-2929.87"
+        attribute \src "ls180.v:2974.4-2987.7"
+        switch $and$ls180.v:2974$51_Y
+          attribute \src "ls180.v:2974.8-2974.87"
           case 1'1
-            assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2930$40_Y
+            assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2975$52_Y
             assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we
-            assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2932$41_Y
-            assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2933$42_Y
-            attribute \src "ls180.v:2934.5-2941.8"
-            switch $or$ls180.v:2934$43_Y
-              attribute \src "ls180.v:2934.9-2934.97"
+            assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2977$53_Y
+            assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2978$54_Y
+            attribute \src "ls180.v:2979.5-2986.8"
+            switch $or$ls180.v:2979$55_Y
+              attribute \src "ls180.v:2979.9-2979.97"
               case 1'1
-                assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2935$44_Y
+                assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2980$56_Y
                 assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:2937.6-2940.9"
-                switch $eq$ls180.v:2937$45_Y
-                  attribute \src "ls180.v:2937.10-2937.55"
+                attribute \src "ls180.v:2982.6-2985.9"
+                switch $eq$ls180.v:2982$57_Y
+                  attribute \src "ls180.v:2982.10-2982.55"
                   case 1'1
                     assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1
                     assign $0\builder_converter2_next_state[0:0] 1'0
@@ -268388,9 +270061,9 @@ module \ls180
       case 
         assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
         assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:2947.4-2949.7"
-        switch $and$ls180.v:2947$46_Y
-          attribute \src "ls180.v:2947.8-2947.87"
+        attribute \src "ls180.v:2992.4-2994.7"
+        switch $and$ls180.v:2992$58_Y
+          attribute \src "ls180.v:2992.8-2992.87"
           case 1'1
             assign $0\builder_converter2_next_state[0:0] 1'1
           case 
@@ -268408,32 +270081,24 @@ module \ls180
       update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
       update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:2955.1-2961.4"
-  process $proc$ls180.v:2955$47
+  attribute \src "ls180.v:3000.1-3006.4"
+  process $proc$ls180.v:3000$59
     assign { } { }
     assign { } { }
-    assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2957$50_Y
-    assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2958$53_Y
-    assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2959$56_Y
-    assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2960$59_Y
+    assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:3002$62_Y
+    assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:3003$65_Y
+    assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:3004$68_Y
+    assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:3005$71_Y
     sync always
       update \main_libresocsim_we $0\main_libresocsim_we[3:0]
   end
-  attribute \src "ls180.v:296.12-296.46"
-  process $proc$ls180.v:296$2837
-    assign { } { }
-    assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
-  end
-  attribute \src "ls180.v:2967.1-2972.4"
-  process $proc$ls180.v:2967$61
+  attribute \src "ls180.v:3012.1-3017.4"
+  process $proc$ls180.v:3012$73
     assign { } { }
     assign $0\main_libresocsim_zero_clear[0:0] 1'0
-    attribute \src "ls180.v:2969.2-2971.5"
-    switch $and$ls180.v:2969$62_Y
-      attribute \src "ls180.v:2969.6-2969.90"
+    attribute \src "ls180.v:3014.2-3016.5"
+    switch $and$ls180.v:3014$74_Y
+      attribute \src "ls180.v:3014.6-3014.90"
       case 1'1
         assign $0\main_libresocsim_zero_clear[0:0] 1'1
       case 
@@ -268441,48 +270106,49 @@ module \ls180
     sync always
       update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
   end
-  attribute \src "ls180.v:297.5-297.44"
-  process $proc$ls180.v:297$2838
+  attribute \src "ls180.v:3021.1-3027.4"
+  process $proc$ls180.v:3021$76
     assign { } { }
-    assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:298.12-298.48"
-  process $proc$ls180.v:298$2839
     assign { } { }
-    assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
+    assign $0\main_sram0_we[3:0] [0] $and$ls180.v:3023$79_Y
+    assign $0\main_sram0_we[3:0] [1] $and$ls180.v:3024$82_Y
+    assign $0\main_sram0_we[3:0] [2] $and$ls180.v:3025$85_Y
+    assign $0\main_sram0_we[3:0] [3] $and$ls180.v:3026$88_Y
     sync always
-    sync init
-      update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
+      update \main_sram0_we $0\main_sram0_we[3:0]
   end
-  attribute \src "ls180.v:299.11-299.43"
-  process $proc$ls180.v:299$2840
+  attribute \src "ls180.v:3031.1-3037.4"
+  process $proc$ls180.v:3031$89
     assign { } { }
-    assign $1\main_sdram_master_p0_bank[1:0] 2'00
+    assign { } { }
+    assign $0\main_sram1_we[3:0] [0] $and$ls180.v:3033$92_Y
+    assign $0\main_sram1_we[3:0] [1] $and$ls180.v:3034$95_Y
+    assign $0\main_sram1_we[3:0] [2] $and$ls180.v:3035$98_Y
+    assign $0\main_sram1_we[3:0] [3] $and$ls180.v:3036$101_Y
     sync always
-    sync init
-      update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
+      update \main_sram1_we $0\main_sram1_we[3:0]
   end
-  attribute \src "ls180.v:300.5-300.38"
-  process $proc$ls180.v:300$2841
+  attribute \src "ls180.v:3041.1-3047.4"
+  process $proc$ls180.v:3041$102
     assign { } { }
-    assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
+    assign { } { }
+    assign $0\main_sram2_we[3:0] [0] $and$ls180.v:3043$105_Y
+    assign $0\main_sram2_we[3:0] [1] $and$ls180.v:3044$108_Y
+    assign $0\main_sram2_we[3:0] [2] $and$ls180.v:3045$111_Y
+    assign $0\main_sram2_we[3:0] [3] $and$ls180.v:3046$114_Y
     sync always
-    sync init
-      update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
+      update \main_sram2_we $0\main_sram2_we[3:0]
   end
-  attribute \src "ls180.v:301.5-301.37"
-  process $proc$ls180.v:301$2842
+  attribute \src "ls180.v:308.12-308.38"
+  process $proc$ls180.v:308$2968
     assign { } { }
-    assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
+    assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
+      update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
   end
-  attribute \src "ls180.v:3011.1-3065.4"
-  process $proc$ls180.v:3011$64
+  attribute \src "ls180.v:3086.1-3140.4"
+  process $proc$ls180.v:3086$115
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268501,12 +270167,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
-    assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0
-    assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0
-    assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00
-    assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0
-    assign $0\main_sdram_master_p0_act_n[0:0] 1'1
     assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
     assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0
     assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000
@@ -268518,10 +270178,16 @@ module \ls180
     assign $0\main_sdram_master_p0_cke[0:0] 1'0
     assign $0\main_sdram_master_p0_odt[0:0] 1'0
     assign $0\main_sdram_master_p0_reset_n[0:0] 1'0
+    assign $0\main_sdram_master_p0_act_n[0:0] 1'1
     assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
-    attribute \src "ls180.v:3030.2-3064.5"
+    assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+    assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0
+    assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0
+    assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00
+    assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0
+    attribute \src "ls180.v:3105.2-3139.5"
     switch \main_sdram_sel
-      attribute \src "ls180.v:3030.6-3030.20"
+      attribute \src "ls180.v:3105.6-3105.20"
       case 1'1
         assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address
         assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank
@@ -268539,7 +270205,7 @@ module \ls180
         assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en
         assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata
         assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid
-      attribute \src "ls180.v:3047.6-3047.10"
+      attribute \src "ls180.v:3122.6-3122.10"
       case 
         assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address
         assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank
@@ -268578,65 +270244,57 @@ module \ls180
       update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0]
       update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
   end
-  attribute \src "ls180.v:302.5-302.38"
-  process $proc$ls180.v:302$2843
-    assign { } { }
-    assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
-  end
-  attribute \src "ls180.v:303.5-303.37"
-  process $proc$ls180.v:303$2844
+  attribute \src "ls180.v:309.5-309.36"
+  process $proc$ls180.v:309$2969
     assign { } { }
-    assign $1\main_sdram_master_p0_we_n[0:0] 1'1
+    assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
+      update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
   end
-  attribute \src "ls180.v:304.5-304.36"
-  process $proc$ls180.v:304$2845
+  attribute \src "ls180.v:310.11-310.32"
+  process $proc$ls180.v:310$2970
     assign { } { }
-    assign $1\main_sdram_master_p0_cke[0:0] 1'0
+    assign $1\main_rddata_en[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
+      update \main_rddata_en $1\main_rddata_en[2:0]
   end
-  attribute \src "ls180.v:305.5-305.36"
-  process $proc$ls180.v:305$2846
+  attribute \src "ls180.v:313.5-313.36"
+  process $proc$ls180.v:313$2971
     assign { } { }
-    assign $1\main_sdram_master_p0_odt[0:0] 1'0
+    assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
+      update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
   end
-  attribute \src "ls180.v:306.5-306.40"
-  process $proc$ls180.v:306$2847
+  attribute \src "ls180.v:314.5-314.35"
+  process $proc$ls180.v:314$2972
     assign { } { }
-    assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
+    assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
+      update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
   end
-  attribute \src "ls180.v:3069.1-3085.4"
-  process $proc$ls180.v:3069$65
+  attribute \src "ls180.v:3144.1-3160.4"
+  process $proc$ls180.v:3144$116
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1
     assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
     assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1
     assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
-    assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1
-    attribute \src "ls180.v:3074.2-3084.5"
+    attribute \src "ls180.v:3149.2-3159.5"
     switch \main_sdram_command_issue_re
-      attribute \src "ls180.v:3074.6-3074.33"
+      attribute \src "ls180.v:3149.6-3149.33"
       case 1'1
-        assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3075$66_Y
-        assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3076$67_Y
-        assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3077$68_Y
-        assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3078$69_Y
-      attribute \src "ls180.v:3079.6-3079.10"
+        assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3150$117_Y
+        assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3151$118_Y
+        assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3152$119_Y
+        assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3153$120_Y
+      attribute \src "ls180.v:3154.6-3154.10"
       case 
         assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
         assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
@@ -268649,48 +270307,32 @@ module \ls180
       update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0]
       update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
   end
-  attribute \src "ls180.v:307.5-307.38"
-  process $proc$ls180.v:307$2848
+  attribute \src "ls180.v:315.5-315.36"
+  process $proc$ls180.v:315$2973
     assign { } { }
-    assign $1\main_sdram_master_p0_act_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
-  end
-  attribute \src "ls180.v:308.12-308.47"
-  process $proc$ls180.v:308$2849
-    assign { } { }
-    assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
-  end
-  attribute \src "ls180.v:309.5-309.42"
-  process $proc$ls180.v:309$2850
-    assign { } { }
-    assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
+    assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
+      update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
   end
-  attribute \src "ls180.v:310.11-310.50"
-  process $proc$ls180.v:310$2851
+  attribute \src "ls180.v:316.5-316.35"
+  process $proc$ls180.v:316$2974
     assign { } { }
-    assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
+    assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
+      update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
   end
-  attribute \src "ls180.v:311.5-311.42"
-  process $proc$ls180.v:311$2852
+  attribute \src "ls180.v:320.5-320.36"
+  process $proc$ls180.v:320$2975
     assign { } { }
-    assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
+    assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
     sync always
+      update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
     sync init
-      update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
   end
-  attribute \src "ls180.v:3128.1-3158.4"
-  process $proc$ls180.v:3128$78
+  attribute \src "ls180.v:3203.1-3233.4"
+  process $proc$ls180.v:3203$129
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268700,14 +270342,14 @@ module \ls180
     assign { } { }
     assign $0\main_sdram_cmd_valid[0:0] 1'0
     assign $0\builder_refresher_next_state[1:0] \builder_refresher_state
-    attribute \src "ls180.v:3134.2-3157.9"
+    attribute \src "ls180.v:3209.2-3232.9"
     switch \builder_refresher_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_sdram_cmd_valid[0:0] 1'1
-        attribute \src "ls180.v:3137.4-3140.7"
+        attribute \src "ls180.v:3212.4-3215.7"
         switch \main_sdram_cmd_ready
-          attribute \src "ls180.v:3137.8-3137.28"
+          attribute \src "ls180.v:3212.8-3212.28"
           case 1'1
             assign $0\main_sdram_sequencer_start0[0:0] 1'1
             assign $0\builder_refresher_next_state[1:0] 2'10
@@ -268716,9 +270358,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
         assign $0\main_sdram_cmd_valid[0:0] 1'1
-        attribute \src "ls180.v:3144.4-3148.7"
+        attribute \src "ls180.v:3219.4-3223.7"
         switch \main_sdram_sequencer_done0
-          attribute \src "ls180.v:3144.8-3144.34"
+          attribute \src "ls180.v:3219.8-3219.34"
           case 1'1
             assign $0\main_sdram_cmd_valid[0:0] 1'0
             assign $0\main_sdram_cmd_last[0:0] 1'1
@@ -268727,13 +270369,13 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:3151.4-3155.7"
+        attribute \src "ls180.v:3226.4-3230.7"
         switch 1'1
-          attribute \src "ls180.v:3151.8-3151.12"
+          attribute \src "ls180.v:3226.8-3226.12"
           case 1'1
-            attribute \src "ls180.v:3152.5-3154.8"
+            attribute \src "ls180.v:3227.5-3229.8"
             switch \main_sdram_wants_refresh
-              attribute \src "ls180.v:3152.9-3152.33"
+              attribute \src "ls180.v:3227.9-3227.33"
               case 1'1
                 assign $0\builder_refresher_next_state[1:0] 2'01
               case 
@@ -268747,43 +270389,43 @@ module \ls180
       update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0]
       update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
   end
-  attribute \src "ls180.v:3173.1-3180.4"
-  process $proc$ls180.v:3173$82
+  attribute \src "ls180.v:3248.1-3255.4"
+  process $proc$ls180.v:3248$133
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:3175.2-3179.5"
+    attribute \src "ls180.v:3250.2-3254.5"
     switch \main_sdram_bankmachine0_row_col_n_addr_sel
-      attribute \src "ls180.v:3175.6-3175.48"
+      attribute \src "ls180.v:3250.6-3250.48"
       case 1'1
         assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:3177.6-3177.10"
+      attribute \src "ls180.v:3252.6-3252.10"
       case 
-        assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3178$84_Y
+        assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3253$135_Y
     end
     sync always
       update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:318.11-318.36"
-  process $proc$ls180.v:318$2853
+  attribute \src "ls180.v:325.12-325.45"
+  process $proc$ls180.v:325$2976
     assign { } { }
-    assign $1\main_sdram_storage[3:0] 4'0001
+    assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_storage $1\main_sdram_storage[3:0]
+      update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
   end
-  attribute \src "ls180.v:3184.1-3191.4"
-  process $proc$ls180.v:3184$91
+  attribute \src "ls180.v:3259.1-3266.4"
+  process $proc$ls180.v:3259$142
     assign { } { }
     assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:3186.2-3190.5"
-    switch $and$ls180.v:3186$92_Y
-      attribute \src "ls180.v:3186.6-3186.115"
+    attribute \src "ls180.v:3261.2-3265.5"
+    switch $and$ls180.v:3261$143_Y
+      attribute \src "ls180.v:3261.6-3261.115"
       case 1'1
-        attribute \src "ls180.v:3187.3-3189.6"
-        switch $ne$ls180.v:3187$93_Y
-          attribute \src "ls180.v:3187.7-3187.143"
+        attribute \src "ls180.v:3262.3-3264.6"
+        switch $ne$ls180.v:3262$144_Y
+          attribute \src "ls180.v:3262.7-3262.143"
           case 1'1
-            assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3188$94_Y
+            assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3263$145_Y
           case 
         end
       case 
@@ -268791,48 +270433,32 @@ module \ls180
     sync always
       update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:319.5-319.25"
-  process $proc$ls180.v:319$2854
-    assign { } { }
-    assign $1\main_sdram_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_re $1\main_sdram_re[0:0]
-  end
-  attribute \src "ls180.v:320.11-320.44"
-  process $proc$ls180.v:320$2855
+  attribute \src "ls180.v:326.5-326.43"
+  process $proc$ls180.v:326$2977
     assign { } { }
-    assign $1\main_sdram_command_storage[5:0] 6'000000
+    assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
+      update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
   end
-  attribute \src "ls180.v:3206.1-3213.4"
-  process $proc$ls180.v:3206$95
+  attribute \src "ls180.v:3281.1-3288.4"
+  process $proc$ls180.v:3281$146
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:3208.2-3212.5"
+    attribute \src "ls180.v:3283.2-3287.5"
     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:3208.6-3208.58"
+      attribute \src "ls180.v:3283.6-3283.58"
       case 1'1
-        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3209$96_Y
-      attribute \src "ls180.v:3210.6-3210.10"
+        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3284$147_Y
+      attribute \src "ls180.v:3285.6-3285.10"
       case 
         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
     end
     sync always
       update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:321.5-321.33"
-  process $proc$ls180.v:321$2856
-    assign { } { }
-    assign $1\main_sdram_command_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_command_re $1\main_sdram_command_re[0:0]
-  end
-  attribute \src "ls180.v:3222.1-3315.4"
-  process $proc$ls180.v:3222$104
+  attribute \src "ls180.v:3297.1-3390.4"
+  process $proc$ls180.v:3297$155
     assign { } { }
     assign { } { }
     assign { } { }
@@ -268847,37 +270473,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
-    assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
-    assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
-    assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
-    assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
     assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0
     assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0
-    assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
     assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state
-    attribute \src "ls180.v:3238.2-3314.9"
+    attribute \src "ls180.v:3313.2-3389.9"
     switch \builder_bankmachine0_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
-        attribute \src "ls180.v:3240.4-3248.7"
-        switch $and$ls180.v:3240$105_Y
-          attribute \src "ls180.v:3240.8-3240.87"
+        attribute \src "ls180.v:3315.4-3323.7"
+        switch $and$ls180.v:3315$156_Y
+          attribute \src "ls180.v:3315.8-3315.87"
           case 1'1
             assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:3242.5-3244.8"
+            attribute \src "ls180.v:3317.5-3319.8"
             switch \main_sdram_bankmachine0_cmd_ready
-              attribute \src "ls180.v:3242.9-3242.42"
+              attribute \src "ls180.v:3317.9-3317.42"
               case 1'1
                 assign $0\builder_bankmachine0_next_state[2:0] 3'101
               case 
@@ -268887,27 +270513,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
-        attribute \src "ls180.v:3252.4-3254.7"
-        switch $and$ls180.v:3252$106_Y
-          attribute \src "ls180.v:3252.8-3252.87"
+        attribute \src "ls180.v:3327.4-3329.7"
+        switch $and$ls180.v:3327$157_Y
+          attribute \src "ls180.v:3327.8-3327.87"
           case 1'1
             assign $0\builder_bankmachine0_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:3258.4-3267.7"
+        attribute \src "ls180.v:3333.4-3342.7"
         switch \main_sdram_bankmachine0_trccon_ready
-          attribute \src "ls180.v:3258.8-3258.44"
+          attribute \src "ls180.v:3333.8-3333.44"
           case 1'1
             assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
             assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
             assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:3263.5-3265.8"
+            attribute \src "ls180.v:3338.5-3340.8"
             switch \main_sdram_bankmachine0_cmd_ready
-              attribute \src "ls180.v:3263.9-3263.42"
+              attribute \src "ls180.v:3338.9-3338.42"
               case 1'1
                 assign $0\builder_bankmachine0_next_state[2:0] 3'110
               case 
@@ -268918,16 +270544,16 @@ module \ls180
       case 3'100
         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
         assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:3270.4-3272.7"
+        attribute \src "ls180.v:3345.4-3347.7"
         switch \main_sdram_bankmachine0_twtpcon_ready
-          attribute \src "ls180.v:3270.8-3270.45"
+          attribute \src "ls180.v:3345.8-3345.45"
           case 1'1
             assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:3275.4-3277.7"
-        switch $not$ls180.v:3275$107_Y
-          attribute \src "ls180.v:3275.8-3275.46"
+        attribute \src "ls180.v:3350.4-3352.7"
+        switch $not$ls180.v:3350$158_Y
+          attribute \src "ls180.v:3350.8-3350.46"
           case 1'1
             assign $0\builder_bankmachine0_next_state[2:0] 3'000
           case 
@@ -268940,51 +270566,51 @@ module \ls180
         assign $0\builder_bankmachine0_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:3286.4-3312.7"
+        attribute \src "ls180.v:3361.4-3387.7"
         switch \main_sdram_bankmachine0_refresh_req
-          attribute \src "ls180.v:3286.8-3286.43"
+          attribute \src "ls180.v:3361.8-3361.43"
           case 1'1
             assign $0\builder_bankmachine0_next_state[2:0] 3'100
-          attribute \src "ls180.v:3288.8-3288.12"
+          attribute \src "ls180.v:3363.8-3363.12"
           case 
-            attribute \src "ls180.v:3289.5-3311.8"
+            attribute \src "ls180.v:3364.5-3386.8"
             switch \main_sdram_bankmachine0_cmd_buffer_source_valid
-              attribute \src "ls180.v:3289.9-3289.56"
+              attribute \src "ls180.v:3364.9-3364.56"
               case 1'1
-                attribute \src "ls180.v:3290.6-3310.9"
+                attribute \src "ls180.v:3365.6-3385.9"
                 switch \main_sdram_bankmachine0_row_opened
-                  attribute \src "ls180.v:3290.10-3290.44"
+                  attribute \src "ls180.v:3365.10-3365.44"
                   case 1'1
-                    attribute \src "ls180.v:3291.7-3307.10"
+                    attribute \src "ls180.v:3366.7-3382.10"
                     switch \main_sdram_bankmachine0_row_hit
-                      attribute \src "ls180.v:3291.11-3291.42"
+                      attribute \src "ls180.v:3366.11-3366.42"
                       case 1'1
                         assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
                         assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:3293.8-3300.11"
+                        attribute \src "ls180.v:3368.8-3375.11"
                         switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:3293.12-3293.64"
+                          attribute \src "ls180.v:3368.12-3368.64"
                           case 1'1
                             assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready
                             assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
                             assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:3297.12-3297.16"
+                          attribute \src "ls180.v:3372.12-3372.16"
                           case 
                             assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready
                             assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:3302.8-3304.11"
-                        switch $and$ls180.v:3302$108_Y
-                          attribute \src "ls180.v:3302.12-3302.88"
+                        attribute \src "ls180.v:3377.8-3379.11"
+                        switch $and$ls180.v:3377$159_Y
+                          attribute \src "ls180.v:3377.12-3377.88"
                           case 1'1
                             assign $0\builder_bankmachine0_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:3305.11-3305.15"
+                      attribute \src "ls180.v:3380.11-3380.15"
                       case 
                         assign $0\builder_bankmachine0_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:3308.10-3308.14"
+                  attribute \src "ls180.v:3383.10-3383.14"
                   case 
                     assign $0\builder_bankmachine0_next_state[2:0] 3'011
                 end
@@ -269008,99 +270634,43 @@ module \ls180
       update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
       update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
   end
-  attribute \src "ls180.v:325.5-325.38"
-  process $proc$ls180.v:325$2857
-    assign { } { }
-    assign $0\main_sdram_command_issue_w[0:0] 1'0
-    sync always
-      update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:326.12-326.46"
-  process $proc$ls180.v:326$2858
-    assign { } { }
-    assign $1\main_sdram_address_storage[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
-  end
-  attribute \src "ls180.v:327.5-327.33"
-  process $proc$ls180.v:327$2859
-    assign { } { }
-    assign $1\main_sdram_address_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_address_re $1\main_sdram_address_re[0:0]
-  end
-  attribute \src "ls180.v:328.11-328.45"
-  process $proc$ls180.v:328$2860
-    assign { } { }
-    assign $1\main_sdram_baddress_storage[1:0] 2'00
-    sync always
-    sync init
-      update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
-  end
-  attribute \src "ls180.v:329.5-329.34"
-  process $proc$ls180.v:329$2861
-    assign { } { }
-    assign $1\main_sdram_baddress_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
-  end
-  attribute \src "ls180.v:330.12-330.45"
-  process $proc$ls180.v:330$2862
-    assign { } { }
-    assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
-  end
-  attribute \src "ls180.v:331.5-331.32"
-  process $proc$ls180.v:331$2863
-    assign { } { }
-    assign $1\main_sdram_wrdata_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
-  end
-  attribute \src "ls180.v:332.12-332.37"
-  process $proc$ls180.v:332$2864
-    assign { } { }
-    assign $1\main_sdram_status[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_sdram_status $1\main_sdram_status[15:0]
-  end
-  attribute \src "ls180.v:3330.1-3337.4"
-  process $proc$ls180.v:3330$112
+  attribute \src "ls180.v:3405.1-3412.4"
+  process $proc$ls180.v:3405$163
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:3332.2-3336.5"
+    attribute \src "ls180.v:3407.2-3411.5"
     switch \main_sdram_bankmachine1_row_col_n_addr_sel
-      attribute \src "ls180.v:3332.6-3332.48"
+      attribute \src "ls180.v:3407.6-3407.48"
       case 1'1
         assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:3334.6-3334.10"
+      attribute \src "ls180.v:3409.6-3409.10"
       case 
-        assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3335$114_Y
+        assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3410$165_Y
     end
     sync always
       update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:3341.1-3348.4"
-  process $proc$ls180.v:3341$121
+  attribute \src "ls180.v:341.12-341.46"
+  process $proc$ls180.v:341$2978
+    assign { } { }
+    assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
+  end
+  attribute \src "ls180.v:3416.1-3423.4"
+  process $proc$ls180.v:3416$172
     assign { } { }
     assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:3343.2-3347.5"
-    switch $and$ls180.v:3343$122_Y
-      attribute \src "ls180.v:3343.6-3343.115"
+    attribute \src "ls180.v:3418.2-3422.5"
+    switch $and$ls180.v:3418$173_Y
+      attribute \src "ls180.v:3418.6-3418.115"
       case 1'1
-        attribute \src "ls180.v:3344.3-3346.6"
-        switch $ne$ls180.v:3344$123_Y
-          attribute \src "ls180.v:3344.7-3344.143"
+        attribute \src "ls180.v:3419.3-3421.6"
+        switch $ne$ls180.v:3419$174_Y
+          attribute \src "ls180.v:3419.7-3419.143"
           case 1'1
-            assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3345$124_Y
+            assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3420$175_Y
           case 
         end
       case 
@@ -269108,24 +270678,56 @@ module \ls180
     sync always
       update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:3363.1-3370.4"
-  process $proc$ls180.v:3363$125
+  attribute \src "ls180.v:342.5-342.44"
+  process $proc$ls180.v:342$2979
+    assign { } { }
+    assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
+  end
+  attribute \src "ls180.v:343.12-343.48"
+  process $proc$ls180.v:343$2980
+    assign { } { }
+    assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
+  end
+  attribute \src "ls180.v:3438.1-3445.4"
+  process $proc$ls180.v:3438$176
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:3365.2-3369.5"
+    attribute \src "ls180.v:3440.2-3444.5"
     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:3365.6-3365.58"
+      attribute \src "ls180.v:3440.6-3440.58"
       case 1'1
-        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3366$126_Y
-      attribute \src "ls180.v:3367.6-3367.10"
+        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3441$177_Y
+      attribute \src "ls180.v:3442.6-3442.10"
       case 
         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
     end
     sync always
       update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:3379.1-3472.4"
-  process $proc$ls180.v:3379$134
+  attribute \src "ls180.v:344.11-344.43"
+  process $proc$ls180.v:344$2981
+    assign { } { }
+    assign $1\main_sdram_master_p0_bank[1:0] 2'00
+    sync always
+    sync init
+      update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
+  end
+  attribute \src "ls180.v:345.5-345.38"
+  process $proc$ls180.v:345$2982
+    assign { } { }
+    assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
+    sync always
+    sync init
+      update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
+  end
+  attribute \src "ls180.v:3454.1-3547.4"
+  process $proc$ls180.v:3454$185
     assign { } { }
     assign { } { }
     assign { } { }
@@ -269140,13 +270742,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
     assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
     assign { } { }
@@ -269154,23 +270749,30 @@ module \ls180
     assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0
     assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state
-    attribute \src "ls180.v:3395.2-3471.9"
+    attribute \src "ls180.v:3470.2-3546.9"
     switch \builder_bankmachine1_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
-        attribute \src "ls180.v:3397.4-3405.7"
-        switch $and$ls180.v:3397$135_Y
-          attribute \src "ls180.v:3397.8-3397.87"
+        attribute \src "ls180.v:3472.4-3480.7"
+        switch $and$ls180.v:3472$186_Y
+          attribute \src "ls180.v:3472.8-3472.87"
           case 1'1
             assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:3399.5-3401.8"
+            attribute \src "ls180.v:3474.5-3476.8"
             switch \main_sdram_bankmachine1_cmd_ready
-              attribute \src "ls180.v:3399.9-3399.42"
+              attribute \src "ls180.v:3474.9-3474.42"
               case 1'1
                 assign $0\builder_bankmachine1_next_state[2:0] 3'101
               case 
@@ -269180,27 +270782,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
-        attribute \src "ls180.v:3409.4-3411.7"
-        switch $and$ls180.v:3409$136_Y
-          attribute \src "ls180.v:3409.8-3409.87"
+        attribute \src "ls180.v:3484.4-3486.7"
+        switch $and$ls180.v:3484$187_Y
+          attribute \src "ls180.v:3484.8-3484.87"
           case 1'1
             assign $0\builder_bankmachine1_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:3415.4-3424.7"
+        attribute \src "ls180.v:3490.4-3499.7"
         switch \main_sdram_bankmachine1_trccon_ready
-          attribute \src "ls180.v:3415.8-3415.44"
+          attribute \src "ls180.v:3490.8-3490.44"
           case 1'1
             assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
             assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
             assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:3420.5-3422.8"
+            attribute \src "ls180.v:3495.5-3497.8"
             switch \main_sdram_bankmachine1_cmd_ready
-              attribute \src "ls180.v:3420.9-3420.42"
+              attribute \src "ls180.v:3495.9-3495.42"
               case 1'1
                 assign $0\builder_bankmachine1_next_state[2:0] 3'110
               case 
@@ -269211,16 +270813,16 @@ module \ls180
       case 3'100
         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
         assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:3427.4-3429.7"
+        attribute \src "ls180.v:3502.4-3504.7"
         switch \main_sdram_bankmachine1_twtpcon_ready
-          attribute \src "ls180.v:3427.8-3427.45"
+          attribute \src "ls180.v:3502.8-3502.45"
           case 1'1
             assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:3432.4-3434.7"
-        switch $not$ls180.v:3432$137_Y
-          attribute \src "ls180.v:3432.8-3432.46"
+        attribute \src "ls180.v:3507.4-3509.7"
+        switch $not$ls180.v:3507$188_Y
+          attribute \src "ls180.v:3507.8-3507.46"
           case 1'1
             assign $0\builder_bankmachine1_next_state[2:0] 3'000
           case 
@@ -269233,51 +270835,51 @@ module \ls180
         assign $0\builder_bankmachine1_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:3443.4-3469.7"
+        attribute \src "ls180.v:3518.4-3544.7"
         switch \main_sdram_bankmachine1_refresh_req
-          attribute \src "ls180.v:3443.8-3443.43"
+          attribute \src "ls180.v:3518.8-3518.43"
           case 1'1
             assign $0\builder_bankmachine1_next_state[2:0] 3'100
-          attribute \src "ls180.v:3445.8-3445.12"
+          attribute \src "ls180.v:3520.8-3520.12"
           case 
-            attribute \src "ls180.v:3446.5-3468.8"
+            attribute \src "ls180.v:3521.5-3543.8"
             switch \main_sdram_bankmachine1_cmd_buffer_source_valid
-              attribute \src "ls180.v:3446.9-3446.56"
+              attribute \src "ls180.v:3521.9-3521.56"
               case 1'1
-                attribute \src "ls180.v:3447.6-3467.9"
+                attribute \src "ls180.v:3522.6-3542.9"
                 switch \main_sdram_bankmachine1_row_opened
-                  attribute \src "ls180.v:3447.10-3447.44"
+                  attribute \src "ls180.v:3522.10-3522.44"
                   case 1'1
-                    attribute \src "ls180.v:3448.7-3464.10"
+                    attribute \src "ls180.v:3523.7-3539.10"
                     switch \main_sdram_bankmachine1_row_hit
-                      attribute \src "ls180.v:3448.11-3448.42"
+                      attribute \src "ls180.v:3523.11-3523.42"
                       case 1'1
                         assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
                         assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:3450.8-3457.11"
+                        attribute \src "ls180.v:3525.8-3532.11"
                         switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:3450.12-3450.64"
+                          attribute \src "ls180.v:3525.12-3525.64"
                           case 1'1
                             assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready
                             assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
                             assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:3454.12-3454.16"
+                          attribute \src "ls180.v:3529.12-3529.16"
                           case 
                             assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready
                             assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:3459.8-3461.11"
-                        switch $and$ls180.v:3459$138_Y
-                          attribute \src "ls180.v:3459.12-3459.88"
+                        attribute \src "ls180.v:3534.8-3536.11"
+                        switch $and$ls180.v:3534$189_Y
+                          attribute \src "ls180.v:3534.12-3534.88"
                           case 1'1
                             assign $0\builder_bankmachine1_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:3462.11-3462.15"
+                      attribute \src "ls180.v:3537.11-3537.15"
                       case 
                         assign $0\builder_bankmachine1_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:3465.10-3465.14"
+                  attribute \src "ls180.v:3540.10-3540.14"
                   case 
                     assign $0\builder_bankmachine1_next_state[2:0] 3'011
                 end
@@ -269301,35 +270903,123 @@ module \ls180
       update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
       update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0]
   end
-  attribute \src "ls180.v:3487.1-3494.4"
-  process $proc$ls180.v:3487$142
+  attribute \src "ls180.v:346.5-346.37"
+  process $proc$ls180.v:346$2983
+    assign { } { }
+    assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
+    sync always
+    sync init
+      update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
+  end
+  attribute \src "ls180.v:347.5-347.38"
+  process $proc$ls180.v:347$2984
+    assign { } { }
+    assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
+    sync always
+    sync init
+      update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
+  end
+  attribute \src "ls180.v:348.5-348.37"
+  process $proc$ls180.v:348$2985
+    assign { } { }
+    assign $1\main_sdram_master_p0_we_n[0:0] 1'1
+    sync always
+    sync init
+      update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
+  end
+  attribute \src "ls180.v:349.5-349.36"
+  process $proc$ls180.v:349$2986
+    assign { } { }
+    assign $1\main_sdram_master_p0_cke[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
+  end
+  attribute \src "ls180.v:350.5-350.36"
+  process $proc$ls180.v:350$2987
+    assign { } { }
+    assign $1\main_sdram_master_p0_odt[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
+  end
+  attribute \src "ls180.v:351.5-351.40"
+  process $proc$ls180.v:351$2988
+    assign { } { }
+    assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
+  end
+  attribute \src "ls180.v:352.5-352.38"
+  process $proc$ls180.v:352$2989
+    assign { } { }
+    assign $1\main_sdram_master_p0_act_n[0:0] 1'1
+    sync always
+    sync init
+      update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
+  end
+  attribute \src "ls180.v:353.12-353.47"
+  process $proc$ls180.v:353$2990
+    assign { } { }
+    assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
+  end
+  attribute \src "ls180.v:354.5-354.42"
+  process $proc$ls180.v:354$2991
+    assign { } { }
+    assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
+  end
+  attribute \src "ls180.v:355.11-355.50"
+  process $proc$ls180.v:355$2992
+    assign { } { }
+    assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
+    sync always
+    sync init
+      update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
+  end
+  attribute \src "ls180.v:356.5-356.42"
+  process $proc$ls180.v:356$2993
+    assign { } { }
+    assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
+  end
+  attribute \src "ls180.v:3562.1-3569.4"
+  process $proc$ls180.v:3562$193
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:3489.2-3493.5"
+    attribute \src "ls180.v:3564.2-3568.5"
     switch \main_sdram_bankmachine2_row_col_n_addr_sel
-      attribute \src "ls180.v:3489.6-3489.48"
+      attribute \src "ls180.v:3564.6-3564.48"
       case 1'1
         assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:3491.6-3491.10"
+      attribute \src "ls180.v:3566.6-3566.10"
       case 
-        assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3492$144_Y
+        assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3567$195_Y
     end
     sync always
       update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:3498.1-3505.4"
-  process $proc$ls180.v:3498$151
+  attribute \src "ls180.v:3573.1-3580.4"
+  process $proc$ls180.v:3573$202
     assign { } { }
     assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:3500.2-3504.5"
-    switch $and$ls180.v:3500$152_Y
-      attribute \src "ls180.v:3500.6-3500.115"
+    attribute \src "ls180.v:3575.2-3579.5"
+    switch $and$ls180.v:3575$203_Y
+      attribute \src "ls180.v:3575.6-3575.115"
       case 1'1
-        attribute \src "ls180.v:3501.3-3503.6"
-        switch $ne$ls180.v:3501$153_Y
-          attribute \src "ls180.v:3501.7-3501.143"
+        attribute \src "ls180.v:3576.3-3578.6"
+        switch $ne$ls180.v:3576$204_Y
+          attribute \src "ls180.v:3576.7-3576.143"
           case 1'1
-            assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3502$154_Y
+            assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3577$205_Y
           case 
         end
       case 
@@ -269337,24 +271027,24 @@ module \ls180
     sync always
       update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:3520.1-3527.4"
-  process $proc$ls180.v:3520$155
+  attribute \src "ls180.v:3595.1-3602.4"
+  process $proc$ls180.v:3595$206
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:3522.2-3526.5"
+    attribute \src "ls180.v:3597.2-3601.5"
     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:3522.6-3522.58"
+      attribute \src "ls180.v:3597.6-3597.58"
       case 1'1
-        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3523$156_Y
-      attribute \src "ls180.v:3524.6-3524.10"
+        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3598$207_Y
+      attribute \src "ls180.v:3599.6-3599.10"
       case 
         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
     end
     sync always
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:3536.1-3629.4"
-  process $proc$ls180.v:3536$164
+  attribute \src "ls180.v:3611.1-3704.4"
+  process $proc$ls180.v:3611$215
     assign { } { }
     assign { } { }
     assign { } { }
@@ -269369,37 +271059,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
+    assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+    assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
+    assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
+    assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0
     assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
-    assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
-    assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
-    assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
-    assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
-    assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
     assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state
-    attribute \src "ls180.v:3552.2-3628.9"
+    attribute \src "ls180.v:3627.2-3703.9"
     switch \builder_bankmachine2_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
-        attribute \src "ls180.v:3554.4-3562.7"
-        switch $and$ls180.v:3554$165_Y
-          attribute \src "ls180.v:3554.8-3554.87"
+        attribute \src "ls180.v:3629.4-3637.7"
+        switch $and$ls180.v:3629$216_Y
+          attribute \src "ls180.v:3629.8-3629.87"
           case 1'1
             assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:3556.5-3558.8"
+            attribute \src "ls180.v:3631.5-3633.8"
             switch \main_sdram_bankmachine2_cmd_ready
-              attribute \src "ls180.v:3556.9-3556.42"
+              attribute \src "ls180.v:3631.9-3631.42"
               case 1'1
                 assign $0\builder_bankmachine2_next_state[2:0] 3'101
               case 
@@ -269409,27 +271099,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
-        attribute \src "ls180.v:3566.4-3568.7"
-        switch $and$ls180.v:3566$166_Y
-          attribute \src "ls180.v:3566.8-3566.87"
+        attribute \src "ls180.v:3641.4-3643.7"
+        switch $and$ls180.v:3641$217_Y
+          attribute \src "ls180.v:3641.8-3641.87"
           case 1'1
             assign $0\builder_bankmachine2_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:3572.4-3581.7"
+        attribute \src "ls180.v:3647.4-3656.7"
         switch \main_sdram_bankmachine2_trccon_ready
-          attribute \src "ls180.v:3572.8-3572.44"
+          attribute \src "ls180.v:3647.8-3647.44"
           case 1'1
             assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
             assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
             assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:3577.5-3579.8"
+            attribute \src "ls180.v:3652.5-3654.8"
             switch \main_sdram_bankmachine2_cmd_ready
-              attribute \src "ls180.v:3577.9-3577.42"
+              attribute \src "ls180.v:3652.9-3652.42"
               case 1'1
                 assign $0\builder_bankmachine2_next_state[2:0] 3'110
               case 
@@ -269440,16 +271130,16 @@ module \ls180
       case 3'100
         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
         assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:3584.4-3586.7"
+        attribute \src "ls180.v:3659.4-3661.7"
         switch \main_sdram_bankmachine2_twtpcon_ready
-          attribute \src "ls180.v:3584.8-3584.45"
+          attribute \src "ls180.v:3659.8-3659.45"
           case 1'1
             assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:3589.4-3591.7"
-        switch $not$ls180.v:3589$167_Y
-          attribute \src "ls180.v:3589.8-3589.46"
+        attribute \src "ls180.v:3664.4-3666.7"
+        switch $not$ls180.v:3664$218_Y
+          attribute \src "ls180.v:3664.8-3664.46"
           case 1'1
             assign $0\builder_bankmachine2_next_state[2:0] 3'000
           case 
@@ -269462,51 +271152,51 @@ module \ls180
         assign $0\builder_bankmachine2_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:3600.4-3626.7"
+        attribute \src "ls180.v:3675.4-3701.7"
         switch \main_sdram_bankmachine2_refresh_req
-          attribute \src "ls180.v:3600.8-3600.43"
+          attribute \src "ls180.v:3675.8-3675.43"
           case 1'1
             assign $0\builder_bankmachine2_next_state[2:0] 3'100
-          attribute \src "ls180.v:3602.8-3602.12"
+          attribute \src "ls180.v:3677.8-3677.12"
           case 
-            attribute \src "ls180.v:3603.5-3625.8"
+            attribute \src "ls180.v:3678.5-3700.8"
             switch \main_sdram_bankmachine2_cmd_buffer_source_valid
-              attribute \src "ls180.v:3603.9-3603.56"
+              attribute \src "ls180.v:3678.9-3678.56"
               case 1'1
-                attribute \src "ls180.v:3604.6-3624.9"
+                attribute \src "ls180.v:3679.6-3699.9"
                 switch \main_sdram_bankmachine2_row_opened
-                  attribute \src "ls180.v:3604.10-3604.44"
+                  attribute \src "ls180.v:3679.10-3679.44"
                   case 1'1
-                    attribute \src "ls180.v:3605.7-3621.10"
+                    attribute \src "ls180.v:3680.7-3696.10"
                     switch \main_sdram_bankmachine2_row_hit
-                      attribute \src "ls180.v:3605.11-3605.42"
+                      attribute \src "ls180.v:3680.11-3680.42"
                       case 1'1
                         assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
                         assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:3607.8-3614.11"
+                        attribute \src "ls180.v:3682.8-3689.11"
                         switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:3607.12-3607.64"
+                          attribute \src "ls180.v:3682.12-3682.64"
                           case 1'1
                             assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready
                             assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
                             assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:3611.12-3611.16"
+                          attribute \src "ls180.v:3686.12-3686.16"
                           case 
                             assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready
                             assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:3616.8-3618.11"
-                        switch $and$ls180.v:3616$168_Y
-                          attribute \src "ls180.v:3616.12-3616.88"
+                        attribute \src "ls180.v:3691.8-3693.11"
+                        switch $and$ls180.v:3691$219_Y
+                          attribute \src "ls180.v:3691.12-3691.88"
                           case 1'1
                             assign $0\builder_bankmachine2_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:3619.11-3619.15"
+                      attribute \src "ls180.v:3694.11-3694.15"
                       case 
                         assign $0\builder_bankmachine2_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:3622.10-3622.14"
+                  attribute \src "ls180.v:3697.10-3697.14"
                   case 
                     assign $0\builder_bankmachine2_next_state[2:0] 3'011
                 end
@@ -269530,59 +271220,99 @@ module \ls180
       update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
       update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0]
   end
-  attribute \src "ls180.v:362.12-362.46"
-  process $proc$ls180.v:362$2865
+  attribute \src "ls180.v:363.11-363.36"
+  process $proc$ls180.v:363$2994
     assign { } { }
-    assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
+    assign $1\main_sdram_storage[3:0] 4'0001
     sync always
     sync init
-      update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
+      update \main_sdram_storage $1\main_sdram_storage[3:0]
   end
-  attribute \src "ls180.v:363.11-363.47"
-  process $proc$ls180.v:363$2866
+  attribute \src "ls180.v:364.5-364.25"
+  process $proc$ls180.v:364$2995
     assign { } { }
-    assign $1\main_sdram_interface_wdata_we[1:0] 2'00
+    assign $1\main_sdram_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
+      update \main_sdram_re $1\main_sdram_re[0:0]
+  end
+  attribute \src "ls180.v:365.11-365.44"
+  process $proc$ls180.v:365$2996
+    assign { } { }
+    assign $1\main_sdram_command_storage[5:0] 6'000000
+    sync always
+    sync init
+      update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
+  end
+  attribute \src "ls180.v:366.5-366.33"
+  process $proc$ls180.v:366$2997
+    assign { } { }
+    assign $1\main_sdram_command_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_command_re $1\main_sdram_command_re[0:0]
   end
-  attribute \src "ls180.v:3644.1-3651.4"
-  process $proc$ls180.v:3644$172
+  attribute \src "ls180.v:370.5-370.38"
+  process $proc$ls180.v:370$2998
+    assign { } { }
+    assign $0\main_sdram_command_issue_w[0:0] 1'0
+    sync always
+      update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:371.12-371.46"
+  process $proc$ls180.v:371$2999
+    assign { } { }
+    assign $1\main_sdram_address_storage[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
+  end
+  attribute \src "ls180.v:3719.1-3726.4"
+  process $proc$ls180.v:3719$223
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:3646.2-3650.5"
+    attribute \src "ls180.v:3721.2-3725.5"
     switch \main_sdram_bankmachine3_row_col_n_addr_sel
-      attribute \src "ls180.v:3646.6-3646.48"
+      attribute \src "ls180.v:3721.6-3721.48"
       case 1'1
         assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:3648.6-3648.10"
+      attribute \src "ls180.v:3723.6-3723.10"
       case 
-        assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3649$174_Y
+        assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3724$225_Y
     end
     sync always
       update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:365.12-365.45"
-  process $proc$ls180.v:365$2867
+  attribute \src "ls180.v:372.5-372.33"
+  process $proc$ls180.v:372$3000
     assign { } { }
-    assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
+    assign $1\main_sdram_address_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
+      update \main_sdram_address_re $1\main_sdram_address_re[0:0]
+  end
+  attribute \src "ls180.v:373.11-373.45"
+  process $proc$ls180.v:373$3001
+    assign { } { }
+    assign $1\main_sdram_baddress_storage[1:0] 2'00
+    sync always
+    sync init
+      update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
   end
-  attribute \src "ls180.v:3655.1-3662.4"
-  process $proc$ls180.v:3655$181
+  attribute \src "ls180.v:3730.1-3737.4"
+  process $proc$ls180.v:3730$232
     assign { } { }
     assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:3657.2-3661.5"
-    switch $and$ls180.v:3657$182_Y
-      attribute \src "ls180.v:3657.6-3657.115"
+    attribute \src "ls180.v:3732.2-3736.5"
+    switch $and$ls180.v:3732$233_Y
+      attribute \src "ls180.v:3732.6-3732.115"
       case 1'1
-        attribute \src "ls180.v:3658.3-3660.6"
-        switch $ne$ls180.v:3658$183_Y
-          attribute \src "ls180.v:3658.7-3658.143"
+        attribute \src "ls180.v:3733.3-3735.6"
+        switch $ne$ls180.v:3733$234_Y
+          attribute \src "ls180.v:3733.7-3733.143"
           case 1'1
-            assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3659$184_Y
+            assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3734$235_Y
           case 
         end
       case 
@@ -269590,56 +271320,48 @@ module \ls180
     sync always
       update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:366.11-366.40"
-  process $proc$ls180.v:366$2868
+  attribute \src "ls180.v:374.5-374.34"
+  process $proc$ls180.v:374$3002
     assign { } { }
-    assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
+    assign $1\main_sdram_baddress_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
+      update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
   end
-  attribute \src "ls180.v:367.5-367.35"
-  process $proc$ls180.v:367$2869
+  attribute \src "ls180.v:375.12-375.45"
+  process $proc$ls180.v:375$3003
     assign { } { }
-    assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
+    assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
+      update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
   end
-  attribute \src "ls180.v:3677.1-3684.4"
-  process $proc$ls180.v:3677$185
+  attribute \src "ls180.v:3752.1-3759.4"
+  process $proc$ls180.v:3752$236
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:3679.2-3683.5"
+    attribute \src "ls180.v:3754.2-3758.5"
     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:3679.6-3679.58"
+      attribute \src "ls180.v:3754.6-3754.58"
       case 1'1
-        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3680$186_Y
-      attribute \src "ls180.v:3681.6-3681.10"
+        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3755$237_Y
+      attribute \src "ls180.v:3756.6-3756.10"
       case 
         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
     end
     sync always
       update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:368.5-368.34"
-  process $proc$ls180.v:368$2870
-    assign { } { }
-    assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
-  end
-  attribute \src "ls180.v:369.5-369.35"
-  process $proc$ls180.v:369$2871
+  attribute \src "ls180.v:376.5-376.32"
+  process $proc$ls180.v:376$3004
     assign { } { }
-    assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
+    assign $1\main_sdram_wrdata_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
+      update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
   end
-  attribute \src "ls180.v:3693.1-3786.4"
-  process $proc$ls180.v:3693$194
+  attribute \src "ls180.v:3768.1-3861.4"
+  process $proc$ls180.v:3768$245
     assign { } { }
     assign { } { }
     assign { } { }
@@ -269654,37 +271376,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
-    assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
-    assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
     assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
+    assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
     assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
+    assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
+    assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
+    assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
+    assign { } { }
     assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state
-    attribute \src "ls180.v:3709.2-3785.9"
+    attribute \src "ls180.v:3784.2-3860.9"
     switch \builder_bankmachine3_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
-        attribute \src "ls180.v:3711.4-3719.7"
-        switch $and$ls180.v:3711$195_Y
-          attribute \src "ls180.v:3711.8-3711.87"
+        attribute \src "ls180.v:3786.4-3794.7"
+        switch $and$ls180.v:3786$246_Y
+          attribute \src "ls180.v:3786.8-3786.87"
           case 1'1
             assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:3713.5-3715.8"
+            attribute \src "ls180.v:3788.5-3790.8"
             switch \main_sdram_bankmachine3_cmd_ready
-              attribute \src "ls180.v:3713.9-3713.42"
+              attribute \src "ls180.v:3788.9-3788.42"
               case 1'1
                 assign $0\builder_bankmachine3_next_state[2:0] 3'101
               case 
@@ -269694,27 +271416,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
-        attribute \src "ls180.v:3723.4-3725.7"
-        switch $and$ls180.v:3723$196_Y
-          attribute \src "ls180.v:3723.8-3723.87"
+        attribute \src "ls180.v:3798.4-3800.7"
+        switch $and$ls180.v:3798$247_Y
+          attribute \src "ls180.v:3798.8-3798.87"
           case 1'1
             assign $0\builder_bankmachine3_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:3729.4-3738.7"
+        attribute \src "ls180.v:3804.4-3813.7"
         switch \main_sdram_bankmachine3_trccon_ready
-          attribute \src "ls180.v:3729.8-3729.44"
+          attribute \src "ls180.v:3804.8-3804.44"
           case 1'1
             assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
             assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
             assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:3734.5-3736.8"
+            attribute \src "ls180.v:3809.5-3811.8"
             switch \main_sdram_bankmachine3_cmd_ready
-              attribute \src "ls180.v:3734.9-3734.42"
+              attribute \src "ls180.v:3809.9-3809.42"
               case 1'1
                 assign $0\builder_bankmachine3_next_state[2:0] 3'110
               case 
@@ -269725,16 +271447,16 @@ module \ls180
       case 3'100
         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
         assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:3741.4-3743.7"
+        attribute \src "ls180.v:3816.4-3818.7"
         switch \main_sdram_bankmachine3_twtpcon_ready
-          attribute \src "ls180.v:3741.8-3741.45"
+          attribute \src "ls180.v:3816.8-3816.45"
           case 1'1
             assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:3746.4-3748.7"
-        switch $not$ls180.v:3746$197_Y
-          attribute \src "ls180.v:3746.8-3746.46"
+        attribute \src "ls180.v:3821.4-3823.7"
+        switch $not$ls180.v:3821$248_Y
+          attribute \src "ls180.v:3821.8-3821.46"
           case 1'1
             assign $0\builder_bankmachine3_next_state[2:0] 3'000
           case 
@@ -269747,51 +271469,51 @@ module \ls180
         assign $0\builder_bankmachine3_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:3757.4-3783.7"
+        attribute \src "ls180.v:3832.4-3858.7"
         switch \main_sdram_bankmachine3_refresh_req
-          attribute \src "ls180.v:3757.8-3757.43"
+          attribute \src "ls180.v:3832.8-3832.43"
           case 1'1
             assign $0\builder_bankmachine3_next_state[2:0] 3'100
-          attribute \src "ls180.v:3759.8-3759.12"
+          attribute \src "ls180.v:3834.8-3834.12"
           case 
-            attribute \src "ls180.v:3760.5-3782.8"
+            attribute \src "ls180.v:3835.5-3857.8"
             switch \main_sdram_bankmachine3_cmd_buffer_source_valid
-              attribute \src "ls180.v:3760.9-3760.56"
+              attribute \src "ls180.v:3835.9-3835.56"
               case 1'1
-                attribute \src "ls180.v:3761.6-3781.9"
+                attribute \src "ls180.v:3836.6-3856.9"
                 switch \main_sdram_bankmachine3_row_opened
-                  attribute \src "ls180.v:3761.10-3761.44"
+                  attribute \src "ls180.v:3836.10-3836.44"
                   case 1'1
-                    attribute \src "ls180.v:3762.7-3778.10"
+                    attribute \src "ls180.v:3837.7-3853.10"
                     switch \main_sdram_bankmachine3_row_hit
-                      attribute \src "ls180.v:3762.11-3762.42"
+                      attribute \src "ls180.v:3837.11-3837.42"
                       case 1'1
                         assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
                         assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:3764.8-3771.11"
+                        attribute \src "ls180.v:3839.8-3846.11"
                         switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:3764.12-3764.64"
+                          attribute \src "ls180.v:3839.12-3839.64"
                           case 1'1
                             assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready
                             assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
                             assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:3768.12-3768.16"
+                          attribute \src "ls180.v:3843.12-3843.16"
                           case 
                             assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready
                             assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:3773.8-3775.11"
-                        switch $and$ls180.v:3773$198_Y
-                          attribute \src "ls180.v:3773.12-3773.88"
+                        attribute \src "ls180.v:3848.8-3850.11"
+                        switch $and$ls180.v:3848$249_Y
+                          attribute \src "ls180.v:3848.12-3848.88"
                           case 1'1
                             assign $0\builder_bankmachine3_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:3776.11-3776.15"
+                      attribute \src "ls180.v:3851.11-3851.15"
                       case 
                         assign $0\builder_bankmachine3_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:3779.10-3779.14"
+                  attribute \src "ls180.v:3854.10-3854.14"
                   case 
                     assign $0\builder_bankmachine3_next_state[2:0] 3'011
                 end
@@ -269815,72 +271537,32 @@ module \ls180
       update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
       update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
   end
-  attribute \src "ls180.v:370.5-370.34"
-  process $proc$ls180.v:370$2872
+  attribute \src "ls180.v:377.12-377.37"
+  process $proc$ls180.v:377$3005
     assign { } { }
-    assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
-    sync always
-    sync init
-      update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
-  end
-  attribute \src "ls180.v:374.5-374.35"
-  process $proc$ls180.v:374$2873
-    assign { } { }
-    assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
-    sync always
-      update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:376.5-376.39"
-  process $proc$ls180.v:376$2874
-    assign { } { }
-    assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
-  end
-  attribute \src "ls180.v:378.5-378.39"
-  process $proc$ls180.v:378$2875
-    assign { } { }
-    assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
+    assign $1\main_sdram_status[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
+      update \main_sdram_status $1\main_sdram_status[15:0]
   end
-  attribute \src "ls180.v:3806.1-3812.4"
-  process $proc$ls180.v:3806$237
+  attribute \src "ls180.v:3881.1-3887.4"
+  process $proc$ls180.v:3881$288
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3808$250_Y
-    assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3809$263_Y
-    assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3810$276_Y
-    assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3811$289_Y
+    assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3883$301_Y
+    assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3884$314_Y
+    assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3885$327_Y
+    assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3886$340_Y
     sync always
       update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
   end
-  attribute \src "ls180.v:381.5-381.32"
-  process $proc$ls180.v:381$2876
-    assign { } { }
-    assign $1\main_sdram_cmd_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
-  end
-  attribute \src "ls180.v:382.5-382.32"
-  process $proc$ls180.v:382$2877
-    assign { } { }
-    assign $1\main_sdram_cmd_ready[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
-  end
-  attribute \src "ls180.v:3820.1-3825.4"
-  process $proc$ls180.v:3820$290
+  attribute \src "ls180.v:3895.1-3900.4"
+  process $proc$ls180.v:3895$341
     assign { } { }
     assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
-    attribute \src "ls180.v:3822.2-3824.5"
+    attribute \src "ls180.v:3897.2-3899.5"
     switch \main_sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:3822.6-3822.37"
+      attribute \src "ls180.v:3897.6-3897.37"
       case 1'1
         assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0
       case 
@@ -269888,13 +271570,13 @@ module \ls180
     sync always
       update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:3826.1-3831.4"
-  process $proc$ls180.v:3826$291
+  attribute \src "ls180.v:3901.1-3906.4"
+  process $proc$ls180.v:3901$342
     assign { } { }
     assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
-    attribute \src "ls180.v:3828.2-3830.5"
+    attribute \src "ls180.v:3903.2-3905.5"
     switch \main_sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:3828.6-3828.37"
+      attribute \src "ls180.v:3903.6-3903.37"
       case 1'1
         assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1
       case 
@@ -269902,21 +271584,13 @@ module \ls180
     sync always
       update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:383.5-383.31"
-  process $proc$ls180.v:383$2878
-    assign { } { }
-    assign $1\main_sdram_cmd_last[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
-  end
-  attribute \src "ls180.v:3832.1-3837.4"
-  process $proc$ls180.v:3832$292
+  attribute \src "ls180.v:3907.1-3912.4"
+  process $proc$ls180.v:3907$343
     assign { } { }
     assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
-    attribute \src "ls180.v:3834.2-3836.5"
+    attribute \src "ls180.v:3909.2-3911.5"
     switch \main_sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:3834.6-3834.37"
+      attribute \src "ls180.v:3909.6-3909.37"
       case 1'1
         assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2
       case 
@@ -269924,40 +271598,24 @@ module \ls180
     sync always
       update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:3839.1-3845.4"
-  process $proc$ls180.v:3839$295
+  attribute \src "ls180.v:3914.1-3920.4"
+  process $proc$ls180.v:3914$346
     assign { } { }
     assign { } { }
-    assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3841$308_Y
-    assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3842$321_Y
-    assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3843$334_Y
-    assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3844$347_Y
+    assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3916$359_Y
+    assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3917$372_Y
+    assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3918$385_Y
+    assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3919$398_Y
     sync always
       update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
   end
-  attribute \src "ls180.v:384.12-384.44"
-  process $proc$ls180.v:384$2879
-    assign { } { }
-    assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
-  end
-  attribute \src "ls180.v:385.11-385.43"
-  process $proc$ls180.v:385$2880
-    assign { } { }
-    assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
-    sync always
-    sync init
-      update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
-  end
-  attribute \src "ls180.v:3853.1-3858.4"
-  process $proc$ls180.v:3853$348
+  attribute \src "ls180.v:3928.1-3933.4"
+  process $proc$ls180.v:3928$399
     assign { } { }
     assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
-    attribute \src "ls180.v:3855.2-3857.5"
+    attribute \src "ls180.v:3930.2-3932.5"
     switch \main_sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:3855.6-3855.37"
+      attribute \src "ls180.v:3930.6-3930.37"
       case 1'1
         assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3
       case 
@@ -269965,13 +271623,13 @@ module \ls180
     sync always
       update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:3859.1-3864.4"
-  process $proc$ls180.v:3859$349
+  attribute \src "ls180.v:3934.1-3939.4"
+  process $proc$ls180.v:3934$400
     assign { } { }
     assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
-    attribute \src "ls180.v:3861.2-3863.5"
+    attribute \src "ls180.v:3936.2-3938.5"
     switch \main_sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:3861.6-3861.37"
+      attribute \src "ls180.v:3936.6-3936.37"
       case 1'1
         assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4
       case 
@@ -269979,21 +271637,13 @@ module \ls180
     sync always
       update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:386.5-386.38"
-  process $proc$ls180.v:386$2881
-    assign { } { }
-    assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
-  end
-  attribute \src "ls180.v:3865.1-3870.4"
-  process $proc$ls180.v:3865$350
+  attribute \src "ls180.v:3940.1-3945.4"
+  process $proc$ls180.v:3940$401
     assign { } { }
     assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
-    attribute \src "ls180.v:3867.2-3869.5"
+    attribute \src "ls180.v:3942.2-3944.5"
     switch \main_sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:3867.6-3867.37"
+      attribute \src "ls180.v:3942.6-3942.37"
       case 1'1
         assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5
       case 
@@ -270001,28 +271651,20 @@ module \ls180
     sync always
       update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:387.5-387.38"
-  process $proc$ls180.v:387$2882
-    assign { } { }
-    assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
-  end
-  attribute \src "ls180.v:3871.1-3879.4"
-  process $proc$ls180.v:3871$351
+  attribute \src "ls180.v:3946.1-3954.4"
+  process $proc$ls180.v:3946$402
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:3873.2-3875.5"
-    switch $and$ls180.v:3873$354_Y
-      attribute \src "ls180.v:3873.6-3873.115"
+    attribute \src "ls180.v:3948.2-3950.5"
+    switch $and$ls180.v:3948$405_Y
+      attribute \src "ls180.v:3948.6-3948.115"
       case 1'1
         assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:3876.2-3878.5"
-    switch $and$ls180.v:3876$357_Y
-      attribute \src "ls180.v:3876.6-3876.115"
+    attribute \src "ls180.v:3951.2-3953.5"
+    switch $and$ls180.v:3951$408_Y
+      attribute \src "ls180.v:3951.6-3951.115"
       case 1'1
         assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
       case 
@@ -270030,28 +271672,20 @@ module \ls180
     sync always
       update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:388.5-388.37"
-  process $proc$ls180.v:388$2883
-    assign { } { }
-    assign $1\main_sdram_cmd_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
-  end
-  attribute \src "ls180.v:3880.1-3888.4"
-  process $proc$ls180.v:3880$358
+  attribute \src "ls180.v:3955.1-3963.4"
+  process $proc$ls180.v:3955$409
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:3882.2-3884.5"
-    switch $and$ls180.v:3882$361_Y
-      attribute \src "ls180.v:3882.6-3882.115"
+    attribute \src "ls180.v:3957.2-3959.5"
+    switch $and$ls180.v:3957$412_Y
+      attribute \src "ls180.v:3957.6-3957.115"
       case 1'1
         assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:3885.2-3887.5"
-    switch $and$ls180.v:3885$364_Y
-      attribute \src "ls180.v:3885.6-3885.115"
+    attribute \src "ls180.v:3960.2-3962.5"
+    switch $and$ls180.v:3960$415_Y
+      attribute \src "ls180.v:3960.6-3960.115"
       case 1'1
         assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
       case 
@@ -270059,20 +271693,20 @@ module \ls180
     sync always
       update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:3889.1-3897.4"
-  process $proc$ls180.v:3889$365
+  attribute \src "ls180.v:3964.1-3972.4"
+  process $proc$ls180.v:3964$416
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:3891.2-3893.5"
-    switch $and$ls180.v:3891$368_Y
-      attribute \src "ls180.v:3891.6-3891.115"
+    attribute \src "ls180.v:3966.2-3968.5"
+    switch $and$ls180.v:3966$419_Y
+      attribute \src "ls180.v:3966.6-3966.115"
       case 1'1
         assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:3894.2-3896.5"
-    switch $and$ls180.v:3894$371_Y
-      attribute \src "ls180.v:3894.6-3894.115"
+    attribute \src "ls180.v:3969.2-3971.5"
+    switch $and$ls180.v:3969$422_Y
+      attribute \src "ls180.v:3969.6-3969.115"
       case 1'1
         assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
       case 
@@ -270080,28 +271714,20 @@ module \ls180
     sync always
       update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:389.5-389.42"
-  process $proc$ls180.v:389$2884
-    assign { } { }
-    assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
-    sync always
-      update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:3898.1-3906.4"
-  process $proc$ls180.v:3898$372
+  attribute \src "ls180.v:3973.1-3981.4"
+  process $proc$ls180.v:3973$423
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:3900.2-3902.5"
-    switch $and$ls180.v:3900$375_Y
-      attribute \src "ls180.v:3900.6-3900.115"
+    attribute \src "ls180.v:3975.2-3977.5"
+    switch $and$ls180.v:3975$426_Y
+      attribute \src "ls180.v:3975.6-3975.115"
       case 1'1
         assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:3903.2-3905.5"
-    switch $and$ls180.v:3903$378_Y
-      attribute \src "ls180.v:3903.6-3903.115"
+    attribute \src "ls180.v:3978.2-3980.5"
+    switch $and$ls180.v:3978$429_Y
+      attribute \src "ls180.v:3978.6-3978.115"
       case 1'1
         assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
       case 
@@ -270109,16 +271735,8 @@ module \ls180
     sync always
       update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:390.5-390.43"
-  process $proc$ls180.v:390$2885
-    assign { } { }
-    assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
-    sync always
-      update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:3911.1-3983.4"
-  process $proc$ls180.v:3911$381
+  attribute \src "ls180.v:3986.1-4058.4"
+  process $proc$ls180.v:3986$432
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270128,47 +271746,47 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdram_en1[0:0] 1'0
+    assign $0\main_sdram_choose_req_want_reads[0:0] 1'0
+    assign $0\main_sdram_choose_req_want_writes[0:0] 1'0
+    assign $0\main_sdram_cmd_ready[0:0] 1'0
     assign { } { }
     assign $0\main_sdram_steerer_sel[1:0] 2'00
     assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0
     assign { } { }
     assign $0\main_sdram_en0[0:0] 1'0
-    assign $0\main_sdram_en1[0:0] 1'0
-    assign $0\main_sdram_choose_req_want_reads[0:0] 1'0
-    assign $0\main_sdram_choose_req_want_writes[0:0] 1'0
-    assign $0\main_sdram_cmd_ready[0:0] 1'0
     assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed
     assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state
-    attribute \src "ls180.v:3923.2-3982.9"
+    attribute \src "ls180.v:3998.2-4057.9"
     switch \builder_multiplexer_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdram_en1[0:0] 1'1
         assign $0\main_sdram_choose_req_want_writes[0:0] 1'1
         assign $0\main_sdram_steerer_sel[1:0] 2'10
-        attribute \src "ls180.v:3927.4-3933.7"
+        attribute \src "ls180.v:4002.4-4008.7"
         switch 1'1
-          attribute \src "ls180.v:3927.8-3927.12"
+          attribute \src "ls180.v:4002.8-4002.12"
           case 1'1
-            assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3928$388_Y
+            assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4003$439_Y
           case 
         end
-        attribute \src "ls180.v:3935.4-3939.7"
+        attribute \src "ls180.v:4010.4-4014.7"
         switch \main_sdram_read_available
-          attribute \src "ls180.v:3935.8-3935.33"
+          attribute \src "ls180.v:4010.8-4010.33"
           case 1'1
-            attribute \src "ls180.v:3936.5-3938.8"
-            switch $or$ls180.v:3936$390_Y
-              attribute \src "ls180.v:3936.9-3936.63"
+            attribute \src "ls180.v:4011.5-4013.8"
+            switch $or$ls180.v:4011$441_Y
+              attribute \src "ls180.v:4011.9-4011.63"
               case 1'1
                 assign $0\builder_multiplexer_next_state[2:0] 3'011
               case 
             end
           case 
         end
-        attribute \src "ls180.v:3940.4-3942.7"
+        attribute \src "ls180.v:4015.4-4017.7"
         switch \main_sdram_go_to_refresh
-          attribute \src "ls180.v:3940.8-3940.32"
+          attribute \src "ls180.v:4015.8-4015.32"
           case 1'1
             assign $0\builder_multiplexer_next_state[2:0] 3'010
           case 
@@ -270177,18 +271795,18 @@ module \ls180
       case 3'010
         assign $0\main_sdram_steerer_sel[1:0] 2'11
         assign $0\main_sdram_cmd_ready[0:0] 1'1
-        attribute \src "ls180.v:3947.4-3949.7"
+        attribute \src "ls180.v:4022.4-4024.7"
         switch \main_sdram_cmd_last
-          attribute \src "ls180.v:3947.8-3947.27"
+          attribute \src "ls180.v:4022.8-4022.27"
           case 1'1
             assign $0\builder_multiplexer_next_state[2:0] 3'000
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:3952.4-3954.7"
+        attribute \src "ls180.v:4027.4-4029.7"
         switch \main_sdram_twtrcon_ready
-          attribute \src "ls180.v:3952.8-3952.32"
+          attribute \src "ls180.v:4027.8-4027.32"
           case 1'1
             assign $0\builder_multiplexer_next_state[2:0] 3'000
           case 
@@ -270204,29 +271822,29 @@ module \ls180
         assign $0\main_sdram_en0[0:0] 1'1
         assign $0\main_sdram_choose_req_want_reads[0:0] 1'1
         assign $0\main_sdram_steerer_sel[1:0] 2'10
-        attribute \src "ls180.v:3965.4-3971.7"
+        attribute \src "ls180.v:4040.4-4046.7"
         switch 1'1
-          attribute \src "ls180.v:3965.8-3965.12"
+          attribute \src "ls180.v:4040.8-4040.12"
           case 1'1
-            assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3966$397_Y
+            assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4041$448_Y
           case 
         end
-        attribute \src "ls180.v:3973.4-3977.7"
+        attribute \src "ls180.v:4048.4-4052.7"
         switch \main_sdram_write_available
-          attribute \src "ls180.v:3973.8-3973.34"
+          attribute \src "ls180.v:4048.8-4048.34"
           case 1'1
-            attribute \src "ls180.v:3974.5-3976.8"
-            switch $or$ls180.v:3974$399_Y
-              attribute \src "ls180.v:3974.9-3974.62"
+            attribute \src "ls180.v:4049.5-4051.8"
+            switch $or$ls180.v:4049$450_Y
+              attribute \src "ls180.v:4049.9-4049.62"
               case 1'1
                 assign $0\builder_multiplexer_next_state[2:0] 3'100
               case 
             end
           case 
         end
-        attribute \src "ls180.v:3978.4-3980.7"
+        attribute \src "ls180.v:4053.4-4055.7"
         switch \main_sdram_go_to_refresh
-          attribute \src "ls180.v:3978.8-3978.32"
+          attribute \src "ls180.v:4053.8-4053.32"
           case 1'1
             assign $0\builder_multiplexer_next_state[2:0] 3'010
           case 
@@ -270243,45 +271861,29 @@ module \ls180
       update \main_sdram_en1 $0\main_sdram_en1[0:0]
       update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
   end
-  attribute \src "ls180.v:396.11-396.44"
-  process $proc$ls180.v:396$2886
-    assign { } { }
-    assign $1\main_sdram_timer_count1[9:0] 10'1100001101
-    sync always
-    sync init
-      update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
-  end
-  attribute \src "ls180.v:398.5-398.38"
-  process $proc$ls180.v:398$2887
+  attribute \src "ls180.v:407.12-407.46"
+  process $proc$ls180.v:407$3006
     assign { } { }
-    assign $1\main_sdram_postponer_req_o[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
-  end
-  attribute \src "ls180.v:399.5-399.38"
-  process $proc$ls180.v:399$2888
-    assign { } { }
-    assign $1\main_sdram_postponer_count[0:0] 1'0
+    assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
+      update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
   end
-  attribute \src "ls180.v:400.5-400.39"
-  process $proc$ls180.v:400$2889
+  attribute \src "ls180.v:408.11-408.47"
+  process $proc$ls180.v:408$3007
     assign { } { }
-    assign $1\main_sdram_sequencer_start0[0:0] 1'0
+    assign $1\main_sdram_interface_wdata_we[1:0] 2'00
     sync always
     sync init
-      update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
+      update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
   end
-  attribute \src "ls180.v:4007.1-4020.4"
-  process $proc$ls180.v:4007$528
+  attribute \src "ls180.v:4082.1-4095.4"
+  process $proc$ls180.v:4082$579
     assign { } { }
     assign { } { }
     assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000
     assign $0\main_sdram_interface_wdata_we[1:0] 2'00
-    attribute \src "ls180.v:4010.2-4019.9"
+    attribute \src "ls180.v:4085.2-4094.9"
     switch \builder_new_master_wdata_ready
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
@@ -270296,11 +271898,19 @@ module \ls180
       update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0]
       update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
   end
-  attribute \src "ls180.v:4027.1-4037.4"
-  process $proc$ls180.v:4027$530
+  attribute \src "ls180.v:410.12-410.45"
+  process $proc$ls180.v:410$3008
+    assign { } { }
+    assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
+  end
+  attribute \src "ls180.v:4102.1-4112.4"
+  process $proc$ls180.v:4102$581
     assign { } { }
     assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000
-    attribute \src "ls180.v:4029.2-4036.9"
+    attribute \src "ls180.v:4104.2-4111.9"
     switch \main_converter_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
@@ -270313,16 +271923,16 @@ module \ls180
     sync always
       update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
   end
-  attribute \src "ls180.v:403.5-403.38"
-  process $proc$ls180.v:403$2890
+  attribute \src "ls180.v:411.11-411.40"
+  process $proc$ls180.v:411$3009
     assign { } { }
-    assign $1\main_sdram_sequencer_done1[0:0] 1'0
+    assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
     sync always
     sync init
-      update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
+      update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
   end
-  attribute \src "ls180.v:4039.1-4085.4"
-  process $proc$ls180.v:4039$531
+  attribute \src "ls180.v:4114.1-4160.4"
+  process $proc$ls180.v:4114$582
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270333,9 +271943,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_litedram_wb_we[0:0] 1'0
-    assign $0\main_converter_skip[0:0] 1'0
-    assign $0\main_wb_sdram_ack[0:0] 1'0
     assign { } { }
     assign $0\main_converter_counter_converter_next_value[0:0] 1'0
     assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
@@ -270343,13 +271950,16 @@ module \ls180
     assign $0\main_litedram_wb_sel[1:0] 2'00
     assign $0\main_litedram_wb_cyc[0:0] 1'0
     assign $0\main_litedram_wb_stb[0:0] 1'0
+    assign $0\main_wb_sdram_ack[0:0] 1'0
+    assign $0\main_litedram_wb_we[0:0] 1'0
+    assign $0\main_converter_skip[0:0] 1'0
     assign $0\builder_converter_next_state[0:0] \builder_converter_state
-    attribute \src "ls180.v:4051.2-4084.9"
+    attribute \src "ls180.v:4126.2-4159.9"
     switch \builder_converter_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter }
-        attribute \src "ls180.v:4054.4-4061.11"
+        attribute \src "ls180.v:4129.4-4136.11"
         switch \main_converter_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -270359,23 +271969,23 @@ module \ls180
             assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2]
           case 
         end
-        attribute \src "ls180.v:4062.4-4075.7"
-        switch $and$ls180.v:4062$532_Y
-          attribute \src "ls180.v:4062.8-4062.47"
+        attribute \src "ls180.v:4137.4-4150.7"
+        switch $and$ls180.v:4137$583_Y
+          attribute \src "ls180.v:4137.8-4137.47"
           case 1'1
-            assign $0\main_converter_skip[0:0] $eq$ls180.v:4063$533_Y
+            assign $0\main_converter_skip[0:0] $eq$ls180.v:4138$584_Y
             assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we
-            assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4065$534_Y
-            assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4066$535_Y
-            attribute \src "ls180.v:4067.5-4074.8"
-            switch $or$ls180.v:4067$536_Y
-              attribute \src "ls180.v:4067.9-4067.53"
+            assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4140$585_Y
+            assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4141$586_Y
+            attribute \src "ls180.v:4142.5-4149.8"
+            switch $or$ls180.v:4142$587_Y
+              attribute \src "ls180.v:4142.9-4142.53"
               case 1'1
-                assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4068$537_Y
+                assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4143$588_Y
                 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:4070.6-4073.9"
-                switch $eq$ls180.v:4070$538_Y
-                  attribute \src "ls180.v:4070.10-4070.42"
+                attribute \src "ls180.v:4145.6-4148.9"
+                switch $eq$ls180.v:4145$589_Y
+                  attribute \src "ls180.v:4145.10-4145.42"
                   case 1'1
                     assign $0\main_wb_sdram_ack[0:0] 1'1
                     assign $0\builder_converter_next_state[0:0] 1'0
@@ -270389,9 +271999,9 @@ module \ls180
       case 
         assign $0\main_converter_counter_converter_next_value[0:0] 1'0
         assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4080.4-4082.7"
-        switch $and$ls180.v:4080$539_Y
-          attribute \src "ls180.v:4080.8-4080.47"
+        attribute \src "ls180.v:4155.4-4157.7"
+        switch $and$ls180.v:4155$590_Y
+          attribute \src "ls180.v:4155.8-4155.47"
           case 1'1
             assign $0\builder_converter_next_state[0:0] 1'1
           case 
@@ -270409,45 +272019,53 @@ module \ls180
       update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0]
       update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:404.11-404.46"
-  process $proc$ls180.v:404$2891
+  attribute \src "ls180.v:412.5-412.35"
+  process $proc$ls180.v:412$3010
     assign { } { }
-    assign $1\main_sdram_sequencer_counter[3:0] 4'0000
+    assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
+      update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
   end
-  attribute \src "ls180.v:405.5-405.38"
-  process $proc$ls180.v:405$2892
+  attribute \src "ls180.v:413.5-413.34"
+  process $proc$ls180.v:413$3011
     assign { } { }
-    assign $1\main_sdram_sequencer_count[0:0] 1'0
+    assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
+      update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
   end
-  attribute \src "ls180.v:411.5-411.51"
-  process $proc$ls180.v:411$2893
+  attribute \src "ls180.v:414.5-414.35"
+  process $proc$ls180.v:414$3012
     assign { } { }
-    assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+    assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
+      update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
   end
-  attribute \src "ls180.v:412.5-412.51"
-  process $proc$ls180.v:412$2894
+  attribute \src "ls180.v:415.5-415.34"
+  process $proc$ls180.v:415$3013
     assign { } { }
-    assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+    assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
     sync always
     sync init
-      update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
+      update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
   end
-  attribute \src "ls180.v:4130.1-4135.4"
-  process $proc$ls180.v:4130$571
+  attribute \src "ls180.v:419.5-419.35"
+  process $proc$ls180.v:419$3014
+    assign { } { }
+    assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
+    sync always
+      update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:4205.1-4210.4"
+  process $proc$ls180.v:4205$622
     assign { } { }
     assign $0\main_uart_tx_clear[0:0] 1'0
-    attribute \src "ls180.v:4132.2-4134.5"
-    switch $and$ls180.v:4132$572_Y
-      attribute \src "ls180.v:4132.6-4132.79"
+    attribute \src "ls180.v:4207.2-4209.5"
+    switch $and$ls180.v:4207$623_Y
+      attribute \src "ls180.v:4207.6-4207.79"
       case 1'1
         assign $0\main_uart_tx_clear[0:0] 1'1
       case 
@@ -270455,8 +272073,16 @@ module \ls180
     sync always
       update \main_uart_tx_clear $0\main_uart_tx_clear[0:0]
   end
-  attribute \src "ls180.v:4136.1-4140.4"
-  process $proc$ls180.v:4136$573
+  attribute \src "ls180.v:421.5-421.39"
+  process $proc$ls180.v:421$3015
+    assign { } { }
+    assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
+  end
+  attribute \src "ls180.v:4211.1-4215.4"
+  process $proc$ls180.v:4211$624
     assign { } { }
     assign { } { }
     assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status
@@ -270464,21 +272090,13 @@ module \ls180
     sync always
       update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0]
   end
-  attribute \src "ls180.v:414.5-414.47"
-  process $proc$ls180.v:414$2895
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
-  end
-  attribute \src "ls180.v:4141.1-4146.4"
-  process $proc$ls180.v:4141$574
+  attribute \src "ls180.v:4216.1-4221.4"
+  process $proc$ls180.v:4216$625
     assign { } { }
     assign $0\main_uart_rx_clear[0:0] 1'0
-    attribute \src "ls180.v:4143.2-4145.5"
-    switch $and$ls180.v:4143$575_Y
-      attribute \src "ls180.v:4143.6-4143.79"
+    attribute \src "ls180.v:4218.2-4220.5"
+    switch $and$ls180.v:4218$626_Y
+      attribute \src "ls180.v:4218.6-4218.79"
       case 1'1
         assign $0\main_uart_rx_clear[0:0] 1'1
       case 
@@ -270486,8 +272104,8 @@ module \ls180
     sync always
       update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
   end
-  attribute \src "ls180.v:4147.1-4151.4"
-  process $proc$ls180.v:4147$576
+  attribute \src "ls180.v:4222.1-4226.4"
+  process $proc$ls180.v:4222$627
     assign { } { }
     assign { } { }
     assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending
@@ -270495,96 +272113,88 @@ module \ls180
     sync always
       update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
   end
-  attribute \src "ls180.v:415.5-415.45"
-  process $proc$ls180.v:415$2896
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
-  end
-  attribute \src "ls180.v:416.5-416.45"
-  process $proc$ls180.v:416$2897
+  attribute \src "ls180.v:423.5-423.39"
+  process $proc$ls180.v:423$3016
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
+    assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
+      update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
   end
-  attribute \src "ls180.v:4169.1-4176.4"
-  process $proc$ls180.v:4169$584
+  attribute \src "ls180.v:4244.1-4251.4"
+  process $proc$ls180.v:4244$635
     assign { } { }
     assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
-    attribute \src "ls180.v:4171.2-4175.5"
+    attribute \src "ls180.v:4246.2-4250.5"
     switch \main_uart_tx_fifo_replace
-      attribute \src "ls180.v:4171.6-4171.31"
+      attribute \src "ls180.v:4246.6-4246.31"
       case 1'1
-        assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4172$585_Y
-      attribute \src "ls180.v:4173.6-4173.10"
+        assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4247$636_Y
+      attribute \src "ls180.v:4248.6-4248.10"
       case 
         assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce
     end
     sync always
       update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:417.12-417.57"
-  process $proc$ls180.v:417$2898
+  attribute \src "ls180.v:426.5-426.32"
+  process $proc$ls180.v:426$3017
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+    assign $1\main_sdram_cmd_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
+      update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:419.5-419.51"
-  process $proc$ls180.v:419$2899
+  attribute \src "ls180.v:427.5-427.32"
+  process $proc$ls180.v:427$3018
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+    assign $1\main_sdram_cmd_ready[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
+      update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:4199.1-4206.4"
-  process $proc$ls180.v:4199$595
+  attribute \src "ls180.v:4274.1-4281.4"
+  process $proc$ls180.v:4274$646
     assign { } { }
     assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
-    attribute \src "ls180.v:4201.2-4205.5"
+    attribute \src "ls180.v:4276.2-4280.5"
     switch \main_uart_rx_fifo_replace
-      attribute \src "ls180.v:4201.6-4201.31"
+      attribute \src "ls180.v:4276.6-4276.31"
       case 1'1
-        assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4202$596_Y
-      attribute \src "ls180.v:4203.6-4203.10"
+        assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4277$647_Y
+      attribute \src "ls180.v:4278.6-4278.10"
       case 
         assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce
     end
     sync always
       update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:420.5-420.51"
-  process $proc$ls180.v:420$2900
+  attribute \src "ls180.v:428.5-428.31"
+  process $proc$ls180.v:428$3019
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+    assign $1\main_sdram_cmd_last[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
+      update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
   end
-  attribute \src "ls180.v:421.5-421.50"
-  process $proc$ls180.v:421$2901
+  attribute \src "ls180.v:429.12-429.44"
+  process $proc$ls180.v:429$3020
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+    assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
+      update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:422.5-422.54"
-  process $proc$ls180.v:422$2902
+  attribute \src "ls180.v:430.11-430.43"
+  process $proc$ls180.v:430$3021
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+    assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+      update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
   end
-  attribute \src "ls180.v:4229.1-4277.4"
-  process $proc$ls180.v:4229$606
+  attribute \src "ls180.v:4304.1-4352.4"
+  process $proc$ls180.v:4304$657
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270594,25 +272204,25 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_spimaster25_clk_enable[0:0] 1'0
-    assign $0\main_spimaster26_cs_enable[0:0] 1'0
-    assign { } { }
     assign $0\main_spimaster28_mosi_latch[0:0] 1'0
     assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
     assign $0\main_spimaster2_done[0:0] 1'0
     assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
     assign $0\main_spimaster29_miso_latch[0:0] 1'0
     assign $0\main_spimaster3_irq[0:0] 1'0
+    assign $0\main_spimaster25_clk_enable[0:0] 1'0
+    assign $0\main_spimaster26_cs_enable[0:0] 1'0
+    assign { } { }
     assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state
-    attribute \src "ls180.v:4240.2-4276.9"
+    attribute \src "ls180.v:4315.2-4351.9"
     switch \builder_spimaster0_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
         assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4244.4-4247.7"
+        attribute \src "ls180.v:4319.4-4322.7"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:4244.8-4244.33"
+          attribute \src "ls180.v:4319.8-4319.33"
           case 1'1
             assign $0\main_spimaster26_cs_enable[0:0] 1'1
             assign $0\builder_spimaster0_next_state[1:0] 2'10
@@ -270622,15 +272232,15 @@ module \ls180
       case 2'10
         assign $0\main_spimaster25_clk_enable[0:0] 1'1
         assign $0\main_spimaster26_cs_enable[0:0] 1'1
-        attribute \src "ls180.v:4252.4-4258.7"
+        attribute \src "ls180.v:4327.4-4333.7"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:4252.8-4252.33"
+          attribute \src "ls180.v:4327.8-4327.33"
           case 1'1
-            assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4253$607_Y
+            assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4328$658_Y
             assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4255.5-4257.8"
-            switch $eq$ls180.v:4255$609_Y
-              attribute \src "ls180.v:4255.9-4255.68"
+            attribute \src "ls180.v:4330.5-4332.8"
+            switch $eq$ls180.v:4330$660_Y
+              attribute \src "ls180.v:4330.9-4330.68"
               case 1'1
                 assign $0\builder_spimaster0_next_state[1:0] 2'11
               case 
@@ -270640,9 +272250,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 2'11
         assign $0\main_spimaster26_cs_enable[0:0] 1'1
-        attribute \src "ls180.v:4262.4-4266.7"
+        attribute \src "ls180.v:4337.4-4341.7"
         switch \main_spimaster31_clk_rise
-          attribute \src "ls180.v:4262.8-4262.33"
+          attribute \src "ls180.v:4337.8-4337.33"
           case 1'1
             assign $0\main_spimaster29_miso_latch[0:0] 1'1
             assign $0\main_spimaster3_irq[0:0] 1'1
@@ -270652,9 +272262,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 
         assign $0\main_spimaster2_done[0:0] 1'1
-        attribute \src "ls180.v:4270.4-4274.7"
+        attribute \src "ls180.v:4345.4-4349.7"
         switch \main_spimaster0_start
-          attribute \src "ls180.v:4270.8-4270.29"
+          attribute \src "ls180.v:4345.8-4345.29"
           case 1'1
             assign $0\main_spimaster2_done[0:0] 1'0
             assign $0\main_spimaster28_mosi_latch[0:0] 1'1
@@ -270673,41 +272283,48 @@ module \ls180
       update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0]
       update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:423.5-423.55"
-  process $proc$ls180.v:423$2903
+  attribute \src "ls180.v:431.5-431.38"
+  process $proc$ls180.v:431$3022
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+    assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
+      update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:424.5-424.56"
-  process $proc$ls180.v:424$2904
+  attribute \src "ls180.v:432.5-432.38"
+  process $proc$ls180.v:432$3023
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+    assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
+      update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:425.5-425.50"
-  process $proc$ls180.v:425$2905
+  attribute \src "ls180.v:433.5-433.37"
+  process $proc$ls180.v:433$3024
     assign { } { }
-    assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
+    assign $1\main_sdram_cmd_payload_we[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
+      update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:428.5-428.67"
-  process $proc$ls180.v:428$2906
+  attribute \src "ls180.v:434.5-434.42"
+  process $proc$ls180.v:434$3025
     assign { } { }
-    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
+      update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
     sync init
   end
-  attribute \src "ls180.v:4288.1-4336.4"
-  process $proc$ls180.v:4288$614
+  attribute \src "ls180.v:435.5-435.43"
+  process $proc$ls180.v:435$3026
     assign { } { }
+    assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
+    sync always
+      update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:4363.1-4411.4"
+  process $proc$ls180.v:4363$665
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270717,24 +272334,25 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
-    assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
-    assign $0\main_spisdcard_clk_enable[0:0] 1'0
-    assign $0\main_spisdcard_cs_enable[0:0] 1'0
     assign $0\main_spisdcard_mosi_latch[0:0] 1'0
     assign $0\main_spisdcard_done0[0:0] 1'0
     assign $0\main_spisdcard_miso_latch[0:0] 1'0
     assign $0\main_spisdcard_irq[0:0] 1'0
+    assign $0\main_spisdcard_clk_enable[0:0] 1'0
+    assign { } { }
+    assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
+    assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
+    assign $0\main_spisdcard_cs_enable[0:0] 1'0
     assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state
-    attribute \src "ls180.v:4299.2-4335.9"
+    attribute \src "ls180.v:4374.2-4410.9"
     switch \builder_spimaster1_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
         assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4303.4-4306.7"
+        attribute \src "ls180.v:4378.4-4381.7"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:4303.8-4303.31"
+          attribute \src "ls180.v:4378.8-4378.31"
           case 1'1
             assign $0\main_spisdcard_cs_enable[0:0] 1'1
             assign $0\builder_spimaster1_next_state[1:0] 2'10
@@ -270744,15 +272362,15 @@ module \ls180
       case 2'10
         assign $0\main_spisdcard_clk_enable[0:0] 1'1
         assign $0\main_spisdcard_cs_enable[0:0] 1'1
-        attribute \src "ls180.v:4311.4-4317.7"
+        attribute \src "ls180.v:4386.4-4392.7"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:4311.8-4311.31"
+          attribute \src "ls180.v:4386.8-4386.31"
           case 1'1
-            assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4312$615_Y
+            assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4387$666_Y
             assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4314.5-4316.8"
-            switch $eq$ls180.v:4314$617_Y
-              attribute \src "ls180.v:4314.9-4314.66"
+            attribute \src "ls180.v:4389.5-4391.8"
+            switch $eq$ls180.v:4389$668_Y
+              attribute \src "ls180.v:4389.9-4389.66"
               case 1'1
                 assign $0\builder_spimaster1_next_state[1:0] 2'11
               case 
@@ -270762,9 +272380,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 2'11
         assign $0\main_spisdcard_cs_enable[0:0] 1'1
-        attribute \src "ls180.v:4321.4-4325.7"
+        attribute \src "ls180.v:4396.4-4400.7"
         switch \main_spisdcard_clk_rise
-          attribute \src "ls180.v:4321.8-4321.31"
+          attribute \src "ls180.v:4396.8-4396.31"
           case 1'1
             assign $0\main_spisdcard_miso_latch[0:0] 1'1
             assign $0\main_spisdcard_irq[0:0] 1'1
@@ -270774,9 +272392,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 
         assign $0\main_spisdcard_done0[0:0] 1'1
-        attribute \src "ls180.v:4329.4-4333.7"
+        attribute \src "ls180.v:4404.4-4408.7"
         switch \main_spisdcard_start0
-          attribute \src "ls180.v:4329.8-4329.29"
+          attribute \src "ls180.v:4404.8-4404.29"
           case 1'1
             assign $0\main_spisdcard_done0[0:0] 1'0
             assign $0\main_spisdcard_mosi_latch[0:0] 1'1
@@ -270795,19 +272413,35 @@ module \ls180
       update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0]
       update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:429.5-429.66"
-  process $proc$ls180.v:429$2907
+  attribute \src "ls180.v:441.11-441.44"
+  process $proc$ls180.v:441$3027
     assign { } { }
-    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    assign $1\main_sdram_timer_count1[9:0] 10'1100001101
     sync always
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
     sync init
+      update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
   end
-  attribute \src "ls180.v:4368.1-4396.4"
-  process $proc$ls180.v:4368$639
+  attribute \src "ls180.v:443.5-443.38"
+  process $proc$ls180.v:443$3028
+    assign { } { }
+    assign $1\main_sdram_postponer_req_o[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
+  end
+  attribute \src "ls180.v:444.5-444.38"
+  process $proc$ls180.v:444$3029
+    assign { } { }
+    assign $1\main_sdram_postponer_count[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
+  end
+  attribute \src "ls180.v:4443.1-4471.4"
+  process $proc$ls180.v:4443$690
     assign { } { }
     assign $0\main_sdphy_clocker_clk1[0:0] 1'0
-    attribute \src "ls180.v:4370.2-4395.9"
+    attribute \src "ls180.v:4445.2-4470.9"
     switch \main_sdphy_clocker_storage
       attribute \src "ls180.v:0.0-0.0"
       case 9'000000100
@@ -270837,8 +272471,16 @@ module \ls180
     sync always
       update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0]
   end
-  attribute \src "ls180.v:4398.1-4431.4"
-  process $proc$ls180.v:4398$642
+  attribute \src "ls180.v:445.5-445.39"
+  process $proc$ls180.v:445$3030
+    assign { } { }
+    assign $1\main_sdram_sequencer_start0[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
+  end
+  attribute \src "ls180.v:4473.1-4506.4"
+  process $proc$ls180.v:4473$693
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270847,16 +272489,16 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
+    assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
     assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
     assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
-    assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
     assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
     assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
-    assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
     assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state
-    attribute \src "ls180.v:4408.2-4430.9"
+    attribute \src "ls180.v:4483.2-4505.9"
     switch \builder_sdphy_sdphyinit_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
@@ -270865,15 +272507,15 @@ module \ls180
         assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1
         assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1
         assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111
-        attribute \src "ls180.v:4415.4-4421.7"
+        attribute \src "ls180.v:4490.4-4496.7"
         switch \main_sdphy_init_pads_out_ready
-          attribute \src "ls180.v:4415.8-4415.38"
+          attribute \src "ls180.v:4490.8-4490.38"
           case 1'1
-            assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4416$643_Y
+            assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4491$694_Y
             assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4418.5-4420.8"
-            switch $eq$ls180.v:4418$644_Y
-              attribute \src "ls180.v:4418.9-4418.41"
+            attribute \src "ls180.v:4493.5-4495.8"
+            switch $eq$ls180.v:4493$695_Y
+              attribute \src "ls180.v:4493.9-4493.41"
               case 1'1
                 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0
               case 
@@ -270884,9 +272526,9 @@ module \ls180
       case 
         assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
         assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4426.4-4428.7"
+        attribute \src "ls180.v:4501.4-4503.7"
         switch \main_sdphy_init_initialize_re
-          attribute \src "ls180.v:4426.8-4426.37"
+          attribute \src "ls180.v:4501.8-4501.37"
           case 1'1
             assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1
           case 
@@ -270902,8 +272544,32 @@ module \ls180
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:4432.1-4508.4"
-  process $proc$ls180.v:4432$645
+  attribute \src "ls180.v:448.5-448.38"
+  process $proc$ls180.v:448$3031
+    assign { } { }
+    assign $1\main_sdram_sequencer_done1[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
+  end
+  attribute \src "ls180.v:449.11-449.46"
+  process $proc$ls180.v:449$3032
+    assign { } { }
+    assign $1\main_sdram_sequencer_counter[3:0] 4'0000
+    sync always
+    sync init
+      update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
+  end
+  attribute \src "ls180.v:450.5-450.38"
+  process $proc$ls180.v:450$3033
+    assign { } { }
+    assign $1\main_sdram_sequencer_count[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
+  end
+  attribute \src "ls180.v:4507.1-4583.4"
+  process $proc$ls180.v:4507$696
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270912,22 +272578,22 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0
-    assign $0\main_sdphy_cmdw_done[0:0] 1'0
     assign { } { }
-    assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
     assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
+    assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
     assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
     assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
     assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
+    assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0
+    assign $0\main_sdphy_cmdw_done[0:0] 1'0
     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state
-    attribute \src "ls180.v:4442.2-4507.9"
+    attribute \src "ls180.v:4517.2-4582.9"
     switch \builder_sdphy_sdphycmdw_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
-        attribute \src "ls180.v:4446.4-4471.11"
+        attribute \src "ls180.v:4521.4-4546.11"
         switch \main_sdphy_cmdw_count
           attribute \src "ls180.v:0.0-0.0"
           case 8'00000000
@@ -270955,22 +272621,22 @@ module \ls180
             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0]
           case 
         end
-        attribute \src "ls180.v:4472.4-4483.7"
+        attribute \src "ls180.v:4547.4-4558.7"
         switch \main_sdphy_cmdw_pads_out_ready
-          attribute \src "ls180.v:4472.8-4472.38"
+          attribute \src "ls180.v:4547.8-4547.38"
           case 1'1
-            assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4473$646_Y
+            assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4548$697_Y
             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4475.5-4482.8"
-            switch $eq$ls180.v:4475$647_Y
-              attribute \src "ls180.v:4475.9-4475.40"
+            attribute \src "ls180.v:4550.5-4557.8"
+            switch $eq$ls180.v:4550$698_Y
+              attribute \src "ls180.v:4550.9-4550.40"
               case 1'1
-                attribute \src "ls180.v:4476.6-4481.9"
+                attribute \src "ls180.v:4551.6-4556.9"
                 switch \main_sdphy_cmdw_sink_last
-                  attribute \src "ls180.v:4476.10-4476.35"
+                  attribute \src "ls180.v:4551.10-4551.35"
                   case 1'1
                     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10
-                  attribute \src "ls180.v:4478.10-4478.14"
+                  attribute \src "ls180.v:4553.10-4553.14"
                   case 
                     assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
                     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
@@ -270984,15 +272650,15 @@ module \ls180
         assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1
-        attribute \src "ls180.v:4489.4-4496.7"
+        attribute \src "ls180.v:4564.4-4571.7"
         switch \main_sdphy_cmdw_pads_out_ready
-          attribute \src "ls180.v:4489.8-4489.38"
+          attribute \src "ls180.v:4564.8-4564.38"
           case 1'1
-            assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4490$648_Y
+            assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4565$699_Y
             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4492.5-4495.8"
-            switch $eq$ls180.v:4492$649_Y
-              attribute \src "ls180.v:4492.9-4492.40"
+            attribute \src "ls180.v:4567.5-4570.8"
+            switch $eq$ls180.v:4567$700_Y
+              attribute \src "ls180.v:4567.9-4567.40"
               case 1'1
                 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
                 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
@@ -271004,12 +272670,12 @@ module \ls180
       case 
         assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
         assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4501.4-4505.7"
-        switch $and$ls180.v:4501$650_Y
-          attribute \src "ls180.v:4501.8-4501.69"
+        attribute \src "ls180.v:4576.4-4580.7"
+        switch $and$ls180.v:4576$701_Y
+          attribute \src "ls180.v:4576.8-4576.69"
           case 1'1
             assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01
-          attribute \src "ls180.v:4503.8-4503.12"
+          attribute \src "ls180.v:4578.8-4578.12"
           case 
             assign $0\main_sdphy_cmdw_done[0:0] 1'1
         end
@@ -271024,48 +272690,48 @@ module \ls180
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:444.11-444.68"
-  process $proc$ls180.v:444$2908
+  attribute \src "ls180.v:456.5-456.51"
+  process $proc$ls180.v:456$3034
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
+    assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
+      update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:445.5-445.64"
-  process $proc$ls180.v:445$2909
+  attribute \src "ls180.v:457.5-457.51"
+  process $proc$ls180.v:457$3035
     assign { } { }
-    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
     sync init
+      update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:446.11-446.70"
-  process $proc$ls180.v:446$2910
+  attribute \src "ls180.v:459.5-459.47"
+  process $proc$ls180.v:459$3036
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
+    assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
+      update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:447.11-447.70"
-  process $proc$ls180.v:447$2911
+  attribute \src "ls180.v:460.5-460.45"
+  process $proc$ls180.v:460$3037
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
+    assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
+      update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:448.11-448.73"
-  process $proc$ls180.v:448$2912
+  attribute \src "ls180.v:461.5-461.45"
+  process $proc$ls180.v:461$3038
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+    assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
+      update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:4542.1-4635.4"
-  process $proc$ls180.v:4542$659
+  attribute \src "ls180.v:4617.1-4710.4"
+  process $proc$ls180.v:4617$710
     assign { } { }
     assign { } { }
     assign { } { }
@@ -271082,9 +272748,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
-    assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
-    assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
     assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
     assign { } { }
     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
@@ -271093,31 +272756,34 @@ module \ls180
     assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
     assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
     assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
-    assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
     assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
+    assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
     assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0
+    assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
+    assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
+    assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state
-    attribute \src "ls180.v:4560.2-4634.9"
+    attribute \src "ls180.v:4635.2-4709.9"
     switch \builder_sdphy_sdphycmdr_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
         assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
-        assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4568$660_Y
+        assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4643$711_Y
         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
-        attribute \src "ls180.v:4565.4-4567.7"
+        attribute \src "ls180.v:4640.4-4642.7"
         switch \main_sdphy_cmdr_cmdr_source_source_valid0
-          attribute \src "ls180.v:4565.8-4565.49"
+          attribute \src "ls180.v:4640.8-4640.49"
           case 1'1
             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010
           case 
         end
-        attribute \src "ls180.v:4570.4-4573.7"
-        switch $eq$ls180.v:4570$661_Y
-          attribute \src "ls180.v:4570.8-4570.41"
+        attribute \src "ls180.v:4645.4-4648.7"
+        switch $eq$ls180.v:4645$712_Y
+          attribute \src "ls180.v:4645.8-4645.41"
           case 1'1
             assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
@@ -271128,30 +272794,30 @@ module \ls180
         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0
         assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
-        assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4579$663_Y
+        assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4654$714_Y
         assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0
-        assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4596$666_Y
+        assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4671$717_Y
         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
-        attribute \src "ls180.v:4581.4-4595.7"
-        switch $and$ls180.v:4581$664_Y
-          attribute \src "ls180.v:4581.8-4581.69"
+        attribute \src "ls180.v:4656.4-4670.7"
+        switch $and$ls180.v:4656$715_Y
+          attribute \src "ls180.v:4656.8-4656.69"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1
-            assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4583$665_Y
+            assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4658$716_Y
             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
-            attribute \src "ls180.v:4585.5-4594.8"
+            attribute \src "ls180.v:4660.5-4669.8"
             switch \main_sdphy_cmdr_source_last
-              attribute \src "ls180.v:4585.9-4585.36"
+              attribute \src "ls180.v:4660.9-4660.36"
               case 1'1
                 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
-                attribute \src "ls180.v:4587.6-4593.9"
+                attribute \src "ls180.v:4662.6-4668.9"
                 switch \main_sdphy_cmdr_sink_last
-                  attribute \src "ls180.v:4587.10-4587.35"
+                  attribute \src "ls180.v:4662.10-4662.35"
                   case 1'1
                     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
                     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
                     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011
-                  attribute \src "ls180.v:4591.10-4591.14"
+                  attribute \src "ls180.v:4666.10-4666.14"
                   case 
                     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
                 end
@@ -271159,9 +272825,9 @@ module \ls180
             end
           case 
         end
-        attribute \src "ls180.v:4598.4-4601.7"
-        switch $eq$ls180.v:4598$667_Y
-          attribute \src "ls180.v:4598.8-4598.41"
+        attribute \src "ls180.v:4673.4-4676.7"
+        switch $eq$ls180.v:4673$718_Y
+          attribute \src "ls180.v:4673.8-4673.41"
           case 1'1
             assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
@@ -271172,15 +272838,15 @@ module \ls180
         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1
         assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1
-        attribute \src "ls180.v:4607.4-4613.7"
+        attribute \src "ls180.v:4682.4-4688.7"
         switch \main_sdphy_cmdr_pads_out_ready
-          attribute \src "ls180.v:4607.8-4607.38"
+          attribute \src "ls180.v:4682.8-4682.38"
           case 1'1
-            assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4608$668_Y
+            assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4683$719_Y
             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
-            attribute \src "ls180.v:4610.5-4612.8"
-            switch $eq$ls180.v:4610$669_Y
-              attribute \src "ls180.v:4610.9-4610.40"
+            attribute \src "ls180.v:4685.5-4687.8"
+            switch $eq$ls180.v:4685$720_Y
+              attribute \src "ls180.v:4685.9-4685.40"
               case 1'1
                 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
               case 
@@ -271192,9 +272858,9 @@ module \ls180
         assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1
         assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001
         assign $0\main_sdphy_cmdr_source_last[0:0] 1'1
-        attribute \src "ls180.v:4619.4-4621.7"
-        switch $and$ls180.v:4619$670_Y
-          attribute \src "ls180.v:4619.8-4619.69"
+        attribute \src "ls180.v:4694.4-4696.7"
+        switch $and$ls180.v:4694$721_Y
+          attribute \src "ls180.v:4694.8-4694.69"
           case 1'1
             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
           case 
@@ -271205,9 +272871,9 @@ module \ls180
         assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000
         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
-        attribute \src "ls180.v:4628.4-4632.7"
-        switch $and$ls180.v:4628$672_Y
-          attribute \src "ls180.v:4628.8-4628.94"
+        attribute \src "ls180.v:4703.4-4707.7"
+        switch $and$ls180.v:4703$723_Y
+          attribute \src "ls180.v:4703.8-4703.94"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1
             assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
@@ -271233,42 +272899,122 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:4669.1-4696.4"
-  process $proc$ls180.v:4669$680
+  attribute \src "ls180.v:462.12-462.57"
+  process $proc$ls180.v:462$3039
     assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
+  end
+  attribute \src "ls180.v:464.5-464.51"
+  process $proc$ls180.v:464$3040
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
+  end
+  attribute \src "ls180.v:465.5-465.51"
+  process $proc$ls180.v:465$3041
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
+  end
+  attribute \src "ls180.v:466.5-466.50"
+  process $proc$ls180.v:466$3042
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
+  end
+  attribute \src "ls180.v:467.5-467.54"
+  process $proc$ls180.v:467$3043
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+  end
+  attribute \src "ls180.v:468.5-468.55"
+  process $proc$ls180.v:468$3044
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
+  end
+  attribute \src "ls180.v:469.5-469.56"
+  process $proc$ls180.v:469$3045
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
+  end
+  attribute \src "ls180.v:470.5-470.50"
+  process $proc$ls180.v:470$3046
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
+  end
+  attribute \src "ls180.v:473.5-473.67"
+  process $proc$ls180.v:473$3047
+    assign { } { }
+    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    sync always
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:474.5-474.66"
+  process $proc$ls180.v:474$3048
+    assign { } { }
+    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    sync always
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:4744.1-4771.4"
+  process $proc$ls180.v:4744$731
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
-    assign $0\main_sdphy_dataw_error[0:0] 1'0
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
+    assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
+    assign { } { }
     assign $0\main_sdphy_dataw_valid[0:0] 1'0
+    assign $0\main_sdphy_dataw_error[0:0] 1'0
     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
     assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state
-    attribute \src "ls180.v:4677.2-4695.9"
+    attribute \src "ls180.v:4752.2-4770.9"
     switch \builder_sdphy_sdphycrcr_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
         assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
         assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1
-        attribute \src "ls180.v:4682.4-4686.7"
+        attribute \src "ls180.v:4757.4-4761.7"
         switch \main_sdphy_dataw_crcr_source_source_valid0
-          attribute \src "ls180.v:4682.8-4682.50"
+          attribute \src "ls180.v:4757.8-4757.50"
           case 1'1
-            assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4683$681_Y
-            assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4684$682_Y
+            assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4758$732_Y
+            assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4759$733_Y
             assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:4689.4-4693.7"
+        attribute \src "ls180.v:4764.4-4768.7"
         switch \main_sdphy_dataw_start
-          attribute \src "ls180.v:4689.8-4689.30"
+          attribute \src "ls180.v:4764.8-4764.30"
           case 1'1
             assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1
             assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
@@ -271284,16 +273030,9 @@ module \ls180
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:469.5-469.59"
-  process $proc$ls180.v:469$2913
+  attribute \src "ls180.v:4772.1-4844.4"
+  process $proc$ls180.v:4772$734
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
-  end
-  attribute \src "ls180.v:4697.1-4769.4"
-  process $proc$ls180.v:4697$683
     assign { } { }
     assign { } { }
     assign { } { }
@@ -271302,37 +273041,36 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign { } { }
-    assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
-    assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
-    assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
     assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
     assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0
     assign $0\main_sdphy_dataw_start[0:0] 1'0
     assign $0\main_sdphy_dataw_stop[0:0] 1'0
     assign { } { }
     assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
+    assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
+    assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
+    assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
     assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state
-    attribute \src "ls180.v:4708.2-4768.9"
+    attribute \src "ls180.v:4783.2-4843.9"
     switch \builder_sdphy_fsm_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
         assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
-        attribute \src "ls180.v:4713.4-4715.7"
+        attribute \src "ls180.v:4788.4-4790.7"
         switch \main_sdphy_dataw_pads_out_ready
-          attribute \src "ls180.v:4713.8-4713.39"
+          attribute \src "ls180.v:4788.8-4788.39"
           case 1'1
             assign $0\builder_sdphy_fsm_next_state[2:0] 3'010
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
-        assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4718$684_Y
+        assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4793$735_Y
         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
-        attribute \src "ls180.v:4721.4-4728.11"
+        attribute \src "ls180.v:4796.4-4803.11"
         switch \main_sdphy_dataw_count
           attribute \src "ls180.v:0.0-0.0"
           case 8'00000000
@@ -271342,24 +273080,24 @@ module \ls180
             assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0]
           case 
         end
-        attribute \src "ls180.v:4729.4-4741.7"
+        attribute \src "ls180.v:4804.4-4816.7"
         switch \main_sdphy_dataw_pads_out_ready
-          attribute \src "ls180.v:4729.8-4729.39"
+          attribute \src "ls180.v:4804.8-4804.39"
           case 1'1
-            assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4730$685_Y
+            assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4805$736_Y
             assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:4732.5-4740.8"
-            switch $eq$ls180.v:4732$686_Y
-              attribute \src "ls180.v:4732.9-4732.41"
+            attribute \src "ls180.v:4807.5-4815.8"
+            switch $eq$ls180.v:4807$737_Y
+              attribute \src "ls180.v:4807.9-4807.41"
               case 1'1
                 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
                 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:4735.6-4739.9"
+                attribute \src "ls180.v:4810.6-4814.9"
                 switch \main_sdphy_dataw_sink_last
-                  attribute \src "ls180.v:4735.10-4735.36"
+                  attribute \src "ls180.v:4810.10-4810.36"
                   case 1'1
                     assign $0\builder_sdphy_fsm_next_state[2:0] 3'011
-                  attribute \src "ls180.v:4737.10-4737.14"
+                  attribute \src "ls180.v:4812.10-4812.14"
                   case 
                     assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
                 end
@@ -271372,9 +273110,9 @@ module \ls180
         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
         assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111
-        attribute \src "ls180.v:4747.4-4750.7"
+        attribute \src "ls180.v:4822.4-4825.7"
         switch \main_sdphy_dataw_pads_out_ready
-          attribute \src "ls180.v:4747.8-4747.39"
+          attribute \src "ls180.v:4822.8-4822.39"
           case 1'1
             assign $0\main_sdphy_dataw_start[0:0] 1'1
             assign $0\builder_sdphy_fsm_next_state[2:0] 3'100
@@ -271383,13 +273121,13 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'100
         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
-        attribute \src "ls180.v:4754.4-4759.7"
+        attribute \src "ls180.v:4829.4-4834.7"
         switch \main_sdphy_dataw_pads_out_ready
-          attribute \src "ls180.v:4754.8-4754.39"
+          attribute \src "ls180.v:4829.8-4829.39"
           case 1'1
-            attribute \src "ls180.v:4755.5-4758.8"
+            attribute \src "ls180.v:4830.5-4833.8"
             switch \main_sdphy_dataw_pads_in_payload_data_i [0]
-              attribute \src "ls180.v:4755.9-4755.51"
+              attribute \src "ls180.v:4830.9-4830.51"
               case 1'1
                 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
                 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000
@@ -271401,9 +273139,9 @@ module \ls180
       case 
         assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
         assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:4764.4-4766.7"
-        switch $and$ls180.v:4764$687_Y
-          attribute \src "ls180.v:4764.8-4764.71"
+        attribute \src "ls180.v:4839.4-4841.7"
+        switch $and$ls180.v:4839$738_Y
+          attribute \src "ls180.v:4839.8-4839.71"
           case 1'1
             assign $0\builder_sdphy_fsm_next_state[2:0] 3'001
           case 
@@ -271420,80 +273158,9 @@ module \ls180
       update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:471.5-471.59"
-  process $proc$ls180.v:471$2914
+  attribute \src "ls180.v:4878.1-4979.4"
+  process $proc$ls180.v:4878$746
     assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  end
-  attribute \src "ls180.v:472.5-472.58"
-  process $proc$ls180.v:472$2915
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  end
-  attribute \src "ls180.v:473.5-473.64"
-  process $proc$ls180.v:473$2916
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  end
-  attribute \src "ls180.v:474.12-474.74"
-  process $proc$ls180.v:474$2917
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  end
-  attribute \src "ls180.v:475.12-475.47"
-  process $proc$ls180.v:475$2918
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
-  end
-  attribute \src "ls180.v:476.5-476.46"
-  process $proc$ls180.v:476$2919
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
-  end
-  attribute \src "ls180.v:478.5-478.44"
-  process $proc$ls180.v:478$2920
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
-  end
-  attribute \src "ls180.v:479.5-479.45"
-  process $proc$ls180.v:479$2921
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
-  end
-  attribute \src "ls180.v:480.5-480.54"
-  process $proc$ls180.v:480$2922
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
-  end
-  attribute \src "ls180.v:4803.1-4904.4"
-  process $proc$ls180.v:4803$695
     assign { } { }
     assign { } { }
     assign { } { }
@@ -271508,7 +273175,10 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
+    assign $0\main_sdphy_datar_source_valid[0:0] 1'0
     assign { } { }
+    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
     assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
     assign $0\main_sdphy_datar_source_last[0:0] 1'0
     assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
@@ -271520,12 +273190,8 @@ module \ls180
     assign $0\main_sdphy_datar_stop[0:0] 1'0
     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
-    assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
-    assign $0\main_sdphy_datar_source_valid[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
     assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state
-    attribute \src "ls180.v:4820.2-4903.9"
+    attribute \src "ls180.v:4895.2-4978.9"
     switch \builder_sdphy_sdphydatar_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
@@ -271534,18 +273200,18 @@ module \ls180
         assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1
         assign { } { }
         assign { } { }
-        assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4830$697_Y
+        assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4905$748_Y
         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
-        attribute \src "ls180.v:4827.4-4829.7"
+        attribute \src "ls180.v:4902.4-4904.7"
         switch \main_sdphy_datar_datar_source_source_valid0
-          attribute \src "ls180.v:4827.8-4827.51"
+          attribute \src "ls180.v:4902.8-4902.51"
           case 1'1
             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010
           case 
         end
-        attribute \src "ls180.v:4832.4-4835.7"
-        switch $eq$ls180.v:4832$698_Y
-          attribute \src "ls180.v:4832.8-4832.42"
+        attribute \src "ls180.v:4907.4-4910.7"
+        switch $eq$ls180.v:4907$749_Y
+          attribute \src "ls180.v:4907.8-4907.42"
           case 1'1
             assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
@@ -271556,48 +273222,48 @@ module \ls180
         assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
         assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0
         assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
-        assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4841$701_Y
+        assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4916$752_Y
         assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0
-        assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4862$703_Y
+        assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4937$754_Y
         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
-        attribute \src "ls180.v:4843.4-4861.7"
+        attribute \src "ls180.v:4918.4-4936.7"
         switch \main_sdphy_datar_source_valid
-          attribute \src "ls180.v:4843.8-4843.37"
+          attribute \src "ls180.v:4918.8-4918.37"
           case 1'1
-            attribute \src "ls180.v:4844.5-4860.8"
+            attribute \src "ls180.v:4919.5-4935.8"
             switch \main_sdphy_datar_source_ready
-              attribute \src "ls180.v:4844.9-4844.38"
+              attribute \src "ls180.v:4919.9-4919.38"
               case 1'1
                 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1
-                assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4846$702_Y
+                assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4921$753_Y
                 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
-                attribute \src "ls180.v:4848.6-4857.9"
+                attribute \src "ls180.v:4923.6-4932.9"
                 switch \main_sdphy_datar_source_last
-                  attribute \src "ls180.v:4848.10-4848.38"
+                  attribute \src "ls180.v:4923.10-4923.38"
                   case 1'1
                     assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
-                    attribute \src "ls180.v:4850.7-4856.10"
+                    attribute \src "ls180.v:4925.7-4931.10"
                     switch \main_sdphy_datar_sink_last
-                      attribute \src "ls180.v:4850.11-4850.37"
+                      attribute \src "ls180.v:4925.11-4925.37"
                       case 1'1
                         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
                         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
                         assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011
-                      attribute \src "ls180.v:4854.11-4854.15"
+                      attribute \src "ls180.v:4929.11-4929.15"
                       case 
                         assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
                     end
                   case 
                 end
-              attribute \src "ls180.v:4858.9-4858.13"
+              attribute \src "ls180.v:4933.9-4933.13"
               case 
                 assign $0\main_sdphy_datar_stop[0:0] 1'1
             end
           case 
         end
-        attribute \src "ls180.v:4864.4-4867.7"
-        switch $eq$ls180.v:4864$704_Y
-          attribute \src "ls180.v:4864.8-4864.42"
+        attribute \src "ls180.v:4939.4-4942.7"
+        switch $eq$ls180.v:4939$755_Y
+          attribute \src "ls180.v:4939.8-4939.42"
           case 1'1
             assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
@@ -271606,15 +273272,15 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
         assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
-        attribute \src "ls180.v:4871.4-4877.7"
+        attribute \src "ls180.v:4946.4-4952.7"
         switch \main_sdphy_datar_pads_out_ready
-          attribute \src "ls180.v:4871.8-4871.39"
+          attribute \src "ls180.v:4946.8-4946.39"
           case 1'1
-            assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4872$705_Y
+            assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4947$756_Y
             assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
-            attribute \src "ls180.v:4874.5-4876.8"
-            switch $eq$ls180.v:4874$706_Y
-              attribute \src "ls180.v:4874.9-4874.42"
+            attribute \src "ls180.v:4949.5-4951.8"
+            switch $eq$ls180.v:4949$757_Y
+              attribute \src "ls180.v:4949.9-4949.42"
               case 1'1
                 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
               case 
@@ -271626,9 +273292,9 @@ module \ls180
         assign $0\main_sdphy_datar_source_valid[0:0] 1'1
         assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001
         assign $0\main_sdphy_datar_source_last[0:0] 1'1
-        attribute \src "ls180.v:4883.4-4885.7"
-        switch $and$ls180.v:4883$707_Y
-          attribute \src "ls180.v:4883.8-4883.71"
+        attribute \src "ls180.v:4958.4-4960.7"
+        switch $and$ls180.v:4958$758_Y
+          attribute \src "ls180.v:4958.8-4958.71"
           case 1'1
             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
           case 
@@ -271637,14 +273303,14 @@ module \ls180
       case 
         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
-        attribute \src "ls180.v:4890.4-4901.7"
-        switch $and$ls180.v:4890$708_Y
-          attribute \src "ls180.v:4890.8-4890.71"
+        attribute \src "ls180.v:4965.4-4976.7"
+        switch $and$ls180.v:4965$759_Y
+          attribute \src "ls180.v:4965.8-4965.71"
           case 1'1
             assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
-            attribute \src "ls180.v:4892.5-4900.8"
+            attribute \src "ls180.v:4967.5-4975.8"
             switch \main_sdphy_datar_pads_out_ready
-              attribute \src "ls180.v:4892.9-4892.40"
+              attribute \src "ls180.v:4967.9-4967.40"
               case 1'1
                 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000
                 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
@@ -271675,184 +273341,128 @@ module \ls180
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:482.32-482.76"
-  process $proc$ls180.v:482$2923
+  attribute \src "ls180.v:489.11-489.68"
+  process $proc$ls180.v:489$3049
     assign { } { }
-    assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
-  end
-  attribute \src "ls180.v:483.11-483.55"
-  process $proc$ls180.v:483$2924
-    assign { } { }
-    assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
-  end
-  attribute \src "ls180.v:485.32-485.75"
-  process $proc$ls180.v:485$2925
-    assign { } { }
-    assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
+    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
-      update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
     sync init
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:487.32-487.76"
-  process $proc$ls180.v:487$2926
+  attribute \src "ls180.v:490.5-490.64"
+  process $proc$ls180.v:490$3050
     assign { } { }
-    assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
+    assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:493.5-493.51"
-  process $proc$ls180.v:493$2927
+  attribute \src "ls180.v:491.11-491.70"
+  process $proc$ls180.v:491$3051
     assign { } { }
-    assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:494.5-494.51"
-  process $proc$ls180.v:494$2928
+  attribute \src "ls180.v:492.11-492.70"
+  process $proc$ls180.v:492$3052
     assign { } { }
-    assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:496.5-496.47"
-  process $proc$ls180.v:496$2929
+  attribute \src "ls180.v:493.11-493.73"
+  process $proc$ls180.v:493$3053
     assign { } { }
-    assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:4962.1-4969.4"
-  process $proc$ls180.v:4962$830
+  attribute \src "ls180.v:5037.1-5044.4"
+  process $proc$ls180.v:5037$881
     assign { } { }
     assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
-    attribute \src "ls180.v:4964.2-4968.5"
+    attribute \src "ls180.v:5039.2-5043.5"
     switch \main_sdcore_crc7_inserter_enable
-      attribute \src "ls180.v:4964.6-4964.38"
+      attribute \src "ls180.v:5039.6-5039.38"
       case 1'1
         assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40
-      attribute \src "ls180.v:4966.6-4966.10"
+      attribute \src "ls180.v:5041.6-5041.10"
       case 
         assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0
     end
     sync always
       update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
   end
-  attribute \src "ls180.v:497.5-497.45"
-  process $proc$ls180.v:497$2930
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
-  end
-  attribute \src "ls180.v:498.5-498.45"
-  process $proc$ls180.v:498$2931
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
-  end
-  attribute \src "ls180.v:4984.1-4991.4"
-  process $proc$ls180.v:4984$853
+  attribute \src "ls180.v:5059.1-5066.4"
+  process $proc$ls180.v:5059$904
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:4986.2-4990.5"
+    attribute \src "ls180.v:5061.2-5065.5"
     switch \main_sdcore_crc16_inserter_crc0_enable
-      attribute \src "ls180.v:4986.6-4986.44"
+      attribute \src "ls180.v:5061.6-5061.44"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
-      attribute \src "ls180.v:4988.6-4988.10"
+      attribute \src "ls180.v:5063.6-5063.10"
       case 
         assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0
     end
     sync always
       update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
   end
-  attribute \src "ls180.v:499.12-499.57"
-  process $proc$ls180.v:499$2932
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
-  end
-  attribute \src "ls180.v:4994.1-5001.4"
-  process $proc$ls180.v:4994$864
+  attribute \src "ls180.v:5069.1-5076.4"
+  process $proc$ls180.v:5069$915
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:4996.2-5000.5"
+    attribute \src "ls180.v:5071.2-5075.5"
     switch \main_sdcore_crc16_inserter_crc1_enable
-      attribute \src "ls180.v:4996.6-4996.44"
+      attribute \src "ls180.v:5071.6-5071.44"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
-      attribute \src "ls180.v:4998.6-4998.10"
+      attribute \src "ls180.v:5073.6-5073.10"
       case 
         assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0
     end
     sync always
       update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
   end
-  attribute \src "ls180.v:5004.1-5011.4"
-  process $proc$ls180.v:5004$875
+  attribute \src "ls180.v:5079.1-5086.4"
+  process $proc$ls180.v:5079$926
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5006.2-5010.5"
+    attribute \src "ls180.v:5081.2-5085.5"
     switch \main_sdcore_crc16_inserter_crc2_enable
-      attribute \src "ls180.v:5006.6-5006.44"
+      attribute \src "ls180.v:5081.6-5081.44"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
-      attribute \src "ls180.v:5008.6-5008.10"
+      attribute \src "ls180.v:5083.6-5083.10"
       case 
         assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0
     end
     sync always
       update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
   end
-  attribute \src "ls180.v:501.5-501.51"
-  process $proc$ls180.v:501$2933
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
-  end
-  attribute \src "ls180.v:5014.1-5021.4"
-  process $proc$ls180.v:5014$886
+  attribute \src "ls180.v:5089.1-5096.4"
+  process $proc$ls180.v:5089$937
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5016.2-5020.5"
+    attribute \src "ls180.v:5091.2-5095.5"
     switch \main_sdcore_crc16_inserter_crc3_enable
-      attribute \src "ls180.v:5016.6-5016.44"
+      attribute \src "ls180.v:5091.6-5091.44"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
-      attribute \src "ls180.v:5018.6-5018.10"
+      attribute \src "ls180.v:5093.6-5093.10"
       case 
         assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0
     end
     sync always
       update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
   end
-  attribute \src "ls180.v:502.5-502.51"
-  process $proc$ls180.v:502$2934
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
-  end
-  attribute \src "ls180.v:5022.1-5101.4"
-  process $proc$ls180.v:5022$887
+  attribute \src "ls180.v:5097.1-5176.4"
+  process $proc$ls180.v:5097$938
     assign { } { }
     assign { } { }
     assign { } { }
@@ -271868,12 +273478,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
-    assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
-    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
     assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
     assign { } { }
@@ -271882,22 +273486,28 @@ module \ls180
     assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
     assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
+    assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
+    assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
+    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
     assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state
-    attribute \src "ls180.v:5039.2-5100.9"
+    attribute \src "ls180.v:5114.2-5175.9"
     switch \builder_sdcore_crcupstreaminserter_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
         assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1
-        attribute \src "ls180.v:5043.4-5045.7"
-        switch $eq$ls180.v:5043$888_Y
-          attribute \src "ls180.v:5043.8-5043.48"
+        attribute \src "ls180.v:5118.4-5120.7"
+        switch $eq$ls180.v:5118$939_Y
+          attribute \src "ls180.v:5118.8-5118.48"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:5046.4-5071.11"
+        attribute \src "ls180.v:5121.4-5146.11"
         switch \main_sdcore_crc16_inserter_cnt
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -271925,18 +273535,18 @@ module \ls180
             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] }
           case 
         end
-        attribute \src "ls180.v:5072.4-5079.7"
+        attribute \src "ls180.v:5147.4-5154.7"
         switch \main_sdcore_crc16_inserter_source_ready
-          attribute \src "ls180.v:5072.8-5072.47"
+          attribute \src "ls180.v:5147.8-5147.47"
           case 1'1
-            attribute \src "ls180.v:5073.5-5078.8"
-            switch $eq$ls180.v:5073$889_Y
-              attribute \src "ls180.v:5073.9-5073.49"
+            attribute \src "ls180.v:5148.5-5153.8"
+            switch $eq$ls180.v:5148$940_Y
+              attribute \src "ls180.v:5148.9-5148.49"
               case 1'1
                 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
-              attribute \src "ls180.v:5075.9-5075.13"
+              attribute \src "ls180.v:5150.9-5150.13"
               case 
-                assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5076$890_Y
+                assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5151$941_Y
                 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1
             end
           case 
@@ -271955,9 +273565,9 @@ module \ls180
         assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc
         assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1
-        attribute \src "ls180.v:5094.4-5098.7"
-        switch $and$ls180.v:5094$892_Y
-          attribute \src "ls180.v:5094.8-5094.128"
+        attribute \src "ls180.v:5169.4-5173.7"
+        switch $and$ls180.v:5169$943_Y
+          attribute \src "ls180.v:5169.8-5169.128"
           case 1'1
             assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1
             assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
@@ -271982,61 +273592,37 @@ module \ls180
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
   end
-  attribute \src "ls180.v:503.5-503.50"
-  process $proc$ls180.v:503$2935
+  attribute \src "ls180.v:514.5-514.59"
+  process $proc$ls180.v:514$3054
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
-  end
-  attribute \src "ls180.v:504.5-504.54"
-  process $proc$ls180.v:504$2936
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
-  end
-  attribute \src "ls180.v:505.5-505.55"
-  process $proc$ls180.v:505$2937
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
-  end
-  attribute \src "ls180.v:506.5-506.56"
-  process $proc$ls180.v:506$2938
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:507.5-507.50"
-  process $proc$ls180.v:507$2939
+  attribute \src "ls180.v:516.5-516.59"
+  process $proc$ls180.v:516$3055
     assign { } { }
-    assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
+      update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:510.5-510.67"
-  process $proc$ls180.v:510$2940
+  attribute \src "ls180.v:517.5-517.58"
+  process $proc$ls180.v:517$3056
     assign { } { }
-    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
     sync init
+      update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
   end
-  attribute \src "ls180.v:5102.1-5107.4"
-  process $proc$ls180.v:5102$893
+  attribute \src "ls180.v:5177.1-5182.4"
+  process $proc$ls180.v:5177$944
     assign { } { }
     assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0
-    attribute \src "ls180.v:5104.2-5106.5"
-    switch $and$ls180.v:5104$900_Y
-      attribute \src "ls180.v:5104.6-5104.301"
+    attribute \src "ls180.v:5179.2-5181.5"
+    switch $and$ls180.v:5179$951_Y
+      attribute \src "ls180.v:5179.6-5179.301"
       case 1'1
         assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1
       case 
@@ -272044,85 +273630,109 @@ module \ls180
     sync always
       update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
   end
-  attribute \src "ls180.v:511.5-511.66"
-  process $proc$ls180.v:511$2941
+  attribute \src "ls180.v:518.5-518.64"
+  process $proc$ls180.v:518$3057
     assign { } { }
-    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
     sync init
+      update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
   end
-  attribute \src "ls180.v:5110.1-5117.4"
-  process $proc$ls180.v:5110$902
+  attribute \src "ls180.v:5185.1-5192.4"
+  process $proc$ls180.v:5185$953
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
-    attribute \src "ls180.v:5112.2-5116.5"
-    switch $eq$ls180.v:5112$903_Y
-      attribute \src "ls180.v:5112.6-5112.45"
+    attribute \src "ls180.v:5187.2-5191.5"
+    switch $eq$ls180.v:5187$954_Y
+      attribute \src "ls180.v:5187.6-5187.45"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1
-      attribute \src "ls180.v:5114.6-5114.10"
+      attribute \src "ls180.v:5189.6-5189.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
     end
     sync always
       update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0]
   end
-  attribute \src "ls180.v:5120.1-5127.4"
-  process $proc$ls180.v:5120$905
+  attribute \src "ls180.v:519.12-519.74"
+  process $proc$ls180.v:519$3058
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
+  end
+  attribute \src "ls180.v:5195.1-5202.4"
+  process $proc$ls180.v:5195$956
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
-    attribute \src "ls180.v:5122.2-5126.5"
-    switch $eq$ls180.v:5122$906_Y
-      attribute \src "ls180.v:5122.6-5122.45"
+    attribute \src "ls180.v:5197.2-5201.5"
+    switch $eq$ls180.v:5197$957_Y
+      attribute \src "ls180.v:5197.6-5197.45"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1
-      attribute \src "ls180.v:5124.6-5124.10"
+      attribute \src "ls180.v:5199.6-5199.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
     end
     sync always
       update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0]
   end
-  attribute \src "ls180.v:5130.1-5137.4"
-  process $proc$ls180.v:5130$908
+  attribute \src "ls180.v:520.12-520.47"
+  process $proc$ls180.v:520$3059
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
+  end
+  attribute \src "ls180.v:5205.1-5212.4"
+  process $proc$ls180.v:5205$959
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
-    attribute \src "ls180.v:5132.2-5136.5"
-    switch $eq$ls180.v:5132$909_Y
-      attribute \src "ls180.v:5132.6-5132.45"
+    attribute \src "ls180.v:5207.2-5211.5"
+    switch $eq$ls180.v:5207$960_Y
+      attribute \src "ls180.v:5207.6-5207.45"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1
-      attribute \src "ls180.v:5134.6-5134.10"
+      attribute \src "ls180.v:5209.6-5209.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
     end
     sync always
       update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
   end
-  attribute \src "ls180.v:5140.1-5147.4"
-  process $proc$ls180.v:5140$911
+  attribute \src "ls180.v:521.5-521.46"
+  process $proc$ls180.v:521$3060
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
+  end
+  attribute \src "ls180.v:5215.1-5222.4"
+  process $proc$ls180.v:5215$962
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
-    attribute \src "ls180.v:5142.2-5146.5"
-    switch $eq$ls180.v:5142$912_Y
-      attribute \src "ls180.v:5142.6-5142.45"
+    attribute \src "ls180.v:5217.2-5221.5"
+    switch $eq$ls180.v:5217$963_Y
+      attribute \src "ls180.v:5217.6-5217.45"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1
-      attribute \src "ls180.v:5144.6-5144.10"
+      attribute \src "ls180.v:5219.6-5219.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
     end
     sync always
       update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
   end
-  attribute \src "ls180.v:5149.1-5154.4"
-  process $proc$ls180.v:5149$913
+  attribute \src "ls180.v:5224.1-5229.4"
+  process $proc$ls180.v:5224$964
     assign { } { }
     assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0
-    attribute \src "ls180.v:5151.2-5153.5"
-    switch $and$ls180.v:5151$915_Y
-      attribute \src "ls180.v:5151.6-5151.85"
+    attribute \src "ls180.v:5226.2-5228.5"
+    switch $and$ls180.v:5226$966_Y
+      attribute \src "ls180.v:5226.6-5226.85"
       case 1'1
         assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1
       case 
@@ -272130,88 +273740,120 @@ module \ls180
     sync always
       update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0]
   end
-  attribute \src "ls180.v:5155.1-5162.4"
-  process $proc$ls180.v:5155$916
+  attribute \src "ls180.v:523.5-523.44"
+  process $proc$ls180.v:523$3061
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
+  end
+  attribute \src "ls180.v:5230.1-5237.4"
+  process $proc$ls180.v:5230$967
     assign { } { }
     assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
-    attribute \src "ls180.v:5157.2-5161.5"
-    switch $lt$ls180.v:5157$917_Y
-      attribute \src "ls180.v:5157.6-5157.44"
+    attribute \src "ls180.v:5232.2-5236.5"
+    switch $lt$ls180.v:5232$968_Y
+      attribute \src "ls180.v:5232.6-5232.44"
       case 1'1
         assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1
-      attribute \src "ls180.v:5159.6-5159.10"
+      attribute \src "ls180.v:5234.6-5234.10"
       case 
         assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready
     end
     sync always
       update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0]
   end
-  attribute \src "ls180.v:5166.1-5173.4"
-  process $proc$ls180.v:5166$928
+  attribute \src "ls180.v:524.5-524.45"
+  process $proc$ls180.v:524$3062
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
+  end
+  attribute \src "ls180.v:5241.1-5248.4"
+  process $proc$ls180.v:5241$979
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5168.2-5172.5"
+    attribute \src "ls180.v:5243.2-5247.5"
     switch \main_sdcore_crc16_checker_crc0_enable
-      attribute \src "ls180.v:5168.6-5168.43"
+      attribute \src "ls180.v:5243.6-5243.43"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
-      attribute \src "ls180.v:5170.6-5170.10"
+      attribute \src "ls180.v:5245.6-5245.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0
     end
     sync always
       update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0]
   end
-  attribute \src "ls180.v:5176.1-5183.4"
-  process $proc$ls180.v:5176$939
+  attribute \src "ls180.v:525.5-525.54"
+  process $proc$ls180.v:525$3063
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
+  end
+  attribute \src "ls180.v:5251.1-5258.4"
+  process $proc$ls180.v:5251$990
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5178.2-5182.5"
+    attribute \src "ls180.v:5253.2-5257.5"
     switch \main_sdcore_crc16_checker_crc1_enable
-      attribute \src "ls180.v:5178.6-5178.43"
+      attribute \src "ls180.v:5253.6-5253.43"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
-      attribute \src "ls180.v:5180.6-5180.10"
+      attribute \src "ls180.v:5255.6-5255.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0
     end
     sync always
       update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0]
   end
-  attribute \src "ls180.v:5186.1-5193.4"
-  process $proc$ls180.v:5186$950
+  attribute \src "ls180.v:5261.1-5268.4"
+  process $proc$ls180.v:5261$1001
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5188.2-5192.5"
+    attribute \src "ls180.v:5263.2-5267.5"
     switch \main_sdcore_crc16_checker_crc2_enable
-      attribute \src "ls180.v:5188.6-5188.43"
+      attribute \src "ls180.v:5263.6-5263.43"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
-      attribute \src "ls180.v:5190.6-5190.10"
+      attribute \src "ls180.v:5265.6-5265.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0
     end
     sync always
       update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0]
   end
-  attribute \src "ls180.v:5196.1-5203.4"
-  process $proc$ls180.v:5196$961
+  attribute \src "ls180.v:527.32-527.76"
+  process $proc$ls180.v:527$3064
+    assign { } { }
+    assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
+  end
+  attribute \src "ls180.v:5271.1-5278.4"
+  process $proc$ls180.v:5271$1012
     assign { } { }
     assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
-    attribute \src "ls180.v:5198.2-5202.5"
+    attribute \src "ls180.v:5273.2-5277.5"
     switch \main_sdcore_crc16_checker_crc3_enable
-      attribute \src "ls180.v:5198.6-5198.43"
+      attribute \src "ls180.v:5273.6-5273.43"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
-      attribute \src "ls180.v:5200.6-5200.10"
+      attribute \src "ls180.v:5275.6-5275.10"
       case 
         assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0
     end
     sync always
       update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0]
   end
-  attribute \src "ls180.v:5204.1-5394.4"
-  process $proc$ls180.v:5204$962
+  attribute \src "ls180.v:5279.1-5469.4"
+  process $proc$ls180.v:5279$1013
     assign { } { }
     assign { } { }
     assign { } { }
@@ -272251,6 +273893,18 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
+    assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
+    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
+    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
+    assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
+    assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
+    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
+    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
+    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
+    assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
     assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
     assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
     assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
@@ -272278,25 +273932,13 @@ module \ls180
     assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0
     assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
     assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0
-    assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
-    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
-    assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
-    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
-    assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
-    assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
-    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
-    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
-    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
-    assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
     assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state
-    attribute \src "ls180.v:5245.2-5393.9"
+    attribute \src "ls180.v:5320.2-5468.9"
     switch \builder_sdcore_fsm_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1
-        attribute \src "ls180.v:5248.4-5268.11"
+        attribute \src "ls180.v:5323.4-5343.11"
         switch \main_sdcore_cmd_count
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -272316,27 +273958,27 @@ module \ls180
           attribute \src "ls180.v:0.0-0.0"
           case 3'101
             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 }
-            assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5266$963_Y
+            assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5341$1014_Y
           case 
         end
-        attribute \src "ls180.v:5269.4-5281.7"
-        switch $and$ls180.v:5269$964_Y
-          attribute \src "ls180.v:5269.8-5269.65"
+        attribute \src "ls180.v:5344.4-5356.7"
+        switch $and$ls180.v:5344$1015_Y
+          attribute \src "ls180.v:5344.8-5344.65"
           case 1'1
-            assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5270$965_Y
+            assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5345$1016_Y
             assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
-            attribute \src "ls180.v:5272.5-5280.8"
-            switch $eq$ls180.v:5272$966_Y
-              attribute \src "ls180.v:5272.9-5272.40"
+            attribute \src "ls180.v:5347.5-5355.8"
+            switch $eq$ls180.v:5347$1017_Y
+              attribute \src "ls180.v:5347.9-5347.40"
               case 1'1
-                attribute \src "ls180.v:5273.6-5279.9"
-                switch $eq$ls180.v:5273$967_Y
-                  attribute \src "ls180.v:5273.10-5273.40"
+                attribute \src "ls180.v:5348.6-5354.9"
+                switch $eq$ls180.v:5348$1018_Y
+                  attribute \src "ls180.v:5348.10-5348.40"
                   case 1'1
                     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1
                     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
                     assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
-                  attribute \src "ls180.v:5277.10-5277.14"
+                  attribute \src "ls180.v:5352.10-5352.14"
                   case 
                     assign $0\builder_sdcore_fsm_next_state[2:0] 3'010
                 end
@@ -272347,52 +273989,52 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1
-        assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5285$968_Y
+        assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5360$1019_Y
         assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1
-        attribute \src "ls180.v:5286.4-5290.7"
-        switch $eq$ls180.v:5286$969_Y
-          attribute \src "ls180.v:5286.8-5286.38"
+        attribute \src "ls180.v:5361.4-5365.7"
+        switch $eq$ls180.v:5361$1020_Y
+          attribute \src "ls180.v:5361.8-5361.38"
           case 1'1
             assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001
-          attribute \src "ls180.v:5288.8-5288.12"
+          attribute \src "ls180.v:5363.8-5363.12"
           case 
             assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110
         end
-        attribute \src "ls180.v:5292.4-5313.7"
+        attribute \src "ls180.v:5367.4-5388.7"
         switch \main_sdphy_cmdr_source_valid
-          attribute \src "ls180.v:5292.8-5292.36"
+          attribute \src "ls180.v:5367.8-5367.36"
           case 1'1
-            attribute \src "ls180.v:5293.5-5312.8"
-            switch $eq$ls180.v:5293$970_Y
-              attribute \src "ls180.v:5293.9-5293.56"
+            attribute \src "ls180.v:5368.5-5387.8"
+            switch $eq$ls180.v:5368$1021_Y
+              attribute \src "ls180.v:5368.9-5368.56"
               case 1'1
                 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1
                 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1
                 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
-              attribute \src "ls180.v:5297.9-5297.13"
+              attribute \src "ls180.v:5372.9-5372.13"
               case 
-                attribute \src "ls180.v:5298.6-5311.9"
+                attribute \src "ls180.v:5373.6-5386.9"
                 switch \main_sdphy_cmdr_source_last
-                  attribute \src "ls180.v:5298.10-5298.37"
+                  attribute \src "ls180.v:5373.10-5373.37"
                   case 1'1
-                    attribute \src "ls180.v:5299.7-5307.10"
-                    switch $eq$ls180.v:5299$971_Y
-                      attribute \src "ls180.v:5299.11-5299.42"
+                    attribute \src "ls180.v:5374.7-5382.10"
+                    switch $eq$ls180.v:5374$1022_Y
+                      attribute \src "ls180.v:5374.11-5374.42"
                       case 1'1
                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'011
-                      attribute \src "ls180.v:5301.11-5301.15"
+                      attribute \src "ls180.v:5376.11-5376.15"
                       case 
-                        attribute \src "ls180.v:5302.8-5306.11"
-                        switch $eq$ls180.v:5302$972_Y
-                          attribute \src "ls180.v:5302.12-5302.43"
+                        attribute \src "ls180.v:5377.8-5381.11"
+                        switch $eq$ls180.v:5377$1023_Y
+                          attribute \src "ls180.v:5377.12-5377.43"
                           case 1'1
                             assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
-                          attribute \src "ls180.v:5304.12-5304.16"
+                          attribute \src "ls180.v:5379.12-5379.16"
                           case 
                             assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
                         end
                     end
-                  attribute \src "ls180.v:5308.10-5308.14"
+                  attribute \src "ls180.v:5383.10-5383.14"
                   case 
                     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data }
                     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1
@@ -272408,28 +274050,28 @@ module \ls180
         assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last
         assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data
         assign $0\main_sdphy_datar_source_ready[0:0] 1'1
-        attribute \src "ls180.v:5321.4-5327.7"
-        switch $and$ls180.v:5321$974_Y
-          attribute \src "ls180.v:5321.8-5321.98"
+        attribute \src "ls180.v:5396.4-5402.7"
+        switch $and$ls180.v:5396$1025_Y
+          attribute \src "ls180.v:5396.8-5396.98"
           case 1'1
-            assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5322$975_Y
+            assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5397$1026_Y
             assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
-            attribute \src "ls180.v:5324.5-5326.8"
-            switch $eq$ls180.v:5324$977_Y
-              attribute \src "ls180.v:5324.9-5324.77"
+            attribute \src "ls180.v:5399.5-5401.8"
+            switch $eq$ls180.v:5399$1028_Y
+              attribute \src "ls180.v:5399.9-5399.77"
               case 1'1
                 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
               case 
             end
           case 
         end
-        attribute \src "ls180.v:5329.4-5334.7"
+        attribute \src "ls180.v:5404.4-5409.7"
         switch \main_sdphy_datar_source_valid
-          attribute \src "ls180.v:5329.8-5329.37"
+          attribute \src "ls180.v:5404.8-5404.37"
           case 1'1
-            attribute \src "ls180.v:5330.5-5333.8"
-            switch $ne$ls180.v:5330$978_Y
-              attribute \src "ls180.v:5330.9-5330.57"
+            attribute \src "ls180.v:5405.5-5408.8"
+            switch $ne$ls180.v:5405$1029_Y
+              attribute \src "ls180.v:5405.9-5405.57"
               case 1'1
                 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1
                 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1
@@ -272441,42 +274083,42 @@ module \ls180
       case 3'100
         assign $0\main_sdphy_datar_sink_valid[0:0] 1'1
         assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage
-        assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5339$980_Y
-        attribute \src "ls180.v:5340.4-5366.7"
+        assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5414$1031_Y
+        attribute \src "ls180.v:5415.4-5441.7"
         switch \main_sdphy_datar_source_valid
-          attribute \src "ls180.v:5340.8-5340.37"
+          attribute \src "ls180.v:5415.8-5415.37"
           case 1'1
-            attribute \src "ls180.v:5341.5-5365.8"
-            switch $eq$ls180.v:5341$981_Y
-              attribute \src "ls180.v:5341.9-5341.57"
+            attribute \src "ls180.v:5416.5-5440.8"
+            switch $eq$ls180.v:5416$1032_Y
+              attribute \src "ls180.v:5416.9-5416.57"
               case 1'1
                 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid
                 assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready
                 assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first
                 assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last
                 assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data
-                attribute \src "ls180.v:5347.6-5355.9"
-                switch $and$ls180.v:5347$982_Y
-                  attribute \src "ls180.v:5347.10-5347.72"
+                attribute \src "ls180.v:5422.6-5430.9"
+                switch $and$ls180.v:5422$1033_Y
+                  attribute \src "ls180.v:5422.10-5422.72"
                   case 1'1
-                    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5348$983_Y
+                    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5423$1034_Y
                     assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
-                    attribute \src "ls180.v:5350.7-5354.10"
-                    switch $eq$ls180.v:5350$985_Y
-                      attribute \src "ls180.v:5350.11-5350.79"
+                    attribute \src "ls180.v:5425.7-5429.10"
+                    switch $eq$ls180.v:5425$1036_Y
+                      attribute \src "ls180.v:5425.11-5425.79"
                       case 1'1
                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
-                      attribute \src "ls180.v:5352.11-5352.15"
+                      attribute \src "ls180.v:5427.11-5427.15"
                       case 
                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
                     end
                   case 
                 end
-              attribute \src "ls180.v:5356.9-5356.13"
+              attribute \src "ls180.v:5431.9-5431.13"
               case 
-                attribute \src "ls180.v:5357.6-5364.9"
-                switch $eq$ls180.v:5357$986_Y
-                  attribute \src "ls180.v:5357.10-5357.58"
+                attribute \src "ls180.v:5432.6-5439.9"
+                switch $eq$ls180.v:5432$1037_Y
+                  attribute \src "ls180.v:5432.10-5432.58"
                   case 1'1
                     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1
                     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1
@@ -272499,9 +274141,9 @@ module \ls180
         assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
         assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
         assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
-        attribute \src "ls180.v:5377.4-5391.7"
+        attribute \src "ls180.v:5452.4-5466.7"
         switch \main_sdcore_cmd_send_re
-          attribute \src "ls180.v:5377.8-5377.31"
+          attribute \src "ls180.v:5452.8-5452.31"
           case 1'1
             assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
             assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
@@ -272560,106 +274202,202 @@ module \ls180
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
   end
-  attribute \src "ls180.v:526.11-526.68"
-  process $proc$ls180.v:526$2942
+  attribute \src "ls180.v:528.11-528.55"
+  process $proc$ls180.v:528$3065
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
+    assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
+      update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
   end
-  attribute \src "ls180.v:527.5-527.64"
-  process $proc$ls180.v:527$2943
+  attribute \src "ls180.v:530.32-530.75"
+  process $proc$ls180.v:530$3066
     assign { } { }
-    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
+    assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
     sync always
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
+      update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:528.11-528.70"
-  process $proc$ls180.v:528$2944
+  attribute \src "ls180.v:532.32-532.76"
+  process $proc$ls180.v:532$3067
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
+    assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
     sync always
+      update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:529.11-529.70"
-  process $proc$ls180.v:529$2945
+  attribute \src "ls180.v:538.5-538.51"
+  process $proc$ls180.v:538$3068
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
+    assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
+      update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:530.11-530.73"
-  process $proc$ls180.v:530$2946
+  attribute \src "ls180.v:539.5-539.51"
+  process $proc$ls180.v:539$3069
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+    assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
+      update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
+  end
+  attribute \src "ls180.v:541.5-541.47"
+  process $proc$ls180.v:541$3070
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
+  end
+  attribute \src "ls180.v:542.5-542.45"
+  process $proc$ls180.v:542$3071
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
+  end
+  attribute \src "ls180.v:543.5-543.45"
+  process $proc$ls180.v:543$3072
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
+  end
+  attribute \src "ls180.v:544.12-544.57"
+  process $proc$ls180.v:544$3073
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
+  end
+  attribute \src "ls180.v:546.5-546.51"
+  process $proc$ls180.v:546$3074
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
+  end
+  attribute \src "ls180.v:547.5-547.51"
+  process $proc$ls180.v:547$3075
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
+  end
+  attribute \src "ls180.v:548.5-548.50"
+  process $proc$ls180.v:548$3076
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
+  end
+  attribute \src "ls180.v:549.5-549.54"
+  process $proc$ls180.v:549$3077
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
   end
-  attribute \src "ls180.v:5422.1-5429.4"
-  process $proc$ls180.v:5422$987
+  attribute \src "ls180.v:5497.1-5504.4"
+  process $proc$ls180.v:5497$1038
     assign { } { }
     assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
-    attribute \src "ls180.v:5424.2-5428.5"
+    attribute \src "ls180.v:5499.2-5503.5"
     switch \main_sdblock2mem_fifo_replace
-      attribute \src "ls180.v:5424.6-5424.35"
+      attribute \src "ls180.v:5499.6-5499.35"
       case 1'1
-        assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5425$988_Y
-      attribute \src "ls180.v:5426.6-5426.10"
+        assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5500$1039_Y
+      attribute \src "ls180.v:5501.6-5501.10"
       case 
         assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce
     end
     sync always
       update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
   end
-  attribute \src "ls180.v:5455.1-5494.4"
-  process $proc$ls180.v:5455$998
+  attribute \src "ls180.v:55.5-55.42"
+  process $proc$ls180.v:55$2895
     assign { } { }
+    assign $1\main_libresocsim_reset_storage[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
+  end
+  attribute \src "ls180.v:550.5-550.55"
+  process $proc$ls180.v:550$3078
     assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
+  end
+  attribute \src "ls180.v:551.5-551.56"
+  process $proc$ls180.v:551$3079
     assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
+  end
+  attribute \src "ls180.v:552.5-552.50"
+  process $proc$ls180.v:552$3080
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
+  end
+  attribute \src "ls180.v:5530.1-5569.4"
+  process $proc$ls180.v:5530$1049
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
     assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
     assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
     assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
-    assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
-    assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
-    assign { } { }
     assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state
-    attribute \src "ls180.v:5465.2-5493.9"
+    attribute \src "ls180.v:5540.2-5568.9"
     switch \builder_sdblock2memdma_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid
         assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data
-        assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5469$999_Y
+        assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5544$1050_Y
         assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1
-        attribute \src "ls180.v:5471.4-5482.7"
-        switch $and$ls180.v:5471$1000_Y
-          attribute \src "ls180.v:5471.8-5471.103"
+        attribute \src "ls180.v:5546.4-5557.7"
+        switch $and$ls180.v:5546$1051_Y
+          attribute \src "ls180.v:5546.8-5546.103"
           case 1'1
-            assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5472$1001_Y
+            assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5547$1052_Y
             assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:5474.5-5481.8"
-            switch $eq$ls180.v:5474$1003_Y
-              attribute \src "ls180.v:5474.9-5474.106"
+            attribute \src "ls180.v:5549.5-5556.8"
+            switch $eq$ls180.v:5549$1054_Y
+              attribute \src "ls180.v:5549.9-5549.106"
               case 1'1
-                attribute \src "ls180.v:5475.6-5480.9"
+                attribute \src "ls180.v:5550.6-5555.9"
                 switch \main_sdblock2mem_wishbonedmawriter_loop_storage
-                  attribute \src "ls180.v:5475.10-5475.57"
+                  attribute \src "ls180.v:5550.10-5550.57"
                   case 1'1
                     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
                     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
-                  attribute \src "ls180.v:5478.10-5478.14"
+                  attribute \src "ls180.v:5553.10-5553.14"
                   case 
                     assign $0\builder_sdblock2memdma_next_state[1:0] 2'10
                 end
@@ -272687,24 +274425,24 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:55.5-55.42"
-  process $proc$ls180.v:55$2763
+  attribute \src "ls180.v:555.5-555.67"
+  process $proc$ls180.v:555$3081
     assign { } { }
-    assign $1\main_libresocsim_reset_storage[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
     sync init
-      update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
   end
-  attribute \src "ls180.v:551.5-551.59"
-  process $proc$ls180.v:551$2947
+  attribute \src "ls180.v:556.5-556.66"
+  process $proc$ls180.v:556$3082
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:5514.1-5551.4"
-  process $proc$ls180.v:5514$1005
+  attribute \src "ls180.v:5589.1-5626.4"
+  process $proc$ls180.v:5589$1056
     assign { } { }
     assign { } { }
     assign { } { }
@@ -272717,29 +274455,29 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_interface1_bus_adr[31:0] 0
-    assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
-    assign $0\main_interface1_bus_sel[3:0] 4'0000
-    assign $0\main_interface1_bus_cyc[0:0] 1'0
-    assign $0\main_interface1_bus_stb[0:0] 1'0
-    assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
     assign $0\main_interface1_bus_we[0:0] 1'0
     assign $0\main_sdmem2block_dma_source_last[0:0] 1'0
     assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0
     assign { } { }
     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
+    assign $0\main_interface1_bus_adr[31:0] 0
+    assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
+    assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
+    assign $0\main_interface1_bus_sel[3:0] 4'0000
+    assign $0\main_interface1_bus_cyc[0:0] 1'0
+    assign $0\main_interface1_bus_stb[0:0] 1'0
     assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state
-    attribute \src "ls180.v:5528.2-5550.9"
+    attribute \src "ls180.v:5603.2-5625.9"
     switch \builder_sdmem2blockdma_fsm_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1
         assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last
         assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data
-        attribute \src "ls180.v:5533.4-5536.7"
+        attribute \src "ls180.v:5608.4-5611.7"
         switch \main_sdmem2block_dma_source_ready
-          attribute \src "ls180.v:5533.8-5533.41"
+          attribute \src "ls180.v:5608.8-5608.41"
           case 1'1
             assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1
             assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
@@ -272752,9 +274490,9 @@ module \ls180
         assign $0\main_interface1_bus_we[0:0] 1'0
         assign $0\main_interface1_bus_sel[3:0] 4'1111
         assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address
-        attribute \src "ls180.v:5544.4-5548.7"
-        switch $and$ls180.v:5544$1006_Y
-          attribute \src "ls180.v:5544.8-5544.59"
+        attribute \src "ls180.v:5619.4-5623.7"
+        switch $and$ls180.v:5619$1057_Y
+          attribute \src "ls180.v:5619.8-5619.59"
           case 1'1
             assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] }
             assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1
@@ -272776,32 +274514,16 @@ module \ls180
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:553.5-553.59"
-  process $proc$ls180.v:553$2948
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  end
-  attribute \src "ls180.v:554.5-554.58"
-  process $proc$ls180.v:554$2949
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  end
-  attribute \src "ls180.v:555.5-555.64"
-  process $proc$ls180.v:555$2950
+  attribute \src "ls180.v:56.5-56.37"
+  process $proc$ls180.v:56$2896
     assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
+    assign $1\main_libresocsim_reset_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
+      update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
   end
-  attribute \src "ls180.v:5552.1-5588.4"
-  process $proc$ls180.v:5552$1007
+  attribute \src "ls180.v:5627.1-5663.4"
+  process $proc$ls180.v:5627$1058
     assign { } { }
     assign { } { }
     assign { } { }
@@ -272809,38 +274531,38 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
-    assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
     assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
+    assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
     assign { } { }
-    assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
+    assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
+    assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
     assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state
-    attribute \src "ls180.v:5561.2-5587.9"
+    attribute \src "ls180.v:5636.2-5662.9"
     switch \builder_sdmem2blockdma_resetinserter_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1
-        assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5564$1009_Y
-        assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5565$1010_Y
-        attribute \src "ls180.v:5566.4-5577.7"
+        assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5639$1060_Y
+        assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5640$1061_Y
+        attribute \src "ls180.v:5641.4-5652.7"
         switch \main_sdmem2block_dma_sink_ready
-          attribute \src "ls180.v:5566.8-5566.39"
+          attribute \src "ls180.v:5641.8-5641.39"
           case 1'1
-            assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5567$1011_Y
+            assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5642$1062_Y
             assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
-            attribute \src "ls180.v:5569.5-5576.8"
+            attribute \src "ls180.v:5644.5-5651.8"
             switch \main_sdmem2block_dma_sink_last
-              attribute \src "ls180.v:5569.9-5569.39"
+              attribute \src "ls180.v:5644.9-5644.39"
               case 1'1
-                attribute \src "ls180.v:5570.6-5575.9"
+                attribute \src "ls180.v:5645.6-5650.9"
                 switch \main_sdmem2block_dma_loop_storage
-                  attribute \src "ls180.v:5570.10-5570.43"
+                  attribute \src "ls180.v:5645.10-5645.43"
                   case 1'1
                     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
                     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
-                  attribute \src "ls180.v:5573.10-5573.14"
+                  attribute \src "ls180.v:5648.10-5648.14"
                   case 
                     assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10
                 end
@@ -272866,51 +274588,11 @@ module \ls180
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:556.12-556.74"
-  process $proc$ls180.v:556$2951
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  end
-  attribute \src "ls180.v:557.12-557.47"
-  process $proc$ls180.v:557$2952
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
-  end
-  attribute \src "ls180.v:558.5-558.46"
-  process $proc$ls180.v:558$2953
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
-  end
-  attribute \src "ls180.v:56.5-56.37"
-  process $proc$ls180.v:56$2764
-    assign { } { }
-    assign $1\main_libresocsim_reset_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
-  end
-  attribute \src "ls180.v:560.5-560.44"
-  process $proc$ls180.v:560$2954
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
-  end
-  attribute \src "ls180.v:5600.1-5616.4"
-  process $proc$ls180.v:5600$1017
+  attribute \src "ls180.v:5675.1-5691.4"
+  process $proc$ls180.v:5675$1068
     assign { } { }
     assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
-    attribute \src "ls180.v:5602.2-5615.9"
+    attribute \src "ls180.v:5677.2-5690.9"
     switch \main_sdmem2block_converter_mux
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -272928,48 +274610,48 @@ module \ls180
     sync always
       update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:561.5-561.45"
-  process $proc$ls180.v:561$2955
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
-  end
-  attribute \src "ls180.v:562.5-562.54"
-  process $proc$ls180.v:562$2956
+  attribute \src "ls180.v:57.12-57.60"
+  process $proc$ls180.v:57$2897
     assign { } { }
-    assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+    assign $1\main_libresocsim_scratch_storage[31:0] 305419896
     sync always
     sync init
-      update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
+      update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
   end
-  attribute \src "ls180.v:5630.1-5637.4"
-  process $proc$ls180.v:5630$1018
+  attribute \src "ls180.v:5705.1-5712.4"
+  process $proc$ls180.v:5705$1069
     assign { } { }
     assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
-    attribute \src "ls180.v:5632.2-5636.5"
+    attribute \src "ls180.v:5707.2-5711.5"
     switch \main_sdmem2block_fifo_replace
-      attribute \src "ls180.v:5632.6-5632.35"
+      attribute \src "ls180.v:5707.6-5707.35"
       case 1'1
-        assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5633$1019_Y
-      attribute \src "ls180.v:5634.6-5634.10"
+        assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5708$1070_Y
+      attribute \src "ls180.v:5709.6-5709.10"
       case 
         assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce
     end
     sync always
       update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
   end
-  attribute \src "ls180.v:564.32-564.76"
-  process $proc$ls180.v:564$2957
+  attribute \src "ls180.v:571.11-571.68"
+  process $proc$ls180.v:571$3083
     assign { } { }
-    assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
-      update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:5645.1-5681.4"
-  process $proc$ls180.v:5645$1025
+  attribute \src "ls180.v:572.5-572.64"
+  process $proc$ls180.v:572$3084
+    assign { } { }
+    assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
+    sync always
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:5720.1-5756.4"
+  process $proc$ls180.v:5720$1076
     assign { } { }
     assign { } { }
     assign { } { }
@@ -272979,17 +274661,17 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
-    assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
-    assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
-    assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
     assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
     assign { } { }
     assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
     assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
     assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
+    assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
+    assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
+    assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
+    assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
     assign $0\builder_next_state[1:0] \builder_state
-    attribute \src "ls180.v:5656.2-5680.9"
+    attribute \src "ls180.v:5731.2-5755.9"
     switch \builder_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
@@ -273007,13 +274689,13 @@ module \ls180
       case 
         assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0]
         assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1
-        attribute \src "ls180.v:5672.4-5678.7"
-        switch $and$ls180.v:5672$1026_Y
-          attribute \src "ls180.v:5672.8-5672.77"
+        attribute \src "ls180.v:5747.4-5753.7"
+        switch $and$ls180.v:5747$1077_Y
+          attribute \src "ls180.v:5747.8-5747.77"
           case 1'1
             assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0]
             assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1
-            assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5675$1028_Y
+            assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5750$1079_Y
             assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1
             assign $0\builder_next_state[1:0] 2'01
           case 
@@ -273030,71 +274712,66 @@ module \ls180
       update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0]
       update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:565.11-565.55"
-  process $proc$ls180.v:565$2958
-    assign { } { }
-    assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
-  end
-  attribute \src "ls180.v:567.32-567.75"
-  process $proc$ls180.v:567$2959
+  attribute \src "ls180.v:573.11-573.70"
+  process $proc$ls180.v:573$3085
     assign { } { }
-    assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
+    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
-      update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
     sync init
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:569.32-569.76"
-  process $proc$ls180.v:569$2960
+  attribute \src "ls180.v:574.11-574.70"
+  process $proc$ls180.v:574$3086
     assign { } { }
-    assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
+    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
-      update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
     sync init
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:57.12-57.60"
-  process $proc$ls180.v:57$2765
+  attribute \src "ls180.v:575.11-575.73"
+  process $proc$ls180.v:575$3087
     assign { } { }
-    assign $1\main_libresocsim_scratch_storage[31:0] 305419896
+    assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
-      update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
+      update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:5706.1-5713.4"
-  process $proc$ls180.v:5706$1049
+  attribute \src "ls180.v:5781.1-5791.4"
+  process $proc$ls180.v:5781$1100
     assign { } { }
     assign { } { }
-    assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5708$1050_Y
-    assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5709$1051_Y
-    assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5710$1052_Y
-    assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5711$1053_Y
-    assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5712$1054_Y
+    assign $0\builder_slave_sel[7:0] [0] $eq$ls180.v:5783$1101_Y
+    assign $0\builder_slave_sel[7:0] [1] $eq$ls180.v:5784$1102_Y
+    assign $0\builder_slave_sel[7:0] [2] $eq$ls180.v:5785$1103_Y
+    assign $0\builder_slave_sel[7:0] [3] $eq$ls180.v:5786$1104_Y
+    assign $0\builder_slave_sel[7:0] [4] $eq$ls180.v:5787$1105_Y
+    assign $0\builder_slave_sel[7:0] [5] $eq$ls180.v:5788$1106_Y
+    assign $0\builder_slave_sel[7:0] [6] $eq$ls180.v:5789$1107_Y
+    assign $0\builder_slave_sel[7:0] [7] $eq$ls180.v:5790$1108_Y
     sync always
-      update \builder_slave_sel $0\builder_slave_sel[4:0]
+      update \builder_slave_sel $0\builder_slave_sel[7:0]
   end
-  attribute \src "ls180.v:575.5-575.51"
-  process $proc$ls180.v:575$2961
+  attribute \src "ls180.v:58.5-58.39"
+  process $proc$ls180.v:58$2898
     assign { } { }
-    assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+    assign $1\main_libresocsim_scratch_re[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
+      update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
   end
-  attribute \src "ls180.v:5756.1-5767.4"
-  process $proc$ls180.v:5756$1067
-    assign { } { }
+  attribute \src "ls180.v:5858.1-5869.4"
+  process $proc$ls180.v:5858$1127
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\builder_error[0:0] 1'0
-    assign $0\builder_shared_ack[0:0] $or$ls180.v:5760$1071_Y
-    assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5761$1080_Y
-    attribute \src "ls180.v:5762.2-5766.5"
+    assign { } { }
+    assign $0\builder_shared_ack[0:0] $or$ls180.v:5862$1134_Y
+    assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5863$1149_Y
+    attribute \src "ls180.v:5864.2-5868.5"
     switch \builder_done
-      attribute \src "ls180.v:5762.6-5762.18"
+      attribute \src "ls180.v:5864.6-5864.18"
       case 1'1
         assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111
         assign $0\builder_shared_ack[0:0] 1'1
@@ -273106,173 +274783,253 @@ module \ls180
       update \builder_shared_ack $0\builder_shared_ack[0:0]
       update \builder_error $0\builder_error[0:0]
   end
-  attribute \src "ls180.v:576.5-576.51"
-  process $proc$ls180.v:576$2962
+  attribute \src "ls180.v:596.5-596.59"
+  process $proc$ls180.v:596$3088
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
+  end
+  attribute \src "ls180.v:598.5-598.59"
+  process $proc$ls180.v:598$3089
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
+  end
+  attribute \src "ls180.v:599.5-599.58"
+  process $proc$ls180.v:599$3090
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
+  end
+  attribute \src "ls180.v:600.5-600.64"
+  process $proc$ls180.v:600$3091
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
+  end
+  attribute \src "ls180.v:601.12-601.74"
+  process $proc$ls180.v:601$3092
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
+  end
+  attribute \src "ls180.v:602.12-602.47"
+  process $proc$ls180.v:602$3093
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
+  end
+  attribute \src "ls180.v:603.5-603.46"
+  process $proc$ls180.v:603$3094
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
+  end
+  attribute \src "ls180.v:605.5-605.44"
+  process $proc$ls180.v:605$3095
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
+  end
+  attribute \src "ls180.v:606.5-606.45"
+  process $proc$ls180.v:606$3096
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
+  end
+  attribute \src "ls180.v:607.5-607.54"
+  process $proc$ls180.v:607$3097
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
+  end
+  attribute \src "ls180.v:609.32-609.76"
+  process $proc$ls180.v:609$3098
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
+  end
+  attribute \src "ls180.v:610.11-610.55"
+  process $proc$ls180.v:610$3099
+    assign { } { }
+    assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
+    sync always
+    sync init
+      update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
+  end
+  attribute \src "ls180.v:612.32-612.75"
+  process $proc$ls180.v:612$3100
+    assign { } { }
+    assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:614.32-614.76"
+  process $proc$ls180.v:614$3101
+    assign { } { }
+    assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:620.5-620.51"
+  process $proc$ls180.v:620$3102
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
+  end
+  attribute \src "ls180.v:621.5-621.51"
+  process $proc$ls180.v:621$3103
     assign { } { }
     assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:578.5-578.47"
-  process $proc$ls180.v:578$2963
+  attribute \src "ls180.v:623.5-623.47"
+  process $proc$ls180.v:623$3104
     assign { } { }
     assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:579.5-579.45"
-  process $proc$ls180.v:579$2964
+  attribute \src "ls180.v:624.5-624.45"
+  process $proc$ls180.v:624$3105
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:58.5-58.39"
-  process $proc$ls180.v:58$2766
-    assign { } { }
-    assign $1\main_libresocsim_scratch_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
-  end
-  attribute \src "ls180.v:580.5-580.45"
-  process $proc$ls180.v:580$2965
+  attribute \src "ls180.v:625.5-625.45"
+  process $proc$ls180.v:625$3106
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:581.12-581.57"
-  process $proc$ls180.v:581$2966
+  attribute \src "ls180.v:626.12-626.57"
+  process $proc$ls180.v:626$3107
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:583.5-583.51"
-  process $proc$ls180.v:583$2967
+  attribute \src "ls180.v:628.5-628.51"
+  process $proc$ls180.v:628$3108
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:584.5-584.51"
-  process $proc$ls180.v:584$2968
+  attribute \src "ls180.v:629.5-629.51"
+  process $proc$ls180.v:629$3109
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:585.5-585.50"
-  process $proc$ls180.v:585$2969
+  attribute \src "ls180.v:63.12-63.47"
+  process $proc$ls180.v:63$2899
+    assign { } { }
+    assign $1\main_libresocsim_bus_errors[31:0] 0
+    sync always
+    sync init
+      update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
+  end
+  attribute \src "ls180.v:630.5-630.50"
+  process $proc$ls180.v:630$3110
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:586.5-586.54"
-  process $proc$ls180.v:586$2970
+  attribute \src "ls180.v:631.5-631.54"
+  process $proc$ls180.v:631$3111
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
   end
-  attribute \src "ls180.v:587.5-587.55"
-  process $proc$ls180.v:587$2971
+  attribute \src "ls180.v:632.5-632.55"
+  process $proc$ls180.v:632$3112
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
   end
-  attribute \src "ls180.v:588.5-588.56"
-  process $proc$ls180.v:588$2972
+  attribute \src "ls180.v:633.5-633.56"
+  process $proc$ls180.v:633$3113
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
   end
-  attribute \src "ls180.v:589.5-589.50"
-  process $proc$ls180.v:589$2973
+  attribute \src "ls180.v:634.5-634.50"
+  process $proc$ls180.v:634$3114
     assign { } { }
     assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
     sync always
     sync init
       update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:592.5-592.67"
-  process $proc$ls180.v:592$2974
+  attribute \src "ls180.v:637.5-637.67"
+  process $proc$ls180.v:637$3115
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:593.5-593.66"
-  process $proc$ls180.v:593$2975
+  attribute \src "ls180.v:638.5-638.66"
+  process $proc$ls180.v:638$3116
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:608.11-608.68"
-  process $proc$ls180.v:608$2976
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  end
-  attribute \src "ls180.v:609.5-609.64"
-  process $proc$ls180.v:609$2977
-    assign { } { }
-    assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
-    sync always
-      update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:610.11-610.70"
-  process $proc$ls180.v:610$2978
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
-  end
-  attribute \src "ls180.v:611.11-611.70"
-  process $proc$ls180.v:611$2979
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  end
-  attribute \src "ls180.v:612.11-612.73"
-  process $proc$ls180.v:612$2980
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  end
-  attribute \src "ls180.v:6281.1-6286.4"
-  process $proc$ls180.v:6281$1954
+  attribute \src "ls180.v:6383.1-6388.4"
+  process $proc$ls180.v:6383$2023
     assign { } { }
     assign $0\main_spimaster9_start[0:0] 1'0
-    attribute \src "ls180.v:6283.2-6285.5"
+    attribute \src "ls180.v:6385.2-6387.5"
     switch \main_spimaster12_re
-      attribute \src "ls180.v:6283.6-6283.25"
+      attribute \src "ls180.v:6385.6-6385.25"
       case 1'1
         assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0]
       case 
@@ -273280,21 +275037,13 @@ module \ls180
     sync always
       update \main_spimaster9_start $0\main_spimaster9_start[0:0]
   end
-  attribute \src "ls180.v:63.12-63.47"
-  process $proc$ls180.v:63$2767
-    assign { } { }
-    assign $1\main_libresocsim_bus_errors[31:0] 0
-    sync always
-    sync init
-      update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
-  end
-  attribute \src "ls180.v:6327.1-6332.4"
-  process $proc$ls180.v:6327$2019
+  attribute \src "ls180.v:6429.1-6434.4"
+  process $proc$ls180.v:6429$2088
     assign { } { }
     assign $0\main_spisdcard_start1[0:0] 1'0
-    attribute \src "ls180.v:6329.2-6331.5"
+    attribute \src "ls180.v:6431.2-6433.5"
     switch \main_spisdcard_control_re
-      attribute \src "ls180.v:6329.6-6329.31"
+      attribute \src "ls180.v:6431.6-6431.31"
       case 1'1
         assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0]
       case 
@@ -273302,131 +275051,59 @@ module \ls180
     sync always
       update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
   end
-  attribute \src "ls180.v:633.5-633.59"
-  process $proc$ls180.v:633$2981
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
-  end
-  attribute \src "ls180.v:635.5-635.59"
-  process $proc$ls180.v:635$2982
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  end
-  attribute \src "ls180.v:636.5-636.58"
-  process $proc$ls180.v:636$2983
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  end
-  attribute \src "ls180.v:637.5-637.64"
-  process $proc$ls180.v:637$2984
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  end
-  attribute \src "ls180.v:638.12-638.74"
-  process $proc$ls180.v:638$2985
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  end
-  attribute \src "ls180.v:639.12-639.47"
-  process $proc$ls180.v:639$2986
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
-  end
-  attribute \src "ls180.v:640.5-640.46"
-  process $proc$ls180.v:640$2987
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
-  end
-  attribute \src "ls180.v:642.5-642.44"
-  process $proc$ls180.v:642$2988
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
-  end
-  attribute \src "ls180.v:643.5-643.45"
-  process $proc$ls180.v:643$2989
-    assign { } { }
-    assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
-  end
-  attribute \src "ls180.v:644.5-644.54"
-  process $proc$ls180.v:644$2990
+  attribute \src "ls180.v:65.12-65.55"
+  process $proc$ls180.v:65$2900
     assign { } { }
-    assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
+    assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
     sync always
     sync init
-      update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
+      update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
   end
-  attribute \src "ls180.v:646.32-646.76"
-  process $proc$ls180.v:646$2991
+  attribute \src "ls180.v:653.11-653.68"
+  process $proc$ls180.v:653$3117
     assign { } { }
-    assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
-      update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
+      update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:647.11-647.55"
-  process $proc$ls180.v:647$2992
+  attribute \src "ls180.v:654.5-654.64"
+  process $proc$ls180.v:654$3118
     assign { } { }
-    assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
+    assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
+      update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
     sync init
-      update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0]
   end
-  attribute \src "ls180.v:649.32-649.75"
-  process $proc$ls180.v:649$2993
+  attribute \src "ls180.v:655.11-655.70"
+  process $proc$ls180.v:655$3119
     assign { } { }
-    assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
+    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
-      update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
     sync init
+      update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:65.12-65.55"
-  process $proc$ls180.v:65$2768
+  attribute \src "ls180.v:656.11-656.70"
+  process $proc$ls180.v:656$3120
     assign { } { }
-    assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
+    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
-      update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
+      update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:651.32-651.76"
-  process $proc$ls180.v:651$2994
+  attribute \src "ls180.v:657.11-657.73"
+  process $proc$ls180.v:657$3121
     assign { } { }
-    assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
+    assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
-      update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
     sync init
+      update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:6516.1-6532.4"
-  process $proc$ls180.v:6516$2240
+  attribute \src "ls180.v:6618.1-6634.4"
+  process $proc$ls180.v:6618$2309
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0
-    attribute \src "ls180.v:6518.2-6531.9"
+    attribute \src "ls180.v:6620.2-6633.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273444,11 +275121,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:6533.1-6549.4"
-  process $proc$ls180.v:6533$2241
+  attribute \src "ls180.v:6635.1-6651.4"
+  process $proc$ls180.v:6635$2310
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
-    attribute \src "ls180.v:6535.2-6548.9"
+    attribute \src "ls180.v:6637.2-6650.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273466,11 +275143,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:6550.1-6566.4"
-  process $proc$ls180.v:6550$2242
+  attribute \src "ls180.v:6652.1-6668.4"
+  process $proc$ls180.v:6652$2311
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00
-    attribute \src "ls180.v:6552.2-6565.9"
+    attribute \src "ls180.v:6654.2-6667.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273488,11 +275165,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0]
   end
-  attribute \src "ls180.v:6567.1-6583.4"
-  process $proc$ls180.v:6567$2243
+  attribute \src "ls180.v:6669.1-6685.4"
+  process $proc$ls180.v:6669$2312
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:6569.2-6582.9"
+    attribute \src "ls180.v:6671.2-6684.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273510,27 +275187,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:657.5-657.51"
-  process $proc$ls180.v:657$2995
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
-  end
-  attribute \src "ls180.v:658.5-658.51"
-  process $proc$ls180.v:658$2996
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
-  end
-  attribute \src "ls180.v:6584.1-6600.4"
-  process $proc$ls180.v:6584$2244
+  attribute \src "ls180.v:6686.1-6702.4"
+  process $proc$ls180.v:6686$2313
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:6586.2-6599.9"
+    attribute \src "ls180.v:6688.2-6701.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273548,19 +275209,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:660.5-660.47"
-  process $proc$ls180.v:660$2997
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
-  end
-  attribute \src "ls180.v:6601.1-6617.4"
-  process $proc$ls180.v:6601$2245
+  attribute \src "ls180.v:6703.1-6719.4"
+  process $proc$ls180.v:6703$2314
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:6603.2-6616.9"
+    attribute \src "ls180.v:6705.2-6718.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273578,19 +275231,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:661.5-661.45"
-  process $proc$ls180.v:661$2998
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
-  end
-  attribute \src "ls180.v:6618.1-6634.4"
-  process $proc$ls180.v:6618$2246
+  attribute \src "ls180.v:6720.1-6736.4"
+  process $proc$ls180.v:6720$2315
     assign { } { }
     assign $0\builder_comb_t_array_muxed0[0:0] 1'0
-    attribute \src "ls180.v:6620.2-6633.9"
+    attribute \src "ls180.v:6722.2-6735.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273608,27 +275253,11 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:662.5-662.45"
-  process $proc$ls180.v:662$2999
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
-  end
-  attribute \src "ls180.v:663.12-663.57"
-  process $proc$ls180.v:663$3000
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
-  end
-  attribute \src "ls180.v:6635.1-6651.4"
-  process $proc$ls180.v:6635$2247
+  attribute \src "ls180.v:6737.1-6753.4"
+  process $proc$ls180.v:6737$2316
     assign { } { }
     assign $0\builder_comb_t_array_muxed1[0:0] 1'0
-    attribute \src "ls180.v:6637.2-6650.9"
+    attribute \src "ls180.v:6739.2-6752.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273646,19 +275275,11 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:665.5-665.51"
-  process $proc$ls180.v:665$3001
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
-  end
-  attribute \src "ls180.v:6652.1-6668.4"
-  process $proc$ls180.v:6652$2248
+  attribute \src "ls180.v:6754.1-6770.4"
+  process $proc$ls180.v:6754$2317
     assign { } { }
     assign $0\builder_comb_t_array_muxed2[0:0] 1'0
-    attribute \src "ls180.v:6654.2-6667.9"
+    attribute \src "ls180.v:6756.2-6769.9"
     switch \main_sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273676,19 +275297,11 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:666.5-666.51"
-  process $proc$ls180.v:666$3002
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
-  end
-  attribute \src "ls180.v:6669.1-6685.4"
-  process $proc$ls180.v:6669$2249
+  attribute \src "ls180.v:6771.1-6787.4"
+  process $proc$ls180.v:6771$2318
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0
-    attribute \src "ls180.v:6671.2-6684.9"
+    attribute \src "ls180.v:6773.2-6786.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273706,27 +275319,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:667.5-667.50"
-  process $proc$ls180.v:667$3003
+  attribute \src "ls180.v:678.5-678.59"
+  process $proc$ls180.v:678$3122
     assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
-  end
-  attribute \src "ls180.v:668.5-668.54"
-  process $proc$ls180.v:668$3004
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
+      update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:6686.1-6702.4"
-  process $proc$ls180.v:6686$2250
+  attribute \src "ls180.v:6788.1-6804.4"
+  process $proc$ls180.v:6788$2319
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
-    attribute \src "ls180.v:6688.2-6701.9"
+    attribute \src "ls180.v:6790.2-6803.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273744,27 +275349,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
   end
-  attribute \src "ls180.v:669.5-669.55"
-  process $proc$ls180.v:669$3005
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
-  end
-  attribute \src "ls180.v:670.5-670.56"
-  process $proc$ls180.v:670$3006
+  attribute \src "ls180.v:680.5-680.59"
+  process $proc$ls180.v:680$3123
     assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
+      update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:6703.1-6719.4"
-  process $proc$ls180.v:6703$2251
+  attribute \src "ls180.v:6805.1-6821.4"
+  process $proc$ls180.v:6805$2320
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00
-    attribute \src "ls180.v:6705.2-6718.9"
+    attribute \src "ls180.v:6807.2-6820.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273782,19 +275379,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
   end
-  attribute \src "ls180.v:671.5-671.50"
-  process $proc$ls180.v:671$3007
+  attribute \src "ls180.v:681.5-681.58"
+  process $proc$ls180.v:681$3124
     assign { } { }
-    assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
+      update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
   end
-  attribute \src "ls180.v:6720.1-6736.4"
-  process $proc$ls180.v:6720$2252
+  attribute \src "ls180.v:682.5-682.64"
+  process $proc$ls180.v:682$3125
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
+  end
+  attribute \src "ls180.v:6822.1-6838.4"
+  process $proc$ls180.v:6822$2321
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0
-    attribute \src "ls180.v:6722.2-6735.9"
+    attribute \src "ls180.v:6824.2-6837.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273812,11 +275417,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
   end
-  attribute \src "ls180.v:6737.1-6753.4"
-  process $proc$ls180.v:6737$2253
+  attribute \src "ls180.v:683.12-683.74"
+  process $proc$ls180.v:683$3126
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
+  end
+  attribute \src "ls180.v:6839.1-6855.4"
+  process $proc$ls180.v:6839$2322
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0
-    attribute \src "ls180.v:6739.2-6752.9"
+    attribute \src "ls180.v:6841.2-6854.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273834,27 +275447,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
   end
-  attribute \src "ls180.v:674.5-674.67"
-  process $proc$ls180.v:674$3008
+  attribute \src "ls180.v:684.12-684.47"
+  process $proc$ls180.v:684$3127
     assign { } { }
-    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
     sync always
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
     sync init
+      update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
   end
-  attribute \src "ls180.v:675.5-675.66"
-  process $proc$ls180.v:675$3009
+  attribute \src "ls180.v:685.5-685.46"
+  process $proc$ls180.v:685$3128
     assign { } { }
-    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
     sync init
+      update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
   end
-  attribute \src "ls180.v:6754.1-6770.4"
-  process $proc$ls180.v:6754$2254
+  attribute \src "ls180.v:6856.1-6872.4"
+  process $proc$ls180.v:6856$2323
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0
-    attribute \src "ls180.v:6756.2-6769.9"
+    attribute \src "ls180.v:6858.2-6871.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273872,11 +275485,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0]
   end
-  attribute \src "ls180.v:6771.1-6787.4"
-  process $proc$ls180.v:6771$2255
+  attribute \src "ls180.v:687.5-687.44"
+  process $proc$ls180.v:687$3129
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
+  end
+  attribute \src "ls180.v:6873.1-6889.4"
+  process $proc$ls180.v:6873$2324
     assign { } { }
     assign $0\builder_comb_t_array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:6773.2-6786.9"
+    attribute \src "ls180.v:6875.2-6888.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273894,11 +275515,27 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:6788.1-6804.4"
-  process $proc$ls180.v:6788$2256
+  attribute \src "ls180.v:688.5-688.45"
+  process $proc$ls180.v:688$3130
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
+  end
+  attribute \src "ls180.v:689.5-689.54"
+  process $proc$ls180.v:689$3131
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
+  end
+  attribute \src "ls180.v:6890.1-6906.4"
+  process $proc$ls180.v:6890$2325
     assign { } { }
     assign $0\builder_comb_t_array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:6790.2-6803.9"
+    attribute \src "ls180.v:6892.2-6905.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273916,11 +275553,11 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:6805.1-6821.4"
-  process $proc$ls180.v:6805$2257
+  attribute \src "ls180.v:6907.1-6923.4"
+  process $proc$ls180.v:6907$2326
     assign { } { }
     assign $0\builder_comb_t_array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:6807.2-6820.9"
+    attribute \src "ls180.v:6909.2-6922.9"
     switch \main_sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -273938,11 +275575,27 @@ module \ls180
     sync always
       update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:6822.1-6829.4"
-  process $proc$ls180.v:6822$2258
+  attribute \src "ls180.v:691.32-691.76"
+  process $proc$ls180.v:691$3132
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
+  end
+  attribute \src "ls180.v:692.11-692.55"
+  process $proc$ls180.v:692$3133
+    assign { } { }
+    assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
+    sync always
+    sync init
+      update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0]
+  end
+  attribute \src "ls180.v:6924.1-6931.4"
+  process $proc$ls180.v:6924$2327
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:6824.2-6828.9"
+    attribute \src "ls180.v:6926.2-6930.9"
     switch \builder_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -273951,11 +275604,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0]
   end
-  attribute \src "ls180.v:6830.1-6837.4"
-  process $proc$ls180.v:6830$2259
+  attribute \src "ls180.v:6932.1-6939.4"
+  process $proc$ls180.v:6932$2328
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0
-    attribute \src "ls180.v:6832.2-6836.9"
+    attribute \src "ls180.v:6934.2-6938.9"
     switch \builder_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -273964,24 +275617,32 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0]
   end
-  attribute \src "ls180.v:6838.1-6845.4"
-  process $proc$ls180.v:6838$2260
+  attribute \src "ls180.v:694.32-694.75"
+  process $proc$ls180.v:694$3134
+    assign { } { }
+    assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:6940.1-6947.4"
+  process $proc$ls180.v:6940$2329
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0
-    attribute \src "ls180.v:6840.2-6844.9"
+    attribute \src "ls180.v:6942.2-6946.9"
     switch \builder_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6842$2273_Y
+        assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6944$2342_Y
     end
     sync always
       update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0]
   end
-  attribute \src "ls180.v:6846.1-6853.4"
-  process $proc$ls180.v:6846$2274
+  attribute \src "ls180.v:6948.1-6955.4"
+  process $proc$ls180.v:6948$2343
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:6848.2-6852.9"
+    attribute \src "ls180.v:6950.2-6954.9"
     switch \builder_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -273990,11 +275651,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0]
   end
-  attribute \src "ls180.v:6854.1-6861.4"
-  process $proc$ls180.v:6854$2275
+  attribute \src "ls180.v:6956.1-6963.4"
+  process $proc$ls180.v:6956$2344
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0
-    attribute \src "ls180.v:6856.2-6860.9"
+    attribute \src "ls180.v:6958.2-6962.9"
     switch \builder_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -274003,24 +275664,32 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0]
   end
-  attribute \src "ls180.v:6862.1-6869.4"
-  process $proc$ls180.v:6862$2276
+  attribute \src "ls180.v:696.32-696.76"
+  process $proc$ls180.v:696$3135
+    assign { } { }
+    assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:6964.1-6971.4"
+  process $proc$ls180.v:6964$2345
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0
-    attribute \src "ls180.v:6864.2-6868.9"
+    attribute \src "ls180.v:6966.2-6970.9"
     switch \builder_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6866$2289_Y
+        assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6968$2358_Y
     end
     sync always
       update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0]
   end
-  attribute \src "ls180.v:6870.1-6877.4"
-  process $proc$ls180.v:6870$2290
+  attribute \src "ls180.v:6972.1-6979.4"
+  process $proc$ls180.v:6972$2359
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:6872.2-6876.9"
+    attribute \src "ls180.v:6974.2-6978.9"
     switch \builder_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -274029,11 +275698,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0]
   end
-  attribute \src "ls180.v:6878.1-6885.4"
-  process $proc$ls180.v:6878$2291
+  attribute \src "ls180.v:6980.1-6987.4"
+  process $proc$ls180.v:6980$2360
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0
-    attribute \src "ls180.v:6880.2-6884.9"
+    attribute \src "ls180.v:6982.2-6986.9"
     switch \builder_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -274042,24 +275711,24 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0]
   end
-  attribute \src "ls180.v:6886.1-6893.4"
-  process $proc$ls180.v:6886$2292
+  attribute \src "ls180.v:6988.1-6995.4"
+  process $proc$ls180.v:6988$2361
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0
-    attribute \src "ls180.v:6888.2-6892.9"
+    attribute \src "ls180.v:6990.2-6994.9"
     switch \builder_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6890$2305_Y
+        assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6992$2374_Y
     end
     sync always
       update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0]
   end
-  attribute \src "ls180.v:6894.1-6901.4"
-  process $proc$ls180.v:6894$2306
+  attribute \src "ls180.v:6996.1-7003.4"
+  process $proc$ls180.v:6996$2375
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:6896.2-6900.9"
+    attribute \src "ls180.v:6998.2-7002.9"
     switch \builder_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -274068,19 +275737,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0]
   end
-  attribute \src "ls180.v:690.11-690.68"
-  process $proc$ls180.v:690$3010
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  end
-  attribute \src "ls180.v:6902.1-6909.4"
-  process $proc$ls180.v:6902$2307
+  attribute \src "ls180.v:7004.1-7011.4"
+  process $proc$ls180.v:7004$2376
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0
-    attribute \src "ls180.v:6904.2-6908.9"
+    attribute \src "ls180.v:7006.2-7010.9"
     switch \builder_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -274089,32 +275750,32 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0]
   end
-  attribute \src "ls180.v:691.5-691.64"
-  process $proc$ls180.v:691$3011
-    assign { } { }
-    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
-    sync always
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:6910.1-6917.4"
-  process $proc$ls180.v:6910$2308
+  attribute \src "ls180.v:7012.1-7019.4"
+  process $proc$ls180.v:7012$2377
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0
-    attribute \src "ls180.v:6912.2-6916.9"
+    attribute \src "ls180.v:7014.2-7018.9"
     switch \builder_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6914$2321_Y
+        assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7016$2390_Y
     end
     sync always
       update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0]
   end
-  attribute \src "ls180.v:6918.1-6937.4"
-  process $proc$ls180.v:6918$2322
+  attribute \src "ls180.v:702.5-702.51"
+  process $proc$ls180.v:702$3136
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
+  end
+  attribute \src "ls180.v:7020.1-7039.4"
+  process $proc$ls180.v:7020$2391
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed24[31:0] 0
-    attribute \src "ls180.v:6920.2-6936.9"
+    attribute \src "ls180.v:7022.2-7038.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274135,27 +275796,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
   end
-  attribute \src "ls180.v:692.11-692.70"
-  process $proc$ls180.v:692$3012
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
-  end
-  attribute \src "ls180.v:693.11-693.70"
-  process $proc$ls180.v:693$3013
+  attribute \src "ls180.v:703.5-703.51"
+  process $proc$ls180.v:703$3137
     assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
+    assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
+      update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:6938.1-6957.4"
-  process $proc$ls180.v:6938$2323
+  attribute \src "ls180.v:7040.1-7059.4"
+  process $proc$ls180.v:7040$2392
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed25[31:0] 0
-    attribute \src "ls180.v:6940.2-6956.9"
+    attribute \src "ls180.v:7042.2-7058.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274176,19 +275829,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
   end
-  attribute \src "ls180.v:694.11-694.73"
-  process $proc$ls180.v:694$3014
+  attribute \src "ls180.v:705.5-705.47"
+  process $proc$ls180.v:705$3138
     assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+    assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
     sync always
     sync init
-      update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
+      update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
+  end
+  attribute \src "ls180.v:706.5-706.45"
+  process $proc$ls180.v:706$3139
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:6958.1-6977.4"
-  process $proc$ls180.v:6958$2324
+  attribute \src "ls180.v:7060.1-7079.4"
+  process $proc$ls180.v:7060$2393
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000
-    attribute \src "ls180.v:6960.2-6976.9"
+    attribute \src "ls180.v:7062.2-7078.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274209,11 +275870,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
   end
-  attribute \src "ls180.v:6978.1-6997.4"
-  process $proc$ls180.v:6978$2325
+  attribute \src "ls180.v:707.5-707.45"
+  process $proc$ls180.v:707$3140
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
+  end
+  attribute \src "ls180.v:708.12-708.57"
+  process $proc$ls180.v:708$3141
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
+  end
+  attribute \src "ls180.v:7080.1-7099.4"
+  process $proc$ls180.v:7080$2394
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0
-    attribute \src "ls180.v:6980.2-6996.9"
+    attribute \src "ls180.v:7082.2-7098.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274234,11 +275911,19 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0]
   end
-  attribute \src "ls180.v:6998.1-7017.4"
-  process $proc$ls180.v:6998$2326
+  attribute \src "ls180.v:710.5-710.51"
+  process $proc$ls180.v:710$3142
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
+  end
+  attribute \src "ls180.v:7100.1-7119.4"
+  process $proc$ls180.v:7100$2395
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0
-    attribute \src "ls180.v:7000.2-7016.9"
+    attribute \src "ls180.v:7102.2-7118.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274259,11 +275944,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0]
   end
-  attribute \src "ls180.v:7018.1-7037.4"
-  process $proc$ls180.v:7018$2327
+  attribute \src "ls180.v:711.5-711.51"
+  process $proc$ls180.v:711$3143
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
+  end
+  attribute \src "ls180.v:712.5-712.50"
+  process $proc$ls180.v:712$3144
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
+  end
+  attribute \src "ls180.v:7120.1-7139.4"
+  process $proc$ls180.v:7120$2396
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0
-    attribute \src "ls180.v:7020.2-7036.9"
+    attribute \src "ls180.v:7122.2-7138.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274284,11 +275985,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0]
   end
-  attribute \src "ls180.v:7038.1-7057.4"
-  process $proc$ls180.v:7038$2328
+  attribute \src "ls180.v:713.5-713.54"
+  process $proc$ls180.v:713$3145
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
+  end
+  attribute \src "ls180.v:714.5-714.55"
+  process $proc$ls180.v:714$3146
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
+  end
+  attribute \src "ls180.v:7140.1-7159.4"
+  process $proc$ls180.v:7140$2397
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000
-    attribute \src "ls180.v:7040.2-7056.9"
+    attribute \src "ls180.v:7142.2-7158.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274309,11 +276026,27 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0]
   end
-  attribute \src "ls180.v:7058.1-7077.4"
-  process $proc$ls180.v:7058$2329
+  attribute \src "ls180.v:715.5-715.56"
+  process $proc$ls180.v:715$3147
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
+  end
+  attribute \src "ls180.v:716.5-716.50"
+  process $proc$ls180.v:716$3148
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
+  end
+  attribute \src "ls180.v:7160.1-7179.4"
+  process $proc$ls180.v:7160$2398
     assign { } { }
     assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00
-    attribute \src "ls180.v:7060.2-7076.9"
+    attribute \src "ls180.v:7162.2-7178.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274334,11 +276067,11 @@ module \ls180
     sync always
       update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0]
   end
-  attribute \src "ls180.v:7078.1-7094.4"
-  process $proc$ls180.v:7078$2330
+  attribute \src "ls180.v:7180.1-7196.4"
+  process $proc$ls180.v:7180$2399
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00
-    attribute \src "ls180.v:7080.2-7093.9"
+    attribute \src "ls180.v:7182.2-7195.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -274356,11 +276089,19 @@ module \ls180
     sync always
       update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0]
   end
-  attribute \src "ls180.v:7095.1-7111.4"
-  process $proc$ls180.v:7095$2331
+  attribute \src "ls180.v:719.5-719.67"
+  process $proc$ls180.v:719$3149
+    assign { } { }
+    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    sync always
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:7197.1-7213.4"
+  process $proc$ls180.v:7197$2400
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
-    attribute \src "ls180.v:7097.2-7110.9"
+    attribute \src "ls180.v:7199.2-7212.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -274378,153 +276119,137 @@ module \ls180
     sync always
       update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:7112.1-7128.4"
-  process $proc$ls180.v:7112$2332
+  attribute \src "ls180.v:72.5-72.46"
+  process $proc$ls180.v:72$2901
+    assign { } { }
+    assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
+  end
+  attribute \src "ls180.v:720.5-720.66"
+  process $proc$ls180.v:720$3150
+    assign { } { }
+    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    sync always
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:7214.1-7230.4"
+  process $proc$ls180.v:7214$2401
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
-    attribute \src "ls180.v:7114.2-7127.9"
+    attribute \src "ls180.v:7216.2-7229.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7119$2334_Y
+        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7221$2403_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7122$2336_Y
+        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7224$2405_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7125$2338_Y
+        assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7227$2407_Y
     end
     sync always
       update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:7129.1-7145.4"
-  process $proc$ls180.v:7129$2339
+  attribute \src "ls180.v:7231.1-7247.4"
+  process $proc$ls180.v:7231$2408
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:7131.2-7144.9"
+    attribute \src "ls180.v:7233.2-7246.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7136$2341_Y
+        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7238$2410_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7139$2343_Y
+        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7241$2412_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7142$2345_Y
+        assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7244$2414_Y
     end
     sync always
       update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:7146.1-7162.4"
-  process $proc$ls180.v:7146$2346
+  attribute \src "ls180.v:7248.1-7264.4"
+  process $proc$ls180.v:7248$2415
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:7148.2-7161.9"
+    attribute \src "ls180.v:7250.2-7263.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7153$2348_Y
+        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7255$2417_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7156$2350_Y
+        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7258$2419_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7159$2352_Y
+        assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7261$2421_Y
     end
     sync always
       update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:715.5-715.59"
-  process $proc$ls180.v:715$3015
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
-  end
-  attribute \src "ls180.v:7163.1-7179.4"
-  process $proc$ls180.v:7163$2353
+  attribute \src "ls180.v:7265.1-7281.4"
+  process $proc$ls180.v:7265$2422
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:7165.2-7178.9"
+    attribute \src "ls180.v:7267.2-7280.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7170$2355_Y
+        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7272$2424_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7173$2357_Y
+        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7275$2426_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7176$2359_Y
+        assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7278$2428_Y
     end
     sync always
       update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:717.5-717.59"
-  process $proc$ls180.v:717$3016
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  end
-  attribute \src "ls180.v:718.5-718.58"
-  process $proc$ls180.v:718$3017
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  end
-  attribute \src "ls180.v:7180.1-7196.4"
-  process $proc$ls180.v:7180$2360
+  attribute \src "ls180.v:7282.1-7298.4"
+  process $proc$ls180.v:7282$2429
     assign { } { }
     assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
-    attribute \src "ls180.v:7182.2-7195.9"
+    attribute \src "ls180.v:7284.2-7297.9"
     switch \main_sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7187$2362_Y
+        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7289$2431_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7190$2364_Y
+        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7292$2433_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7193$2366_Y
+        assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7295$2435_Y
     end
     sync always
       update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:719.5-719.64"
-  process $proc$ls180.v:719$3018
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  end
-  attribute \src "ls180.v:7197.1-7225.4"
-  process $proc$ls180.v:7197$2367
+  attribute \src "ls180.v:7299.1-7327.4"
+  process $proc$ls180.v:7299$2436
     assign { } { }
     assign $0\builder_sync_f_array_muxed0[0:0] 1'0
-    attribute \src "ls180.v:7199.2-7224.9"
+    attribute \src "ls180.v:7301.2-7326.9"
     switch \main_spimaster34_mosi_sel
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274554,43 +276279,11 @@ module \ls180
     sync always
       update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:72.5-72.46"
-  process $proc$ls180.v:72$2769
-    assign { } { }
-    assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
-  end
-  attribute \src "ls180.v:720.12-720.74"
-  process $proc$ls180.v:720$3019
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  end
-  attribute \src "ls180.v:721.12-721.47"
-  process $proc$ls180.v:721$3020
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
-  end
-  attribute \src "ls180.v:722.5-722.46"
-  process $proc$ls180.v:722$3021
-    assign { } { }
-    assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
-    sync always
-    sync init
-      update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
-  end
-  attribute \src "ls180.v:7226.1-7254.4"
-  process $proc$ls180.v:7226$2368
+  attribute \src "ls180.v:7328.1-7356.4"
+  process $proc$ls180.v:7328$2437
     assign { } { }
     assign $0\builder_sync_f_array_muxed1[0:0] 1'0
-    attribute \src "ls180.v:7228.2-7253.9"
+    attribute \src "ls180.v:7330.2-7355.9"
     switch \main_spisdcard_mosi_sel
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
@@ -274620,56 +276313,56 @@ module \ls180
     sync always
       update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:724.5-724.44"
-  process $proc$ls180.v:724$3022
+  attribute \src "ls180.v:735.11-735.68"
+  process $proc$ls180.v:735$3151
     assign { } { }
-    assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
+    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
-      update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:725.5-725.45"
-  process $proc$ls180.v:725$3023
+  attribute \src "ls180.v:736.5-736.64"
+  process $proc$ls180.v:736$3152
     assign { } { }
-    assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
+    assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
     sync init
-      update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
   end
-  attribute \src "ls180.v:726.5-726.54"
-  process $proc$ls180.v:726$3024
+  attribute \src "ls180.v:737.11-737.70"
+  process $proc$ls180.v:737$3153
     assign { } { }
-    assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
+    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:728.32-728.76"
-  process $proc$ls180.v:728$3025
+  attribute \src "ls180.v:738.11-738.70"
+  process $proc$ls180.v:738$3154
     assign { } { }
-    assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
+    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:729.11-729.55"
-  process $proc$ls180.v:729$3026
+  attribute \src "ls180.v:739.11-739.73"
+  process $proc$ls180.v:739$3155
     assign { } { }
-    assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
+    assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
-      update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
+      update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:731.32-731.75"
-  process $proc$ls180.v:731$3027
+  attribute \src "ls180.v:74.5-74.46"
+  process $proc$ls180.v:74$2902
     assign { } { }
-    assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
+    assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
     sync always
-      update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
+      update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
     sync init
   end
-  attribute \src "ls180.v:7312.1-7330.4"
-  process $proc$ls180.v:7312$2369
+  attribute \src "ls180.v:7414.1-7432.4"
+  process $proc$ls180.v:7414$2438
     assign { } { }
     assign { } { }
     assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1
@@ -274691,23 +276384,15 @@ module \ls180
     sync always
       update \main_gpio_status $0\main_gpio_status[15:0]
   end
-  attribute \src "ls180.v:733.32-733.76"
-  process $proc$ls180.v:733$3028
-    assign { } { }
-    assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
-    sync always
-      update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:7351.1-7353.4"
-  process $proc$ls180.v:7351$2370
+  attribute \src "ls180.v:7453.1-7455.4"
+  process $proc$ls180.v:7453$2439
     assign { } { }
     assign $0\main_int_rst[0:0] \sys_rst
     sync posedge \por_clk
       update \main_int_rst $0\main_int_rst[0:0]
   end
-  attribute \src "ls180.v:7355.1-7425.4"
-  process $proc$ls180.v:7355$2371
+  attribute \src "ls180.v:7457.1-7527.4"
+  process $proc$ls180.v:7457$2440
     assign { } { }
     assign { } { }
     assign { } { }
@@ -274783,7 +276468,7 @@ module \ls180
     assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0]
     assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1]
     assign $0\sdram_clock[0:0] \sys_clk_1
-    assign $0\sdcard_clk[0:0] $and$ls180.v:7412$2373_Y
+    assign $0\sdcard_clk[0:0] $and$ls180.v:7514$2442_Y
     assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe
     assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o
     assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i
@@ -274817,64 +276502,16 @@ module \ls180
       update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
       update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
   end
-  attribute \src "ls180.v:736.5-736.44"
-  process $proc$ls180.v:736$3029
-    assign { } { }
-    assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
-    sync always
-      update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:737.5-737.45"
-  process $proc$ls180.v:737$3030
-    assign { } { }
-    assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
-    sync always
-      update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:738.5-738.43"
-  process $proc$ls180.v:738$3031
-    assign { } { }
-    assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
-    sync always
-      update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:739.5-739.48"
-  process $proc$ls180.v:739$3032
-    assign { } { }
-    assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
-    sync always
-      update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:74.5-74.46"
-  process $proc$ls180.v:74$2770
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:741.5-741.43"
-  process $proc$ls180.v:741$3033
+  attribute \src "ls180.v:7529.1-10156.4"
+  process $proc$ls180.v:7529$2443
+    assign $0\uart_tx[0:0] \uart_tx
+    assign $0\spisdcard_clk[0:0] \spisdcard_clk
+    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
     assign { } { }
-    assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
-    sync always
-      update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:7427.1-10039.4"
-  process $proc$ls180.v:7427$2374
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
     assign $0\pwm[1:0] \pwm
-    assign $0\uart_tx[0:0] \uart_tx
-    assign $0\spisdcard_clk[0:0] \spisdcard_clk
-    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
-    assign { } { }
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -274903,6 +276540,9 @@ module \ls180
     assign $0\main_libresocsim_value[31:0] \main_libresocsim_value
     assign { } { }
     assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
     assign $0\main_sdram_storage[3:0] \main_sdram_storage
     assign { } { }
     assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage
@@ -275279,35 +276919,38 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_dummy[23:0] [0] $or$ls180.v:7428$2375_Y
-    assign $0\main_dummy[23:0] [1] $or$ls180.v:7429$2376_Y
-    assign $0\main_dummy[23:0] [2] $or$ls180.v:7430$2377_Y
-    assign $0\main_dummy[23:0] [3] $or$ls180.v:7431$2378_Y
-    assign $0\main_dummy[23:0] [4] $or$ls180.v:7432$2379_Y
-    assign $0\main_dummy[23:0] [5] $or$ls180.v:7433$2380_Y
-    assign $0\main_dummy[23:0] [6] $or$ls180.v:7434$2381_Y
-    assign $0\main_dummy[23:0] [7] $or$ls180.v:7435$2382_Y
-    assign $0\main_dummy[23:0] [8] $or$ls180.v:7436$2383_Y
-    assign $0\main_dummy[23:0] [9] $or$ls180.v:7437$2384_Y
-    assign $0\main_dummy[23:0] [10] $or$ls180.v:7438$2385_Y
-    assign $0\main_dummy[23:0] [11] $or$ls180.v:7439$2386_Y
-    assign $0\main_dummy[23:0] [12] $or$ls180.v:7440$2387_Y
-    assign $0\main_dummy[23:0] [13] $or$ls180.v:7441$2388_Y
-    assign $0\main_dummy[23:0] [14] $or$ls180.v:7442$2389_Y
-    assign $0\main_dummy[23:0] [15] $or$ls180.v:7443$2390_Y
-    assign $0\main_dummy[23:0] [16] $or$ls180.v:7444$2391_Y
-    assign $0\main_dummy[23:0] [17] $or$ls180.v:7445$2392_Y
-    assign $0\main_dummy[23:0] [18] $or$ls180.v:7446$2393_Y
-    assign $0\main_dummy[23:0] [19] $or$ls180.v:7447$2394_Y
-    assign $0\main_dummy[23:0] [20] $or$ls180.v:7448$2395_Y
-    assign $0\main_dummy[23:0] [21] $or$ls180.v:7449$2396_Y
-    assign $0\main_dummy[23:0] [22] $or$ls180.v:7450$2397_Y
-    assign $0\main_dummy[23:0] [23] $or$ls180.v:7451$2398_Y
+    assign $0\main_dummy[23:0] [0] $or$ls180.v:7530$2444_Y
+    assign $0\main_dummy[23:0] [1] $or$ls180.v:7531$2445_Y
+    assign $0\main_dummy[23:0] [2] $or$ls180.v:7532$2446_Y
+    assign $0\main_dummy[23:0] [3] $or$ls180.v:7533$2447_Y
+    assign $0\main_dummy[23:0] [4] $or$ls180.v:7534$2448_Y
+    assign $0\main_dummy[23:0] [5] $or$ls180.v:7535$2449_Y
+    assign $0\main_dummy[23:0] [6] $or$ls180.v:7536$2450_Y
+    assign $0\main_dummy[23:0] [7] $or$ls180.v:7537$2451_Y
+    assign $0\main_dummy[23:0] [8] $or$ls180.v:7538$2452_Y
+    assign $0\main_dummy[23:0] [9] $or$ls180.v:7539$2453_Y
+    assign $0\main_dummy[23:0] [10] $or$ls180.v:7540$2454_Y
+    assign $0\main_dummy[23:0] [11] $or$ls180.v:7541$2455_Y
+    assign $0\main_dummy[23:0] [12] $or$ls180.v:7542$2456_Y
+    assign $0\main_dummy[23:0] [13] $or$ls180.v:7543$2457_Y
+    assign $0\main_dummy[23:0] [14] $or$ls180.v:7544$2458_Y
+    assign $0\main_dummy[23:0] [15] $or$ls180.v:7545$2459_Y
+    assign $0\main_dummy[23:0] [16] $or$ls180.v:7546$2460_Y
+    assign $0\main_dummy[23:0] [17] $or$ls180.v:7547$2461_Y
+    assign $0\main_dummy[23:0] [18] $or$ls180.v:7548$2462_Y
+    assign $0\main_dummy[23:0] [19] $or$ls180.v:7549$2463_Y
+    assign $0\main_dummy[23:0] [20] $or$ls180.v:7550$2464_Y
+    assign $0\main_dummy[23:0] [21] $or$ls180.v:7551$2465_Y
+    assign $0\main_dummy[23:0] [22] $or$ls180.v:7552$2466_Y
+    assign $0\main_dummy[23:0] [23] $or$ls180.v:7553$2467_Y
     assign $0\builder_converter0_state[0:0] \builder_converter0_next_state
     assign $0\builder_converter1_state[0:0] \builder_converter1_next_state
     assign $0\builder_converter2_state[0:0] \builder_converter2_next_state
     assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
     assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger
+    assign $0\main_interface0_ram_bus_ack[0:0] 1'0
+    assign $0\main_interface1_ram_bus_ack[0:0] 1'0
+    assign $0\main_interface2_ram_bus_ack[0:0] 1'0
     assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en }
     assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2]
     assign $0\main_sdram_postponer_req_o[0:0] 1'0
@@ -275325,14 +276968,14 @@ module \ls180
     assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0
     assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0
     assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1
-    assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7893$2495_Y
-    assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7894$2496_Y
-    assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7895$2497_Y
+    assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8007$2573_Y
+    assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8008$2574_Y
+    assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8009$2575_Y
     assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5
     assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6
     assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state
-    assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7929$2515_Y
-    assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7930$2527_Y
+    assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8043$2593_Y
+    assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8044$2605_Y
     assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0
     assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1
     assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2
@@ -275342,11 +276985,11 @@ module \ls180
     assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx
     assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger
     assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger
-    assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8088$2573_Y
-    assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8097$2576_Y
+    assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8202$2651_Y
+    assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8211$2654_Y
     assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state
-    assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8123$2578_Y
-    assign $0\spimaster_cs_n[0:0] $or$ls180.v:8132$2581_Y
+    assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8237$2656_Y
+    assign $0\spimaster_cs_n[0:0] $or$ls180.v:8246$2659_Y
     assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state
     assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1
     assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1
@@ -275362,7 +277005,7 @@ module \ls180
     assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state
     assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state
     assign $0\builder_state[1:0] \builder_next_state
-    assign $0\builder_slave_sel_r[4:0] \builder_slave_sel
+    assign $0\builder_slave_sel_r[7:0] \builder_slave_sel
     assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
     assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re
     assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re
@@ -275457,154 +277100,175 @@ module \ls180
     assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0
     assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15]
     assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0
-    attribute \src "ls180.v:7452.2-7454.5"
-    switch $or$ls180.v:7452$2399_Y
-      attribute \src "ls180.v:7452.6-7452.94"
+    attribute \src "ls180.v:7554.2-7556.5"
+    switch $or$ls180.v:7554$2468_Y
+      attribute \src "ls180.v:7554.6-7554.94"
       case 1'1
         assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r
       case 
     end
-    attribute \src "ls180.v:7456.2-7458.5"
+    attribute \src "ls180.v:7558.2-7560.5"
     switch \main_libresocsim_converter0_counter_converter0_next_value_ce
-      attribute \src "ls180.v:7456.6-7456.66"
+      attribute \src "ls180.v:7558.6-7558.66"
       case 1'1
         assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value
       case 
     end
-    attribute \src "ls180.v:7459.2-7462.5"
+    attribute \src "ls180.v:7561.2-7564.5"
     switch \main_libresocsim_converter0_reset
-      attribute \src "ls180.v:7459.6-7459.39"
+      attribute \src "ls180.v:7561.6-7561.39"
       case 1'1
         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
         assign $0\builder_converter0_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7463.2-7465.5"
-    switch $or$ls180.v:7463$2400_Y
-      attribute \src "ls180.v:7463.6-7463.94"
+    attribute \src "ls180.v:7565.2-7567.5"
+    switch $or$ls180.v:7565$2469_Y
+      attribute \src "ls180.v:7565.6-7565.94"
       case 1'1
         assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r
       case 
     end
-    attribute \src "ls180.v:7467.2-7469.5"
+    attribute \src "ls180.v:7569.2-7571.5"
     switch \main_libresocsim_converter1_counter_converter1_next_value_ce
-      attribute \src "ls180.v:7467.6-7467.66"
+      attribute \src "ls180.v:7569.6-7569.66"
       case 1'1
         assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value
       case 
     end
-    attribute \src "ls180.v:7470.2-7473.5"
+    attribute \src "ls180.v:7572.2-7575.5"
     switch \main_libresocsim_converter1_reset
-      attribute \src "ls180.v:7470.6-7470.39"
+      attribute \src "ls180.v:7572.6-7572.39"
       case 1'1
         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
         assign $0\builder_converter1_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7474.2-7476.5"
-    switch $or$ls180.v:7474$2401_Y
-      attribute \src "ls180.v:7474.6-7474.94"
+    attribute \src "ls180.v:7576.2-7578.5"
+    switch $or$ls180.v:7576$2470_Y
+      attribute \src "ls180.v:7576.6-7576.94"
       case 1'1
         assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r
       case 
     end
-    attribute \src "ls180.v:7478.2-7480.5"
+    attribute \src "ls180.v:7580.2-7582.5"
     switch \main_libresocsim_converter2_counter_converter2_next_value_ce
-      attribute \src "ls180.v:7478.6-7478.66"
+      attribute \src "ls180.v:7580.6-7580.66"
       case 1'1
         assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value
       case 
     end
-    attribute \src "ls180.v:7481.2-7484.5"
+    attribute \src "ls180.v:7583.2-7586.5"
     switch \main_libresocsim_converter2_reset
-      attribute \src "ls180.v:7481.6-7481.39"
+      attribute \src "ls180.v:7583.6-7583.39"
       case 1'1
         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
         assign $0\builder_converter2_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7485.2-7489.5"
-    switch $ne$ls180.v:7485$2402_Y
-      attribute \src "ls180.v:7485.6-7485.53"
+    attribute \src "ls180.v:7587.2-7591.5"
+    switch $ne$ls180.v:7587$2471_Y
+      attribute \src "ls180.v:7587.6-7587.53"
       case 1'1
-        attribute \src "ls180.v:7486.3-7488.6"
+        attribute \src "ls180.v:7588.3-7590.6"
         switch \main_libresocsim_bus_error
-          attribute \src "ls180.v:7486.7-7486.33"
+          attribute \src "ls180.v:7588.7-7588.33"
           case 1'1
-            assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7487$2403_Y
+            assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7589$2472_Y
           case 
         end
       case 
     end
-    attribute \src "ls180.v:7491.2-7493.5"
-    switch $and$ls180.v:7491$2406_Y
-      attribute \src "ls180.v:7491.6-7491.103"
+    attribute \src "ls180.v:7593.2-7595.5"
+    switch $and$ls180.v:7593$2475_Y
+      attribute \src "ls180.v:7593.6-7593.103"
       case 1'1
         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7494.2-7502.5"
+    attribute \src "ls180.v:7596.2-7604.5"
     switch \main_libresocsim_en_storage
-      attribute \src "ls180.v:7494.6-7494.33"
+      attribute \src "ls180.v:7596.6-7596.33"
       case 1'1
-        attribute \src "ls180.v:7495.3-7499.6"
-        switch $eq$ls180.v:7495$2407_Y
-          attribute \src "ls180.v:7495.7-7495.39"
+        attribute \src "ls180.v:7597.3-7601.6"
+        switch $eq$ls180.v:7597$2476_Y
+          attribute \src "ls180.v:7597.7-7597.39"
           case 1'1
             assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage
-          attribute \src "ls180.v:7497.7-7497.11"
+          attribute \src "ls180.v:7599.7-7599.11"
           case 
-            assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7498$2408_Y
+            assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7600$2477_Y
         end
-      attribute \src "ls180.v:7500.6-7500.10"
+      attribute \src "ls180.v:7602.6-7602.10"
       case 
         assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage
     end
-    attribute \src "ls180.v:7503.2-7505.5"
+    attribute \src "ls180.v:7605.2-7607.5"
     switch \main_libresocsim_update_value_re
-      attribute \src "ls180.v:7503.6-7503.38"
+      attribute \src "ls180.v:7605.6-7605.38"
       case 1'1
         assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value
       case 
     end
-    attribute \src "ls180.v:7506.2-7508.5"
+    attribute \src "ls180.v:7608.2-7610.5"
     switch \main_libresocsim_zero_clear
-      attribute \src "ls180.v:7506.6-7506.33"
+      attribute \src "ls180.v:7608.6-7608.33"
       case 1'1
         assign $0\main_libresocsim_zero_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7510.2-7512.5"
-    switch $and$ls180.v:7510$2410_Y
-      attribute \src "ls180.v:7510.6-7510.76"
+    attribute \src "ls180.v:7612.2-7614.5"
+    switch $and$ls180.v:7612$2479_Y
+      attribute \src "ls180.v:7612.6-7612.76"
       case 1'1
         assign $0\main_libresocsim_zero_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7515.2-7517.5"
+    attribute \src "ls180.v:7616.2-7618.5"
+    switch $and$ls180.v:7616$2482_Y
+      attribute \src "ls180.v:7616.6-7616.100"
+      case 1'1
+        assign $0\main_interface0_ram_bus_ack[0:0] 1'1
+      case 
+    end
+    attribute \src "ls180.v:7620.2-7622.5"
+    switch $and$ls180.v:7620$2485_Y
+      attribute \src "ls180.v:7620.6-7620.100"
+      case 1'1
+        assign $0\main_interface1_ram_bus_ack[0:0] 1'1
+      case 
+    end
+    attribute \src "ls180.v:7624.2-7626.5"
+    switch $and$ls180.v:7624$2488_Y
+      attribute \src "ls180.v:7624.6-7624.100"
+      case 1'1
+        assign $0\main_interface2_ram_bus_ack[0:0] 1'1
+      case 
+    end
+    attribute \src "ls180.v:7629.2-7631.5"
     switch \main_sdram_inti_p0_rddata_valid
-      attribute \src "ls180.v:7515.6-7515.37"
+      attribute \src "ls180.v:7629.6-7629.37"
       case 1'1
         assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata
       case 
     end
-    attribute \src "ls180.v:7518.2-7522.5"
-    switch $and$ls180.v:7518$2412_Y
-      attribute \src "ls180.v:7518.6-7518.57"
+    attribute \src "ls180.v:7632.2-7636.5"
+    switch $and$ls180.v:7632$2490_Y
+      attribute \src "ls180.v:7632.6-7632.57"
       case 1'1
-        assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7519$2413_Y
-      attribute \src "ls180.v:7520.6-7520.10"
+        assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7633$2491_Y
+      attribute \src "ls180.v:7634.6-7634.10"
       case 
         assign $0\main_sdram_timer_count1[9:0] 10'1100001101
     end
-    attribute \src "ls180.v:7524.2-7530.5"
+    attribute \src "ls180.v:7638.2-7644.5"
     switch \main_sdram_postponer_req_i
-      attribute \src "ls180.v:7524.6-7524.32"
+      attribute \src "ls180.v:7638.6-7638.32"
       case 1'1
-        assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7525$2414_Y
-        attribute \src "ls180.v:7526.3-7529.6"
-        switch $eq$ls180.v:7526$2415_Y
-          attribute \src "ls180.v:7526.7-7526.43"
+        assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7639$2492_Y
+        attribute \src "ls180.v:7640.3-7643.6"
+        switch $eq$ls180.v:7640$2493_Y
+          attribute \src "ls180.v:7640.7-7640.43"
           case 1'1
             assign $0\main_sdram_postponer_count[0:0] 1'0
             assign $0\main_sdram_postponer_req_o[0:0] 1'1
@@ -275612,30 +277276,30 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7531.2-7539.5"
+    attribute \src "ls180.v:7645.2-7653.5"
     switch \main_sdram_sequencer_start0
-      attribute \src "ls180.v:7531.6-7531.33"
+      attribute \src "ls180.v:7645.6-7645.33"
       case 1'1
         assign $0\main_sdram_sequencer_count[0:0] 1'0
-      attribute \src "ls180.v:7533.6-7533.10"
+      attribute \src "ls180.v:7647.6-7647.10"
       case 
-        attribute \src "ls180.v:7534.3-7538.6"
+        attribute \src "ls180.v:7648.3-7652.6"
         switch \main_sdram_sequencer_done1
-          attribute \src "ls180.v:7534.7-7534.33"
+          attribute \src "ls180.v:7648.7-7648.33"
           case 1'1
-            attribute \src "ls180.v:7535.4-7537.7"
-            switch $ne$ls180.v:7535$2416_Y
-              attribute \src "ls180.v:7535.8-7535.44"
+            attribute \src "ls180.v:7649.4-7651.7"
+            switch $ne$ls180.v:7649$2494_Y
+              attribute \src "ls180.v:7649.8-7649.44"
               case 1'1
-                assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7536$2417_Y
+                assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7650$2495_Y
               case 
             end
           case 
         end
     end
-    attribute \src "ls180.v:7546.2-7552.5"
-    switch $and$ls180.v:7546$2419_Y
-      attribute \src "ls180.v:7546.6-7546.76"
+    attribute \src "ls180.v:7660.2-7666.5"
+    switch $and$ls180.v:7660$2497_Y
+      attribute \src "ls180.v:7660.6-7660.76"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -275644,9 +277308,9 @@ module \ls180
         assign $0\main_sdram_cmd_payload_we[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7553.2-7559.5"
-    switch $eq$ls180.v:7553$2420_Y
-      attribute \src "ls180.v:7553.6-7553.44"
+    attribute \src "ls180.v:7667.2-7673.5"
+    switch $eq$ls180.v:7667$2498_Y
+      attribute \src "ls180.v:7667.6-7667.44"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -275655,9 +277319,9 @@ module \ls180
         assign $0\main_sdram_cmd_payload_we[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7560.2-7567.5"
-    switch $eq$ls180.v:7560$2421_Y
-      attribute \src "ls180.v:7560.6-7560.44"
+    attribute \src "ls180.v:7674.2-7681.5"
+    switch $eq$ls180.v:7674$2499_Y
+      attribute \src "ls180.v:7674.6-7674.44"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -275667,83 +277331,83 @@ module \ls180
         assign $0\main_sdram_sequencer_done1[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7568.2-7578.5"
-    switch $eq$ls180.v:7568$2422_Y
-      attribute \src "ls180.v:7568.6-7568.44"
+    attribute \src "ls180.v:7682.2-7692.5"
+    switch $eq$ls180.v:7682$2500_Y
+      attribute \src "ls180.v:7682.6-7682.44"
       case 1'1
         assign $0\main_sdram_sequencer_counter[3:0] 4'0000
-      attribute \src "ls180.v:7570.6-7570.10"
+      attribute \src "ls180.v:7684.6-7684.10"
       case 
-        attribute \src "ls180.v:7571.3-7577.6"
-        switch $ne$ls180.v:7571$2423_Y
-          attribute \src "ls180.v:7571.7-7571.45"
+        attribute \src "ls180.v:7685.3-7691.6"
+        switch $ne$ls180.v:7685$2501_Y
+          attribute \src "ls180.v:7685.7-7685.45"
           case 1'1
-            assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7572$2424_Y
-          attribute \src "ls180.v:7573.7-7573.11"
+            assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7686$2502_Y
+          attribute \src "ls180.v:7687.7-7687.11"
           case 
-            attribute \src "ls180.v:7574.4-7576.7"
+            attribute \src "ls180.v:7688.4-7690.7"
             switch \main_sdram_sequencer_start1
-              attribute \src "ls180.v:7574.8-7574.35"
+              attribute \src "ls180.v:7688.8-7688.35"
               case 1'1
                 assign $0\main_sdram_sequencer_counter[3:0] 4'0001
               case 
             end
         end
     end
-    attribute \src "ls180.v:7580.2-7587.5"
+    attribute \src "ls180.v:7694.2-7701.5"
     switch \main_sdram_bankmachine0_row_close
-      attribute \src "ls180.v:7580.6-7580.39"
+      attribute \src "ls180.v:7694.6-7694.39"
       case 1'1
         assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7582.6-7582.10"
+      attribute \src "ls180.v:7696.6-7696.10"
       case 
-        attribute \src "ls180.v:7583.3-7586.6"
+        attribute \src "ls180.v:7697.3-7700.6"
         switch \main_sdram_bankmachine0_row_open
-          attribute \src "ls180.v:7583.7-7583.39"
+          attribute \src "ls180.v:7697.7-7697.39"
           case 1'1
             assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7588.2-7590.5"
-    switch $and$ls180.v:7588$2427_Y
-      attribute \src "ls180.v:7588.6-7588.191"
+    attribute \src "ls180.v:7702.2-7704.5"
+    switch $and$ls180.v:7702$2505_Y
+      attribute \src "ls180.v:7702.6-7702.191"
       case 1'1
-        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7589$2428_Y
+        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7703$2506_Y
       case 
     end
-    attribute \src "ls180.v:7591.2-7593.5"
+    attribute \src "ls180.v:7705.2-7707.5"
     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7591.6-7591.58"
+      attribute \src "ls180.v:7705.6-7705.58"
       case 1'1
-        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7592$2429_Y
+        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7706$2507_Y
       case 
     end
-    attribute \src "ls180.v:7594.2-7602.5"
-    switch $and$ls180.v:7594$2432_Y
-      attribute \src "ls180.v:7594.6-7594.191"
+    attribute \src "ls180.v:7708.2-7716.5"
+    switch $and$ls180.v:7708$2510_Y
+      attribute \src "ls180.v:7708.6-7708.191"
       case 1'1
-        attribute \src "ls180.v:7595.3-7597.6"
-        switch $not$ls180.v:7595$2433_Y
-          attribute \src "ls180.v:7595.7-7595.62"
+        attribute \src "ls180.v:7709.3-7711.6"
+        switch $not$ls180.v:7709$2511_Y
+          attribute \src "ls180.v:7709.7-7709.62"
           case 1'1
-            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7596$2434_Y
+            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7710$2512_Y
           case 
         end
-      attribute \src "ls180.v:7598.6-7598.10"
+      attribute \src "ls180.v:7712.6-7712.10"
       case 
-        attribute \src "ls180.v:7599.3-7601.6"
+        attribute \src "ls180.v:7713.3-7715.6"
         switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7599.7-7599.59"
+          attribute \src "ls180.v:7713.7-7713.59"
           case 1'1
-            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7600$2435_Y
+            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7714$2513_Y
           case 
         end
     end
-    attribute \src "ls180.v:7603.2-7609.5"
-    switch $or$ls180.v:7603$2437_Y
-      attribute \src "ls180.v:7603.6-7603.108"
+    attribute \src "ls180.v:7717.2-7723.5"
+    switch $or$ls180.v:7717$2515_Y
+      attribute \src "ls180.v:7717.6-7717.108"
       case 1'1
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first
@@ -275752,27 +277416,27 @@ module \ls180
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7610.2-7624.5"
+    attribute \src "ls180.v:7724.2-7738.5"
     switch \main_sdram_bankmachine0_twtpcon_valid
-      attribute \src "ls180.v:7610.6-7610.43"
+      attribute \src "ls180.v:7724.6-7724.43"
       case 1'1
         assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7612.3-7616.6"
+        attribute \src "ls180.v:7726.3-7730.6"
         switch 1'0
-          attribute \src "ls180.v:7614.7-7614.11"
+          attribute \src "ls180.v:7728.7-7728.11"
           case 
             assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7617.6-7617.10"
+      attribute \src "ls180.v:7731.6-7731.10"
       case 
-        attribute \src "ls180.v:7618.3-7623.6"
-        switch $not$ls180.v:7618$2438_Y
-          attribute \src "ls180.v:7618.7-7618.47"
+        attribute \src "ls180.v:7732.3-7737.6"
+        switch $not$ls180.v:7732$2516_Y
+          attribute \src "ls180.v:7732.7-7732.47"
           case 1'1
-            assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7619$2439_Y
-            attribute \src "ls180.v:7620.4-7622.7"
-            switch $eq$ls180.v:7620$2440_Y
-              attribute \src "ls180.v:7620.8-7620.55"
+            assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7733$2517_Y
+            attribute \src "ls180.v:7734.4-7736.7"
+            switch $eq$ls180.v:7734$2518_Y
+              attribute \src "ls180.v:7734.8-7734.55"
               case 1'1
                 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1
               case 
@@ -275780,60 +277444,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7626.2-7633.5"
+    attribute \src "ls180.v:7740.2-7747.5"
     switch \main_sdram_bankmachine1_row_close
-      attribute \src "ls180.v:7626.6-7626.39"
+      attribute \src "ls180.v:7740.6-7740.39"
       case 1'1
         assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7628.6-7628.10"
+      attribute \src "ls180.v:7742.6-7742.10"
       case 
-        attribute \src "ls180.v:7629.3-7632.6"
+        attribute \src "ls180.v:7743.3-7746.6"
         switch \main_sdram_bankmachine1_row_open
-          attribute \src "ls180.v:7629.7-7629.39"
+          attribute \src "ls180.v:7743.7-7743.39"
           case 1'1
             assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7634.2-7636.5"
-    switch $and$ls180.v:7634$2443_Y
-      attribute \src "ls180.v:7634.6-7634.191"
+    attribute \src "ls180.v:7748.2-7750.5"
+    switch $and$ls180.v:7748$2521_Y
+      attribute \src "ls180.v:7748.6-7748.191"
       case 1'1
-        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7635$2444_Y
+        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7749$2522_Y
       case 
     end
-    attribute \src "ls180.v:7637.2-7639.5"
+    attribute \src "ls180.v:7751.2-7753.5"
     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7637.6-7637.58"
+      attribute \src "ls180.v:7751.6-7751.58"
       case 1'1
-        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7638$2445_Y
+        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7752$2523_Y
       case 
     end
-    attribute \src "ls180.v:7640.2-7648.5"
-    switch $and$ls180.v:7640$2448_Y
-      attribute \src "ls180.v:7640.6-7640.191"
+    attribute \src "ls180.v:7754.2-7762.5"
+    switch $and$ls180.v:7754$2526_Y
+      attribute \src "ls180.v:7754.6-7754.191"
       case 1'1
-        attribute \src "ls180.v:7641.3-7643.6"
-        switch $not$ls180.v:7641$2449_Y
-          attribute \src "ls180.v:7641.7-7641.62"
+        attribute \src "ls180.v:7755.3-7757.6"
+        switch $not$ls180.v:7755$2527_Y
+          attribute \src "ls180.v:7755.7-7755.62"
           case 1'1
-            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7642$2450_Y
+            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7756$2528_Y
           case 
         end
-      attribute \src "ls180.v:7644.6-7644.10"
+      attribute \src "ls180.v:7758.6-7758.10"
       case 
-        attribute \src "ls180.v:7645.3-7647.6"
+        attribute \src "ls180.v:7759.3-7761.6"
         switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7645.7-7645.59"
+          attribute \src "ls180.v:7759.7-7759.59"
           case 1'1
-            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7646$2451_Y
+            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7760$2529_Y
           case 
         end
     end
-    attribute \src "ls180.v:7649.2-7655.5"
-    switch $or$ls180.v:7649$2453_Y
-      attribute \src "ls180.v:7649.6-7649.108"
+    attribute \src "ls180.v:7763.2-7769.5"
+    switch $or$ls180.v:7763$2531_Y
+      attribute \src "ls180.v:7763.6-7763.108"
       case 1'1
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first
@@ -275842,27 +277506,27 @@ module \ls180
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7656.2-7670.5"
+    attribute \src "ls180.v:7770.2-7784.5"
     switch \main_sdram_bankmachine1_twtpcon_valid
-      attribute \src "ls180.v:7656.6-7656.43"
+      attribute \src "ls180.v:7770.6-7770.43"
       case 1'1
         assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7658.3-7662.6"
+        attribute \src "ls180.v:7772.3-7776.6"
         switch 1'0
-          attribute \src "ls180.v:7660.7-7660.11"
+          attribute \src "ls180.v:7774.7-7774.11"
           case 
             assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7663.6-7663.10"
+      attribute \src "ls180.v:7777.6-7777.10"
       case 
-        attribute \src "ls180.v:7664.3-7669.6"
-        switch $not$ls180.v:7664$2454_Y
-          attribute \src "ls180.v:7664.7-7664.47"
+        attribute \src "ls180.v:7778.3-7783.6"
+        switch $not$ls180.v:7778$2532_Y
+          attribute \src "ls180.v:7778.7-7778.47"
           case 1'1
-            assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7665$2455_Y
-            attribute \src "ls180.v:7666.4-7668.7"
-            switch $eq$ls180.v:7666$2456_Y
-              attribute \src "ls180.v:7666.8-7666.55"
+            assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7779$2533_Y
+            attribute \src "ls180.v:7780.4-7782.7"
+            switch $eq$ls180.v:7780$2534_Y
+              attribute \src "ls180.v:7780.8-7780.55"
               case 1'1
                 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1
               case 
@@ -275870,60 +277534,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7672.2-7679.5"
+    attribute \src "ls180.v:7786.2-7793.5"
     switch \main_sdram_bankmachine2_row_close
-      attribute \src "ls180.v:7672.6-7672.39"
+      attribute \src "ls180.v:7786.6-7786.39"
       case 1'1
         assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7674.6-7674.10"
+      attribute \src "ls180.v:7788.6-7788.10"
       case 
-        attribute \src "ls180.v:7675.3-7678.6"
+        attribute \src "ls180.v:7789.3-7792.6"
         switch \main_sdram_bankmachine2_row_open
-          attribute \src "ls180.v:7675.7-7675.39"
+          attribute \src "ls180.v:7789.7-7789.39"
           case 1'1
             assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7680.2-7682.5"
-    switch $and$ls180.v:7680$2459_Y
-      attribute \src "ls180.v:7680.6-7680.191"
+    attribute \src "ls180.v:7794.2-7796.5"
+    switch $and$ls180.v:7794$2537_Y
+      attribute \src "ls180.v:7794.6-7794.191"
       case 1'1
-        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7681$2460_Y
+        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7795$2538_Y
       case 
     end
-    attribute \src "ls180.v:7683.2-7685.5"
+    attribute \src "ls180.v:7797.2-7799.5"
     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7683.6-7683.58"
+      attribute \src "ls180.v:7797.6-7797.58"
       case 1'1
-        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7684$2461_Y
+        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7798$2539_Y
       case 
     end
-    attribute \src "ls180.v:7686.2-7694.5"
-    switch $and$ls180.v:7686$2464_Y
-      attribute \src "ls180.v:7686.6-7686.191"
+    attribute \src "ls180.v:7800.2-7808.5"
+    switch $and$ls180.v:7800$2542_Y
+      attribute \src "ls180.v:7800.6-7800.191"
       case 1'1
-        attribute \src "ls180.v:7687.3-7689.6"
-        switch $not$ls180.v:7687$2465_Y
-          attribute \src "ls180.v:7687.7-7687.62"
+        attribute \src "ls180.v:7801.3-7803.6"
+        switch $not$ls180.v:7801$2543_Y
+          attribute \src "ls180.v:7801.7-7801.62"
           case 1'1
-            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7688$2466_Y
+            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7802$2544_Y
           case 
         end
-      attribute \src "ls180.v:7690.6-7690.10"
+      attribute \src "ls180.v:7804.6-7804.10"
       case 
-        attribute \src "ls180.v:7691.3-7693.6"
+        attribute \src "ls180.v:7805.3-7807.6"
         switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7691.7-7691.59"
+          attribute \src "ls180.v:7805.7-7805.59"
           case 1'1
-            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7692$2467_Y
+            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7806$2545_Y
           case 
         end
     end
-    attribute \src "ls180.v:7695.2-7701.5"
-    switch $or$ls180.v:7695$2469_Y
-      attribute \src "ls180.v:7695.6-7695.108"
+    attribute \src "ls180.v:7809.2-7815.5"
+    switch $or$ls180.v:7809$2547_Y
+      attribute \src "ls180.v:7809.6-7809.108"
       case 1'1
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first
@@ -275932,27 +277596,27 @@ module \ls180
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7702.2-7716.5"
+    attribute \src "ls180.v:7816.2-7830.5"
     switch \main_sdram_bankmachine2_twtpcon_valid
-      attribute \src "ls180.v:7702.6-7702.43"
+      attribute \src "ls180.v:7816.6-7816.43"
       case 1'1
         assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7704.3-7708.6"
+        attribute \src "ls180.v:7818.3-7822.6"
         switch 1'0
-          attribute \src "ls180.v:7706.7-7706.11"
+          attribute \src "ls180.v:7820.7-7820.11"
           case 
             assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7709.6-7709.10"
+      attribute \src "ls180.v:7823.6-7823.10"
       case 
-        attribute \src "ls180.v:7710.3-7715.6"
-        switch $not$ls180.v:7710$2470_Y
-          attribute \src "ls180.v:7710.7-7710.47"
+        attribute \src "ls180.v:7824.3-7829.6"
+        switch $not$ls180.v:7824$2548_Y
+          attribute \src "ls180.v:7824.7-7824.47"
           case 1'1
-            assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7711$2471_Y
-            attribute \src "ls180.v:7712.4-7714.7"
-            switch $eq$ls180.v:7712$2472_Y
-              attribute \src "ls180.v:7712.8-7712.55"
+            assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7825$2549_Y
+            attribute \src "ls180.v:7826.4-7828.7"
+            switch $eq$ls180.v:7826$2550_Y
+              attribute \src "ls180.v:7826.8-7826.55"
               case 1'1
                 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1
               case 
@@ -275960,60 +277624,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7718.2-7725.5"
+    attribute \src "ls180.v:7832.2-7839.5"
     switch \main_sdram_bankmachine3_row_close
-      attribute \src "ls180.v:7718.6-7718.39"
+      attribute \src "ls180.v:7832.6-7832.39"
       case 1'1
         assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7720.6-7720.10"
+      attribute \src "ls180.v:7834.6-7834.10"
       case 
-        attribute \src "ls180.v:7721.3-7724.6"
+        attribute \src "ls180.v:7835.3-7838.6"
         switch \main_sdram_bankmachine3_row_open
-          attribute \src "ls180.v:7721.7-7721.39"
+          attribute \src "ls180.v:7835.7-7835.39"
           case 1'1
             assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7726.2-7728.5"
-    switch $and$ls180.v:7726$2475_Y
-      attribute \src "ls180.v:7726.6-7726.191"
+    attribute \src "ls180.v:7840.2-7842.5"
+    switch $and$ls180.v:7840$2553_Y
+      attribute \src "ls180.v:7840.6-7840.191"
       case 1'1
-        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7727$2476_Y
+        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7841$2554_Y
       case 
     end
-    attribute \src "ls180.v:7729.2-7731.5"
+    attribute \src "ls180.v:7843.2-7845.5"
     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7729.6-7729.58"
+      attribute \src "ls180.v:7843.6-7843.58"
       case 1'1
-        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7730$2477_Y
+        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7844$2555_Y
       case 
     end
-    attribute \src "ls180.v:7732.2-7740.5"
-    switch $and$ls180.v:7732$2480_Y
-      attribute \src "ls180.v:7732.6-7732.191"
+    attribute \src "ls180.v:7846.2-7854.5"
+    switch $and$ls180.v:7846$2558_Y
+      attribute \src "ls180.v:7846.6-7846.191"
       case 1'1
-        attribute \src "ls180.v:7733.3-7735.6"
-        switch $not$ls180.v:7733$2481_Y
-          attribute \src "ls180.v:7733.7-7733.62"
+        attribute \src "ls180.v:7847.3-7849.6"
+        switch $not$ls180.v:7847$2559_Y
+          attribute \src "ls180.v:7847.7-7847.62"
           case 1'1
-            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7734$2482_Y
+            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7848$2560_Y
           case 
         end
-      attribute \src "ls180.v:7736.6-7736.10"
+      attribute \src "ls180.v:7850.6-7850.10"
       case 
-        attribute \src "ls180.v:7737.3-7739.6"
+        attribute \src "ls180.v:7851.3-7853.6"
         switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7737.7-7737.59"
+          attribute \src "ls180.v:7851.7-7851.59"
           case 1'1
-            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7738$2483_Y
+            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7852$2561_Y
           case 
         end
     end
-    attribute \src "ls180.v:7741.2-7747.5"
-    switch $or$ls180.v:7741$2485_Y
-      attribute \src "ls180.v:7741.6-7741.108"
+    attribute \src "ls180.v:7855.2-7861.5"
+    switch $or$ls180.v:7855$2563_Y
+      attribute \src "ls180.v:7855.6-7855.108"
       case 1'1
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first
@@ -276022,27 +277686,27 @@ module \ls180
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7748.2-7762.5"
+    attribute \src "ls180.v:7862.2-7876.5"
     switch \main_sdram_bankmachine3_twtpcon_valid
-      attribute \src "ls180.v:7748.6-7748.43"
+      attribute \src "ls180.v:7862.6-7862.43"
       case 1'1
         assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7750.3-7754.6"
+        attribute \src "ls180.v:7864.3-7868.6"
         switch 1'0
-          attribute \src "ls180.v:7752.7-7752.11"
+          attribute \src "ls180.v:7866.7-7866.11"
           case 
             assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7755.6-7755.10"
+      attribute \src "ls180.v:7869.6-7869.10"
       case 
-        attribute \src "ls180.v:7756.3-7761.6"
-        switch $not$ls180.v:7756$2486_Y
-          attribute \src "ls180.v:7756.7-7756.47"
+        attribute \src "ls180.v:7870.3-7875.6"
+        switch $not$ls180.v:7870$2564_Y
+          attribute \src "ls180.v:7870.7-7870.47"
           case 1'1
-            assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7757$2487_Y
-            attribute \src "ls180.v:7758.4-7760.7"
-            switch $eq$ls180.v:7758$2488_Y
-              attribute \src "ls180.v:7758.8-7758.55"
+            assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7871$2565_Y
+            attribute \src "ls180.v:7872.4-7874.7"
+            switch $eq$ls180.v:7872$2566_Y
+              attribute \src "ls180.v:7872.8-7872.55"
               case 1'1
                 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1
               case 
@@ -276050,61 +277714,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7764.2-7770.5"
-    switch $not$ls180.v:7764$2489_Y
-      attribute \src "ls180.v:7764.6-7764.23"
+    attribute \src "ls180.v:7878.2-7884.5"
+    switch $not$ls180.v:7878$2567_Y
+      attribute \src "ls180.v:7878.6-7878.23"
       case 1'1
         assign $0\main_sdram_time0[4:0] 5'11111
-      attribute \src "ls180.v:7766.6-7766.10"
+      attribute \src "ls180.v:7880.6-7880.10"
       case 
-        attribute \src "ls180.v:7767.3-7769.6"
-        switch $not$ls180.v:7767$2490_Y
-          attribute \src "ls180.v:7767.7-7767.30"
+        attribute \src "ls180.v:7881.3-7883.6"
+        switch $not$ls180.v:7881$2568_Y
+          attribute \src "ls180.v:7881.7-7881.30"
           case 1'1
-            assign $0\main_sdram_time0[4:0] $sub$ls180.v:7768$2491_Y
+            assign $0\main_sdram_time0[4:0] $sub$ls180.v:7882$2569_Y
           case 
         end
     end
-    attribute \src "ls180.v:7771.2-7777.5"
-    switch $not$ls180.v:7771$2492_Y
-      attribute \src "ls180.v:7771.6-7771.23"
+    attribute \src "ls180.v:7885.2-7891.5"
+    switch $not$ls180.v:7885$2570_Y
+      attribute \src "ls180.v:7885.6-7885.23"
       case 1'1
         assign $0\main_sdram_time1[3:0] 4'1111
-      attribute \src "ls180.v:7773.6-7773.10"
+      attribute \src "ls180.v:7887.6-7887.10"
       case 
-        attribute \src "ls180.v:7774.3-7776.6"
-        switch $not$ls180.v:7774$2493_Y
-          attribute \src "ls180.v:7774.7-7774.30"
+        attribute \src "ls180.v:7888.3-7890.6"
+        switch $not$ls180.v:7888$2571_Y
+          attribute \src "ls180.v:7888.7-7888.30"
           case 1'1
-            assign $0\main_sdram_time1[3:0] $sub$ls180.v:7775$2494_Y
+            assign $0\main_sdram_time1[3:0] $sub$ls180.v:7889$2572_Y
           case 
         end
     end
-    attribute \src "ls180.v:7778.2-7833.5"
+    attribute \src "ls180.v:7892.2-7947.5"
     switch \main_sdram_choose_cmd_ce
-      attribute \src "ls180.v:7778.6-7778.30"
+      attribute \src "ls180.v:7892.6-7892.30"
       case 1'1
-        attribute \src "ls180.v:7779.3-7832.10"
+        attribute \src "ls180.v:7893.3-7946.10"
         switch \main_sdram_choose_cmd_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:7781.5-7791.8"
+            attribute \src "ls180.v:7895.5-7905.8"
             switch \main_sdram_choose_cmd_request [1]
-              attribute \src "ls180.v:7781.9-7781.41"
+              attribute \src "ls180.v:7895.9-7895.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
-              attribute \src "ls180.v:7783.9-7783.13"
+              attribute \src "ls180.v:7897.9-7897.13"
               case 
-                attribute \src "ls180.v:7784.6-7790.9"
+                attribute \src "ls180.v:7898.6-7904.9"
                 switch \main_sdram_choose_cmd_request [2]
-                  attribute \src "ls180.v:7784.10-7784.42"
+                  attribute \src "ls180.v:7898.10-7898.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
-                  attribute \src "ls180.v:7786.10-7786.14"
+                  attribute \src "ls180.v:7900.10-7900.14"
                   case 
-                    attribute \src "ls180.v:7787.7-7789.10"
+                    attribute \src "ls180.v:7901.7-7903.10"
                     switch \main_sdram_choose_cmd_request [3]
-                      attribute \src "ls180.v:7787.11-7787.43"
+                      attribute \src "ls180.v:7901.11-7901.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
                       case 
@@ -276113,23 +277777,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:7794.5-7804.8"
+            attribute \src "ls180.v:7908.5-7918.8"
             switch \main_sdram_choose_cmd_request [2]
-              attribute \src "ls180.v:7794.9-7794.41"
+              attribute \src "ls180.v:7908.9-7908.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
-              attribute \src "ls180.v:7796.9-7796.13"
+              attribute \src "ls180.v:7910.9-7910.13"
               case 
-                attribute \src "ls180.v:7797.6-7803.9"
+                attribute \src "ls180.v:7911.6-7917.9"
                 switch \main_sdram_choose_cmd_request [3]
-                  attribute \src "ls180.v:7797.10-7797.42"
+                  attribute \src "ls180.v:7911.10-7911.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
-                  attribute \src "ls180.v:7799.10-7799.14"
+                  attribute \src "ls180.v:7913.10-7913.14"
                   case 
-                    attribute \src "ls180.v:7800.7-7802.10"
+                    attribute \src "ls180.v:7914.7-7916.10"
                     switch \main_sdram_choose_cmd_request [0]
-                      attribute \src "ls180.v:7800.11-7800.43"
+                      attribute \src "ls180.v:7914.11-7914.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
                       case 
@@ -276138,23 +277802,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:7807.5-7817.8"
+            attribute \src "ls180.v:7921.5-7931.8"
             switch \main_sdram_choose_cmd_request [3]
-              attribute \src "ls180.v:7807.9-7807.41"
+              attribute \src "ls180.v:7921.9-7921.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
-              attribute \src "ls180.v:7809.9-7809.13"
+              attribute \src "ls180.v:7923.9-7923.13"
               case 
-                attribute \src "ls180.v:7810.6-7816.9"
+                attribute \src "ls180.v:7924.6-7930.9"
                 switch \main_sdram_choose_cmd_request [0]
-                  attribute \src "ls180.v:7810.10-7810.42"
+                  attribute \src "ls180.v:7924.10-7924.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
-                  attribute \src "ls180.v:7812.10-7812.14"
+                  attribute \src "ls180.v:7926.10-7926.14"
                   case 
-                    attribute \src "ls180.v:7813.7-7815.10"
+                    attribute \src "ls180.v:7927.7-7929.10"
                     switch \main_sdram_choose_cmd_request [1]
-                      attribute \src "ls180.v:7813.11-7813.43"
+                      attribute \src "ls180.v:7927.11-7927.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
                       case 
@@ -276163,23 +277827,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:7820.5-7830.8"
+            attribute \src "ls180.v:7934.5-7944.8"
             switch \main_sdram_choose_cmd_request [0]
-              attribute \src "ls180.v:7820.9-7820.41"
+              attribute \src "ls180.v:7934.9-7934.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
-              attribute \src "ls180.v:7822.9-7822.13"
+              attribute \src "ls180.v:7936.9-7936.13"
               case 
-                attribute \src "ls180.v:7823.6-7829.9"
+                attribute \src "ls180.v:7937.6-7943.9"
                 switch \main_sdram_choose_cmd_request [1]
-                  attribute \src "ls180.v:7823.10-7823.42"
+                  attribute \src "ls180.v:7937.10-7937.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
-                  attribute \src "ls180.v:7825.10-7825.14"
+                  attribute \src "ls180.v:7939.10-7939.14"
                   case 
-                    attribute \src "ls180.v:7826.7-7828.10"
+                    attribute \src "ls180.v:7940.7-7942.10"
                     switch \main_sdram_choose_cmd_request [2]
-                      attribute \src "ls180.v:7826.11-7826.43"
+                      attribute \src "ls180.v:7940.11-7940.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
                       case 
@@ -276190,31 +277854,31 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7834.2-7889.5"
+    attribute \src "ls180.v:7948.2-8003.5"
     switch \main_sdram_choose_req_ce
-      attribute \src "ls180.v:7834.6-7834.30"
+      attribute \src "ls180.v:7948.6-7948.30"
       case 1'1
-        attribute \src "ls180.v:7835.3-7888.10"
+        attribute \src "ls180.v:7949.3-8002.10"
         switch \main_sdram_choose_req_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:7837.5-7847.8"
+            attribute \src "ls180.v:7951.5-7961.8"
             switch \main_sdram_choose_req_request [1]
-              attribute \src "ls180.v:7837.9-7837.41"
+              attribute \src "ls180.v:7951.9-7951.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'01
-              attribute \src "ls180.v:7839.9-7839.13"
+              attribute \src "ls180.v:7953.9-7953.13"
               case 
-                attribute \src "ls180.v:7840.6-7846.9"
+                attribute \src "ls180.v:7954.6-7960.9"
                 switch \main_sdram_choose_req_request [2]
-                  attribute \src "ls180.v:7840.10-7840.42"
+                  attribute \src "ls180.v:7954.10-7954.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'10
-                  attribute \src "ls180.v:7842.10-7842.14"
+                  attribute \src "ls180.v:7956.10-7956.14"
                   case 
-                    attribute \src "ls180.v:7843.7-7845.10"
+                    attribute \src "ls180.v:7957.7-7959.10"
                     switch \main_sdram_choose_req_request [3]
-                      attribute \src "ls180.v:7843.11-7843.43"
+                      attribute \src "ls180.v:7957.11-7957.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'11
                       case 
@@ -276223,23 +277887,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:7850.5-7860.8"
+            attribute \src "ls180.v:7964.5-7974.8"
             switch \main_sdram_choose_req_request [2]
-              attribute \src "ls180.v:7850.9-7850.41"
+              attribute \src "ls180.v:7964.9-7964.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'10
-              attribute \src "ls180.v:7852.9-7852.13"
+              attribute \src "ls180.v:7966.9-7966.13"
               case 
-                attribute \src "ls180.v:7853.6-7859.9"
+                attribute \src "ls180.v:7967.6-7973.9"
                 switch \main_sdram_choose_req_request [3]
-                  attribute \src "ls180.v:7853.10-7853.42"
+                  attribute \src "ls180.v:7967.10-7967.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'11
-                  attribute \src "ls180.v:7855.10-7855.14"
+                  attribute \src "ls180.v:7969.10-7969.14"
                   case 
-                    attribute \src "ls180.v:7856.7-7858.10"
+                    attribute \src "ls180.v:7970.7-7972.10"
                     switch \main_sdram_choose_req_request [0]
-                      attribute \src "ls180.v:7856.11-7856.43"
+                      attribute \src "ls180.v:7970.11-7970.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'00
                       case 
@@ -276248,23 +277912,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:7863.5-7873.8"
+            attribute \src "ls180.v:7977.5-7987.8"
             switch \main_sdram_choose_req_request [3]
-              attribute \src "ls180.v:7863.9-7863.41"
+              attribute \src "ls180.v:7977.9-7977.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'11
-              attribute \src "ls180.v:7865.9-7865.13"
+              attribute \src "ls180.v:7979.9-7979.13"
               case 
-                attribute \src "ls180.v:7866.6-7872.9"
+                attribute \src "ls180.v:7980.6-7986.9"
                 switch \main_sdram_choose_req_request [0]
-                  attribute \src "ls180.v:7866.10-7866.42"
+                  attribute \src "ls180.v:7980.10-7980.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'00
-                  attribute \src "ls180.v:7868.10-7868.14"
+                  attribute \src "ls180.v:7982.10-7982.14"
                   case 
-                    attribute \src "ls180.v:7869.7-7871.10"
+                    attribute \src "ls180.v:7983.7-7985.10"
                     switch \main_sdram_choose_req_request [1]
-                      attribute \src "ls180.v:7869.11-7869.43"
+                      attribute \src "ls180.v:7983.11-7983.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'01
                       case 
@@ -276273,23 +277937,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:7876.5-7886.8"
+            attribute \src "ls180.v:7990.5-8000.8"
             switch \main_sdram_choose_req_request [0]
-              attribute \src "ls180.v:7876.9-7876.41"
+              attribute \src "ls180.v:7990.9-7990.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'00
-              attribute \src "ls180.v:7878.9-7878.13"
+              attribute \src "ls180.v:7992.9-7992.13"
               case 
-                attribute \src "ls180.v:7879.6-7885.9"
+                attribute \src "ls180.v:7993.6-7999.9"
                 switch \main_sdram_choose_req_request [1]
-                  attribute \src "ls180.v:7879.10-7879.42"
+                  attribute \src "ls180.v:7993.10-7993.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'01
-                  attribute \src "ls180.v:7881.10-7881.14"
+                  attribute \src "ls180.v:7995.10-7995.14"
                   case 
-                    attribute \src "ls180.v:7882.7-7884.10"
+                    attribute \src "ls180.v:7996.7-7998.10"
                     switch \main_sdram_choose_req_request [2]
-                      attribute \src "ls180.v:7882.11-7882.43"
+                      attribute \src "ls180.v:7996.11-7996.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'10
                       case 
@@ -276300,28 +277964,28 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7898.2-7912.5"
+    attribute \src "ls180.v:8012.2-8026.5"
     switch \main_sdram_tccdcon_valid
-      attribute \src "ls180.v:7898.6-7898.30"
+      attribute \src "ls180.v:8012.6-8012.30"
       case 1'1
         assign $0\main_sdram_tccdcon_count[0:0] 1'0
-        attribute \src "ls180.v:7900.3-7904.6"
+        attribute \src "ls180.v:8014.3-8018.6"
         switch 1'1
-          attribute \src "ls180.v:7900.7-7900.11"
+          attribute \src "ls180.v:8014.7-8014.11"
           case 1'1
             assign $0\main_sdram_tccdcon_ready[0:0] 1'1
           case 
         end
-      attribute \src "ls180.v:7905.6-7905.10"
+      attribute \src "ls180.v:8019.6-8019.10"
       case 
-        attribute \src "ls180.v:7906.3-7911.6"
-        switch $not$ls180.v:7906$2498_Y
-          attribute \src "ls180.v:7906.7-7906.34"
+        attribute \src "ls180.v:8020.3-8025.6"
+        switch $not$ls180.v:8020$2576_Y
+          attribute \src "ls180.v:8020.7-8020.34"
           case 1'1
-            assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7907$2499_Y
-            attribute \src "ls180.v:7908.4-7910.7"
-            switch $eq$ls180.v:7908$2500_Y
-              attribute \src "ls180.v:7908.8-7908.42"
+            assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8021$2577_Y
+            attribute \src "ls180.v:8022.4-8024.7"
+            switch $eq$ls180.v:8022$2578_Y
+              attribute \src "ls180.v:8022.8-8022.42"
               case 1'1
                 assign $0\main_sdram_tccdcon_ready[0:0] 1'1
               case 
@@ -276329,27 +277993,27 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7913.2-7927.5"
+    attribute \src "ls180.v:8027.2-8041.5"
     switch \main_sdram_twtrcon_valid
-      attribute \src "ls180.v:7913.6-7913.30"
+      attribute \src "ls180.v:8027.6-8027.30"
       case 1'1
         assign $0\main_sdram_twtrcon_count[2:0] 3'100
-        attribute \src "ls180.v:7915.3-7919.6"
+        attribute \src "ls180.v:8029.3-8033.6"
         switch 1'0
-          attribute \src "ls180.v:7917.7-7917.11"
+          attribute \src "ls180.v:8031.7-8031.11"
           case 
             assign $0\main_sdram_twtrcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7920.6-7920.10"
+      attribute \src "ls180.v:8034.6-8034.10"
       case 
-        attribute \src "ls180.v:7921.3-7926.6"
-        switch $not$ls180.v:7921$2501_Y
-          attribute \src "ls180.v:7921.7-7921.34"
+        attribute \src "ls180.v:8035.3-8040.6"
+        switch $not$ls180.v:8035$2579_Y
+          attribute \src "ls180.v:8035.7-8035.34"
           case 1'1
-            assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7922$2502_Y
-            attribute \src "ls180.v:7923.4-7925.7"
-            switch $eq$ls180.v:7923$2503_Y
-              attribute \src "ls180.v:7923.8-7923.42"
+            assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8036$2580_Y
+            attribute \src "ls180.v:8037.4-8039.7"
+            switch $eq$ls180.v:8037$2581_Y
+              attribute \src "ls180.v:8037.8-8037.42"
               case 1'1
                 assign $0\main_sdram_twtrcon_ready[0:0] 1'1
               case 
@@ -276357,81 +278021,81 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7934.2-7936.5"
-    switch $or$ls180.v:7934$2528_Y
-      attribute \src "ls180.v:7934.6-7934.50"
+    attribute \src "ls180.v:8048.2-8050.5"
+    switch $or$ls180.v:8048$2606_Y
+      attribute \src "ls180.v:8048.6-8048.50"
       case 1'1
         assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r
       case 
     end
-    attribute \src "ls180.v:7938.2-7940.5"
+    attribute \src "ls180.v:8052.2-8054.5"
     switch \main_converter_counter_converter_next_value_ce
-      attribute \src "ls180.v:7938.6-7938.52"
+      attribute \src "ls180.v:8052.6-8052.52"
       case 1'1
         assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value
       case 
     end
-    attribute \src "ls180.v:7941.2-7944.5"
+    attribute \src "ls180.v:8055.2-8058.5"
     switch \main_converter_reset
-      attribute \src "ls180.v:7941.6-7941.26"
+      attribute \src "ls180.v:8055.6-8055.26"
       case 1'1
         assign $0\main_converter_counter[0:0] 1'0
         assign $0\builder_converter_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7945.2-7955.5"
+    attribute \src "ls180.v:8059.2-8069.5"
     switch \main_litedram_wb_ack
-      attribute \src "ls180.v:7945.6-7945.26"
+      attribute \src "ls180.v:8059.6-8059.26"
       case 1'1
         assign $0\main_cmd_consumed[0:0] 1'0
         assign $0\main_wdata_consumed[0:0] 1'0
-      attribute \src "ls180.v:7948.6-7948.10"
+      attribute \src "ls180.v:8062.6-8062.10"
       case 
-        attribute \src "ls180.v:7949.3-7951.6"
-        switch $and$ls180.v:7949$2529_Y
-          attribute \src "ls180.v:7949.7-7949.50"
+        attribute \src "ls180.v:8063.3-8065.6"
+        switch $and$ls180.v:8063$2607_Y
+          attribute \src "ls180.v:8063.7-8063.50"
           case 1'1
             assign $0\main_cmd_consumed[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:7952.3-7954.6"
-        switch $and$ls180.v:7952$2530_Y
-          attribute \src "ls180.v:7952.7-7952.54"
+        attribute \src "ls180.v:8066.3-8068.6"
+        switch $and$ls180.v:8066$2608_Y
+          attribute \src "ls180.v:8066.7-8066.54"
           case 1'1
             assign $0\main_wdata_consumed[0:0] 1'1
           case 
         end
     end
-    attribute \src "ls180.v:7957.2-7978.5"
-    switch $and$ls180.v:7957$2534_Y
-      attribute \src "ls180.v:7957.6-7957.91"
+    attribute \src "ls180.v:8071.2-8092.5"
+    switch $and$ls180.v:8071$2612_Y
+      attribute \src "ls180.v:8071.6-8071.91"
       case 1'1
         assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data
         assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000
         assign $0\main_uart_phy_tx_busy[0:0] 1'1
         assign $0\uart_tx[0:0] 1'0
-      attribute \src "ls180.v:7962.6-7962.10"
+      attribute \src "ls180.v:8076.6-8076.10"
       case 
-        attribute \src "ls180.v:7963.3-7977.6"
-        switch $and$ls180.v:7963$2535_Y
-          attribute \src "ls180.v:7963.7-7963.60"
+        attribute \src "ls180.v:8077.3-8091.6"
+        switch $and$ls180.v:8077$2613_Y
+          attribute \src "ls180.v:8077.7-8077.60"
           case 1'1
-            assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7964$2536_Y
-            attribute \src "ls180.v:7965.4-7976.7"
-            switch $eq$ls180.v:7965$2537_Y
-              attribute \src "ls180.v:7965.8-7965.43"
+            assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8078$2614_Y
+            attribute \src "ls180.v:8079.4-8090.7"
+            switch $eq$ls180.v:8079$2615_Y
+              attribute \src "ls180.v:8079.8-8079.43"
               case 1'1
                 assign $0\uart_tx[0:0] 1'1
-              attribute \src "ls180.v:7967.8-7967.12"
+              attribute \src "ls180.v:8081.8-8081.12"
               case 
-                attribute \src "ls180.v:7968.5-7975.8"
-                switch $eq$ls180.v:7968$2538_Y
-                  attribute \src "ls180.v:7968.9-7968.44"
+                attribute \src "ls180.v:8082.5-8089.8"
+                switch $eq$ls180.v:8082$2616_Y
+                  attribute \src "ls180.v:8082.9-8082.44"
                   case 1'1
                     assign $0\uart_tx[0:0] 1'1
                     assign $0\main_uart_phy_tx_busy[0:0] 1'0
                     assign $0\main_uart_phy_sink_ready[0:0] 1'1
-                  attribute \src "ls180.v:7972.9-7972.13"
+                  attribute \src "ls180.v:8086.9-8086.13"
                   case 
                     assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0]
                     assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] }
@@ -276440,61 +278104,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7979.2-7983.5"
+    attribute \src "ls180.v:8093.2-8097.5"
     switch \main_uart_phy_tx_busy
-      attribute \src "ls180.v:7979.6-7979.27"
+      attribute \src "ls180.v:8093.6-8093.27"
       case 1'1
-        assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7980$2539_Y
-      attribute \src "ls180.v:7981.6-7981.10"
+        assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8094$2617_Y
+      attribute \src "ls180.v:8095.6-8095.10"
       case 
         assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage }
     end
-    attribute \src "ls180.v:7986.2-8010.5"
-    switch $not$ls180.v:7986$2540_Y
-      attribute \src "ls180.v:7986.6-7986.30"
+    attribute \src "ls180.v:8100.2-8124.5"
+    switch $not$ls180.v:8100$2618_Y
+      attribute \src "ls180.v:8100.6-8100.30"
       case 1'1
-        attribute \src "ls180.v:7987.3-7990.6"
-        switch $and$ls180.v:7987$2542_Y
-          attribute \src "ls180.v:7987.7-7987.49"
+        attribute \src "ls180.v:8101.3-8104.6"
+        switch $and$ls180.v:8101$2620_Y
+          attribute \src "ls180.v:8101.7-8101.49"
           case 1'1
             assign $0\main_uart_phy_rx_busy[0:0] 1'1
             assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000
           case 
         end
-      attribute \src "ls180.v:7991.6-7991.10"
+      attribute \src "ls180.v:8105.6-8105.10"
       case 
-        attribute \src "ls180.v:7992.3-8009.6"
+        attribute \src "ls180.v:8106.3-8123.6"
         switch \main_uart_phy_uart_clk_rxen
-          attribute \src "ls180.v:7992.7-7992.34"
+          attribute \src "ls180.v:8106.7-8106.34"
           case 1'1
-            assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7993$2543_Y
-            attribute \src "ls180.v:7994.4-8008.7"
-            switch $eq$ls180.v:7994$2544_Y
-              attribute \src "ls180.v:7994.8-7994.43"
+            assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8107$2621_Y
+            attribute \src "ls180.v:8108.4-8122.7"
+            switch $eq$ls180.v:8108$2622_Y
+              attribute \src "ls180.v:8108.8-8108.43"
               case 1'1
-                attribute \src "ls180.v:7995.5-7997.8"
+                attribute \src "ls180.v:8109.5-8111.8"
                 switch \main_uart_phy_rx
-                  attribute \src "ls180.v:7995.9-7995.25"
+                  attribute \src "ls180.v:8109.9-8109.25"
                   case 1'1
                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
                   case 
                 end
-              attribute \src "ls180.v:7998.8-7998.12"
+              attribute \src "ls180.v:8112.8-8112.12"
               case 
-                attribute \src "ls180.v:7999.5-8007.8"
-                switch $eq$ls180.v:7999$2545_Y
-                  attribute \src "ls180.v:7999.9-7999.44"
+                attribute \src "ls180.v:8113.5-8121.8"
+                switch $eq$ls180.v:8113$2623_Y
+                  attribute \src "ls180.v:8113.9-8113.44"
                   case 1'1
                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
-                    attribute \src "ls180.v:8001.6-8004.9"
+                    attribute \src "ls180.v:8115.6-8118.9"
                     switch \main_uart_phy_rx
-                      attribute \src "ls180.v:8001.10-8001.26"
+                      attribute \src "ls180.v:8115.10-8115.26"
                       case 1'1
                         assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg
                         assign $0\main_uart_phy_source_valid[0:0] 1'1
                       case 
                     end
-                  attribute \src "ls180.v:8005.9-8005.13"
+                  attribute \src "ls180.v:8119.9-8119.13"
                   case 
                     assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] }
                 end
@@ -276502,146 +278166,146 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8011.2-8015.5"
+    attribute \src "ls180.v:8125.2-8129.5"
     switch \main_uart_phy_rx_busy
-      attribute \src "ls180.v:8011.6-8011.27"
+      attribute \src "ls180.v:8125.6-8125.27"
       case 1'1
-        assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8012$2546_Y
-      attribute \src "ls180.v:8013.6-8013.10"
+        assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8126$2624_Y
+      attribute \src "ls180.v:8127.6-8127.10"
       case 
         assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
     end
-    attribute \src "ls180.v:8016.2-8018.5"
+    attribute \src "ls180.v:8130.2-8132.5"
     switch \main_uart_tx_clear
-      attribute \src "ls180.v:8016.6-8016.24"
+      attribute \src "ls180.v:8130.6-8130.24"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8020.2-8022.5"
-    switch $and$ls180.v:8020$2548_Y
-      attribute \src "ls180.v:8020.6-8020.58"
+    attribute \src "ls180.v:8134.2-8136.5"
+    switch $and$ls180.v:8134$2626_Y
+      attribute \src "ls180.v:8134.6-8134.58"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:8023.2-8025.5"
+    attribute \src "ls180.v:8137.2-8139.5"
     switch \main_uart_rx_clear
-      attribute \src "ls180.v:8023.6-8023.24"
+      attribute \src "ls180.v:8137.6-8137.24"
       case 1'1
         assign $0\main_uart_rx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8027.2-8029.5"
-    switch $and$ls180.v:8027$2550_Y
-      attribute \src "ls180.v:8027.6-8027.58"
+    attribute \src "ls180.v:8141.2-8143.5"
+    switch $and$ls180.v:8141$2628_Y
+      attribute \src "ls180.v:8141.6-8141.58"
       case 1'1
         assign $0\main_uart_rx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:8030.2-8036.5"
+    attribute \src "ls180.v:8144.2-8150.5"
     switch \main_uart_tx_fifo_syncfifo_re
-      attribute \src "ls180.v:8030.6-8030.35"
+      attribute \src "ls180.v:8144.6-8144.35"
       case 1'1
         assign $0\main_uart_tx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:8032.6-8032.10"
+      attribute \src "ls180.v:8146.6-8146.10"
       case 
-        attribute \src "ls180.v:8033.3-8035.6"
+        attribute \src "ls180.v:8147.3-8149.6"
         switch \main_uart_tx_fifo_re
-          attribute \src "ls180.v:8033.7-8033.27"
+          attribute \src "ls180.v:8147.7-8147.27"
           case 1'1
             assign $0\main_uart_tx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8037.2-8039.5"
-    switch $and$ls180.v:8037$2553_Y
-      attribute \src "ls180.v:8037.6-8037.108"
+    attribute \src "ls180.v:8151.2-8153.5"
+    switch $and$ls180.v:8151$2631_Y
+      attribute \src "ls180.v:8151.6-8151.108"
       case 1'1
-        assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8038$2554_Y
+        assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8152$2632_Y
       case 
     end
-    attribute \src "ls180.v:8040.2-8042.5"
+    attribute \src "ls180.v:8154.2-8156.5"
     switch \main_uart_tx_fifo_do_read
-      attribute \src "ls180.v:8040.6-8040.31"
+      attribute \src "ls180.v:8154.6-8154.31"
       case 1'1
-        assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8041$2555_Y
+        assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8155$2633_Y
       case 
     end
-    attribute \src "ls180.v:8043.2-8051.5"
-    switch $and$ls180.v:8043$2558_Y
-      attribute \src "ls180.v:8043.6-8043.108"
+    attribute \src "ls180.v:8157.2-8165.5"
+    switch $and$ls180.v:8157$2636_Y
+      attribute \src "ls180.v:8157.6-8157.108"
       case 1'1
-        attribute \src "ls180.v:8044.3-8046.6"
-        switch $not$ls180.v:8044$2559_Y
-          attribute \src "ls180.v:8044.7-8044.35"
+        attribute \src "ls180.v:8158.3-8160.6"
+        switch $not$ls180.v:8158$2637_Y
+          attribute \src "ls180.v:8158.7-8158.35"
           case 1'1
-            assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8045$2560_Y
+            assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8159$2638_Y
           case 
         end
-      attribute \src "ls180.v:8047.6-8047.10"
+      attribute \src "ls180.v:8161.6-8161.10"
       case 
-        attribute \src "ls180.v:8048.3-8050.6"
+        attribute \src "ls180.v:8162.3-8164.6"
         switch \main_uart_tx_fifo_do_read
-          attribute \src "ls180.v:8048.7-8048.32"
+          attribute \src "ls180.v:8162.7-8162.32"
           case 1'1
-            assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8049$2561_Y
+            assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8163$2639_Y
           case 
         end
     end
-    attribute \src "ls180.v:8052.2-8058.5"
+    attribute \src "ls180.v:8166.2-8172.5"
     switch \main_uart_rx_fifo_syncfifo_re
-      attribute \src "ls180.v:8052.6-8052.35"
+      attribute \src "ls180.v:8166.6-8166.35"
       case 1'1
         assign $0\main_uart_rx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:8054.6-8054.10"
+      attribute \src "ls180.v:8168.6-8168.10"
       case 
-        attribute \src "ls180.v:8055.3-8057.6"
+        attribute \src "ls180.v:8169.3-8171.6"
         switch \main_uart_rx_fifo_re
-          attribute \src "ls180.v:8055.7-8055.27"
+          attribute \src "ls180.v:8169.7-8169.27"
           case 1'1
             assign $0\main_uart_rx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8059.2-8061.5"
-    switch $and$ls180.v:8059$2564_Y
-      attribute \src "ls180.v:8059.6-8059.108"
+    attribute \src "ls180.v:8173.2-8175.5"
+    switch $and$ls180.v:8173$2642_Y
+      attribute \src "ls180.v:8173.6-8173.108"
       case 1'1
-        assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8060$2565_Y
+        assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8174$2643_Y
       case 
     end
-    attribute \src "ls180.v:8062.2-8064.5"
+    attribute \src "ls180.v:8176.2-8178.5"
     switch \main_uart_rx_fifo_do_read
-      attribute \src "ls180.v:8062.6-8062.31"
+      attribute \src "ls180.v:8176.6-8176.31"
       case 1'1
-        assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8063$2566_Y
+        assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8177$2644_Y
       case 
     end
-    attribute \src "ls180.v:8065.2-8073.5"
-    switch $and$ls180.v:8065$2569_Y
-      attribute \src "ls180.v:8065.6-8065.108"
+    attribute \src "ls180.v:8179.2-8187.5"
+    switch $and$ls180.v:8179$2647_Y
+      attribute \src "ls180.v:8179.6-8179.108"
       case 1'1
-        attribute \src "ls180.v:8066.3-8068.6"
-        switch $not$ls180.v:8066$2570_Y
-          attribute \src "ls180.v:8066.7-8066.35"
+        attribute \src "ls180.v:8180.3-8182.6"
+        switch $not$ls180.v:8180$2648_Y
+          attribute \src "ls180.v:8180.7-8180.35"
           case 1'1
-            assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8067$2571_Y
+            assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8181$2649_Y
           case 
         end
-      attribute \src "ls180.v:8069.6-8069.10"
+      attribute \src "ls180.v:8183.6-8183.10"
       case 
-        attribute \src "ls180.v:8070.3-8072.6"
+        attribute \src "ls180.v:8184.3-8186.6"
         switch \main_uart_rx_fifo_do_read
-          attribute \src "ls180.v:8070.7-8070.32"
+          attribute \src "ls180.v:8184.7-8184.32"
           case 1'1
-            assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8071$2572_Y
+            assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8185$2650_Y
           case 
         end
     end
-    attribute \src "ls180.v:8074.2-8087.5"
+    attribute \src "ls180.v:8188.2-8201.5"
     switch \main_uart_reset
-      attribute \src "ls180.v:8074.6-8074.21"
+      attribute \src "ls180.v:8188.6-8188.21"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'0
         assign $0\main_uart_tx_old_trigger[0:0] 1'0
@@ -276657,38 +278321,38 @@ module \ls180
         assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
       case 
     end
-    attribute \src "ls180.v:8089.2-8096.5"
+    attribute \src "ls180.v:8203.2-8210.5"
     switch \main_spimaster31_clk_rise
-      attribute \src "ls180.v:8089.6-8089.31"
+      attribute \src "ls180.v:8203.6-8203.31"
       case 1'1
         assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable
-      attribute \src "ls180.v:8091.6-8091.10"
+      attribute \src "ls180.v:8205.6-8205.10"
       case 
-        attribute \src "ls180.v:8092.3-8095.6"
+        attribute \src "ls180.v:8206.3-8209.6"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:8092.7-8092.32"
+          attribute \src "ls180.v:8206.7-8206.32"
           case 1'1
             assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000
             assign $0\spisdcard_clk[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8098.2-8108.5"
+    attribute \src "ls180.v:8212.2-8222.5"
     switch \main_spimaster28_mosi_latch
-      attribute \src "ls180.v:8098.6-8098.33"
+      attribute \src "ls180.v:8212.6-8212.33"
       case 1'1
         assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi
         assign $0\main_spimaster34_mosi_sel[2:0] 3'111
-      attribute \src "ls180.v:8101.6-8101.10"
+      attribute \src "ls180.v:8215.6-8215.10"
       case 
-        attribute \src "ls180.v:8102.3-8107.6"
+        attribute \src "ls180.v:8216.3-8221.6"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:8102.7-8102.32"
+          attribute \src "ls180.v:8216.7-8216.32"
           case 1'1
-            assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8106$2577_Y
-            attribute \src "ls180.v:8103.4-8105.7"
+            assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8220$2655_Y
+            attribute \src "ls180.v:8217.4-8219.7"
             switch \main_spimaster26_cs_enable
-              attribute \src "ls180.v:8103.8-8103.34"
+              attribute \src "ls180.v:8217.8-8217.34"
               case 1'1
                 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0
               case 
@@ -276696,67 +278360,67 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8109.2-8115.5"
+    attribute \src "ls180.v:8223.2-8229.5"
     switch \main_spimaster31_clk_rise
-      attribute \src "ls180.v:8109.6-8109.31"
+      attribute \src "ls180.v:8223.6-8223.31"
       case 1'1
-        attribute \src "ls180.v:8110.3-8114.6"
+        attribute \src "ls180.v:8224.3-8228.6"
         switch \main_spimaster7_loopback
-          attribute \src "ls180.v:8110.7-8110.31"
+          attribute \src "ls180.v:8224.7-8224.31"
           case 1'1
             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi }
-          attribute \src "ls180.v:8112.7-8112.11"
+          attribute \src "ls180.v:8226.7-8226.11"
           case 
             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso }
         end
       case 
     end
-    attribute \src "ls180.v:8116.2-8118.5"
+    attribute \src "ls180.v:8230.2-8232.5"
     switch \main_spimaster29_miso_latch
-      attribute \src "ls180.v:8116.6-8116.33"
+      attribute \src "ls180.v:8230.6-8230.33"
       case 1'1
         assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data
       case 
     end
-    attribute \src "ls180.v:8120.2-8122.5"
+    attribute \src "ls180.v:8234.2-8236.5"
     switch \main_spimaster27_count_spimaster0_next_value_ce
-      attribute \src "ls180.v:8120.6-8120.53"
+      attribute \src "ls180.v:8234.6-8234.53"
       case 1'1
         assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value
       case 
     end
-    attribute \src "ls180.v:8124.2-8131.5"
+    attribute \src "ls180.v:8238.2-8245.5"
     switch \main_spisdcard_clk_rise
-      attribute \src "ls180.v:8124.6-8124.29"
+      attribute \src "ls180.v:8238.6-8238.29"
       case 1'1
         assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable
-      attribute \src "ls180.v:8126.6-8126.10"
+      attribute \src "ls180.v:8240.6-8240.10"
       case 
-        attribute \src "ls180.v:8127.3-8130.6"
+        attribute \src "ls180.v:8241.3-8244.6"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:8127.7-8127.30"
+          attribute \src "ls180.v:8241.7-8241.30"
           case 1'1
             assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
             assign $0\spimaster_clk[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8133.2-8143.5"
+    attribute \src "ls180.v:8247.2-8257.5"
     switch \main_spisdcard_mosi_latch
-      attribute \src "ls180.v:8133.6-8133.31"
+      attribute \src "ls180.v:8247.6-8247.31"
       case 1'1
         assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi
         assign $0\main_spisdcard_mosi_sel[2:0] 3'111
-      attribute \src "ls180.v:8136.6-8136.10"
+      attribute \src "ls180.v:8250.6-8250.10"
       case 
-        attribute \src "ls180.v:8137.3-8142.6"
+        attribute \src "ls180.v:8251.3-8256.6"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:8137.7-8137.30"
+          attribute \src "ls180.v:8251.7-8251.30"
           case 1'1
-            assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8141$2582_Y
-            attribute \src "ls180.v:8138.4-8140.7"
+            assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8255$2660_Y
+            attribute \src "ls180.v:8252.4-8254.7"
             switch \main_spisdcard_cs_enable
-              attribute \src "ls180.v:8138.8-8138.32"
+              attribute \src "ls180.v:8252.8-8252.32"
               case 1'1
                 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1
               case 
@@ -276764,169 +278428,169 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8144.2-8150.5"
+    attribute \src "ls180.v:8258.2-8264.5"
     switch \main_spisdcard_clk_rise
-      attribute \src "ls180.v:8144.6-8144.29"
+      attribute \src "ls180.v:8258.6-8258.29"
       case 1'1
-        attribute \src "ls180.v:8145.3-8149.6"
+        attribute \src "ls180.v:8259.3-8263.6"
         switch \main_spisdcard_loopback
-          attribute \src "ls180.v:8145.7-8145.30"
+          attribute \src "ls180.v:8259.7-8259.30"
           case 1'1
             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi }
-          attribute \src "ls180.v:8147.7-8147.11"
+          attribute \src "ls180.v:8261.7-8261.11"
           case 
             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso }
         end
       case 
     end
-    attribute \src "ls180.v:8151.2-8153.5"
+    attribute \src "ls180.v:8265.2-8267.5"
     switch \main_spisdcard_miso_latch
-      attribute \src "ls180.v:8151.6-8151.31"
+      attribute \src "ls180.v:8265.6-8265.31"
       case 1'1
         assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data
       case 
     end
-    attribute \src "ls180.v:8155.2-8157.5"
+    attribute \src "ls180.v:8269.2-8271.5"
     switch \main_spisdcard_count_spimaster1_next_value_ce
-      attribute \src "ls180.v:8155.6-8155.51"
+      attribute \src "ls180.v:8269.6-8269.51"
       case 1'1
         assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value
       case 
     end
-    attribute \src "ls180.v:8158.2-8171.5"
+    attribute \src "ls180.v:8272.2-8285.5"
     switch \main_pwm0_enable
-      attribute \src "ls180.v:8158.6-8158.22"
+      attribute \src "ls180.v:8272.6-8272.22"
       case 1'1
-        assign $0\main_pwm0_counter[31:0] $add$ls180.v:8159$2583_Y
-        attribute \src "ls180.v:8160.3-8164.6"
-        switch $lt$ls180.v:8160$2584_Y
-          attribute \src "ls180.v:8160.7-8160.44"
+        assign $0\main_pwm0_counter[31:0] $add$ls180.v:8273$2661_Y
+        attribute \src "ls180.v:8274.3-8278.6"
+        switch $lt$ls180.v:8274$2662_Y
+          attribute \src "ls180.v:8274.7-8274.44"
           case 1'1
             assign $0\pwm[1:0] [0] 1'1
-          attribute \src "ls180.v:8162.7-8162.11"
+          attribute \src "ls180.v:8276.7-8276.11"
           case 
             assign $0\pwm[1:0] [0] 1'0
         end
-        attribute \src "ls180.v:8165.3-8167.6"
-        switch $ge$ls180.v:8165$2586_Y
-          attribute \src "ls180.v:8165.7-8165.55"
+        attribute \src "ls180.v:8279.3-8281.6"
+        switch $ge$ls180.v:8279$2664_Y
+          attribute \src "ls180.v:8279.7-8279.55"
           case 1'1
             assign $0\main_pwm0_counter[31:0] 0
           case 
         end
-      attribute \src "ls180.v:8168.6-8168.10"
+      attribute \src "ls180.v:8282.6-8282.10"
       case 
         assign $0\main_pwm0_counter[31:0] 0
         assign $0\pwm[1:0] [0] 1'0
     end
-    attribute \src "ls180.v:8172.2-8185.5"
+    attribute \src "ls180.v:8286.2-8299.5"
     switch \main_pwm1_enable
-      attribute \src "ls180.v:8172.6-8172.22"
+      attribute \src "ls180.v:8286.6-8286.22"
       case 1'1
-        assign $0\main_pwm1_counter[31:0] $add$ls180.v:8173$2587_Y
-        attribute \src "ls180.v:8174.3-8178.6"
-        switch $lt$ls180.v:8174$2588_Y
-          attribute \src "ls180.v:8174.7-8174.44"
+        assign $0\main_pwm1_counter[31:0] $add$ls180.v:8287$2665_Y
+        attribute \src "ls180.v:8288.3-8292.6"
+        switch $lt$ls180.v:8288$2666_Y
+          attribute \src "ls180.v:8288.7-8288.44"
           case 1'1
             assign $0\pwm[1:0] [1] 1'1
-          attribute \src "ls180.v:8176.7-8176.11"
+          attribute \src "ls180.v:8290.7-8290.11"
           case 
             assign $0\pwm[1:0] [1] 1'0
         end
-        attribute \src "ls180.v:8179.3-8181.6"
-        switch $ge$ls180.v:8179$2590_Y
-          attribute \src "ls180.v:8179.7-8179.55"
+        attribute \src "ls180.v:8293.3-8295.6"
+        switch $ge$ls180.v:8293$2668_Y
+          attribute \src "ls180.v:8293.7-8293.55"
           case 1'1
             assign $0\main_pwm1_counter[31:0] 0
           case 
         end
-      attribute \src "ls180.v:8182.6-8182.10"
+      attribute \src "ls180.v:8296.6-8296.10"
       case 
         assign $0\main_pwm1_counter[31:0] 0
         assign $0\pwm[1:0] [1] 1'0
     end
-    attribute \src "ls180.v:8186.2-8188.5"
-    switch $not$ls180.v:8186$2591_Y
-      attribute \src "ls180.v:8186.6-8186.32"
+    attribute \src "ls180.v:8300.2-8302.5"
+    switch $not$ls180.v:8300$2669_Y
+      attribute \src "ls180.v:8300.6-8300.32"
       case 1'1
-        assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8187$2592_Y
+        assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8301$2670_Y
       case 
     end
-    attribute \src "ls180.v:8192.2-8194.5"
+    attribute \src "ls180.v:8306.2-8308.5"
     switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
-      attribute \src "ls180.v:8192.6-8192.57"
+      attribute \src "ls180.v:8306.6-8306.57"
       case 1'1
         assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value
       case 
     end
-    attribute \src "ls180.v:8196.2-8198.5"
+    attribute \src "ls180.v:8310.2-8312.5"
     switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
-      attribute \src "ls180.v:8196.6-8196.57"
+      attribute \src "ls180.v:8310.6-8310.57"
       case 1'1
         assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
       case 
     end
-    attribute \src "ls180.v:8199.2-8201.5"
+    attribute \src "ls180.v:8313.2-8315.5"
     switch \main_sdphy_cmdr_cmdr_pads_in_valid
-      attribute \src "ls180.v:8199.6-8199.40"
+      attribute \src "ls180.v:8313.6-8313.40"
       case 1'1
-        assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8200$2593_Y
+        assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8314$2671_Y
       case 
     end
-    attribute \src "ls180.v:8202.2-8204.5"
+    attribute \src "ls180.v:8316.2-8318.5"
     switch \main_sdphy_cmdr_cmdr_converter_source_ready
-      attribute \src "ls180.v:8202.6-8202.49"
+      attribute \src "ls180.v:8316.6-8316.49"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8205.2-8212.5"
+    attribute \src "ls180.v:8319.2-8326.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8205.6-8205.46"
+      attribute \src "ls180.v:8319.6-8319.46"
       case 1'1
-        attribute \src "ls180.v:8206.3-8211.6"
-        switch $or$ls180.v:8206$2595_Y
-          attribute \src "ls180.v:8206.7-8206.98"
+        attribute \src "ls180.v:8320.3-8325.6"
+        switch $or$ls180.v:8320$2673_Y
+          attribute \src "ls180.v:8320.7-8320.98"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
             assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8209.7-8209.11"
+          attribute \src "ls180.v:8323.7-8323.11"
           case 
-            assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8210$2596_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8324$2674_Y
         end
       case 
     end
-    attribute \src "ls180.v:8213.2-8226.5"
-    switch $and$ls180.v:8213$2597_Y
-      attribute \src "ls180.v:8213.6-8213.97"
+    attribute \src "ls180.v:8327.2-8340.5"
+    switch $and$ls180.v:8327$2675_Y
+      attribute \src "ls180.v:8327.6-8327.97"
       case 1'1
-        attribute \src "ls180.v:8214.3-8220.6"
-        switch $and$ls180.v:8214$2598_Y
-          attribute \src "ls180.v:8214.7-8214.94"
+        attribute \src "ls180.v:8328.3-8334.6"
+        switch $and$ls180.v:8328$2676_Y
+          attribute \src "ls180.v:8328.7-8328.94"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first
             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last
-          attribute \src "ls180.v:8217.7-8217.11"
+          attribute \src "ls180.v:8331.7-8331.11"
           case 
             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8221.6-8221.10"
+      attribute \src "ls180.v:8335.6-8335.10"
       case 
-        attribute \src "ls180.v:8222.3-8225.6"
-        switch $and$ls180.v:8222$2599_Y
-          attribute \src "ls180.v:8222.7-8222.94"
+        attribute \src "ls180.v:8336.3-8339.6"
+        switch $and$ls180.v:8336$2677_Y
+          attribute \src "ls180.v:8336.7-8336.94"
           case 1'1
-            assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8223$2600_Y
-            assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8224$2601_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8337$2678_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8338$2679_Y
           case 
         end
     end
-    attribute \src "ls180.v:8227.2-8254.5"
+    attribute \src "ls180.v:8341.2-8368.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8227.6-8227.46"
+      attribute \src "ls180.v:8341.6-8341.46"
       case 1'1
-        attribute \src "ls180.v:8228.3-8253.10"
+        attribute \src "ls180.v:8342.3-8367.10"
         switch \main_sdphy_cmdr_cmdr_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -276956,16 +278620,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8255.2-8257.5"
+    attribute \src "ls180.v:8369.2-8371.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8255.6-8255.46"
+      attribute \src "ls180.v:8369.6-8369.46"
       case 1'1
-        assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8256$2602_Y
+        assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8370$2680_Y
       case 
     end
-    attribute \src "ls180.v:8258.2-8263.5"
-    switch $or$ls180.v:8258$2604_Y
-      attribute \src "ls180.v:8258.6-8258.88"
+    attribute \src "ls180.v:8372.2-8377.5"
+    switch $or$ls180.v:8372$2682_Y
+      attribute \src "ls180.v:8372.6-8372.88"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid
         assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first
@@ -276973,9 +278637,9 @@ module \ls180
         assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8264.2-8269.5"
+    attribute \src "ls180.v:8378.2-8383.5"
     switch \main_sdphy_cmdr_cmdr_reset
-      attribute \src "ls180.v:8264.6-8264.32"
+      attribute \src "ls180.v:8378.6-8378.32"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
         assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
@@ -276983,88 +278647,88 @@ module \ls180
         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8271.2-8273.5"
+    attribute \src "ls180.v:8385.2-8387.5"
     switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
-      attribute \src "ls180.v:8271.6-8271.58"
+      attribute \src "ls180.v:8385.6-8385.58"
       case 1'1
         assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
       case 
     end
-    attribute \src "ls180.v:8274.2-8276.5"
+    attribute \src "ls180.v:8388.2-8390.5"
     switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
-      attribute \src "ls180.v:8274.6-8274.60"
+      attribute \src "ls180.v:8388.6-8388.60"
       case 1'1
         assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
       case 
     end
-    attribute \src "ls180.v:8277.2-8279.5"
+    attribute \src "ls180.v:8391.2-8393.5"
     switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
-      attribute \src "ls180.v:8277.6-8277.63"
+      attribute \src "ls180.v:8391.6-8391.63"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
       case 
     end
-    attribute \src "ls180.v:8280.2-8282.5"
+    attribute \src "ls180.v:8394.2-8396.5"
     switch \main_sdphy_dataw_crcr_pads_in_valid
-      attribute \src "ls180.v:8280.6-8280.41"
+      attribute \src "ls180.v:8394.6-8394.41"
       case 1'1
-        assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8281$2605_Y
+        assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8395$2683_Y
       case 
     end
-    attribute \src "ls180.v:8283.2-8285.5"
+    attribute \src "ls180.v:8397.2-8399.5"
     switch \main_sdphy_dataw_crcr_converter_source_ready
-      attribute \src "ls180.v:8283.6-8283.50"
+      attribute \src "ls180.v:8397.6-8397.50"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8286.2-8293.5"
+    attribute \src "ls180.v:8400.2-8407.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8286.6-8286.47"
+      attribute \src "ls180.v:8400.6-8400.47"
       case 1'1
-        attribute \src "ls180.v:8287.3-8292.6"
-        switch $or$ls180.v:8287$2607_Y
-          attribute \src "ls180.v:8287.7-8287.100"
+        attribute \src "ls180.v:8401.3-8406.6"
+        switch $or$ls180.v:8401$2685_Y
+          attribute \src "ls180.v:8401.7-8401.100"
           case 1'1
             assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
             assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8290.7-8290.11"
+          attribute \src "ls180.v:8404.7-8404.11"
           case 
-            assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8291$2608_Y
+            assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8405$2686_Y
         end
       case 
     end
-    attribute \src "ls180.v:8294.2-8307.5"
-    switch $and$ls180.v:8294$2609_Y
-      attribute \src "ls180.v:8294.6-8294.99"
+    attribute \src "ls180.v:8408.2-8421.5"
+    switch $and$ls180.v:8408$2687_Y
+      attribute \src "ls180.v:8408.6-8408.99"
       case 1'1
-        attribute \src "ls180.v:8295.3-8301.6"
-        switch $and$ls180.v:8295$2610_Y
-          attribute \src "ls180.v:8295.7-8295.96"
+        attribute \src "ls180.v:8409.3-8415.6"
+        switch $and$ls180.v:8409$2688_Y
+          attribute \src "ls180.v:8409.7-8409.96"
           case 1'1
             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first
             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last
-          attribute \src "ls180.v:8298.7-8298.11"
+          attribute \src "ls180.v:8412.7-8412.11"
           case 
             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8302.6-8302.10"
+      attribute \src "ls180.v:8416.6-8416.10"
       case 
-        attribute \src "ls180.v:8303.3-8306.6"
-        switch $and$ls180.v:8303$2611_Y
-          attribute \src "ls180.v:8303.7-8303.96"
+        attribute \src "ls180.v:8417.3-8420.6"
+        switch $and$ls180.v:8417$2689_Y
+          attribute \src "ls180.v:8417.7-8417.96"
           case 1'1
-            assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8304$2612_Y
-            assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8305$2613_Y
+            assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8418$2690_Y
+            assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8419$2691_Y
           case 
         end
     end
-    attribute \src "ls180.v:8308.2-8335.5"
+    attribute \src "ls180.v:8422.2-8449.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8308.6-8308.47"
+      attribute \src "ls180.v:8422.6-8422.47"
       case 1'1
-        attribute \src "ls180.v:8309.3-8334.10"
+        attribute \src "ls180.v:8423.3-8448.10"
         switch \main_sdphy_dataw_crcr_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -277094,16 +278758,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8336.2-8338.5"
+    attribute \src "ls180.v:8450.2-8452.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8336.6-8336.47"
+      attribute \src "ls180.v:8450.6-8450.47"
       case 1'1
-        assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8337$2614_Y
+        assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8451$2692_Y
       case 
     end
-    attribute \src "ls180.v:8339.2-8344.5"
-    switch $or$ls180.v:8339$2616_Y
-      attribute \src "ls180.v:8339.6-8339.90"
+    attribute \src "ls180.v:8453.2-8458.5"
+    switch $or$ls180.v:8453$2694_Y
+      attribute \src "ls180.v:8453.6-8453.90"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid
         assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first
@@ -277111,9 +278775,9 @@ module \ls180
         assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8345.2-8350.5"
+    attribute \src "ls180.v:8459.2-8464.5"
     switch \main_sdphy_dataw_crcr_reset
-      attribute \src "ls180.v:8345.6-8345.33"
+      attribute \src "ls180.v:8459.6-8459.33"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
         assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
@@ -277121,81 +278785,81 @@ module \ls180
         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8352.2-8354.5"
+    attribute \src "ls180.v:8466.2-8468.5"
     switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
-      attribute \src "ls180.v:8352.6-8352.63"
+      attribute \src "ls180.v:8466.6-8466.63"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
       case 
     end
-    attribute \src "ls180.v:8356.2-8358.5"
+    attribute \src "ls180.v:8470.2-8472.5"
     switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
-      attribute \src "ls180.v:8356.6-8356.52"
+      attribute \src "ls180.v:8470.6-8470.52"
       case 1'1
         assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value
       case 
     end
-    attribute \src "ls180.v:8359.2-8361.5"
+    attribute \src "ls180.v:8473.2-8475.5"
     switch \main_sdphy_datar_datar_pads_in_valid
-      attribute \src "ls180.v:8359.6-8359.42"
+      attribute \src "ls180.v:8473.6-8473.42"
       case 1'1
-        assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8360$2617_Y
+        assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8474$2695_Y
       case 
     end
-    attribute \src "ls180.v:8362.2-8364.5"
+    attribute \src "ls180.v:8476.2-8478.5"
     switch \main_sdphy_datar_datar_converter_source_ready
-      attribute \src "ls180.v:8362.6-8362.51"
+      attribute \src "ls180.v:8476.6-8476.51"
       case 1'1
         assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8365.2-8372.5"
+    attribute \src "ls180.v:8479.2-8486.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8365.6-8365.48"
+      attribute \src "ls180.v:8479.6-8479.48"
       case 1'1
-        attribute \src "ls180.v:8366.3-8371.6"
-        switch $or$ls180.v:8366$2619_Y
-          attribute \src "ls180.v:8366.7-8366.102"
+        attribute \src "ls180.v:8480.3-8485.6"
+        switch $or$ls180.v:8480$2697_Y
+          attribute \src "ls180.v:8480.7-8480.102"
           case 1'1
             assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
             assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8369.7-8369.11"
+          attribute \src "ls180.v:8483.7-8483.11"
           case 
-            assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8370$2620_Y
+            assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8484$2698_Y
         end
       case 
     end
-    attribute \src "ls180.v:8373.2-8386.5"
-    switch $and$ls180.v:8373$2621_Y
-      attribute \src "ls180.v:8373.6-8373.101"
+    attribute \src "ls180.v:8487.2-8500.5"
+    switch $and$ls180.v:8487$2699_Y
+      attribute \src "ls180.v:8487.6-8487.101"
       case 1'1
-        attribute \src "ls180.v:8374.3-8380.6"
-        switch $and$ls180.v:8374$2622_Y
-          attribute \src "ls180.v:8374.7-8374.98"
+        attribute \src "ls180.v:8488.3-8494.6"
+        switch $and$ls180.v:8488$2700_Y
+          attribute \src "ls180.v:8488.7-8488.98"
           case 1'1
             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first
             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last
-          attribute \src "ls180.v:8377.7-8377.11"
+          attribute \src "ls180.v:8491.7-8491.11"
           case 
             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8381.6-8381.10"
+      attribute \src "ls180.v:8495.6-8495.10"
       case 
-        attribute \src "ls180.v:8382.3-8385.6"
-        switch $and$ls180.v:8382$2623_Y
-          attribute \src "ls180.v:8382.7-8382.98"
+        attribute \src "ls180.v:8496.3-8499.6"
+        switch $and$ls180.v:8496$2701_Y
+          attribute \src "ls180.v:8496.7-8496.98"
           case 1'1
-            assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8383$2624_Y
-            assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8384$2625_Y
+            assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8497$2702_Y
+            assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8498$2703_Y
           case 
         end
     end
-    attribute \src "ls180.v:8387.2-8396.5"
+    attribute \src "ls180.v:8501.2-8510.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8387.6-8387.48"
+      attribute \src "ls180.v:8501.6-8501.48"
       case 1'1
-        attribute \src "ls180.v:8388.3-8395.10"
+        attribute \src "ls180.v:8502.3-8509.10"
         switch \main_sdphy_datar_datar_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -277207,16 +278871,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8397.2-8399.5"
+    attribute \src "ls180.v:8511.2-8513.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8397.6-8397.48"
+      attribute \src "ls180.v:8511.6-8511.48"
       case 1'1
-        assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8398$2626_Y
+        assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8512$2704_Y
       case 
     end
-    attribute \src "ls180.v:8400.2-8405.5"
-    switch $or$ls180.v:8400$2628_Y
-      attribute \src "ls180.v:8400.6-8400.92"
+    attribute \src "ls180.v:8514.2-8519.5"
+    switch $or$ls180.v:8514$2706_Y
+      attribute \src "ls180.v:8514.6-8514.92"
       case 1'1
         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid
         assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first
@@ -277224,9 +278888,9 @@ module \ls180
         assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8406.2-8411.5"
+    attribute \src "ls180.v:8520.2-8525.5"
     switch \main_sdphy_datar_datar_reset
-      attribute \src "ls180.v:8406.6-8406.34"
+      attribute \src "ls180.v:8520.6-8520.34"
       case 1'1
         assign $0\main_sdphy_datar_datar_run[0:0] 1'0
         assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
@@ -277234,434 +278898,434 @@ module \ls180
         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8413.2-8415.5"
+    attribute \src "ls180.v:8527.2-8529.5"
     switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
-      attribute \src "ls180.v:8413.6-8413.60"
+      attribute \src "ls180.v:8527.6-8527.60"
       case 1'1
         assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
       case 
     end
-    attribute \src "ls180.v:8416.2-8418.5"
+    attribute \src "ls180.v:8530.2-8532.5"
     switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
-      attribute \src "ls180.v:8416.6-8416.62"
+      attribute \src "ls180.v:8530.6-8530.62"
       case 1'1
         assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
       case 
     end
-    attribute \src "ls180.v:8419.2-8421.5"
+    attribute \src "ls180.v:8533.2-8535.5"
     switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
-      attribute \src "ls180.v:8419.6-8419.66"
+      attribute \src "ls180.v:8533.6-8533.66"
       case 1'1
         assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
       case 
     end
-    attribute \src "ls180.v:8422.2-8428.5"
+    attribute \src "ls180.v:8536.2-8542.5"
     switch \main_sdcore_crc7_inserter_clr
-      attribute \src "ls180.v:8422.6-8422.35"
+      attribute \src "ls180.v:8536.6-8536.35"
       case 1'1
         assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
-      attribute \src "ls180.v:8424.6-8424.10"
+      attribute \src "ls180.v:8538.6-8538.10"
       case 
-        attribute \src "ls180.v:8425.3-8427.6"
+        attribute \src "ls180.v:8539.3-8541.6"
         switch \main_sdcore_crc7_inserter_enable
-          attribute \src "ls180.v:8425.7-8425.39"
+          attribute \src "ls180.v:8539.7-8539.39"
           case 1'1
             assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40
           case 
         end
     end
-    attribute \src "ls180.v:8429.2-8435.5"
+    attribute \src "ls180.v:8543.2-8549.5"
     switch \main_sdcore_crc16_inserter_crc0_clr
-      attribute \src "ls180.v:8429.6-8429.41"
+      attribute \src "ls180.v:8543.6-8543.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8431.6-8431.10"
+      attribute \src "ls180.v:8545.6-8545.10"
       case 
-        attribute \src "ls180.v:8432.3-8434.6"
+        attribute \src "ls180.v:8546.3-8548.6"
         switch \main_sdcore_crc16_inserter_crc0_enable
-          attribute \src "ls180.v:8432.7-8432.45"
+          attribute \src "ls180.v:8546.7-8546.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8436.2-8442.5"
+    attribute \src "ls180.v:8550.2-8556.5"
     switch \main_sdcore_crc16_inserter_crc1_clr
-      attribute \src "ls180.v:8436.6-8436.41"
+      attribute \src "ls180.v:8550.6-8550.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8438.6-8438.10"
+      attribute \src "ls180.v:8552.6-8552.10"
       case 
-        attribute \src "ls180.v:8439.3-8441.6"
+        attribute \src "ls180.v:8553.3-8555.6"
         switch \main_sdcore_crc16_inserter_crc1_enable
-          attribute \src "ls180.v:8439.7-8439.45"
+          attribute \src "ls180.v:8553.7-8553.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8443.2-8449.5"
+    attribute \src "ls180.v:8557.2-8563.5"
     switch \main_sdcore_crc16_inserter_crc2_clr
-      attribute \src "ls180.v:8443.6-8443.41"
+      attribute \src "ls180.v:8557.6-8557.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8445.6-8445.10"
+      attribute \src "ls180.v:8559.6-8559.10"
       case 
-        attribute \src "ls180.v:8446.3-8448.6"
+        attribute \src "ls180.v:8560.3-8562.6"
         switch \main_sdcore_crc16_inserter_crc2_enable
-          attribute \src "ls180.v:8446.7-8446.45"
+          attribute \src "ls180.v:8560.7-8560.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8450.2-8456.5"
+    attribute \src "ls180.v:8564.2-8570.5"
     switch \main_sdcore_crc16_inserter_crc3_clr
-      attribute \src "ls180.v:8450.6-8450.41"
+      attribute \src "ls180.v:8564.6-8564.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8452.6-8452.10"
+      attribute \src "ls180.v:8566.6-8566.10"
       case 
-        attribute \src "ls180.v:8453.3-8455.6"
+        attribute \src "ls180.v:8567.3-8569.6"
         switch \main_sdcore_crc16_inserter_crc3_enable
-          attribute \src "ls180.v:8453.7-8453.45"
+          attribute \src "ls180.v:8567.7-8567.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8458.2-8460.5"
+    attribute \src "ls180.v:8572.2-8574.5"
     switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
-      attribute \src "ls180.v:8458.6-8458.82"
+      attribute \src "ls180.v:8572.6-8572.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
       case 
     end
-    attribute \src "ls180.v:8461.2-8463.5"
+    attribute \src "ls180.v:8575.2-8577.5"
     switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
-      attribute \src "ls180.v:8461.6-8461.82"
+      attribute \src "ls180.v:8575.6-8575.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
       case 
     end
-    attribute \src "ls180.v:8464.2-8466.5"
+    attribute \src "ls180.v:8578.2-8580.5"
     switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
-      attribute \src "ls180.v:8464.6-8464.82"
+      attribute \src "ls180.v:8578.6-8578.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
       case 
     end
-    attribute \src "ls180.v:8467.2-8469.5"
+    attribute \src "ls180.v:8581.2-8583.5"
     switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
-      attribute \src "ls180.v:8467.6-8467.82"
+      attribute \src "ls180.v:8581.6-8581.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
       case 
     end
-    attribute \src "ls180.v:8470.2-8472.5"
+    attribute \src "ls180.v:8584.2-8586.5"
     switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
-      attribute \src "ls180.v:8470.6-8470.78"
+      attribute \src "ls180.v:8584.6-8584.78"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
       case 
     end
-    attribute \src "ls180.v:8473.2-8475.5"
-    switch $and$ls180.v:8473$2629_Y
-      attribute \src "ls180.v:8473.6-8473.83"
+    attribute \src "ls180.v:8587.2-8589.5"
+    switch $and$ls180.v:8587$2707_Y
+      attribute \src "ls180.v:8587.6-8587.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc
       case 
     end
-    attribute \src "ls180.v:8476.2-8478.5"
-    switch $and$ls180.v:8476$2630_Y
-      attribute \src "ls180.v:8476.6-8476.83"
+    attribute \src "ls180.v:8590.2-8592.5"
+    switch $and$ls180.v:8590$2708_Y
+      attribute \src "ls180.v:8590.6-8590.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc
       case 
     end
-    attribute \src "ls180.v:8479.2-8481.5"
-    switch $and$ls180.v:8479$2631_Y
-      attribute \src "ls180.v:8479.6-8479.83"
+    attribute \src "ls180.v:8593.2-8595.5"
+    switch $and$ls180.v:8593$2709_Y
+      attribute \src "ls180.v:8593.6-8593.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc
       case 
     end
-    attribute \src "ls180.v:8482.2-8484.5"
-    switch $and$ls180.v:8482$2632_Y
-      attribute \src "ls180.v:8482.6-8482.83"
+    attribute \src "ls180.v:8596.2-8598.5"
+    switch $and$ls180.v:8596$2710_Y
+      attribute \src "ls180.v:8596.6-8596.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc
       case 
     end
-    attribute \src "ls180.v:8485.2-8489.5"
-    switch $and$ls180.v:8485$2633_Y
-      attribute \src "ls180.v:8485.6-8485.83"
+    attribute \src "ls180.v:8599.2-8603.5"
+    switch $and$ls180.v:8599$2711_Y
+      attribute \src "ls180.v:8599.6-8599.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12]
       case 
     end
-    attribute \src "ls180.v:8490.2-8494.5"
-    switch $and$ls180.v:8490$2634_Y
-      attribute \src "ls180.v:8490.6-8490.83"
+    attribute \src "ls180.v:8604.2-8608.5"
+    switch $and$ls180.v:8604$2712_Y
+      attribute \src "ls180.v:8604.6-8604.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12]
       case 
     end
-    attribute \src "ls180.v:8495.2-8499.5"
-    switch $and$ls180.v:8495$2635_Y
-      attribute \src "ls180.v:8495.6-8495.83"
+    attribute \src "ls180.v:8609.2-8613.5"
+    switch $and$ls180.v:8609$2713_Y
+      attribute \src "ls180.v:8609.6-8609.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12]
       case 
     end
-    attribute \src "ls180.v:8500.2-8504.5"
-    switch $and$ls180.v:8500$2636_Y
-      attribute \src "ls180.v:8500.6-8500.83"
+    attribute \src "ls180.v:8614.2-8618.5"
+    switch $and$ls180.v:8614$2714_Y
+      attribute \src "ls180.v:8614.6-8614.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12]
       case 
     end
-    attribute \src "ls180.v:8505.2-8513.5"
-    switch $and$ls180.v:8505$2637_Y
-      attribute \src "ls180.v:8505.6-8505.83"
+    attribute \src "ls180.v:8619.2-8627.5"
+    switch $and$ls180.v:8619$2715_Y
+      attribute \src "ls180.v:8619.6-8619.83"
       case 1'1
-        attribute \src "ls180.v:8506.3-8512.6"
+        attribute \src "ls180.v:8620.3-8626.6"
         switch \main_sdcore_crc16_checker_sink_last
-          attribute \src "ls180.v:8506.7-8506.42"
+          attribute \src "ls180.v:8620.7-8620.42"
           case 1'1
             assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
-          attribute \src "ls180.v:8508.7-8508.11"
+          attribute \src "ls180.v:8622.7-8622.11"
           case 
-            attribute \src "ls180.v:8509.4-8511.7"
-            switch $ne$ls180.v:8509$2638_Y
-              attribute \src "ls180.v:8509.8-8509.48"
+            attribute \src "ls180.v:8623.4-8625.7"
+            switch $ne$ls180.v:8623$2716_Y
+              attribute \src "ls180.v:8623.8-8623.48"
               case 1'1
-                assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8510$2639_Y
+                assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8624$2717_Y
               case 
             end
         end
       case 
     end
-    attribute \src "ls180.v:8514.2-8520.5"
+    attribute \src "ls180.v:8628.2-8634.5"
     switch \main_sdcore_crc16_checker_crc0_clr
-      attribute \src "ls180.v:8514.6-8514.40"
+      attribute \src "ls180.v:8628.6-8628.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8516.6-8516.10"
+      attribute \src "ls180.v:8630.6-8630.10"
       case 
-        attribute \src "ls180.v:8517.3-8519.6"
+        attribute \src "ls180.v:8631.3-8633.6"
         switch \main_sdcore_crc16_checker_crc0_enable
-          attribute \src "ls180.v:8517.7-8517.44"
+          attribute \src "ls180.v:8631.7-8631.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8521.2-8527.5"
+    attribute \src "ls180.v:8635.2-8641.5"
     switch \main_sdcore_crc16_checker_crc1_clr
-      attribute \src "ls180.v:8521.6-8521.40"
+      attribute \src "ls180.v:8635.6-8635.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8523.6-8523.10"
+      attribute \src "ls180.v:8637.6-8637.10"
       case 
-        attribute \src "ls180.v:8524.3-8526.6"
+        attribute \src "ls180.v:8638.3-8640.6"
         switch \main_sdcore_crc16_checker_crc1_enable
-          attribute \src "ls180.v:8524.7-8524.44"
+          attribute \src "ls180.v:8638.7-8638.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8528.2-8534.5"
+    attribute \src "ls180.v:8642.2-8648.5"
     switch \main_sdcore_crc16_checker_crc2_clr
-      attribute \src "ls180.v:8528.6-8528.40"
+      attribute \src "ls180.v:8642.6-8642.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8530.6-8530.10"
+      attribute \src "ls180.v:8644.6-8644.10"
       case 
-        attribute \src "ls180.v:8531.3-8533.6"
+        attribute \src "ls180.v:8645.3-8647.6"
         switch \main_sdcore_crc16_checker_crc2_enable
-          attribute \src "ls180.v:8531.7-8531.44"
+          attribute \src "ls180.v:8645.7-8645.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8535.2-8541.5"
+    attribute \src "ls180.v:8649.2-8655.5"
     switch \main_sdcore_crc16_checker_crc3_clr
-      attribute \src "ls180.v:8535.6-8535.40"
+      attribute \src "ls180.v:8649.6-8649.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8537.6-8537.10"
+      attribute \src "ls180.v:8651.6-8651.10"
       case 
-        attribute \src "ls180.v:8538.3-8540.6"
+        attribute \src "ls180.v:8652.3-8654.6"
         switch \main_sdcore_crc16_checker_crc3_enable
-          attribute \src "ls180.v:8538.7-8538.44"
+          attribute \src "ls180.v:8652.7-8652.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8543.2-8545.5"
+    attribute \src "ls180.v:8657.2-8659.5"
     switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
-      attribute \src "ls180.v:8543.6-8543.52"
+      attribute \src "ls180.v:8657.6-8657.52"
       case 1'1
         assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0
       case 
     end
-    attribute \src "ls180.v:8546.2-8548.5"
+    attribute \src "ls180.v:8660.2-8662.5"
     switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1
-      attribute \src "ls180.v:8546.6-8546.53"
+      attribute \src "ls180.v:8660.6-8660.53"
       case 1'1
         assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1
       case 
     end
-    attribute \src "ls180.v:8549.2-8551.5"
+    attribute \src "ls180.v:8663.2-8665.5"
     switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
-      attribute \src "ls180.v:8549.6-8549.53"
+      attribute \src "ls180.v:8663.6-8663.53"
       case 1'1
         assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2
       case 
     end
-    attribute \src "ls180.v:8552.2-8554.5"
+    attribute \src "ls180.v:8666.2-8668.5"
     switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3
-      attribute \src "ls180.v:8552.6-8552.54"
+      attribute \src "ls180.v:8666.6-8666.54"
       case 1'1
         assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3
       case 
     end
-    attribute \src "ls180.v:8555.2-8557.5"
+    attribute \src "ls180.v:8669.2-8671.5"
     switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
-      attribute \src "ls180.v:8555.6-8555.53"
+      attribute \src "ls180.v:8669.6-8669.53"
       case 1'1
         assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4
       case 
     end
-    attribute \src "ls180.v:8558.2-8560.5"
+    attribute \src "ls180.v:8672.2-8674.5"
     switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
-      attribute \src "ls180.v:8558.6-8558.55"
+      attribute \src "ls180.v:8672.6-8672.55"
       case 1'1
         assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
       case 
     end
-    attribute \src "ls180.v:8561.2-8563.5"
+    attribute \src "ls180.v:8675.2-8677.5"
     switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6
-      attribute \src "ls180.v:8561.6-8561.54"
+      attribute \src "ls180.v:8675.6-8675.54"
       case 1'1
         assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6
       case 
     end
-    attribute \src "ls180.v:8564.2-8566.5"
+    attribute \src "ls180.v:8678.2-8680.5"
     switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
-      attribute \src "ls180.v:8564.6-8564.56"
+      attribute \src "ls180.v:8678.6-8678.56"
       case 1'1
         assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7
       case 
     end
-    attribute \src "ls180.v:8567.2-8569.5"
+    attribute \src "ls180.v:8681.2-8683.5"
     switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
-      attribute \src "ls180.v:8567.6-8567.63"
+      attribute \src "ls180.v:8681.6-8681.63"
       case 1'1
         assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
       case 
     end
-    attribute \src "ls180.v:8570.2-8572.5"
-    switch $and$ls180.v:8570$2642_Y
-      attribute \src "ls180.v:8570.6-8570.120"
+    attribute \src "ls180.v:8684.2-8686.5"
+    switch $and$ls180.v:8684$2720_Y
+      attribute \src "ls180.v:8684.6-8684.120"
       case 1'1
-        assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8571$2643_Y
+        assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8685$2721_Y
       case 
     end
-    attribute \src "ls180.v:8573.2-8575.5"
+    attribute \src "ls180.v:8687.2-8689.5"
     switch \main_sdblock2mem_fifo_do_read
-      attribute \src "ls180.v:8573.6-8573.35"
+      attribute \src "ls180.v:8687.6-8687.35"
       case 1'1
-        assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8574$2644_Y
+        assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8688$2722_Y
       case 
     end
-    attribute \src "ls180.v:8576.2-8584.5"
-    switch $and$ls180.v:8576$2647_Y
-      attribute \src "ls180.v:8576.6-8576.120"
+    attribute \src "ls180.v:8690.2-8698.5"
+    switch $and$ls180.v:8690$2725_Y
+      attribute \src "ls180.v:8690.6-8690.120"
       case 1'1
-        attribute \src "ls180.v:8577.3-8579.6"
-        switch $not$ls180.v:8577$2648_Y
-          attribute \src "ls180.v:8577.7-8577.39"
+        attribute \src "ls180.v:8691.3-8693.6"
+        switch $not$ls180.v:8691$2726_Y
+          attribute \src "ls180.v:8691.7-8691.39"
           case 1'1
-            assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8578$2649_Y
+            assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8692$2727_Y
           case 
         end
-      attribute \src "ls180.v:8580.6-8580.10"
+      attribute \src "ls180.v:8694.6-8694.10"
       case 
-        attribute \src "ls180.v:8581.3-8583.6"
+        attribute \src "ls180.v:8695.3-8697.6"
         switch \main_sdblock2mem_fifo_do_read
-          attribute \src "ls180.v:8581.7-8581.36"
+          attribute \src "ls180.v:8695.7-8695.36"
           case 1'1
-            assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8582$2650_Y
+            assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8696$2728_Y
           case 
         end
     end
-    attribute \src "ls180.v:8585.2-8587.5"
+    attribute \src "ls180.v:8699.2-8701.5"
     switch \main_sdblock2mem_converter_source_ready
-      attribute \src "ls180.v:8585.6-8585.45"
+      attribute \src "ls180.v:8699.6-8699.45"
       case 1'1
         assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8588.2-8595.5"
+    attribute \src "ls180.v:8702.2-8709.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8588.6-8588.42"
+      attribute \src "ls180.v:8702.6-8702.42"
       case 1'1
-        attribute \src "ls180.v:8589.3-8594.6"
-        switch $or$ls180.v:8589$2652_Y
-          attribute \src "ls180.v:8589.7-8589.90"
+        attribute \src "ls180.v:8703.3-8708.6"
+        switch $or$ls180.v:8703$2730_Y
+          attribute \src "ls180.v:8703.7-8703.90"
           case 1'1
             assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
             assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8592.7-8592.11"
+          attribute \src "ls180.v:8706.7-8706.11"
           case 
-            assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8593$2653_Y
+            assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8707$2731_Y
         end
       case 
     end
-    attribute \src "ls180.v:8596.2-8609.5"
-    switch $and$ls180.v:8596$2654_Y
-      attribute \src "ls180.v:8596.6-8596.89"
+    attribute \src "ls180.v:8710.2-8723.5"
+    switch $and$ls180.v:8710$2732_Y
+      attribute \src "ls180.v:8710.6-8710.89"
       case 1'1
-        attribute \src "ls180.v:8597.3-8603.6"
-        switch $and$ls180.v:8597$2655_Y
-          attribute \src "ls180.v:8597.7-8597.86"
+        attribute \src "ls180.v:8711.3-8717.6"
+        switch $and$ls180.v:8711$2733_Y
+          attribute \src "ls180.v:8711.7-8711.86"
           case 1'1
             assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first
             assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last
-          attribute \src "ls180.v:8600.7-8600.11"
+          attribute \src "ls180.v:8714.7-8714.11"
           case 
             assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0
             assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8604.6-8604.10"
+      attribute \src "ls180.v:8718.6-8718.10"
       case 
-        attribute \src "ls180.v:8605.3-8608.6"
-        switch $and$ls180.v:8605$2656_Y
-          attribute \src "ls180.v:8605.7-8605.86"
+        attribute \src "ls180.v:8719.3-8722.6"
+        switch $and$ls180.v:8719$2734_Y
+          attribute \src "ls180.v:8719.7-8719.86"
           case 1'1
-            assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8606$2657_Y
-            assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8607$2658_Y
+            assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8720$2735_Y
+            assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8721$2736_Y
           case 
         end
     end
-    attribute \src "ls180.v:8610.2-8625.5"
+    attribute \src "ls180.v:8724.2-8739.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8610.6-8610.42"
+      attribute \src "ls180.v:8724.6-8724.42"
       case 1'1
-        attribute \src "ls180.v:8611.3-8624.10"
+        attribute \src "ls180.v:8725.3-8738.10"
         switch \main_sdblock2mem_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -277679,153 +279343,153 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8626.2-8628.5"
+    attribute \src "ls180.v:8740.2-8742.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8626.6-8626.42"
+      attribute \src "ls180.v:8740.6-8740.42"
       case 1'1
-        assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8627$2659_Y
+        assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8741$2737_Y
       case 
     end
-    attribute \src "ls180.v:8630.2-8632.5"
+    attribute \src "ls180.v:8744.2-8746.5"
     switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
-      attribute \src "ls180.v:8630.6-8630.76"
+      attribute \src "ls180.v:8744.6-8744.76"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
       case 
     end
-    attribute \src "ls180.v:8633.2-8636.5"
+    attribute \src "ls180.v:8747.2-8750.5"
     switch \main_sdblock2mem_wishbonedmawriter_reset
-      attribute \src "ls180.v:8633.6-8633.46"
+      attribute \src "ls180.v:8747.6-8747.46"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
         assign $0\builder_sdblock2memdma_state[1:0] 2'00
       case 
     end
-    attribute \src "ls180.v:8638.2-8640.5"
+    attribute \src "ls180.v:8752.2-8754.5"
     switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
-      attribute \src "ls180.v:8638.6-8638.64"
+      attribute \src "ls180.v:8752.6-8752.64"
       case 1'1
         assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
       case 
     end
-    attribute \src "ls180.v:8642.2-8644.5"
+    attribute \src "ls180.v:8756.2-8758.5"
     switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
-      attribute \src "ls180.v:8642.6-8642.76"
+      attribute \src "ls180.v:8756.6-8756.76"
       case 1'1
         assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
       case 
     end
-    attribute \src "ls180.v:8645.2-8648.5"
+    attribute \src "ls180.v:8759.2-8762.5"
     switch \main_sdmem2block_dma_reset
-      attribute \src "ls180.v:8645.6-8645.32"
+      attribute \src "ls180.v:8759.6-8759.32"
       case 1'1
         assign $0\main_sdmem2block_dma_offset[31:0] 0
         assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
       case 
     end
-    attribute \src "ls180.v:8649.2-8655.5"
-    switch $and$ls180.v:8649$2660_Y
-      attribute \src "ls180.v:8649.6-8649.89"
+    attribute \src "ls180.v:8763.2-8769.5"
+    switch $and$ls180.v:8763$2738_Y
+      attribute \src "ls180.v:8763.6-8763.89"
       case 1'1
-        attribute \src "ls180.v:8650.3-8654.6"
+        attribute \src "ls180.v:8764.3-8768.6"
         switch \main_sdmem2block_converter_last
-          attribute \src "ls180.v:8650.7-8650.38"
+          attribute \src "ls180.v:8764.7-8764.38"
           case 1'1
             assign $0\main_sdmem2block_converter_mux[1:0] 2'00
-          attribute \src "ls180.v:8652.7-8652.11"
+          attribute \src "ls180.v:8766.7-8766.11"
           case 
-            assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8653$2661_Y
+            assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8767$2739_Y
         end
       case 
     end
-    attribute \src "ls180.v:8656.2-8658.5"
-    switch $and$ls180.v:8656$2664_Y
-      attribute \src "ls180.v:8656.6-8656.120"
+    attribute \src "ls180.v:8770.2-8772.5"
+    switch $and$ls180.v:8770$2742_Y
+      attribute \src "ls180.v:8770.6-8770.120"
       case 1'1
-        assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8657$2665_Y
+        assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8771$2743_Y
       case 
     end
-    attribute \src "ls180.v:8659.2-8661.5"
+    attribute \src "ls180.v:8773.2-8775.5"
     switch \main_sdmem2block_fifo_do_read
-      attribute \src "ls180.v:8659.6-8659.35"
+      attribute \src "ls180.v:8773.6-8773.35"
       case 1'1
-        assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8660$2666_Y
+        assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8774$2744_Y
       case 
     end
-    attribute \src "ls180.v:8662.2-8670.5"
-    switch $and$ls180.v:8662$2669_Y
-      attribute \src "ls180.v:8662.6-8662.120"
+    attribute \src "ls180.v:8776.2-8784.5"
+    switch $and$ls180.v:8776$2747_Y
+      attribute \src "ls180.v:8776.6-8776.120"
       case 1'1
-        attribute \src "ls180.v:8663.3-8665.6"
-        switch $not$ls180.v:8663$2670_Y
-          attribute \src "ls180.v:8663.7-8663.39"
+        attribute \src "ls180.v:8777.3-8779.6"
+        switch $not$ls180.v:8777$2748_Y
+          attribute \src "ls180.v:8777.7-8777.39"
           case 1'1
-            assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8664$2671_Y
+            assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8778$2749_Y
           case 
         end
-      attribute \src "ls180.v:8666.6-8666.10"
+      attribute \src "ls180.v:8780.6-8780.10"
       case 
-        attribute \src "ls180.v:8667.3-8669.6"
+        attribute \src "ls180.v:8781.3-8783.6"
         switch \main_sdmem2block_fifo_do_read
-          attribute \src "ls180.v:8667.7-8667.36"
+          attribute \src "ls180.v:8781.7-8781.36"
           case 1'1
-            assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8668$2672_Y
+            assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8782$2750_Y
           case 
         end
     end
-    attribute \src "ls180.v:8672.2-8674.5"
+    attribute \src "ls180.v:8786.2-8788.5"
     switch \builder_libresocsim_dat_w_next_value_ce0
-      attribute \src "ls180.v:8672.6-8672.46"
+      attribute \src "ls180.v:8786.6-8786.46"
       case 1'1
         assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0
       case 
     end
-    attribute \src "ls180.v:8675.2-8677.5"
+    attribute \src "ls180.v:8789.2-8791.5"
     switch \builder_libresocsim_adr_next_value_ce1
-      attribute \src "ls180.v:8675.6-8675.44"
+      attribute \src "ls180.v:8789.6-8789.44"
       case 1'1
         assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1
       case 
     end
-    attribute \src "ls180.v:8678.2-8680.5"
+    attribute \src "ls180.v:8792.2-8794.5"
     switch \builder_libresocsim_we_next_value_ce2
-      attribute \src "ls180.v:8678.6-8678.43"
+      attribute \src "ls180.v:8792.6-8792.43"
       case 1'1
         assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2
       case 
     end
-    attribute \src "ls180.v:8681.2-8777.9"
+    attribute \src "ls180.v:8795.2-8891.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
-        attribute \src "ls180.v:8683.4-8699.7"
-        switch $not$ls180.v:8683$2673_Y
-          attribute \src "ls180.v:8683.8-8683.29"
+        attribute \src "ls180.v:8797.4-8813.7"
+        switch $not$ls180.v:8797$2751_Y
+          attribute \src "ls180.v:8797.8-8797.29"
           case 1'1
-            attribute \src "ls180.v:8684.5-8698.8"
+            attribute \src "ls180.v:8798.5-8812.8"
             switch \builder_request [1]
-              attribute \src "ls180.v:8684.9-8684.27"
+              attribute \src "ls180.v:8798.9-8798.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'001
-              attribute \src "ls180.v:8686.9-8686.13"
+              attribute \src "ls180.v:8800.9-8800.13"
               case 
-                attribute \src "ls180.v:8687.6-8697.9"
+                attribute \src "ls180.v:8801.6-8811.9"
                 switch \builder_request [2]
-                  attribute \src "ls180.v:8687.10-8687.28"
+                  attribute \src "ls180.v:8801.10-8801.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'010
-                  attribute \src "ls180.v:8689.10-8689.14"
+                  attribute \src "ls180.v:8803.10-8803.14"
                   case 
-                    attribute \src "ls180.v:8690.7-8696.10"
+                    attribute \src "ls180.v:8804.7-8810.10"
                     switch \builder_request [3]
-                      attribute \src "ls180.v:8690.11-8690.29"
+                      attribute \src "ls180.v:8804.11-8804.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'011
-                      attribute \src "ls180.v:8692.11-8692.15"
+                      attribute \src "ls180.v:8806.11-8806.15"
                       case 
-                        attribute \src "ls180.v:8693.8-8695.11"
+                        attribute \src "ls180.v:8807.8-8809.11"
                         switch \builder_request [4]
-                          attribute \src "ls180.v:8693.12-8693.30"
+                          attribute \src "ls180.v:8807.12-8807.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'100
                           case 
@@ -277837,34 +279501,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
-        attribute \src "ls180.v:8702.4-8718.7"
-        switch $not$ls180.v:8702$2674_Y
-          attribute \src "ls180.v:8702.8-8702.29"
+        attribute \src "ls180.v:8816.4-8832.7"
+        switch $not$ls180.v:8816$2752_Y
+          attribute \src "ls180.v:8816.8-8816.29"
           case 1'1
-            attribute \src "ls180.v:8703.5-8717.8"
+            attribute \src "ls180.v:8817.5-8831.8"
             switch \builder_request [2]
-              attribute \src "ls180.v:8703.9-8703.27"
+              attribute \src "ls180.v:8817.9-8817.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'010
-              attribute \src "ls180.v:8705.9-8705.13"
+              attribute \src "ls180.v:8819.9-8819.13"
               case 
-                attribute \src "ls180.v:8706.6-8716.9"
+                attribute \src "ls180.v:8820.6-8830.9"
                 switch \builder_request [3]
-                  attribute \src "ls180.v:8706.10-8706.28"
+                  attribute \src "ls180.v:8820.10-8820.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'011
-                  attribute \src "ls180.v:8708.10-8708.14"
+                  attribute \src "ls180.v:8822.10-8822.14"
                   case 
-                    attribute \src "ls180.v:8709.7-8715.10"
+                    attribute \src "ls180.v:8823.7-8829.10"
                     switch \builder_request [4]
-                      attribute \src "ls180.v:8709.11-8709.29"
+                      attribute \src "ls180.v:8823.11-8823.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'100
-                      attribute \src "ls180.v:8711.11-8711.15"
+                      attribute \src "ls180.v:8825.11-8825.15"
                       case 
-                        attribute \src "ls180.v:8712.8-8714.11"
+                        attribute \src "ls180.v:8826.8-8828.11"
                         switch \builder_request [0]
-                          attribute \src "ls180.v:8712.12-8712.30"
+                          attribute \src "ls180.v:8826.12-8826.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'000
                           case 
@@ -277876,34 +279540,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
-        attribute \src "ls180.v:8721.4-8737.7"
-        switch $not$ls180.v:8721$2675_Y
-          attribute \src "ls180.v:8721.8-8721.29"
+        attribute \src "ls180.v:8835.4-8851.7"
+        switch $not$ls180.v:8835$2753_Y
+          attribute \src "ls180.v:8835.8-8835.29"
           case 1'1
-            attribute \src "ls180.v:8722.5-8736.8"
+            attribute \src "ls180.v:8836.5-8850.8"
             switch \builder_request [3]
-              attribute \src "ls180.v:8722.9-8722.27"
+              attribute \src "ls180.v:8836.9-8836.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'011
-              attribute \src "ls180.v:8724.9-8724.13"
+              attribute \src "ls180.v:8838.9-8838.13"
               case 
-                attribute \src "ls180.v:8725.6-8735.9"
+                attribute \src "ls180.v:8839.6-8849.9"
                 switch \builder_request [4]
-                  attribute \src "ls180.v:8725.10-8725.28"
+                  attribute \src "ls180.v:8839.10-8839.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'100
-                  attribute \src "ls180.v:8727.10-8727.14"
+                  attribute \src "ls180.v:8841.10-8841.14"
                   case 
-                    attribute \src "ls180.v:8728.7-8734.10"
+                    attribute \src "ls180.v:8842.7-8848.10"
                     switch \builder_request [0]
-                      attribute \src "ls180.v:8728.11-8728.29"
+                      attribute \src "ls180.v:8842.11-8842.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'000
-                      attribute \src "ls180.v:8730.11-8730.15"
+                      attribute \src "ls180.v:8844.11-8844.15"
                       case 
-                        attribute \src "ls180.v:8731.8-8733.11"
+                        attribute \src "ls180.v:8845.8-8847.11"
                         switch \builder_request [1]
-                          attribute \src "ls180.v:8731.12-8731.30"
+                          attribute \src "ls180.v:8845.12-8845.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'001
                           case 
@@ -277915,34 +279579,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:8740.4-8756.7"
-        switch $not$ls180.v:8740$2676_Y
-          attribute \src "ls180.v:8740.8-8740.29"
+        attribute \src "ls180.v:8854.4-8870.7"
+        switch $not$ls180.v:8854$2754_Y
+          attribute \src "ls180.v:8854.8-8854.29"
           case 1'1
-            attribute \src "ls180.v:8741.5-8755.8"
+            attribute \src "ls180.v:8855.5-8869.8"
             switch \builder_request [4]
-              attribute \src "ls180.v:8741.9-8741.27"
+              attribute \src "ls180.v:8855.9-8855.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'100
-              attribute \src "ls180.v:8743.9-8743.13"
+              attribute \src "ls180.v:8857.9-8857.13"
               case 
-                attribute \src "ls180.v:8744.6-8754.9"
+                attribute \src "ls180.v:8858.6-8868.9"
                 switch \builder_request [0]
-                  attribute \src "ls180.v:8744.10-8744.28"
+                  attribute \src "ls180.v:8858.10-8858.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'000
-                  attribute \src "ls180.v:8746.10-8746.14"
+                  attribute \src "ls180.v:8860.10-8860.14"
                   case 
-                    attribute \src "ls180.v:8747.7-8753.10"
+                    attribute \src "ls180.v:8861.7-8867.10"
                     switch \builder_request [1]
-                      attribute \src "ls180.v:8747.11-8747.29"
+                      attribute \src "ls180.v:8861.11-8861.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'001
-                      attribute \src "ls180.v:8749.11-8749.15"
+                      attribute \src "ls180.v:8863.11-8863.15"
                       case 
-                        attribute \src "ls180.v:8750.8-8752.11"
+                        attribute \src "ls180.v:8864.8-8866.11"
                         switch \builder_request [2]
-                          attribute \src "ls180.v:8750.12-8750.30"
+                          attribute \src "ls180.v:8864.12-8864.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'010
                           case 
@@ -277954,34 +279618,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'100
-        attribute \src "ls180.v:8759.4-8775.7"
-        switch $not$ls180.v:8759$2677_Y
-          attribute \src "ls180.v:8759.8-8759.29"
+        attribute \src "ls180.v:8873.4-8889.7"
+        switch $not$ls180.v:8873$2755_Y
+          attribute \src "ls180.v:8873.8-8873.29"
           case 1'1
-            attribute \src "ls180.v:8760.5-8774.8"
+            attribute \src "ls180.v:8874.5-8888.8"
             switch \builder_request [0]
-              attribute \src "ls180.v:8760.9-8760.27"
+              attribute \src "ls180.v:8874.9-8874.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'000
-              attribute \src "ls180.v:8762.9-8762.13"
+              attribute \src "ls180.v:8876.9-8876.13"
               case 
-                attribute \src "ls180.v:8763.6-8773.9"
+                attribute \src "ls180.v:8877.6-8887.9"
                 switch \builder_request [1]
-                  attribute \src "ls180.v:8763.10-8763.28"
+                  attribute \src "ls180.v:8877.10-8877.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'001
-                  attribute \src "ls180.v:8765.10-8765.14"
+                  attribute \src "ls180.v:8879.10-8879.14"
                   case 
-                    attribute \src "ls180.v:8766.7-8772.10"
+                    attribute \src "ls180.v:8880.7-8886.10"
                     switch \builder_request [2]
-                      attribute \src "ls180.v:8766.11-8766.29"
+                      attribute \src "ls180.v:8880.11-8880.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'010
-                      attribute \src "ls180.v:8768.11-8768.15"
+                      attribute \src "ls180.v:8882.11-8882.15"
                       case 
-                        attribute \src "ls180.v:8769.8-8771.11"
+                        attribute \src "ls180.v:8883.8-8885.11"
                         switch \builder_request [3]
-                          attribute \src "ls180.v:8769.12-8769.30"
+                          attribute \src "ls180.v:8883.12-8883.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'011
                           case 
@@ -277993,26 +279657,26 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8779.2-8785.5"
+    attribute \src "ls180.v:8893.2-8899.5"
     switch \builder_wait
-      attribute \src "ls180.v:8779.6-8779.18"
+      attribute \src "ls180.v:8893.6-8893.18"
       case 1'1
-        attribute \src "ls180.v:8780.3-8782.6"
-        switch $not$ls180.v:8780$2678_Y
-          attribute \src "ls180.v:8780.7-8780.22"
+        attribute \src "ls180.v:8894.3-8896.6"
+        switch $not$ls180.v:8894$2756_Y
+          attribute \src "ls180.v:8894.7-8894.22"
           case 1'1
-            assign $0\builder_count[19:0] $sub$ls180.v:8781$2679_Y
+            assign $0\builder_count[19:0] $sub$ls180.v:8895$2757_Y
           case 
         end
-      attribute \src "ls180.v:8783.6-8783.10"
+      attribute \src "ls180.v:8897.6-8897.10"
       case 
         assign $0\builder_count[19:0] 20'11110100001001000000
     end
-    attribute \src "ls180.v:8787.2-8817.5"
+    attribute \src "ls180.v:8901.2-8931.5"
     switch \builder_csrbank0_sel
-      attribute \src "ls180.v:8787.6-8787.26"
+      attribute \src "ls180.v:8901.6-8901.26"
       case 1'1
-        attribute \src "ls180.v:8788.3-8816.10"
+        attribute \src "ls180.v:8902.3-8930.10"
         switch \builder_interface0_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -278045,46 +279709,46 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8818.2-8820.5"
+    attribute \src "ls180.v:8932.2-8934.5"
     switch \builder_csrbank0_reset0_re
-      attribute \src "ls180.v:8818.6-8818.32"
+      attribute \src "ls180.v:8932.6-8932.32"
       case 1'1
         assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r
       case 
     end
-    attribute \src "ls180.v:8822.2-8824.5"
+    attribute \src "ls180.v:8936.2-8938.5"
     switch \builder_csrbank0_scratch3_re
-      attribute \src "ls180.v:8822.6-8822.34"
+      attribute \src "ls180.v:8936.6-8936.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r
       case 
     end
-    attribute \src "ls180.v:8825.2-8827.5"
+    attribute \src "ls180.v:8939.2-8941.5"
     switch \builder_csrbank0_scratch2_re
-      attribute \src "ls180.v:8825.6-8825.34"
+      attribute \src "ls180.v:8939.6-8939.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r
       case 
     end
-    attribute \src "ls180.v:8828.2-8830.5"
+    attribute \src "ls180.v:8942.2-8944.5"
     switch \builder_csrbank0_scratch1_re
-      attribute \src "ls180.v:8828.6-8828.34"
+      attribute \src "ls180.v:8942.6-8942.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r
       case 
     end
-    attribute \src "ls180.v:8831.2-8833.5"
+    attribute \src "ls180.v:8945.2-8947.5"
     switch \builder_csrbank0_scratch0_re
-      attribute \src "ls180.v:8831.6-8831.34"
+      attribute \src "ls180.v:8945.6-8945.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r
       case 
     end
-    attribute \src "ls180.v:8836.2-8857.5"
+    attribute \src "ls180.v:8950.2-8971.5"
     switch \builder_csrbank1_sel
-      attribute \src "ls180.v:8836.6-8836.26"
+      attribute \src "ls180.v:8950.6-8950.26"
       case 1'1
-        attribute \src "ls180.v:8837.3-8856.10"
+        attribute \src "ls180.v:8951.3-8970.10"
         switch \builder_interface1_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -278108,39 +279772,39 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8858.2-8860.5"
+    attribute \src "ls180.v:8972.2-8974.5"
     switch \builder_csrbank1_oe1_re
-      attribute \src "ls180.v:8858.6-8858.29"
+      attribute \src "ls180.v:8972.6-8972.29"
       case 1'1
         assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r
       case 
     end
-    attribute \src "ls180.v:8861.2-8863.5"
+    attribute \src "ls180.v:8975.2-8977.5"
     switch \builder_csrbank1_oe0_re
-      attribute \src "ls180.v:8861.6-8861.29"
+      attribute \src "ls180.v:8975.6-8975.29"
       case 1'1
         assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r
       case 
     end
-    attribute \src "ls180.v:8865.2-8867.5"
+    attribute \src "ls180.v:8979.2-8981.5"
     switch \builder_csrbank1_out1_re
-      attribute \src "ls180.v:8865.6-8865.30"
+      attribute \src "ls180.v:8979.6-8979.30"
       case 1'1
         assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r
       case 
     end
-    attribute \src "ls180.v:8868.2-8870.5"
+    attribute \src "ls180.v:8982.2-8984.5"
     switch \builder_csrbank1_out0_re
-      attribute \src "ls180.v:8868.6-8868.30"
+      attribute \src "ls180.v:8982.6-8982.30"
       case 1'1
         assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r
       case 
     end
-    attribute \src "ls180.v:8873.2-8882.5"
+    attribute \src "ls180.v:8987.2-8996.5"
     switch \builder_csrbank2_sel
-      attribute \src "ls180.v:8873.6-8873.26"
+      attribute \src "ls180.v:8987.6-8987.26"
       case 1'1
-        attribute \src "ls180.v:8874.3-8881.10"
+        attribute \src "ls180.v:8988.3-8995.10"
         switch \builder_interface2_bank_bus_adr [0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -278152,18 +279816,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8883.2-8885.5"
+    attribute \src "ls180.v:8997.2-8999.5"
     switch \builder_csrbank2_w0_re
-      attribute \src "ls180.v:8883.6-8883.28"
+      attribute \src "ls180.v:8997.6-8997.28"
       case 1'1
         assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r
       case 
     end
-    attribute \src "ls180.v:8888.2-8918.5"
+    attribute \src "ls180.v:9002.2-9032.5"
     switch \builder_csrbank3_sel
-      attribute \src "ls180.v:8888.6-8888.26"
+      attribute \src "ls180.v:9002.6-9002.26"
       case 1'1
-        attribute \src "ls180.v:8889.3-8917.10"
+        attribute \src "ls180.v:9003.3-9031.10"
         switch \builder_interface3_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -278196,74 +279860,74 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8919.2-8921.5"
+    attribute \src "ls180.v:9033.2-9035.5"
     switch \builder_csrbank3_enable0_re
-      attribute \src "ls180.v:8919.6-8919.33"
+      attribute \src "ls180.v:9033.6-9033.33"
       case 1'1
         assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r
       case 
     end
-    attribute \src "ls180.v:8923.2-8925.5"
+    attribute \src "ls180.v:9037.2-9039.5"
     switch \builder_csrbank3_width3_re
-      attribute \src "ls180.v:8923.6-8923.32"
+      attribute \src "ls180.v:9037.6-9037.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
       case 
     end
-    attribute \src "ls180.v:8926.2-8928.5"
+    attribute \src "ls180.v:9040.2-9042.5"
     switch \builder_csrbank3_width2_re
-      attribute \src "ls180.v:8926.6-8926.32"
+      attribute \src "ls180.v:9040.6-9040.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
       case 
     end
-    attribute \src "ls180.v:8929.2-8931.5"
+    attribute \src "ls180.v:9043.2-9045.5"
     switch \builder_csrbank3_width1_re
-      attribute \src "ls180.v:8929.6-8929.32"
+      attribute \src "ls180.v:9043.6-9043.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
       case 
     end
-    attribute \src "ls180.v:8932.2-8934.5"
+    attribute \src "ls180.v:9046.2-9048.5"
     switch \builder_csrbank3_width0_re
-      attribute \src "ls180.v:8932.6-8932.32"
+      attribute \src "ls180.v:9046.6-9046.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
       case 
     end
-    attribute \src "ls180.v:8936.2-8938.5"
+    attribute \src "ls180.v:9050.2-9052.5"
     switch \builder_csrbank3_period3_re
-      attribute \src "ls180.v:8936.6-8936.33"
+      attribute \src "ls180.v:9050.6-9050.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
       case 
     end
-    attribute \src "ls180.v:8939.2-8941.5"
+    attribute \src "ls180.v:9053.2-9055.5"
     switch \builder_csrbank3_period2_re
-      attribute \src "ls180.v:8939.6-8939.33"
+      attribute \src "ls180.v:9053.6-9053.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
       case 
     end
-    attribute \src "ls180.v:8942.2-8944.5"
+    attribute \src "ls180.v:9056.2-9058.5"
     switch \builder_csrbank3_period1_re
-      attribute \src "ls180.v:8942.6-8942.33"
+      attribute \src "ls180.v:9056.6-9056.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
       case 
     end
-    attribute \src "ls180.v:8945.2-8947.5"
+    attribute \src "ls180.v:9059.2-9061.5"
     switch \builder_csrbank3_period0_re
-      attribute \src "ls180.v:8945.6-8945.33"
+      attribute \src "ls180.v:9059.6-9059.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
       case 
     end
-    attribute \src "ls180.v:8950.2-8980.5"
+    attribute \src "ls180.v:9064.2-9094.5"
     switch \builder_csrbank4_sel
-      attribute \src "ls180.v:8950.6-8950.26"
+      attribute \src "ls180.v:9064.6-9064.26"
       case 1'1
-        attribute \src "ls180.v:8951.3-8979.10"
+        attribute \src "ls180.v:9065.3-9093.10"
         switch \builder_interface4_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -278296,74 +279960,74 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8981.2-8983.5"
+    attribute \src "ls180.v:9095.2-9097.5"
     switch \builder_csrbank4_enable0_re
-      attribute \src "ls180.v:8981.6-8981.33"
+      attribute \src "ls180.v:9095.6-9095.33"
       case 1'1
         assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r
       case 
     end
-    attribute \src "ls180.v:8985.2-8987.5"
+    attribute \src "ls180.v:9099.2-9101.5"
     switch \builder_csrbank4_width3_re
-      attribute \src "ls180.v:8985.6-8985.32"
+      attribute \src "ls180.v:9099.6-9099.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r
       case 
     end
-    attribute \src "ls180.v:8988.2-8990.5"
+    attribute \src "ls180.v:9102.2-9104.5"
     switch \builder_csrbank4_width2_re
-      attribute \src "ls180.v:8988.6-8988.32"
+      attribute \src "ls180.v:9102.6-9102.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r
       case 
     end
-    attribute \src "ls180.v:8991.2-8993.5"
+    attribute \src "ls180.v:9105.2-9107.5"
     switch \builder_csrbank4_width1_re
-      attribute \src "ls180.v:8991.6-8991.32"
+      attribute \src "ls180.v:9105.6-9105.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r
       case 
     end
-    attribute \src "ls180.v:8994.2-8996.5"
+    attribute \src "ls180.v:9108.2-9110.5"
     switch \builder_csrbank4_width0_re
-      attribute \src "ls180.v:8994.6-8994.32"
+      attribute \src "ls180.v:9108.6-9108.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r
       case 
     end
-    attribute \src "ls180.v:8998.2-9000.5"
+    attribute \src "ls180.v:9112.2-9114.5"
     switch \builder_csrbank4_period3_re
-      attribute \src "ls180.v:8998.6-8998.33"
+      attribute \src "ls180.v:9112.6-9112.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r
       case 
     end
-    attribute \src "ls180.v:9001.2-9003.5"
+    attribute \src "ls180.v:9115.2-9117.5"
     switch \builder_csrbank4_period2_re
-      attribute \src "ls180.v:9001.6-9001.33"
+      attribute \src "ls180.v:9115.6-9115.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r
       case 
     end
-    attribute \src "ls180.v:9004.2-9006.5"
+    attribute \src "ls180.v:9118.2-9120.5"
     switch \builder_csrbank4_period1_re
-      attribute \src "ls180.v:9004.6-9004.33"
+      attribute \src "ls180.v:9118.6-9118.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r
       case 
     end
-    attribute \src "ls180.v:9007.2-9009.5"
+    attribute \src "ls180.v:9121.2-9123.5"
     switch \builder_csrbank4_period0_re
-      attribute \src "ls180.v:9007.6-9007.33"
+      attribute \src "ls180.v:9121.6-9121.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r
       case 
     end
-    attribute \src "ls180.v:9012.2-9060.5"
+    attribute \src "ls180.v:9126.2-9174.5"
     switch \builder_csrbank5_sel
-      attribute \src "ls180.v:9012.6-9012.26"
+      attribute \src "ls180.v:9126.6-9126.26"
       case 1'1
-        attribute \src "ls180.v:9013.3-9059.10"
+        attribute \src "ls180.v:9127.3-9173.10"
         switch \builder_interface5_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -278414,109 +280078,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9061.2-9063.5"
+    attribute \src "ls180.v:9175.2-9177.5"
     switch \builder_csrbank5_dma_base7_re
-      attribute \src "ls180.v:9061.6-9061.35"
+      attribute \src "ls180.v:9175.6-9175.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r
       case 
     end
-    attribute \src "ls180.v:9064.2-9066.5"
+    attribute \src "ls180.v:9178.2-9180.5"
     switch \builder_csrbank5_dma_base6_re
-      attribute \src "ls180.v:9064.6-9064.35"
+      attribute \src "ls180.v:9178.6-9178.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r
       case 
     end
-    attribute \src "ls180.v:9067.2-9069.5"
+    attribute \src "ls180.v:9181.2-9183.5"
     switch \builder_csrbank5_dma_base5_re
-      attribute \src "ls180.v:9067.6-9067.35"
+      attribute \src "ls180.v:9181.6-9181.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r
       case 
     end
-    attribute \src "ls180.v:9070.2-9072.5"
+    attribute \src "ls180.v:9184.2-9186.5"
     switch \builder_csrbank5_dma_base4_re
-      attribute \src "ls180.v:9070.6-9070.35"
+      attribute \src "ls180.v:9184.6-9184.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r
       case 
     end
-    attribute \src "ls180.v:9073.2-9075.5"
+    attribute \src "ls180.v:9187.2-9189.5"
     switch \builder_csrbank5_dma_base3_re
-      attribute \src "ls180.v:9073.6-9073.35"
+      attribute \src "ls180.v:9187.6-9187.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r
       case 
     end
-    attribute \src "ls180.v:9076.2-9078.5"
+    attribute \src "ls180.v:9190.2-9192.5"
     switch \builder_csrbank5_dma_base2_re
-      attribute \src "ls180.v:9076.6-9076.35"
+      attribute \src "ls180.v:9190.6-9190.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r
       case 
     end
-    attribute \src "ls180.v:9079.2-9081.5"
+    attribute \src "ls180.v:9193.2-9195.5"
     switch \builder_csrbank5_dma_base1_re
-      attribute \src "ls180.v:9079.6-9079.35"
+      attribute \src "ls180.v:9193.6-9193.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r
       case 
     end
-    attribute \src "ls180.v:9082.2-9084.5"
+    attribute \src "ls180.v:9196.2-9198.5"
     switch \builder_csrbank5_dma_base0_re
-      attribute \src "ls180.v:9082.6-9082.35"
+      attribute \src "ls180.v:9196.6-9196.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r
       case 
     end
-    attribute \src "ls180.v:9086.2-9088.5"
+    attribute \src "ls180.v:9200.2-9202.5"
     switch \builder_csrbank5_dma_length3_re
-      attribute \src "ls180.v:9086.6-9086.37"
+      attribute \src "ls180.v:9200.6-9200.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r
       case 
     end
-    attribute \src "ls180.v:9089.2-9091.5"
+    attribute \src "ls180.v:9203.2-9205.5"
     switch \builder_csrbank5_dma_length2_re
-      attribute \src "ls180.v:9089.6-9089.37"
+      attribute \src "ls180.v:9203.6-9203.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r
       case 
     end
-    attribute \src "ls180.v:9092.2-9094.5"
+    attribute \src "ls180.v:9206.2-9208.5"
     switch \builder_csrbank5_dma_length1_re
-      attribute \src "ls180.v:9092.6-9092.37"
+      attribute \src "ls180.v:9206.6-9206.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r
       case 
     end
-    attribute \src "ls180.v:9095.2-9097.5"
+    attribute \src "ls180.v:9209.2-9211.5"
     switch \builder_csrbank5_dma_length0_re
-      attribute \src "ls180.v:9095.6-9095.37"
+      attribute \src "ls180.v:9209.6-9209.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r
       case 
     end
-    attribute \src "ls180.v:9099.2-9101.5"
+    attribute \src "ls180.v:9213.2-9215.5"
     switch \builder_csrbank5_dma_enable0_re
-      attribute \src "ls180.v:9099.6-9099.37"
+      attribute \src "ls180.v:9213.6-9213.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r
       case 
     end
-    attribute \src "ls180.v:9103.2-9105.5"
+    attribute \src "ls180.v:9217.2-9219.5"
     switch \builder_csrbank5_dma_loop0_re
-      attribute \src "ls180.v:9103.6-9103.35"
+      attribute \src "ls180.v:9217.6-9217.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r
       case 
     end
-    attribute \src "ls180.v:9108.2-9210.5"
+    attribute \src "ls180.v:9222.2-9324.5"
     switch \builder_csrbank6_sel
-      attribute \src "ls180.v:9108.6-9108.26"
+      attribute \src "ls180.v:9222.6-9222.26"
       case 1'1
-        attribute \src "ls180.v:9109.3-9209.10"
+        attribute \src "ls180.v:9223.3-9323.10"
         switch \builder_interface6_bank_bus_adr [5:0]
           attribute \src "ls180.v:0.0-0.0"
           case 6'000000
@@ -278621,109 +280285,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9211.2-9213.5"
+    attribute \src "ls180.v:9325.2-9327.5"
     switch \builder_csrbank6_cmd_argument3_re
-      attribute \src "ls180.v:9211.6-9211.39"
+      attribute \src "ls180.v:9325.6-9325.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r
       case 
     end
-    attribute \src "ls180.v:9214.2-9216.5"
+    attribute \src "ls180.v:9328.2-9330.5"
     switch \builder_csrbank6_cmd_argument2_re
-      attribute \src "ls180.v:9214.6-9214.39"
+      attribute \src "ls180.v:9328.6-9328.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r
       case 
     end
-    attribute \src "ls180.v:9217.2-9219.5"
+    attribute \src "ls180.v:9331.2-9333.5"
     switch \builder_csrbank6_cmd_argument1_re
-      attribute \src "ls180.v:9217.6-9217.39"
+      attribute \src "ls180.v:9331.6-9331.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r
       case 
     end
-    attribute \src "ls180.v:9220.2-9222.5"
+    attribute \src "ls180.v:9334.2-9336.5"
     switch \builder_csrbank6_cmd_argument0_re
-      attribute \src "ls180.v:9220.6-9220.39"
+      attribute \src "ls180.v:9334.6-9334.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r
       case 
     end
-    attribute \src "ls180.v:9224.2-9226.5"
+    attribute \src "ls180.v:9338.2-9340.5"
     switch \builder_csrbank6_cmd_command3_re
-      attribute \src "ls180.v:9224.6-9224.38"
+      attribute \src "ls180.v:9338.6-9338.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r
       case 
     end
-    attribute \src "ls180.v:9227.2-9229.5"
+    attribute \src "ls180.v:9341.2-9343.5"
     switch \builder_csrbank6_cmd_command2_re
-      attribute \src "ls180.v:9227.6-9227.38"
+      attribute \src "ls180.v:9341.6-9341.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r
       case 
     end
-    attribute \src "ls180.v:9230.2-9232.5"
+    attribute \src "ls180.v:9344.2-9346.5"
     switch \builder_csrbank6_cmd_command1_re
-      attribute \src "ls180.v:9230.6-9230.38"
+      attribute \src "ls180.v:9344.6-9344.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r
       case 
     end
-    attribute \src "ls180.v:9233.2-9235.5"
+    attribute \src "ls180.v:9347.2-9349.5"
     switch \builder_csrbank6_cmd_command0_re
-      attribute \src "ls180.v:9233.6-9233.38"
+      attribute \src "ls180.v:9347.6-9347.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r
       case 
     end
-    attribute \src "ls180.v:9237.2-9239.5"
+    attribute \src "ls180.v:9351.2-9353.5"
     switch \builder_csrbank6_block_length1_re
-      attribute \src "ls180.v:9237.6-9237.39"
+      attribute \src "ls180.v:9351.6-9351.39"
       case 1'1
         assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r
       case 
     end
-    attribute \src "ls180.v:9240.2-9242.5"
+    attribute \src "ls180.v:9354.2-9356.5"
     switch \builder_csrbank6_block_length0_re
-      attribute \src "ls180.v:9240.6-9240.39"
+      attribute \src "ls180.v:9354.6-9354.39"
       case 1'1
         assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r
       case 
     end
-    attribute \src "ls180.v:9244.2-9246.5"
+    attribute \src "ls180.v:9358.2-9360.5"
     switch \builder_csrbank6_block_count3_re
-      attribute \src "ls180.v:9244.6-9244.38"
+      attribute \src "ls180.v:9358.6-9358.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r
       case 
     end
-    attribute \src "ls180.v:9247.2-9249.5"
+    attribute \src "ls180.v:9361.2-9363.5"
     switch \builder_csrbank6_block_count2_re
-      attribute \src "ls180.v:9247.6-9247.38"
+      attribute \src "ls180.v:9361.6-9361.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r
       case 
     end
-    attribute \src "ls180.v:9250.2-9252.5"
+    attribute \src "ls180.v:9364.2-9366.5"
     switch \builder_csrbank6_block_count1_re
-      attribute \src "ls180.v:9250.6-9250.38"
+      attribute \src "ls180.v:9364.6-9364.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r
       case 
     end
-    attribute \src "ls180.v:9253.2-9255.5"
+    attribute \src "ls180.v:9367.2-9369.5"
     switch \builder_csrbank6_block_count0_re
-      attribute \src "ls180.v:9253.6-9253.38"
+      attribute \src "ls180.v:9367.6-9367.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r
       case 
     end
-    attribute \src "ls180.v:9258.2-9318.5"
+    attribute \src "ls180.v:9372.2-9432.5"
     switch \builder_csrbank7_sel
-      attribute \src "ls180.v:9258.6-9258.26"
+      attribute \src "ls180.v:9372.6-9372.26"
       case 1'1
-        attribute \src "ls180.v:9259.3-9317.10"
+        attribute \src "ls180.v:9373.3-9431.10"
         switch \builder_interface7_bank_bus_adr [4:0]
           attribute \src "ls180.v:0.0-0.0"
           case 5'00000
@@ -278786,109 +280450,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9319.2-9321.5"
+    attribute \src "ls180.v:9433.2-9435.5"
     switch \builder_csrbank7_dma_base7_re
-      attribute \src "ls180.v:9319.6-9319.35"
+      attribute \src "ls180.v:9433.6-9433.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r
       case 
     end
-    attribute \src "ls180.v:9322.2-9324.5"
+    attribute \src "ls180.v:9436.2-9438.5"
     switch \builder_csrbank7_dma_base6_re
-      attribute \src "ls180.v:9322.6-9322.35"
+      attribute \src "ls180.v:9436.6-9436.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r
       case 
     end
-    attribute \src "ls180.v:9325.2-9327.5"
+    attribute \src "ls180.v:9439.2-9441.5"
     switch \builder_csrbank7_dma_base5_re
-      attribute \src "ls180.v:9325.6-9325.35"
+      attribute \src "ls180.v:9439.6-9439.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r
       case 
     end
-    attribute \src "ls180.v:9328.2-9330.5"
+    attribute \src "ls180.v:9442.2-9444.5"
     switch \builder_csrbank7_dma_base4_re
-      attribute \src "ls180.v:9328.6-9328.35"
+      attribute \src "ls180.v:9442.6-9442.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r
       case 
     end
-    attribute \src "ls180.v:9331.2-9333.5"
+    attribute \src "ls180.v:9445.2-9447.5"
     switch \builder_csrbank7_dma_base3_re
-      attribute \src "ls180.v:9331.6-9331.35"
+      attribute \src "ls180.v:9445.6-9445.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r
       case 
     end
-    attribute \src "ls180.v:9334.2-9336.5"
+    attribute \src "ls180.v:9448.2-9450.5"
     switch \builder_csrbank7_dma_base2_re
-      attribute \src "ls180.v:9334.6-9334.35"
+      attribute \src "ls180.v:9448.6-9448.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r
       case 
     end
-    attribute \src "ls180.v:9337.2-9339.5"
+    attribute \src "ls180.v:9451.2-9453.5"
     switch \builder_csrbank7_dma_base1_re
-      attribute \src "ls180.v:9337.6-9337.35"
+      attribute \src "ls180.v:9451.6-9451.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r
       case 
     end
-    attribute \src "ls180.v:9340.2-9342.5"
+    attribute \src "ls180.v:9454.2-9456.5"
     switch \builder_csrbank7_dma_base0_re
-      attribute \src "ls180.v:9340.6-9340.35"
+      attribute \src "ls180.v:9454.6-9454.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r
       case 
     end
-    attribute \src "ls180.v:9344.2-9346.5"
+    attribute \src "ls180.v:9458.2-9460.5"
     switch \builder_csrbank7_dma_length3_re
-      attribute \src "ls180.v:9344.6-9344.37"
+      attribute \src "ls180.v:9458.6-9458.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r
       case 
     end
-    attribute \src "ls180.v:9347.2-9349.5"
+    attribute \src "ls180.v:9461.2-9463.5"
     switch \builder_csrbank7_dma_length2_re
-      attribute \src "ls180.v:9347.6-9347.37"
+      attribute \src "ls180.v:9461.6-9461.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r
       case 
     end
-    attribute \src "ls180.v:9350.2-9352.5"
+    attribute \src "ls180.v:9464.2-9466.5"
     switch \builder_csrbank7_dma_length1_re
-      attribute \src "ls180.v:9350.6-9350.37"
+      attribute \src "ls180.v:9464.6-9464.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r
       case 
     end
-    attribute \src "ls180.v:9353.2-9355.5"
+    attribute \src "ls180.v:9467.2-9469.5"
     switch \builder_csrbank7_dma_length0_re
-      attribute \src "ls180.v:9353.6-9353.37"
+      attribute \src "ls180.v:9467.6-9467.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r
       case 
     end
-    attribute \src "ls180.v:9357.2-9359.5"
+    attribute \src "ls180.v:9471.2-9473.5"
     switch \builder_csrbank7_dma_enable0_re
-      attribute \src "ls180.v:9357.6-9357.37"
+      attribute \src "ls180.v:9471.6-9471.37"
       case 1'1
         assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r
       case 
     end
-    attribute \src "ls180.v:9361.2-9363.5"
+    attribute \src "ls180.v:9475.2-9477.5"
     switch \builder_csrbank7_dma_loop0_re
-      attribute \src "ls180.v:9361.6-9361.35"
+      attribute \src "ls180.v:9475.6-9475.35"
       case 1'1
         assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r
       case 
     end
-    attribute \src "ls180.v:9366.2-9381.5"
+    attribute \src "ls180.v:9480.2-9495.5"
     switch \builder_csrbank8_sel
-      attribute \src "ls180.v:9366.6-9366.26"
+      attribute \src "ls180.v:9480.6-9480.26"
       case 1'1
-        attribute \src "ls180.v:9367.3-9380.10"
+        attribute \src "ls180.v:9481.3-9494.10"
         switch \builder_interface8_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -278906,25 +280570,25 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9382.2-9384.5"
+    attribute \src "ls180.v:9496.2-9498.5"
     switch \builder_csrbank8_clocker_divider1_re
-      attribute \src "ls180.v:9382.6-9382.42"
+      attribute \src "ls180.v:9496.6-9496.42"
       case 1'1
         assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r
       case 
     end
-    attribute \src "ls180.v:9385.2-9387.5"
+    attribute \src "ls180.v:9499.2-9501.5"
     switch \builder_csrbank8_clocker_divider0_re
-      attribute \src "ls180.v:9385.6-9385.42"
+      attribute \src "ls180.v:9499.6-9499.42"
       case 1'1
         assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r
       case 
     end
-    attribute \src "ls180.v:9390.2-9423.5"
+    attribute \src "ls180.v:9504.2-9537.5"
     switch \builder_csrbank9_sel
-      attribute \src "ls180.v:9390.6-9390.26"
+      attribute \src "ls180.v:9504.6-9504.26"
       case 1'1
-        attribute \src "ls180.v:9391.3-9422.10"
+        attribute \src "ls180.v:9505.3-9536.10"
         switch \builder_interface9_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -278960,60 +280624,60 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9424.2-9426.5"
+    attribute \src "ls180.v:9538.2-9540.5"
     switch \builder_csrbank9_dfii_control0_re
-      attribute \src "ls180.v:9424.6-9424.39"
+      attribute \src "ls180.v:9538.6-9538.39"
       case 1'1
         assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r
       case 
     end
-    attribute \src "ls180.v:9428.2-9430.5"
+    attribute \src "ls180.v:9542.2-9544.5"
     switch \builder_csrbank9_dfii_pi0_command0_re
-      attribute \src "ls180.v:9428.6-9428.43"
+      attribute \src "ls180.v:9542.6-9542.43"
       case 1'1
         assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r
       case 
     end
-    attribute \src "ls180.v:9432.2-9434.5"
+    attribute \src "ls180.v:9546.2-9548.5"
     switch \builder_csrbank9_dfii_pi0_address1_re
-      attribute \src "ls180.v:9432.6-9432.43"
+      attribute \src "ls180.v:9546.6-9546.43"
       case 1'1
         assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r
       case 
     end
-    attribute \src "ls180.v:9435.2-9437.5"
+    attribute \src "ls180.v:9549.2-9551.5"
     switch \builder_csrbank9_dfii_pi0_address0_re
-      attribute \src "ls180.v:9435.6-9435.43"
+      attribute \src "ls180.v:9549.6-9549.43"
       case 1'1
         assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r
       case 
     end
-    attribute \src "ls180.v:9439.2-9441.5"
+    attribute \src "ls180.v:9553.2-9555.5"
     switch \builder_csrbank9_dfii_pi0_baddress0_re
-      attribute \src "ls180.v:9439.6-9439.44"
+      attribute \src "ls180.v:9553.6-9553.44"
       case 1'1
         assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r
       case 
     end
-    attribute \src "ls180.v:9443.2-9445.5"
+    attribute \src "ls180.v:9557.2-9559.5"
     switch \builder_csrbank9_dfii_pi0_wrdata1_re
-      attribute \src "ls180.v:9443.6-9443.42"
+      attribute \src "ls180.v:9557.6-9557.42"
       case 1'1
         assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r
       case 
     end
-    attribute \src "ls180.v:9446.2-9448.5"
+    attribute \src "ls180.v:9560.2-9562.5"
     switch \builder_csrbank9_dfii_pi0_wrdata0_re
-      attribute \src "ls180.v:9446.6-9446.42"
+      attribute \src "ls180.v:9560.6-9560.42"
       case 1'1
         assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r
       case 
     end
-    attribute \src "ls180.v:9451.2-9475.5"
+    attribute \src "ls180.v:9565.2-9589.5"
     switch \builder_csrbank10_sel
-      attribute \src "ls180.v:9451.6-9451.27"
+      attribute \src "ls180.v:9565.6-9565.27"
       case 1'1
-        attribute \src "ls180.v:9452.3-9474.10"
+        attribute \src "ls180.v:9566.3-9588.10"
         switch \builder_interface10_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -279040,46 +280704,46 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9476.2-9478.5"
+    attribute \src "ls180.v:9590.2-9592.5"
     switch \builder_csrbank10_control1_re
-      attribute \src "ls180.v:9476.6-9476.35"
+      attribute \src "ls180.v:9590.6-9590.35"
       case 1'1
         assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r
       case 
     end
-    attribute \src "ls180.v:9479.2-9481.5"
+    attribute \src "ls180.v:9593.2-9595.5"
     switch \builder_csrbank10_control0_re
-      attribute \src "ls180.v:9479.6-9479.35"
+      attribute \src "ls180.v:9593.6-9593.35"
       case 1'1
         assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r
       case 
     end
-    attribute \src "ls180.v:9483.2-9485.5"
+    attribute \src "ls180.v:9597.2-9599.5"
     switch \builder_csrbank10_mosi0_re
-      attribute \src "ls180.v:9483.6-9483.32"
+      attribute \src "ls180.v:9597.6-9597.32"
       case 1'1
         assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r
       case 
     end
-    attribute \src "ls180.v:9487.2-9489.5"
+    attribute \src "ls180.v:9601.2-9603.5"
     switch \builder_csrbank10_cs0_re
-      attribute \src "ls180.v:9487.6-9487.30"
+      attribute \src "ls180.v:9601.6-9601.30"
       case 1'1
         assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r
       case 
     end
-    attribute \src "ls180.v:9491.2-9493.5"
+    attribute \src "ls180.v:9605.2-9607.5"
     switch \builder_csrbank10_loopback0_re
-      attribute \src "ls180.v:9491.6-9491.36"
+      attribute \src "ls180.v:9605.6-9605.36"
       case 1'1
         assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r
       case 
     end
-    attribute \src "ls180.v:9496.2-9526.5"
+    attribute \src "ls180.v:9610.2-9640.5"
     switch \builder_csrbank11_sel
-      attribute \src "ls180.v:9496.6-9496.27"
+      attribute \src "ls180.v:9610.6-9610.27"
       case 1'1
-        attribute \src "ls180.v:9497.3-9525.10"
+        attribute \src "ls180.v:9611.3-9639.10"
         switch \builder_interface11_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -279112,60 +280776,60 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9527.2-9529.5"
+    attribute \src "ls180.v:9641.2-9643.5"
     switch \builder_csrbank11_control1_re
-      attribute \src "ls180.v:9527.6-9527.35"
+      attribute \src "ls180.v:9641.6-9641.35"
       case 1'1
         assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r
       case 
     end
-    attribute \src "ls180.v:9530.2-9532.5"
+    attribute \src "ls180.v:9644.2-9646.5"
     switch \builder_csrbank11_control0_re
-      attribute \src "ls180.v:9530.6-9530.35"
+      attribute \src "ls180.v:9644.6-9644.35"
       case 1'1
         assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r
       case 
     end
-    attribute \src "ls180.v:9534.2-9536.5"
+    attribute \src "ls180.v:9648.2-9650.5"
     switch \builder_csrbank11_mosi0_re
-      attribute \src "ls180.v:9534.6-9534.32"
+      attribute \src "ls180.v:9648.6-9648.32"
       case 1'1
         assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r
       case 
     end
-    attribute \src "ls180.v:9538.2-9540.5"
+    attribute \src "ls180.v:9652.2-9654.5"
     switch \builder_csrbank11_cs0_re
-      attribute \src "ls180.v:9538.6-9538.30"
+      attribute \src "ls180.v:9652.6-9652.30"
       case 1'1
         assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r
       case 
     end
-    attribute \src "ls180.v:9542.2-9544.5"
+    attribute \src "ls180.v:9656.2-9658.5"
     switch \builder_csrbank11_loopback0_re
-      attribute \src "ls180.v:9542.6-9542.36"
+      attribute \src "ls180.v:9656.6-9656.36"
       case 1'1
         assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r
       case 
     end
-    attribute \src "ls180.v:9546.2-9548.5"
+    attribute \src "ls180.v:9660.2-9662.5"
     switch \builder_csrbank11_clk_divider1_re
-      attribute \src "ls180.v:9546.6-9546.39"
+      attribute \src "ls180.v:9660.6-9660.39"
       case 1'1
         assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r
       case 
     end
-    attribute \src "ls180.v:9549.2-9551.5"
+    attribute \src "ls180.v:9663.2-9665.5"
     switch \builder_csrbank11_clk_divider0_re
-      attribute \src "ls180.v:9549.6-9549.39"
+      attribute \src "ls180.v:9663.6-9663.39"
       case 1'1
         assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r
       case 
     end
-    attribute \src "ls180.v:9554.2-9608.5"
+    attribute \src "ls180.v:9668.2-9722.5"
     switch \builder_csrbank12_sel
-      attribute \src "ls180.v:9554.6-9554.27"
+      attribute \src "ls180.v:9668.6-9668.27"
       case 1'1
-        attribute \src "ls180.v:9555.3-9607.10"
+        attribute \src "ls180.v:9669.3-9721.10"
         switch \builder_interface12_bank_bus_adr [4:0]
           attribute \src "ls180.v:0.0-0.0"
           case 5'00000
@@ -279222,88 +280886,88 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9609.2-9611.5"
+    attribute \src "ls180.v:9723.2-9725.5"
     switch \builder_csrbank12_load3_re
-      attribute \src "ls180.v:9609.6-9609.32"
+      attribute \src "ls180.v:9723.6-9723.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r
       case 
     end
-    attribute \src "ls180.v:9612.2-9614.5"
+    attribute \src "ls180.v:9726.2-9728.5"
     switch \builder_csrbank12_load2_re
-      attribute \src "ls180.v:9612.6-9612.32"
+      attribute \src "ls180.v:9726.6-9726.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r
       case 
     end
-    attribute \src "ls180.v:9615.2-9617.5"
+    attribute \src "ls180.v:9729.2-9731.5"
     switch \builder_csrbank12_load1_re
-      attribute \src "ls180.v:9615.6-9615.32"
+      attribute \src "ls180.v:9729.6-9729.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r
       case 
     end
-    attribute \src "ls180.v:9618.2-9620.5"
+    attribute \src "ls180.v:9732.2-9734.5"
     switch \builder_csrbank12_load0_re
-      attribute \src "ls180.v:9618.6-9618.32"
+      attribute \src "ls180.v:9732.6-9732.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r
       case 
     end
-    attribute \src "ls180.v:9622.2-9624.5"
+    attribute \src "ls180.v:9736.2-9738.5"
     switch \builder_csrbank12_reload3_re
-      attribute \src "ls180.v:9622.6-9622.34"
+      attribute \src "ls180.v:9736.6-9736.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r
       case 
     end
-    attribute \src "ls180.v:9625.2-9627.5"
+    attribute \src "ls180.v:9739.2-9741.5"
     switch \builder_csrbank12_reload2_re
-      attribute \src "ls180.v:9625.6-9625.34"
+      attribute \src "ls180.v:9739.6-9739.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r
       case 
     end
-    attribute \src "ls180.v:9628.2-9630.5"
+    attribute \src "ls180.v:9742.2-9744.5"
     switch \builder_csrbank12_reload1_re
-      attribute \src "ls180.v:9628.6-9628.34"
+      attribute \src "ls180.v:9742.6-9742.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r
       case 
     end
-    attribute \src "ls180.v:9631.2-9633.5"
+    attribute \src "ls180.v:9745.2-9747.5"
     switch \builder_csrbank12_reload0_re
-      attribute \src "ls180.v:9631.6-9631.34"
+      attribute \src "ls180.v:9745.6-9745.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r
       case 
     end
-    attribute \src "ls180.v:9635.2-9637.5"
+    attribute \src "ls180.v:9749.2-9751.5"
     switch \builder_csrbank12_en0_re
-      attribute \src "ls180.v:9635.6-9635.30"
+      attribute \src "ls180.v:9749.6-9749.30"
       case 1'1
         assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r
       case 
     end
-    attribute \src "ls180.v:9639.2-9641.5"
+    attribute \src "ls180.v:9753.2-9755.5"
     switch \builder_csrbank12_update_value0_re
-      attribute \src "ls180.v:9639.6-9639.40"
+      attribute \src "ls180.v:9753.6-9753.40"
       case 1'1
         assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r
       case 
     end
-    attribute \src "ls180.v:9643.2-9645.5"
+    attribute \src "ls180.v:9757.2-9759.5"
     switch \builder_csrbank12_ev_enable0_re
-      attribute \src "ls180.v:9643.6-9643.37"
+      attribute \src "ls180.v:9757.6-9757.37"
       case 1'1
         assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:9648.2-9675.5"
+    attribute \src "ls180.v:9762.2-9789.5"
     switch \builder_csrbank13_sel
-      attribute \src "ls180.v:9648.6-9648.27"
+      attribute \src "ls180.v:9762.6-9762.27"
       case 1'1
-        attribute \src "ls180.v:9649.3-9674.10"
+        attribute \src "ls180.v:9763.3-9788.10"
         switch \builder_interface13_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -279333,18 +280997,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9676.2-9678.5"
+    attribute \src "ls180.v:9790.2-9792.5"
     switch \builder_csrbank13_ev_enable0_re
-      attribute \src "ls180.v:9676.6-9676.37"
+      attribute \src "ls180.v:9790.6-9790.37"
       case 1'1
         assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:9681.2-9696.5"
+    attribute \src "ls180.v:9795.2-9810.5"
     switch \builder_csrbank14_sel
-      attribute \src "ls180.v:9681.6-9681.27"
+      attribute \src "ls180.v:9795.6-9795.27"
       case 1'1
-        attribute \src "ls180.v:9682.3-9695.10"
+        attribute \src "ls180.v:9796.3-9809.10"
         switch \builder_interface14_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -279362,51 +281026,51 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9697.2-9699.5"
+    attribute \src "ls180.v:9811.2-9813.5"
     switch \builder_csrbank14_tuning_word3_re
-      attribute \src "ls180.v:9697.6-9697.39"
+      attribute \src "ls180.v:9811.6-9811.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r
       case 
     end
-    attribute \src "ls180.v:9700.2-9702.5"
+    attribute \src "ls180.v:9814.2-9816.5"
     switch \builder_csrbank14_tuning_word2_re
-      attribute \src "ls180.v:9700.6-9700.39"
+      attribute \src "ls180.v:9814.6-9814.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r
       case 
     end
-    attribute \src "ls180.v:9703.2-9705.5"
+    attribute \src "ls180.v:9817.2-9819.5"
     switch \builder_csrbank14_tuning_word1_re
-      attribute \src "ls180.v:9703.6-9703.39"
+      attribute \src "ls180.v:9817.6-9817.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r
       case 
     end
-    attribute \src "ls180.v:9706.2-9708.5"
+    attribute \src "ls180.v:9820.2-9822.5"
     switch \builder_csrbank14_tuning_word0_re
-      attribute \src "ls180.v:9706.6-9706.39"
+      attribute \src "ls180.v:9820.6-9820.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r
       case 
     end
-    attribute \src "ls180.v:9710.2-10004.5"
+    attribute \src "ls180.v:9824.2-10121.5"
     switch \sys_rst_1
-      attribute \src "ls180.v:9710.6-9710.15"
+      attribute \src "ls180.v:9824.6-9824.15"
       case 1'1
         assign $0\main_libresocsim_reset_storage[0:0] 1'0
         assign $0\main_libresocsim_reset_re[0:0] 1'0
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
-        assign $0\spimaster_clk[0:0] 1'0
-        assign $0\spimaster_mosi[0:0] 1'0
-        assign $0\spimaster_cs_n[0:0] 1'0
-        assign $0\pwm[1:0] 2'00
         assign $0\uart_tx[0:0] 1'1
         assign $0\spisdcard_clk[0:0] 1'0
         assign $0\spisdcard_mosi[0:0] 1'0
         assign $0\spisdcard_cs_n[0:0] 1'0
+        assign $0\spimaster_clk[0:0] 1'0
+        assign $0\spimaster_mosi[0:0] 1'0
+        assign $0\spimaster_cs_n[0:0] 1'0
+        assign $0\pwm[1:0] 2'00
         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
@@ -279425,6 +281089,9 @@ module \ls180
         assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0
         assign $0\main_libresocsim_eventmanager_re[0:0] 1'0
         assign $0\main_libresocsim_value[31:0] 0
+        assign $0\main_interface0_ram_bus_ack[0:0] 1'0
+        assign $0\main_interface1_ram_bus_ack[0:0] 1'0
+        assign $0\main_interface2_ram_bus_ack[0:0] 1'0
         assign $0\main_dfi_p0_rddata_valid[0:0] 1'0
         assign $0\main_rddata_en[2:0] 3'000
         assign $0\main_sdram_storage[3:0] 4'0001
@@ -279684,20 +281351,20 @@ module \ls180
         assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
         assign $0\builder_libresocsim_we[0:0] 1'0
         assign $0\builder_grant[2:0] 3'000
-        assign $0\builder_slave_sel_r[4:0] 5'00000
+        assign $0\builder_slave_sel_r[7:0] 8'00000000
         assign $0\builder_count[19:0] 20'11110100001001000000
         assign $0\builder_state[1:0] 2'00
       case 
     end
     sync posedge \sys_clk_1
-      update \spimaster_clk $0\spimaster_clk[0:0]
-      update \spimaster_mosi $0\spimaster_mosi[0:0]
-      update \spimaster_cs_n $0\spimaster_cs_n[0:0]
-      update \pwm $0\pwm[1:0]
       update \uart_tx $0\uart_tx[0:0]
       update \spisdcard_clk $0\spisdcard_clk[0:0]
       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
+      update \spimaster_clk $0\spimaster_clk[0:0]
+      update \spimaster_mosi $0\spimaster_mosi[0:0]
+      update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+      update \pwm $0\pwm[1:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
@@ -279724,6 +281391,9 @@ module \ls180
       update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0]
       update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0]
       update \main_libresocsim_value $0\main_libresocsim_value[31:0]
+      update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0]
+      update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0]
+      update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0]
       update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0]
       update \main_rddata_en $0\main_rddata_en[2:0]
       update \main_sdram_storage $0\main_sdram_storage[3:0]
@@ -280050,7 +281720,7 @@ module \ls180
       update \builder_libresocsim_we $0\builder_libresocsim_we[0:0]
       update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0]
       update \builder_grant $0\builder_grant[2:0]
-      update \builder_slave_sel_r $0\builder_slave_sel_r[4:0]
+      update \builder_slave_sel_r $0\builder_slave_sel_r[7:0]
       update \builder_count $0\builder_count[19:0]
       update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0]
       update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0]
@@ -280103,790 +281773,806 @@ module \ls180
       update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0]
       update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
   end
-  attribute \src "ls180.v:744.5-744.49"
-  process $proc$ls180.v:744$3034
+  attribute \src "ls180.v:760.5-760.59"
+  process $proc$ls180.v:760$3156
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
+  end
+  attribute \src "ls180.v:762.5-762.59"
+  process $proc$ls180.v:762$3157
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
+  end
+  attribute \src "ls180.v:763.5-763.58"
+  process $proc$ls180.v:763$3158
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
+  end
+  attribute \src "ls180.v:764.5-764.64"
+  process $proc$ls180.v:764$3159
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
+  end
+  attribute \src "ls180.v:765.12-765.74"
+  process $proc$ls180.v:765$3160
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
+  end
+  attribute \src "ls180.v:766.12-766.47"
+  process $proc$ls180.v:766$3161
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
+  end
+  attribute \src "ls180.v:767.5-767.46"
+  process $proc$ls180.v:767$3162
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
+  end
+  attribute \src "ls180.v:769.5-769.44"
+  process $proc$ls180.v:769$3163
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
+  end
+  attribute \src "ls180.v:770.5-770.45"
+  process $proc$ls180.v:770$3164
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
+  end
+  attribute \src "ls180.v:771.5-771.54"
+  process $proc$ls180.v:771$3165
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
+  end
+  attribute \src "ls180.v:773.32-773.76"
+  process $proc$ls180.v:773$3166
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
+  end
+  attribute \src "ls180.v:774.11-774.55"
+  process $proc$ls180.v:774$3167
+    assign { } { }
+    assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
+    sync always
+    sync init
+      update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
+  end
+  attribute \src "ls180.v:776.32-776.75"
+  process $proc$ls180.v:776$3168
+    assign { } { }
+    assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:778.32-778.76"
+  process $proc$ls180.v:778$3169
+    assign { } { }
+    assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
+    sync always
+      update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:781.5-781.44"
+  process $proc$ls180.v:781$3170
+    assign { } { }
+    assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
+    sync always
+      update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:782.5-782.45"
+  process $proc$ls180.v:782$3171
+    assign { } { }
+    assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
+    sync always
+      update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:783.5-783.43"
+  process $proc$ls180.v:783$3172
+    assign { } { }
+    assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
+    sync always
+      update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:784.5-784.48"
+  process $proc$ls180.v:784$3173
+    assign { } { }
+    assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
+    sync always
+      update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:786.5-786.43"
+  process $proc$ls180.v:786$3174
+    assign { } { }
+    assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
+    sync always
+      update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:789.5-789.49"
+  process $proc$ls180.v:789$3175
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:745.5-745.49"
-  process $proc$ls180.v:745$3035
+  attribute \src "ls180.v:790.5-790.49"
+  process $proc$ls180.v:790$3176
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:746.5-746.48"
-  process $proc$ls180.v:746$3036
+  attribute \src "ls180.v:791.5-791.48"
+  process $proc$ls180.v:791$3177
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:750.11-750.46"
-  process $proc$ls180.v:750$3037
+  attribute \src "ls180.v:795.11-795.46"
+  process $proc$ls180.v:795$3178
     assign { } { }
     assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
     sync always
     sync init
       update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
   end
-  attribute \src "ls180.v:752.11-752.45"
-  process $proc$ls180.v:752$3038
+  attribute \src "ls180.v:797.11-797.45"
+  process $proc$ls180.v:797$3179
     assign { } { }
     assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
     sync always
     sync init
       update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
   end
-  attribute \src "ls180.v:754.5-754.44"
-  process $proc$ls180.v:754$3039
+  attribute \src "ls180.v:799.5-799.44"
+  process $proc$ls180.v:799$3180
     assign { } { }
     assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
   end
-  attribute \src "ls180.v:755.5-755.45"
-  process $proc$ls180.v:755$3040
+  attribute \src "ls180.v:800.5-800.45"
+  process $proc$ls180.v:800$3181
     assign { } { }
     assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
   end
-  attribute \src "ls180.v:757.5-757.48"
-  process $proc$ls180.v:757$3041
+  attribute \src "ls180.v:802.5-802.48"
+  process $proc$ls180.v:802$3182
     assign { } { }
     assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
   end
-  attribute \src "ls180.v:759.5-759.43"
-  process $proc$ls180.v:759$3042
+  attribute \src "ls180.v:804.5-804.43"
+  process $proc$ls180.v:804$3183
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:762.5-762.49"
-  process $proc$ls180.v:762$3043
+  attribute \src "ls180.v:807.5-807.49"
+  process $proc$ls180.v:807$3184
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:763.5-763.49"
-  process $proc$ls180.v:763$3044
+  attribute \src "ls180.v:808.5-808.49"
+  process $proc$ls180.v:808$3185
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:764.5-764.48"
-  process $proc$ls180.v:764$3045
+  attribute \src "ls180.v:809.5-809.48"
+  process $proc$ls180.v:809$3186
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:768.11-768.46"
-  process $proc$ls180.v:768$3046
+  attribute \src "ls180.v:81.5-81.46"
+  process $proc$ls180.v:81$2903
+    assign { } { }
+    assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
+  end
+  attribute \src "ls180.v:813.11-813.46"
+  process $proc$ls180.v:813$3187
     assign { } { }
     assign $1\main_sdram_choose_req_valids[3:0] 4'0000
     sync always
     sync init
       update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
   end
-  attribute \src "ls180.v:770.11-770.45"
-  process $proc$ls180.v:770$3047
+  attribute \src "ls180.v:815.11-815.45"
+  process $proc$ls180.v:815$3188
     assign { } { }
     assign $1\main_sdram_choose_req_grant[1:0] 2'00
     sync always
     sync init
       update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
   end
-  attribute \src "ls180.v:772.12-772.36"
-  process $proc$ls180.v:772$3048
+  attribute \src "ls180.v:817.12-817.36"
+  process $proc$ls180.v:817$3189
     assign { } { }
     assign $0\main_sdram_nop_a[12:0] 13'0000000000000
     sync always
       update \main_sdram_nop_a $0\main_sdram_nop_a[12:0]
     sync init
   end
-  attribute \src "ls180.v:773.11-773.35"
-  process $proc$ls180.v:773$3049
+  attribute \src "ls180.v:818.11-818.35"
+  process $proc$ls180.v:818$3190
     assign { } { }
     assign $0\main_sdram_nop_ba[1:0] 2'00
     sync always
       update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0]
     sync init
   end
-  attribute \src "ls180.v:774.11-774.40"
-  process $proc$ls180.v:774$3050
+  attribute \src "ls180.v:819.11-819.40"
+  process $proc$ls180.v:819$3191
     assign { } { }
     assign $1\main_sdram_steerer_sel[1:0] 2'00
     sync always
     sync init
       update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
   end
-  attribute \src "ls180.v:775.5-775.31"
-  process $proc$ls180.v:775$3051
+  attribute \src "ls180.v:820.5-820.31"
+  process $proc$ls180.v:820$3192
     assign { } { }
     assign $0\main_sdram_steerer0[0:0] 1'1
     sync always
       update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0]
     sync init
   end
-  attribute \src "ls180.v:776.5-776.31"
-  process $proc$ls180.v:776$3052
+  attribute \src "ls180.v:821.5-821.31"
+  process $proc$ls180.v:821$3193
     assign { } { }
     assign $0\main_sdram_steerer1[0:0] 1'1
     sync always
       update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0]
     sync init
   end
-  attribute \src "ls180.v:778.32-778.63"
-  process $proc$ls180.v:778$3053
+  attribute \src "ls180.v:823.32-823.63"
+  process $proc$ls180.v:823$3194
     assign { } { }
     assign $0\main_sdram_trrdcon_ready[0:0] 1'1
     sync always
       update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:780.32-780.63"
-  process $proc$ls180.v:780$3054
+  attribute \src "ls180.v:825.32-825.63"
+  process $proc$ls180.v:825$3195
     assign { } { }
     assign $0\main_sdram_tfawcon_ready[0:0] 1'1
     sync always
       update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:782.32-782.63"
-  process $proc$ls180.v:782$3055
+  attribute \src "ls180.v:827.32-827.63"
+  process $proc$ls180.v:827$3196
     assign { } { }
     assign $1\main_sdram_tccdcon_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
   end
-  attribute \src "ls180.v:783.5-783.36"
-  process $proc$ls180.v:783$3056
+  attribute \src "ls180.v:828.5-828.36"
+  process $proc$ls180.v:828$3197
     assign { } { }
     assign $1\main_sdram_tccdcon_count[0:0] 1'0
     sync always
     sync init
       update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
   end
-  attribute \src "ls180.v:785.32-785.63"
-  process $proc$ls180.v:785$3057
+  attribute \src "ls180.v:83.5-83.46"
+  process $proc$ls180.v:83$2904
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:830.32-830.63"
+  process $proc$ls180.v:830$3198
     assign { } { }
     assign $1\main_sdram_twtrcon_ready[0:0] 1'0
     sync always
     sync init
       update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
   end
-  attribute \src "ls180.v:786.11-786.42"
-  process $proc$ls180.v:786$3058
+  attribute \src "ls180.v:831.11-831.42"
+  process $proc$ls180.v:831$3199
     assign { } { }
     assign $1\main_sdram_twtrcon_count[2:0] 3'000
     sync always
     sync init
       update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
   end
-  attribute \src "ls180.v:789.5-789.26"
-  process $proc$ls180.v:789$3059
+  attribute \src "ls180.v:834.5-834.26"
+  process $proc$ls180.v:834$3200
     assign { } { }
     assign $1\main_sdram_en0[0:0] 1'0
     sync always
     sync init
       update \main_sdram_en0 $1\main_sdram_en0[0:0]
   end
-  attribute \src "ls180.v:791.11-791.34"
-  process $proc$ls180.v:791$3060
+  attribute \src "ls180.v:836.11-836.34"
+  process $proc$ls180.v:836$3201
     assign { } { }
     assign $1\main_sdram_time0[4:0] 5'00000
     sync always
     sync init
       update \main_sdram_time0 $1\main_sdram_time0[4:0]
   end
-  attribute \src "ls180.v:792.5-792.26"
-  process $proc$ls180.v:792$3061
+  attribute \src "ls180.v:837.5-837.26"
+  process $proc$ls180.v:837$3202
     assign { } { }
     assign $1\main_sdram_en1[0:0] 1'0
     sync always
     sync init
       update \main_sdram_en1 $1\main_sdram_en1[0:0]
   end
-  attribute \src "ls180.v:794.11-794.34"
-  process $proc$ls180.v:794$3062
+  attribute \src "ls180.v:839.11-839.34"
+  process $proc$ls180.v:839$3203
     assign { } { }
     assign $1\main_sdram_time1[3:0] 4'0000
     sync always
     sync init
       update \main_sdram_time1 $1\main_sdram_time1[3:0]
   end
-  attribute \src "ls180.v:81.5-81.46"
-  process $proc$ls180.v:81$2771
-    assign { } { }
-    assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
-    sync always
-    sync init
-      update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
-  end
-  attribute \src "ls180.v:815.5-815.29"
-  process $proc$ls180.v:815$3063
+  attribute \src "ls180.v:860.5-860.29"
+  process $proc$ls180.v:860$3204
     assign { } { }
     assign $1\main_wb_sdram_ack[0:0] 1'0
     sync always
     sync init
       update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
   end
-  attribute \src "ls180.v:819.5-819.29"
-  process $proc$ls180.v:819$3064
+  attribute \src "ls180.v:864.5-864.29"
+  process $proc$ls180.v:864$3205
     assign { } { }
     assign $0\main_wb_sdram_err[0:0] 1'0
     sync always
       update \main_wb_sdram_err $0\main_wb_sdram_err[0:0]
     sync init
   end
-  attribute \src "ls180.v:820.12-820.40"
-  process $proc$ls180.v:820$3065
+  attribute \src "ls180.v:865.12-865.40"
+  process $proc$ls180.v:865$3206
     assign { } { }
     assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
     sync always
     sync init
       update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
   end
-  attribute \src "ls180.v:821.12-821.42"
-  process $proc$ls180.v:821$3066
+  attribute \src "ls180.v:866.12-866.42"
+  process $proc$ls180.v:866$3207
     assign { } { }
     assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
   end
-  attribute \src "ls180.v:823.11-823.38"
-  process $proc$ls180.v:823$3067
+  attribute \src "ls180.v:868.11-868.38"
+  process $proc$ls180.v:868$3208
     assign { } { }
     assign $1\main_litedram_wb_sel[1:0] 2'00
     sync always
     sync init
       update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
   end
-  attribute \src "ls180.v:824.5-824.32"
-  process $proc$ls180.v:824$3068
+  attribute \src "ls180.v:869.5-869.32"
+  process $proc$ls180.v:869$3209
     assign { } { }
     assign $1\main_litedram_wb_cyc[0:0] 1'0
     sync always
     sync init
       update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
   end
-  attribute \src "ls180.v:825.5-825.32"
-  process $proc$ls180.v:825$3069
+  attribute \src "ls180.v:870.5-870.32"
+  process $proc$ls180.v:870$3210
     assign { } { }
     assign $1\main_litedram_wb_stb[0:0] 1'0
     sync always
     sync init
       update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0]
   end
-  attribute \src "ls180.v:827.5-827.31"
-  process $proc$ls180.v:827$3070
+  attribute \src "ls180.v:872.5-872.31"
+  process $proc$ls180.v:872$3211
     assign { } { }
     assign $1\main_litedram_wb_we[0:0] 1'0
     sync always
     sync init
       update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
   end
-  attribute \src "ls180.v:828.5-828.31"
-  process $proc$ls180.v:828$3071
+  attribute \src "ls180.v:873.5-873.31"
+  process $proc$ls180.v:873$3212
     assign { } { }
     assign $1\main_converter_skip[0:0] 1'0
     sync always
     sync init
       update \main_converter_skip $1\main_converter_skip[0:0]
   end
-  attribute \src "ls180.v:829.5-829.34"
-  process $proc$ls180.v:829$3072
+  attribute \src "ls180.v:874.5-874.34"
+  process $proc$ls180.v:874$3213
     assign { } { }
     assign $1\main_converter_counter[0:0] 1'0
     sync always
     sync init
       update \main_converter_counter $1\main_converter_counter[0:0]
   end
-  attribute \src "ls180.v:83.5-83.46"
-  process $proc$ls180.v:83$2772
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:831.12-831.40"
-  process $proc$ls180.v:831$3073
+  attribute \src "ls180.v:876.12-876.40"
+  process $proc$ls180.v:876$3214
     assign { } { }
     assign $1\main_converter_dat_r[31:0] 0
     sync always
     sync init
       update \main_converter_dat_r $1\main_converter_dat_r[31:0]
   end
-  attribute \src "ls180.v:832.5-832.29"
-  process $proc$ls180.v:832$3074
+  attribute \src "ls180.v:877.5-877.29"
+  process $proc$ls180.v:877$3215
     assign { } { }
     assign $1\main_cmd_consumed[0:0] 1'0
     sync always
     sync init
       update \main_cmd_consumed $1\main_cmd_consumed[0:0]
   end
-  attribute \src "ls180.v:833.5-833.31"
-  process $proc$ls180.v:833$3075
+  attribute \src "ls180.v:878.5-878.31"
+  process $proc$ls180.v:878$3216
     assign { } { }
     assign $1\main_wdata_consumed[0:0] 1'0
     sync always
     sync init
       update \main_wdata_consumed $1\main_wdata_consumed[0:0]
   end
-  attribute \src "ls180.v:837.12-837.47"
-  process $proc$ls180.v:837$3076
+  attribute \src "ls180.v:882.12-882.47"
+  process $proc$ls180.v:882$3217
     assign { } { }
     assign $1\main_uart_phy_storage[31:0] 9895604
     sync always
     sync init
       update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
   end
-  attribute \src "ls180.v:838.5-838.28"
-  process $proc$ls180.v:838$3077
+  attribute \src "ls180.v:883.5-883.28"
+  process $proc$ls180.v:883$3218
     assign { } { }
     assign $1\main_uart_phy_re[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_re $1\main_uart_phy_re[0:0]
   end
-  attribute \src "ls180.v:840.5-840.36"
-  process $proc$ls180.v:840$3078
+  attribute \src "ls180.v:885.5-885.36"
+  process $proc$ls180.v:885$3219
     assign { } { }
     assign $1\main_uart_phy_sink_ready[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
   end
-  attribute \src "ls180.v:844.5-844.39"
-  process $proc$ls180.v:844$3079
+  attribute \src "ls180.v:889.5-889.39"
+  process $proc$ls180.v:889$3220
     assign { } { }
     assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
   end
-  attribute \src "ls180.v:845.12-845.54"
-  process $proc$ls180.v:845$3080
+  attribute \src "ls180.v:890.12-890.54"
+  process $proc$ls180.v:890$3221
     assign { } { }
     assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
     sync always
     sync init
       update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
   end
-  attribute \src "ls180.v:846.11-846.38"
-  process $proc$ls180.v:846$3081
+  attribute \src "ls180.v:891.11-891.38"
+  process $proc$ls180.v:891$3222
     assign { } { }
     assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
     sync always
     sync init
       update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
   end
-  attribute \src "ls180.v:847.11-847.43"
-  process $proc$ls180.v:847$3082
+  attribute \src "ls180.v:892.11-892.43"
+  process $proc$ls180.v:892$3223
     assign { } { }
     assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
     sync always
     sync init
       update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
   end
-  attribute \src "ls180.v:848.5-848.33"
-  process $proc$ls180.v:848$3083
+  attribute \src "ls180.v:893.5-893.33"
+  process $proc$ls180.v:893$3224
     assign { } { }
     assign $1\main_uart_phy_tx_busy[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
   end
-  attribute \src "ls180.v:849.5-849.38"
-  process $proc$ls180.v:849$3084
+  attribute \src "ls180.v:894.5-894.38"
+  process $proc$ls180.v:894$3225
     assign { } { }
     assign $1\main_uart_phy_source_valid[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
   end
-  attribute \src "ls180.v:851.5-851.38"
-  process $proc$ls180.v:851$3085
+  attribute \src "ls180.v:896.5-896.38"
+  process $proc$ls180.v:896$3226
     assign { } { }
     assign $0\main_uart_phy_source_first[0:0] 1'0
     sync always
       update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:852.5-852.37"
-  process $proc$ls180.v:852$3086
+  attribute \src "ls180.v:897.5-897.37"
+  process $proc$ls180.v:897$3227
     assign { } { }
     assign $0\main_uart_phy_source_last[0:0] 1'0
     sync always
       update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:853.11-853.51"
-  process $proc$ls180.v:853$3087
+  attribute \src "ls180.v:898.11-898.51"
+  process $proc$ls180.v:898$3228
     assign { } { }
     assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:854.5-854.39"
-  process $proc$ls180.v:854$3088
+  attribute \src "ls180.v:899.5-899.39"
+  process $proc$ls180.v:899$3229
     assign { } { }
     assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
   end
-  attribute \src "ls180.v:855.12-855.54"
-  process $proc$ls180.v:855$3089
+  attribute \src "ls180.v:900.12-900.54"
+  process $proc$ls180.v:900$3230
     assign { } { }
     assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
     sync always
     sync init
       update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
   end
-  attribute \src "ls180.v:857.5-857.30"
-  process $proc$ls180.v:857$3090
+  attribute \src "ls180.v:902.5-902.30"
+  process $proc$ls180.v:902$3231
     assign { } { }
     assign $1\main_uart_phy_rx_r[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
   end
-  attribute \src "ls180.v:858.11-858.38"
-  process $proc$ls180.v:858$3091
+  attribute \src "ls180.v:903.11-903.38"
+  process $proc$ls180.v:903$3232
     assign { } { }
     assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
     sync always
     sync init
       update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
   end
-  attribute \src "ls180.v:859.11-859.43"
-  process $proc$ls180.v:859$3092
+  attribute \src "ls180.v:904.11-904.43"
+  process $proc$ls180.v:904$3233
     assign { } { }
     assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
     sync always
     sync init
       update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
   end
-  attribute \src "ls180.v:860.5-860.33"
-  process $proc$ls180.v:860$3093
+  attribute \src "ls180.v:905.5-905.33"
+  process $proc$ls180.v:905$3234
     assign { } { }
     assign $1\main_uart_phy_rx_busy[0:0] 1'0
     sync always
     sync init
       update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0]
   end
-  attribute \src "ls180.v:871.5-871.32"
-  process $proc$ls180.v:871$3094
+  attribute \src "ls180.v:916.5-916.32"
+  process $proc$ls180.v:916$3235
     assign { } { }
     assign $1\main_uart_tx_pending[0:0] 1'0
     sync always
     sync init
       update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
   end
-  attribute \src "ls180.v:873.5-873.30"
-  process $proc$ls180.v:873$3095
+  attribute \src "ls180.v:918.5-918.30"
+  process $proc$ls180.v:918$3236
     assign { } { }
     assign $1\main_uart_tx_clear[0:0] 1'0
     sync always
     sync init
       update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
   end
-  attribute \src "ls180.v:874.5-874.36"
-  process $proc$ls180.v:874$3096
+  attribute \src "ls180.v:919.5-919.36"
+  process $proc$ls180.v:919$3237
     assign { } { }
     assign $1\main_uart_tx_old_trigger[0:0] 1'0
     sync always
     sync init
       update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
   end
-  attribute \src "ls180.v:876.5-876.32"
-  process $proc$ls180.v:876$3097
+  attribute \src "ls180.v:921.5-921.32"
+  process $proc$ls180.v:921$3238
     assign { } { }
     assign $1\main_uart_rx_pending[0:0] 1'0
     sync always
     sync init
       update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
   end
-  attribute \src "ls180.v:878.5-878.30"
-  process $proc$ls180.v:878$3098
+  attribute \src "ls180.v:923.5-923.30"
+  process $proc$ls180.v:923$3239
     assign { } { }
     assign $1\main_uart_rx_clear[0:0] 1'0
     sync always
     sync init
       update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
   end
-  attribute \src "ls180.v:879.5-879.36"
-  process $proc$ls180.v:879$3099
+  attribute \src "ls180.v:924.5-924.36"
+  process $proc$ls180.v:924$3240
     assign { } { }
     assign $1\main_uart_rx_old_trigger[0:0] 1'0
     sync always
     sync init
       update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
   end
-  attribute \src "ls180.v:883.11-883.49"
-  process $proc$ls180.v:883$3100
+  attribute \src "ls180.v:928.11-928.49"
+  process $proc$ls180.v:928$3241
     assign { } { }
     assign $1\main_uart_eventmanager_status_w[1:0] 2'00
     sync always
     sync init
       update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
   end
-  attribute \src "ls180.v:887.11-887.50"
-  process $proc$ls180.v:887$3101
+  attribute \src "ls180.v:932.11-932.50"
+  process $proc$ls180.v:932$3242
     assign { } { }
     assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
     sync always
     sync init
       update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
   end
-  attribute \src "ls180.v:888.11-888.48"
-  process $proc$ls180.v:888$3102
+  attribute \src "ls180.v:933.11-933.48"
+  process $proc$ls180.v:933$3243
     assign { } { }
     assign $1\main_uart_eventmanager_storage[1:0] 2'00
     sync always
     sync init
       update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
   end
-  attribute \src "ls180.v:889.5-889.37"
-  process $proc$ls180.v:889$3103
+  attribute \src "ls180.v:934.5-934.37"
+  process $proc$ls180.v:934$3244
     assign { } { }
     assign $1\main_uart_eventmanager_re[0:0] 1'0
     sync always
     sync init
       update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
   end
-  attribute \src "ls180.v:906.5-906.40"
-  process $proc$ls180.v:906$3104
+  attribute \src "ls180.v:951.5-951.40"
+  process $proc$ls180.v:951$3245
     assign { } { }
     assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
     sync always
       update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:907.5-907.39"
-  process $proc$ls180.v:907$3105
+  attribute \src "ls180.v:952.5-952.39"
+  process $proc$ls180.v:952$3246
     assign { } { }
     assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
     sync always
       update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:915.5-915.38"
-  process $proc$ls180.v:915$3106
+  attribute \src "ls180.v:960.5-960.38"
+  process $proc$ls180.v:960$3247
     assign { } { }
     assign $1\main_uart_tx_fifo_readable[0:0] 1'0
     sync always
     sync init
       update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
   end
-  attribute \src "ls180.v:922.11-922.42"
-  process $proc$ls180.v:922$3107
+  attribute \src "ls180.v:967.11-967.42"
+  process $proc$ls180.v:967$3248
     assign { } { }
     assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
     sync always
     sync init
       update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
   end
-  attribute \src "ls180.v:923.5-923.37"
-  process $proc$ls180.v:923$3108
+  attribute \src "ls180.v:968.5-968.37"
+  process $proc$ls180.v:968$3249
     assign { } { }
     assign $0\main_uart_tx_fifo_replace[0:0] 1'0
     sync always
       update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:924.11-924.43"
-  process $proc$ls180.v:924$3109
+  attribute \src "ls180.v:969.11-969.43"
+  process $proc$ls180.v:969$3250
     assign { } { }
     assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
     sync always
     sync init
       update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
   end
-  attribute \src "ls180.v:925.11-925.43"
-  process $proc$ls180.v:925$3110
+  attribute \src "ls180.v:970.11-970.43"
+  process $proc$ls180.v:970$3251
     assign { } { }
     assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
     sync always
     sync init
       update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
   end
-  attribute \src "ls180.v:926.11-926.46"
-  process $proc$ls180.v:926$3111
+  attribute \src "ls180.v:971.11-971.46"
+  process $proc$ls180.v:971$3252
     assign { } { }
     assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
     sync always
     sync init
       update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:952.5-952.38"
-  process $proc$ls180.v:952$3112
+  attribute \src "ls180.v:997.5-997.38"
+  process $proc$ls180.v:997$3253
     assign { } { }
     assign $1\main_uart_rx_fifo_readable[0:0] 1'0
     sync always
     sync init
       update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
   end
-  attribute \src "ls180.v:959.11-959.42"
-  process $proc$ls180.v:959$3113
-    assign { } { }
-    assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
-    sync always
-    sync init
-      update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
-  end
-  attribute \src "ls180.v:960.5-960.37"
-  process $proc$ls180.v:960$3114
-    assign { } { }
-    assign $0\main_uart_rx_fifo_replace[0:0] 1'0
-    sync always
-      update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:961.11-961.43"
-  process $proc$ls180.v:961$3115
-    assign { } { }
-    assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
-    sync always
-    sync init
-      update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
-  end
-  attribute \src "ls180.v:962.11-962.43"
-  process $proc$ls180.v:962$3116
-    assign { } { }
-    assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
-    sync always
-    sync init
-      update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
-  end
-  attribute \src "ls180.v:963.11-963.46"
-  process $proc$ls180.v:963$3117
-    assign { } { }
-    assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
-    sync always
-    sync init
-      update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
-  end
-  attribute \src "ls180.v:978.5-978.27"
-  process $proc$ls180.v:978$3118
-    assign { } { }
-    assign $0\main_uart_reset[0:0] 1'0
-    sync always
-      update \main_uart_reset $0\main_uart_reset[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:979.12-979.40"
-  process $proc$ls180.v:979$3119
-    assign { } { }
-    assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
-  end
-  attribute \src "ls180.v:980.5-980.27"
-  process $proc$ls180.v:980$3120
-    assign { } { }
-    assign $1\main_gpio_oe_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
-  end
-  attribute \src "ls180.v:981.12-981.36"
-  process $proc$ls180.v:981$3121
-    assign { } { }
-    assign $1\main_gpio_status[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_gpio_status $1\main_gpio_status[15:0]
-  end
-  attribute \src "ls180.v:983.12-983.41"
-  process $proc$ls180.v:983$3122
-    assign { } { }
-    assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
-  end
-  attribute \src "ls180.v:984.5-984.28"
-  process $proc$ls180.v:984$3123
-    assign { } { }
-    assign $1\main_gpio_out_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_gpio_out_re $1\main_gpio_out_re[0:0]
-  end
-  attribute \src "ls180.v:990.5-990.32"
-  process $proc$ls180.v:990$3124
-    assign { } { }
-    assign $1\main_spimaster2_done[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster2_done $1\main_spimaster2_done[0:0]
-  end
-  attribute \src "ls180.v:991.5-991.31"
-  process $proc$ls180.v:991$3125
-    assign { } { }
-    assign $1\main_spimaster3_irq[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
-  end
-  attribute \src "ls180.v:993.11-993.38"
-  process $proc$ls180.v:993$3126
-    assign { } { }
-    assign $1\main_spimaster5_miso[7:0] 8'00000000
-    sync always
-    sync init
-      update \main_spimaster5_miso $1\main_spimaster5_miso[7:0]
-  end
-  attribute \src "ls180.v:996.12-996.47"
-  process $proc$ls180.v:996$3127
-    assign { } { }
-    assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
-    sync always
-      update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0]
-    sync init
-  end
-  attribute \src "ls180.v:997.5-997.33"
-  process $proc$ls180.v:997$3128
-    assign { } { }
-    assign $1\main_spimaster9_start[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster9_start $1\main_spimaster9_start[0:0]
-  end
-  attribute \src "ls180.v:999.12-999.44"
-  process $proc$ls180.v:999$3129
-    assign { } { }
-    assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
-  end
   connect \main_libresocsim_libresoc_reset \main_libresocsim_reset
   connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i
   connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o
@@ -280907,22 +282593,31 @@ module \ls180
   connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0
   connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0
   connect \main_libresocsim_bus_error \builder_error
-  connect \main_libresocsim_converter0_reset $not$ls180.v:2773$14_Y
+  connect \main_libresocsim_converter0_reset $not$ls180.v:2818$26_Y
   connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] }
-  connect \main_libresocsim_converter1_reset $not$ls180.v:2833$25_Y
+  connect \main_libresocsim_converter1_reset $not$ls180.v:2878$37_Y
   connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] }
-  connect \main_libresocsim_converter2_reset $not$ls180.v:2893$36_Y
+  connect \main_libresocsim_converter2_reset $not$ls180.v:2938$48_Y
   connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] }
   connect \main_libresocsim_reset \main_libresocsim_reset_re
   connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors
   connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0]
   connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r
   connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w
-  connect \main_libresocsim_zero_trigger $ne$ls180.v:2965$60_Y
+  connect \main_libresocsim_zero_trigger $ne$ls180.v:3010$72_Y
   connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status
   connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending
-  connect \main_libresocsim_irq $and$ls180.v:2974$63_Y
+  connect \main_libresocsim_irq $and$ls180.v:3019$75_Y
   connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger
+  connect \main_sram0_adr \main_interface0_ram_bus_adr [6:0]
+  connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r
+  connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w
+  connect \main_sram1_adr \main_interface1_ram_bus_adr [6:0]
+  connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r
+  connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w
+  connect \main_sram2_adr \main_interface2_ram_bus_adr [6:0]
+  connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r
+  connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w
   connect \sys_clk_1 \sys_clk
   connect \por_clk \sys_clk
   connect \sys_rst_1 \main_int_rst
@@ -280963,8 +282658,8 @@ module \ls180
   connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n
   connect \main_sdram_inti_p0_address \main_sdram_address_storage
   connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage
-  connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3088$70_Y
-  connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3089$71_Y
+  connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3163$121_Y
+  connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3164$122_Y
   connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage
   connect \main_sdram_inti_p0_wrdata_mask 2'00
   connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid
@@ -280995,14 +282690,14 @@ module \ls180
   connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock
   connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready
   connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid
-  connect \main_sdram_timer_wait $not$ls180.v:3120$72_Y
+  connect \main_sdram_timer_wait $not$ls180.v:3195$123_Y
   connect \main_sdram_postponer_req_i \main_sdram_timer_done0
   connect \main_sdram_wants_refresh \main_sdram_postponer_req_o
-  connect \main_sdram_timer_done1 $eq$ls180.v:3123$73_Y
+  connect \main_sdram_timer_done1 $eq$ls180.v:3198$124_Y
   connect \main_sdram_timer_done0 \main_sdram_timer_done1
   connect \main_sdram_timer_count0 \main_sdram_timer_count1
-  connect \main_sdram_sequencer_start1 $or$ls180.v:3126$75_Y
-  connect \main_sdram_sequencer_done0 $and$ls180.v:3127$77_Y
+  connect \main_sdram_sequencer_start1 $or$ls180.v:3201$126_Y
+  connect \main_sdram_sequencer_done0 $and$ls180.v:3202$128_Y
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid
   connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we
@@ -281013,13 +282708,13 @@ module \ls180
   connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
   connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
   connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
-  connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3169$79_Y
-  connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3170$80_Y
-  connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3171$81_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3244$130_Y
+  connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3245$131_Y
+  connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3246$132_Y
   connect \main_sdram_bankmachine0_cmd_payload_ba 2'00
-  connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3181$86_Y
-  connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3182$88_Y
-  connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3183$90_Y
+  connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3256$137_Y
+  connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3257$139_Y
+  connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3258$141_Y
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
@@ -281035,13 +282730,13 @@ module \ls180
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3215$98_Y
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3216$99_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3290$149_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3291$150_Y
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3219$100_Y
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3220$101_Y
-  connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3221$103_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3294$151_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3295$152_Y
+  connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3296$154_Y
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid
   connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we
@@ -281052,13 +282747,13 @@ module \ls180
   connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
   connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
   connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
-  connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3326$109_Y
-  connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3327$110_Y
-  connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3328$111_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3401$160_Y
+  connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3402$161_Y
+  connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3403$162_Y
   connect \main_sdram_bankmachine1_cmd_payload_ba 2'01
-  connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3338$116_Y
-  connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3339$118_Y
-  connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3340$120_Y
+  connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3413$167_Y
+  connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3414$169_Y
+  connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3415$171_Y
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
@@ -281074,13 +282769,13 @@ module \ls180
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3372$128_Y
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3373$129_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3447$179_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3448$180_Y
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3376$130_Y
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3377$131_Y
-  connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3378$133_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3451$181_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3452$182_Y
+  connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3453$184_Y
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid
   connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we
@@ -281091,13 +282786,13 @@ module \ls180
   connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
   connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
   connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
-  connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3483$139_Y
-  connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3484$140_Y
-  connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3485$141_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3558$190_Y
+  connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3559$191_Y
+  connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3560$192_Y
   connect \main_sdram_bankmachine2_cmd_payload_ba 2'10
-  connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3495$146_Y
-  connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3496$148_Y
-  connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3497$150_Y
+  connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3570$197_Y
+  connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3571$199_Y
+  connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3572$201_Y
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
@@ -281113,13 +282808,13 @@ module \ls180
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3529$158_Y
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3530$159_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3604$209_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3605$210_Y
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3533$160_Y
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3534$161_Y
-  connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3535$163_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3608$211_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3609$212_Y
+  connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3610$214_Y
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid
   connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we
@@ -281130,13 +282825,13 @@ module \ls180
   connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
   connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
   connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
-  connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3640$169_Y
-  connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3641$170_Y
-  connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3642$171_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3715$220_Y
+  connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3716$221_Y
+  connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3717$222_Y
   connect \main_sdram_bankmachine3_cmd_payload_ba 2'11
-  connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3652$176_Y
-  connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3653$178_Y
-  connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3654$180_Y
+  connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3727$227_Y
+  connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3728$229_Y
+  connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3729$231_Y
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
@@ -281152,32 +282847,32 @@ module \ls180
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3686$188_Y
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3687$189_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3761$239_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3762$240_Y
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3690$190_Y
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3691$191_Y
-  connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3692$193_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3765$241_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3766$242_Y
+  connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3767$244_Y
   connect \main_sdram_choose_req_want_cmds 1'1
-  connect \main_sdram_trrdcon_valid $and$ls180.v:3788$204_Y
-  connect \main_sdram_tfawcon_valid $and$ls180.v:3789$210_Y
-  connect \main_sdram_ras_allowed $and$ls180.v:3790$211_Y
-  connect \main_sdram_tccdcon_valid $and$ls180.v:3791$214_Y
+  connect \main_sdram_trrdcon_valid $and$ls180.v:3863$255_Y
+  connect \main_sdram_tfawcon_valid $and$ls180.v:3864$261_Y
+  connect \main_sdram_ras_allowed $and$ls180.v:3865$262_Y
+  connect \main_sdram_tccdcon_valid $and$ls180.v:3866$265_Y
   connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready
-  connect \main_sdram_twtrcon_valid $and$ls180.v:3793$216_Y
-  connect \main_sdram_read_available $or$ls180.v:3794$223_Y
-  connect \main_sdram_write_available $or$ls180.v:3795$230_Y
-  connect \main_sdram_max_time0 $eq$ls180.v:3796$231_Y
-  connect \main_sdram_max_time1 $eq$ls180.v:3797$232_Y
+  connect \main_sdram_twtrcon_valid $and$ls180.v:3868$267_Y
+  connect \main_sdram_read_available $or$ls180.v:3869$274_Y
+  connect \main_sdram_write_available $or$ls180.v:3870$281_Y
+  connect \main_sdram_max_time0 $eq$ls180.v:3871$282_Y
+  connect \main_sdram_max_time1 $eq$ls180.v:3872$283_Y
   connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid
   connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid
   connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid
   connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid
-  connect \main_sdram_go_to_refresh $and$ls180.v:3802$235_Y
+  connect \main_sdram_go_to_refresh $and$ls180.v:3877$286_Y
   connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata
   connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata
-  connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3805$236_Y
+  connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3880$287_Y
   connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids
   connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0
   connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1
@@ -281185,7 +282880,7 @@ module \ls180
   connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3
   connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4
   connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5
-  connect \main_sdram_choose_cmd_ce $or$ls180.v:3838$294_Y
+  connect \main_sdram_choose_cmd_ce $or$ls180.v:3913$345_Y
   connect \main_sdram_choose_req_request \main_sdram_choose_req_valids
   connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6
   connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7
@@ -281193,31 +282888,31 @@ module \ls180
   connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9
   connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10
   connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11
-  connect \main_sdram_choose_req_ce $or$ls180.v:3907$380_Y
+  connect \main_sdram_choose_req_ce $or$ls180.v:3982$431_Y
   connect \main_sdram_dfi_p0_reset_n 1'1
   connect \main_sdram_dfi_p0_cke \main_sdram_steerer0
   connect \main_sdram_dfi_p0_odt \main_sdram_steerer1
-  connect \builder_roundrobin0_request $and$ls180.v:3984$412_Y
-  connect \builder_roundrobin0_ce $and$ls180.v:3985$415_Y
+  connect \builder_roundrobin0_request $and$ls180.v:4059$463_Y
+  connect \builder_roundrobin0_ce $and$ls180.v:4060$466_Y
   connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12
   connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13
   connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14
-  connect \builder_roundrobin1_request $and$ls180.v:3989$428_Y
-  connect \builder_roundrobin1_ce $and$ls180.v:3990$431_Y
+  connect \builder_roundrobin1_request $and$ls180.v:4064$479_Y
+  connect \builder_roundrobin1_ce $and$ls180.v:4065$482_Y
   connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15
   connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16
   connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17
-  connect \builder_roundrobin2_request $and$ls180.v:3994$444_Y
-  connect \builder_roundrobin2_ce $and$ls180.v:3995$447_Y
+  connect \builder_roundrobin2_request $and$ls180.v:4069$495_Y
+  connect \builder_roundrobin2_ce $and$ls180.v:4070$498_Y
   connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18
   connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19
   connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20
-  connect \builder_roundrobin3_request $and$ls180.v:3999$460_Y
-  connect \builder_roundrobin3_ce $and$ls180.v:4000$463_Y
+  connect \builder_roundrobin3_request $and$ls180.v:4074$511_Y
+  connect \builder_roundrobin3_ce $and$ls180.v:4075$514_Y
   connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21
   connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22
   connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23
-  connect \main_port_cmd_ready $or$ls180.v:4004$527_Y
+  connect \main_port_cmd_ready $or$ls180.v:4079$578_Y
   connect \main_port_wdata_ready \builder_new_master_wdata_ready
   connect \main_port_rdata_valid \builder_new_master_rdata_valid3
   connect \main_port_rdata_payload_data \main_sdram_interface_rdata
@@ -281225,22 +282920,22 @@ module \ls180
   connect \builder_roundrobin1_grant 1'0
   connect \builder_roundrobin2_grant 1'0
   connect \builder_roundrobin3_grant 1'0
-  connect \main_converter_reset $not$ls180.v:4026$529_Y
+  connect \main_converter_reset $not$ls180.v:4101$580_Y
   connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] }
-  connect \main_port_cmd_payload_addr $sub$ls180.v:4086$540_Y [23:0]
+  connect \main_port_cmd_payload_addr $sub$ls180.v:4161$591_Y [23:0]
   connect \main_port_cmd_payload_we \main_litedram_wb_we
   connect \main_port_wdata_payload_data \main_litedram_wb_dat_w
   connect \main_port_wdata_payload_we \main_litedram_wb_sel
   connect \main_litedram_wb_dat_r \main_port_rdata_payload_data
-  connect \main_port_flush $not$ls180.v:4091$541_Y
-  connect \main_port_cmd_last $not$ls180.v:4092$542_Y
-  connect \main_port_cmd_valid $and$ls180.v:4093$545_Y
-  connect \main_port_wdata_valid $and$ls180.v:4094$549_Y
-  connect \main_port_rdata_ready $and$ls180.v:4095$552_Y
-  connect \main_litedram_wb_ack $and$ls180.v:4096$557_Y
-  connect \main_ack_cmd $or$ls180.v:4097$559_Y
-  connect \main_ack_wdata $or$ls180.v:4098$561_Y
-  connect \main_ack_rdata $and$ls180.v:4099$562_Y
+  connect \main_port_flush $not$ls180.v:4166$592_Y
+  connect \main_port_cmd_last $not$ls180.v:4167$593_Y
+  connect \main_port_cmd_valid $and$ls180.v:4168$596_Y
+  connect \main_port_wdata_valid $and$ls180.v:4169$600_Y
+  connect \main_port_rdata_ready $and$ls180.v:4170$603_Y
+  connect \main_litedram_wb_ack $and$ls180.v:4171$608_Y
+  connect \main_ack_cmd $or$ls180.v:4172$610_Y
+  connect \main_ack_wdata $or$ls180.v:4173$612_Y
+  connect \main_ack_rdata $and$ls180.v:4174$613_Y
   connect \main_uart_uart_sink_valid \main_uart_phy_source_valid
   connect \main_uart_phy_source_ready \main_uart_uart_sink_ready
   connect \main_uart_uart_sink_first \main_uart_phy_source_first
@@ -281253,25 +282948,25 @@ module \ls180
   connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data
   connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re
   connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r
-  connect \main_uart_txfull_status $not$ls180.v:4112$563_Y
-  connect \main_uart_txempty_status $not$ls180.v:4113$564_Y
+  connect \main_uart_txfull_status $not$ls180.v:4187$614_Y
+  connect \main_uart_txempty_status $not$ls180.v:4188$615_Y
   connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid
   connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready
   connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first
   connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last
   connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data
-  connect \main_uart_tx_trigger $not$ls180.v:4119$565_Y
+  connect \main_uart_tx_trigger $not$ls180.v:4194$616_Y
   connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid
   connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready
   connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first
   connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last
   connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data
-  connect \main_uart_rxempty_status $not$ls180.v:4125$566_Y
-  connect \main_uart_rxfull_status $not$ls180.v:4126$567_Y
+  connect \main_uart_rxempty_status $not$ls180.v:4200$617_Y
+  connect \main_uart_rxfull_status $not$ls180.v:4201$618_Y
   connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data
-  connect \main_uart_rx_fifo_source_ready $or$ls180.v:4128$569_Y
-  connect \main_uart_rx_trigger $not$ls180.v:4129$570_Y
-  connect \main_uart_irq $or$ls180.v:4152$579_Y
+  connect \main_uart_rx_fifo_source_ready $or$ls180.v:4203$620_Y
+  connect \main_uart_rx_trigger $not$ls180.v:4204$621_Y
+  connect \main_uart_irq $or$ls180.v:4227$630_Y
   connect \main_uart_tx_status \main_uart_tx_trigger
   connect \main_uart_rx_status \main_uart_rx_trigger
   connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data }
@@ -281286,16 +282981,16 @@ module \ls180
   connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last
   connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data
   connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready
-  connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4167$582_Y
-  connect \main_uart_tx_fifo_level1 $add$ls180.v:4168$583_Y
+  connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4242$633_Y
+  connect \main_uart_tx_fifo_level1 $add$ls180.v:4243$634_Y
   connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din
-  connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4178$587_Y
-  connect \main_uart_tx_fifo_do_read $and$ls180.v:4179$588_Y
+  connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4253$638_Y
+  connect \main_uart_tx_fifo_do_read $and$ls180.v:4254$639_Y
   connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume
   connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r
   connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read
-  connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4183$589_Y
-  connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4184$590_Y
+  connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4258$640_Y
+  connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4259$641_Y
   connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data }
   connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout
   connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable
@@ -281308,16 +283003,16 @@ module \ls180
   connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last
   connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data
   connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready
-  connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4197$593_Y
-  connect \main_uart_rx_fifo_level1 $add$ls180.v:4198$594_Y
+  connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4272$644_Y
+  connect \main_uart_rx_fifo_level1 $add$ls180.v:4273$645_Y
   connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din
-  connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4208$598_Y
-  connect \main_uart_rx_fifo_do_read $and$ls180.v:4209$599_Y
+  connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4283$649_Y
+  connect \main_uart_rx_fifo_do_read $and$ls180.v:4284$650_Y
   connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume
   connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r
   connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read
-  connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4213$600_Y
-  connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4214$601_Y
+  connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4288$651_Y
+  connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4289$652_Y
   connect \main_gpio_pads_i \gpio_i
   connect \gpio_o \main_gpio_pads_o
   connect \gpio_oe \main_gpio_pads_oe
@@ -281330,8 +283025,8 @@ module \ls180
   connect \main_spimaster18_status \main_spimaster5_miso
   connect \main_spimaster6_cs \main_spimaster21_storage
   connect \main_spimaster7_loopback \main_spimaster23_storage
-  connect \main_spimaster31_clk_rise $eq$ls180.v:4227$603_Y
-  connect \main_spimaster32_clk_fall $eq$ls180.v:4228$605_Y
+  connect \main_spimaster31_clk_rise $eq$ls180.v:4302$654_Y
+  connect \main_spimaster32_clk_fall $eq$ls180.v:4303$656_Y
   connect \main_spisdcard_start0 \main_spisdcard_start1
   connect \main_spisdcard_length0 \main_spisdcard_length1
   connect \main_spisdcard_mosi \main_spisdcard_mosi_storage
@@ -281339,19 +283034,19 @@ module \ls180
   connect \main_spisdcard_miso_status \main_spisdcard_miso
   connect \main_spisdcard_cs \main_spisdcard_cs_storage
   connect \main_spisdcard_loopback \main_spisdcard_loopback_storage
-  connect \main_spisdcard_clk_rise $eq$ls180.v:4285$611_Y
-  connect \main_spisdcard_clk_fall $eq$ls180.v:4286$613_Y
+  connect \main_spisdcard_clk_rise $eq$ls180.v:4360$662_Y
+  connect \main_spisdcard_clk_fall $eq$ls180.v:4361$664_Y
   connect \main_spisdcard_clk_divider0 \main_spimaster1_storage
   connect \i2c_scl \main_i2c_scl
   connect \i2c_sda_oe \main_i2c_oe
   connect \i2c_sda_o \main_i2c_sda0
   connect \main_i2c_sda1 \i2c_sda_i
   connect \main_sdphy_status 1'0
-  connect \main_sdphy_sdpads_clk $or$ls180.v:4342$621_Y
-  connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4343$625_Y
-  connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4344$629_Y
-  connect \main_sdphy_sdpads_data_oe $or$ls180.v:4345$633_Y
-  connect \main_sdphy_sdpads_data_o $or$ls180.v:4346$637_Y
+  connect \main_sdphy_sdpads_clk $or$ls180.v:4417$672_Y
+  connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4418$676_Y
+  connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4419$680_Y
+  connect \main_sdphy_sdpads_data_oe $or$ls180.v:4420$684_Y
+  connect \main_sdphy_sdpads_data_o $or$ls180.v:4421$688_Y
   connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce
   connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce
   connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce
@@ -281372,8 +283067,8 @@ module \ls180
   connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce
   connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
   connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i
-  connect \main_sdphy_clocker_stop $or$ls180.v:4367$638_Y
-  connect \main_sdphy_clocker_ce $and$ls180.v:4397$641_Y
+  connect \main_sdphy_clocker_stop $or$ls180.v:4442$689_Y
+  connect \main_sdphy_clocker_ce $and$ls180.v:4472$692_Y
   connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid
   connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready
   connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first
@@ -281385,8 +283080,8 @@ module \ls180
   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
-  connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4520$651_Y
-  connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4521$653_Y
+  connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4595$702_Y
+  connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4596$704_Y
   connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
   connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1
   connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready
@@ -281403,10 +283098,10 @@ module \ls180
   connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first
   connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last
   connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data
-  connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4538$655_Y
+  connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4613$706_Y
   connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all
-  connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4540$656_Y
-  connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4541$658_Y
+  connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4615$707_Y
+  connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4616$709_Y
   connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid
   connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready
   connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first
@@ -281418,8 +283113,8 @@ module \ls180
   connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i
   connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o
   connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
-  connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4647$673_Y
-  connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4648$674_Y
+  connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4722$724_Y
+  connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4723$725_Y
   connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
   connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1
   connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready
@@ -281436,10 +283131,10 @@ module \ls180
   connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first
   connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last
   connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data
-  connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4665$676_Y
+  connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4740$727_Y
   connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all
-  connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4667$677_Y
-  connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4668$679_Y
+  connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4742$728_Y
+  connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4743$730_Y
   connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid
   connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready
   connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first
@@ -281451,8 +283146,8 @@ module \ls180
   connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i
   connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o
   connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe
-  connect \main_sdphy_datar_datar_start $eq$ls180.v:4781$688_Y
-  connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4782$689_Y
+  connect \main_sdphy_datar_datar_start $eq$ls180.v:4856$739_Y
+  connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4857$740_Y
   connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i
   connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1
   connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready
@@ -281469,10 +283164,10 @@ module \ls180
   connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first
   connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last
   connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data
-  connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4799$691_Y
+  connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4874$742_Y
   connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all
-  connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4801$692_Y
-  connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4802$694_Y
+  connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4876$743_Y
+  connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4877$745_Y
   connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid
   connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready
   connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first
@@ -281486,88 +283181,88 @@ module \ls180
   connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0]
   connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5]
   connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done }
-  connect \main_sdcore_data_event_status { $not$ls180.v:4918$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
+  connect \main_sdcore_data_event_status { $not$ls180.v:4993$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
   connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage }
   connect \main_sdcore_crc7_inserter_clr 1'1
   connect \main_sdcore_crc7_inserter_enable 1'1
-  connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4922$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4922$710_Y }
-  connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4923$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4923$713_Y }
-  connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4924$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4924$716_Y }
-  connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4925$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4925$719_Y }
-  connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4926$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4926$722_Y }
-  connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4927$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4927$725_Y }
-  connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4928$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4928$728_Y }
-  connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4929$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4929$731_Y }
-  connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4930$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4930$734_Y }
-  connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4931$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4931$737_Y }
-  connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4932$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4932$740_Y }
-  connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4933$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4933$743_Y }
-  connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4934$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4934$746_Y }
-  connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4935$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4935$749_Y }
-  connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4936$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4936$752_Y }
-  connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4937$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4937$755_Y }
-  connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4938$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4938$758_Y }
-  connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4939$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4939$761_Y }
-  connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4940$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4940$764_Y }
-  connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4941$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4941$767_Y }
-  connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4942$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4942$770_Y }
-  connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4943$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4943$773_Y }
-  connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4944$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4944$776_Y }
-  connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4945$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4945$779_Y }
-  connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4946$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4946$782_Y }
-  connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4947$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4947$785_Y }
-  connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4948$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4948$788_Y }
-  connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4949$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4949$791_Y }
-  connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4950$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4950$794_Y }
-  connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4951$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4951$797_Y }
-  connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4952$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4952$800_Y }
-  connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4953$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4953$803_Y }
-  connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4954$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4954$806_Y }
-  connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4955$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4955$809_Y }
-  connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4956$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4956$812_Y }
-  connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4957$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4957$815_Y }
-  connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4958$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4958$818_Y }
-  connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4959$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4959$821_Y }
-  connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4960$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4960$824_Y }
-  connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4961$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4961$827_Y }
+  connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4997$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4997$761_Y }
+  connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4998$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4998$764_Y }
+  connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4999$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4999$767_Y }
+  connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5000$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5000$770_Y }
+  connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5001$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5001$773_Y }
+  connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5002$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5002$776_Y }
+  connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5003$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5003$779_Y }
+  connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5004$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5004$782_Y }
+  connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5005$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5005$785_Y }
+  connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5006$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5006$788_Y }
+  connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5007$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5007$791_Y }
+  connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5008$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5008$794_Y }
+  connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5009$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5009$797_Y }
+  connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5010$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5010$800_Y }
+  connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5011$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5011$803_Y }
+  connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5012$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5012$806_Y }
+  connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5013$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5013$809_Y }
+  connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5014$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5014$812_Y }
+  connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5015$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5015$815_Y }
+  connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5016$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5016$818_Y }
+  connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5017$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5017$821_Y }
+  connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5018$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5018$824_Y }
+  connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5019$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5019$827_Y }
+  connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5020$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5020$830_Y }
+  connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5021$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5021$833_Y }
+  connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5022$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5022$836_Y }
+  connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5023$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5023$839_Y }
+  connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5024$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5024$842_Y }
+  connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5025$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5025$845_Y }
+  connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5026$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5026$848_Y }
+  connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5027$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5027$851_Y }
+  connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5028$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5028$854_Y }
+  connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5029$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5029$857_Y }
+  connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5030$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5030$860_Y }
+  connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5031$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5031$863_Y }
+  connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5032$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5032$866_Y }
+  connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5033$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5033$869_Y }
+  connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5034$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5034$872_Y }
+  connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5035$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5035$875_Y }
+  connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5036$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5036$878_Y }
   connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] }
-  connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4971$832_Y
-  connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4972$833_Y
+  connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5046$883_Y
+  connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5047$884_Y
   connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] }
-  connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4974$835_Y
-  connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4975$836_Y
+  connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5049$886_Y
+  connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5050$887_Y
   connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] }
-  connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4977$838_Y
-  connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4978$839_Y
+  connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5052$889_Y
+  connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5053$890_Y
   connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] }
-  connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4980$841_Y
-  connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4981$842_Y
-  connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4982$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4982$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4982$843_Y }
-  connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4983$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4983$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4983$848_Y }
-  connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4992$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4992$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4992$854_Y }
-  connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4993$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4993$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4993$859_Y }
-  connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5002$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5002$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5002$865_Y }
-  connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5003$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5003$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5003$870_Y }
-  connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5012$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5012$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5012$876_Y }
-  connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5013$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5013$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5013$881_Y }
+  connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5055$892_Y
+  connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5056$893_Y
+  connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5057$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5057$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5057$894_Y }
+  connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5058$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5058$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5058$899_Y }
+  connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5067$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5067$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5067$905_Y }
+  connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5068$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5068$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5068$910_Y }
+  connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5077$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5077$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5077$916_Y }
+  connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5078$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5078$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5078$921_Y }
+  connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5087$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5087$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5087$927_Y }
+  connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5088$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5088$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5088$932_Y }
   connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] }
-  connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5109$901_Y
+  connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5184$952_Y
   connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] }
-  connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5119$904_Y
+  connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5194$955_Y
   connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] }
-  connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5129$907_Y
+  connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5204$958_Y
   connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] }
-  connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5139$910_Y
+  connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5214$961_Y
   connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val
   connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last
-  connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5164$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5164$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5164$918_Y }
-  connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5165$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5165$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5165$923_Y }
-  connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5174$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5174$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5174$929_Y }
-  connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5175$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5175$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5175$934_Y }
-  connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5184$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5184$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5184$940_Y }
-  connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5185$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5185$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5185$945_Y }
-  connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5194$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5194$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5194$951_Y }
-  connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5195$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5195$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5195$956_Y }
+  connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5239$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5239$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5239$969_Y }
+  connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5240$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5240$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5240$974_Y }
+  connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5249$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5249$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5249$980_Y }
+  connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5250$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5250$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5250$985_Y }
+  connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5259$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5259$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5259$991_Y }
+  connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5260$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5260$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5260$996_Y }
+  connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5269$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5269$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5269$1002_Y }
+  connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5270$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5270$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5270$1007_Y }
   connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0
   connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready
   connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first
@@ -281596,20 +283291,20 @@ module \ls180
   connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data
   connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready
   connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din
-  connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5431$990_Y
-  connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5432$991_Y
+  connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5506$1041_Y
+  connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5507$1042_Y
   connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume
   connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r
-  connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5435$992_Y
-  connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5436$993_Y
+  connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5510$1043_Y
+  connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5511$1044_Y
   connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid
   connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready
   connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first
   connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last
   connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data
-  connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5442$995_Y
+  connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5517$1046_Y
   connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all
-  connect \main_sdblock2mem_converter_load_part $and$ls180.v:5444$996_Y
+  connect \main_sdblock2mem_converter_load_part $and$ls180.v:5519$1047_Y
   connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1
   connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1
   connect \main_interface0_bus_we 1'1
@@ -281619,7 +283314,7 @@ module \ls180
   connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack
   connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2]
   connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] }
-  connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5454$997_Y
+  connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5529$1048_Y
   connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid
   connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready
   connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first
@@ -281638,18 +283333,18 @@ module \ls180
   connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2]
   connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] }
   connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset
-  connect \main_sdmem2block_dma_reset $not$ls180.v:5513$1004_Y
+  connect \main_sdmem2block_dma_reset $not$ls180.v:5588$1055_Y
   connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid
   connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1
   connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first
   connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last
   connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data
-  connect \main_sdmem2block_converter_first $eq$ls180.v:5594$1012_Y
-  connect \main_sdmem2block_converter_last $eq$ls180.v:5595$1013_Y
+  connect \main_sdmem2block_converter_first $eq$ls180.v:5669$1063_Y
+  connect \main_sdmem2block_converter_last $eq$ls180.v:5670$1064_Y
   connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid
-  connect \main_sdmem2block_converter_source_first $and$ls180.v:5597$1014_Y
-  connect \main_sdmem2block_converter_source_last $and$ls180.v:5598$1015_Y
-  connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5599$1016_Y
+  connect \main_sdmem2block_converter_source_first $and$ls180.v:5672$1065_Y
+  connect \main_sdmem2block_converter_source_last $and$ls180.v:5673$1066_Y
+  connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5674$1067_Y
   connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last
   connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data }
   connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout
@@ -281664,12 +283359,12 @@ module \ls180
   connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data
   connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready
   connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din
-  connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5639$1021_Y
-  connect \main_sdmem2block_fifo_do_read $and$ls180.v:5640$1022_Y
+  connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5714$1072_Y
+  connect \main_sdmem2block_fifo_do_read $and$ls180.v:5715$1073_Y
   connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume
   connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r
-  connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5643$1023_Y
-  connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5644$1024_Y
+  connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5718$1074_Y
+  connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5719$1075_Y
   connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0]
   connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25
   connect \builder_shared_sel \builder_comb_rhs_array_muxed26
@@ -281683,16 +283378,16 @@ module \ls180
   connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r
   connect \main_interface0_bus_dat_r \builder_shared_dat_r
   connect \main_interface1_bus_dat_r \builder_shared_dat_r
-  connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5695$1030_Y
-  connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5696$1032_Y
-  connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5697$1034_Y
-  connect \main_interface0_bus_ack $and$ls180.v:5698$1036_Y
-  connect \main_interface1_bus_ack $and$ls180.v:5699$1038_Y
-  connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5700$1040_Y
-  connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5701$1042_Y
-  connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5702$1044_Y
-  connect \main_interface0_bus_err $and$ls180.v:5703$1046_Y
-  connect \main_interface1_bus_err $and$ls180.v:5704$1048_Y
+  connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5770$1081_Y
+  connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5771$1083_Y
+  connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5772$1085_Y
+  connect \main_interface0_bus_ack $and$ls180.v:5773$1087_Y
+  connect \main_interface1_bus_ack $and$ls180.v:5774$1089_Y
+  connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5775$1091_Y
+  connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5776$1093_Y
+  connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5777$1095_Y
+  connect \main_interface0_bus_err $and$ls180.v:5778$1097_Y
+  connect \main_interface1_bus_err $and$ls180.v:5779$1099_Y
   connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc }
   connect \main_libresocsim_ram_bus_adr \builder_shared_adr
   connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w
@@ -281701,6 +283396,27 @@ module \ls180
   connect \main_libresocsim_ram_bus_we \builder_shared_we
   connect \main_libresocsim_ram_bus_cti \builder_shared_cti
   connect \main_libresocsim_ram_bus_bte \builder_shared_bte
+  connect \main_interface0_ram_bus_adr \builder_shared_adr
+  connect \main_interface0_ram_bus_dat_w \builder_shared_dat_w
+  connect \main_interface0_ram_bus_sel \builder_shared_sel
+  connect \main_interface0_ram_bus_stb \builder_shared_stb
+  connect \main_interface0_ram_bus_we \builder_shared_we
+  connect \main_interface0_ram_bus_cti \builder_shared_cti
+  connect \main_interface0_ram_bus_bte \builder_shared_bte
+  connect \main_interface1_ram_bus_adr \builder_shared_adr
+  connect \main_interface1_ram_bus_dat_w \builder_shared_dat_w
+  connect \main_interface1_ram_bus_sel \builder_shared_sel
+  connect \main_interface1_ram_bus_stb \builder_shared_stb
+  connect \main_interface1_ram_bus_we \builder_shared_we
+  connect \main_interface1_ram_bus_cti \builder_shared_cti
+  connect \main_interface1_ram_bus_bte \builder_shared_bte
+  connect \main_interface2_ram_bus_adr \builder_shared_adr
+  connect \main_interface2_ram_bus_dat_w \builder_shared_dat_w
+  connect \main_interface2_ram_bus_sel \builder_shared_sel
+  connect \main_interface2_ram_bus_stb \builder_shared_stb
+  connect \main_interface2_ram_bus_we \builder_shared_we
+  connect \main_interface2_ram_bus_cti \builder_shared_cti
+  connect \main_interface2_ram_bus_bte \builder_shared_bte
   connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr
   connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w
   connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel
@@ -281729,42 +283445,45 @@ module \ls180
   connect \builder_libresocsim_wishbone_we \builder_shared_we
   connect \builder_libresocsim_wishbone_cti \builder_shared_cti
   connect \builder_libresocsim_wishbone_bte \builder_shared_bte
-  connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5749$1055_Y
-  connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5750$1056_Y
-  connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5751$1057_Y
-  connect \main_wb_sdram_cyc $and$ls180.v:5752$1058_Y
-  connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5753$1059_Y
-  connect \builder_shared_err $or$ls180.v:5754$1063_Y
-  connect \builder_wait $and$ls180.v:5755$1066_Y
-  connect \builder_done $eq$ls180.v:5768$1081_Y
-  connect \builder_csrbank0_sel $eq$ls180.v:5769$1082_Y
+  connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5848$1109_Y
+  connect \main_interface0_ram_bus_cyc $and$ls180.v:5849$1110_Y
+  connect \main_interface1_ram_bus_cyc $and$ls180.v:5850$1111_Y
+  connect \main_interface2_ram_bus_cyc $and$ls180.v:5851$1112_Y
+  connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5852$1113_Y
+  connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5853$1114_Y
+  connect \main_wb_sdram_cyc $and$ls180.v:5854$1115_Y
+  connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5855$1116_Y
+  connect \builder_shared_err $or$ls180.v:5856$1123_Y
+  connect \builder_wait $and$ls180.v:5857$1126_Y
+  connect \builder_done $eq$ls180.v:5870$1150_Y
+  connect \builder_csrbank0_sel $eq$ls180.v:5871$1151_Y
   connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0]
-  connect \builder_csrbank0_reset0_re $and$ls180.v:5771$1085_Y
-  connect \builder_csrbank0_reset0_we $and$ls180.v:5772$1089_Y
+  connect \builder_csrbank0_reset0_re $and$ls180.v:5873$1154_Y
+  connect \builder_csrbank0_reset0_we $and$ls180.v:5874$1158_Y
   connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_scratch3_re $and$ls180.v:5774$1092_Y
-  connect \builder_csrbank0_scratch3_we $and$ls180.v:5775$1096_Y
+  connect \builder_csrbank0_scratch3_re $and$ls180.v:5876$1161_Y
+  connect \builder_csrbank0_scratch3_we $and$ls180.v:5877$1165_Y
   connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_scratch2_re $and$ls180.v:5777$1099_Y
-  connect \builder_csrbank0_scratch2_we $and$ls180.v:5778$1103_Y
+  connect \builder_csrbank0_scratch2_re $and$ls180.v:5879$1168_Y
+  connect \builder_csrbank0_scratch2_we $and$ls180.v:5880$1172_Y
   connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_scratch1_re $and$ls180.v:5780$1106_Y
-  connect \builder_csrbank0_scratch1_we $and$ls180.v:5781$1110_Y
+  connect \builder_csrbank0_scratch1_re $and$ls180.v:5882$1175_Y
+  connect \builder_csrbank0_scratch1_we $and$ls180.v:5883$1179_Y
   connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_scratch0_re $and$ls180.v:5783$1113_Y
-  connect \builder_csrbank0_scratch0_we $and$ls180.v:5784$1117_Y
+  connect \builder_csrbank0_scratch0_re $and$ls180.v:5885$1182_Y
+  connect \builder_csrbank0_scratch0_we $and$ls180.v:5886$1186_Y
   connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5786$1120_Y
-  connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5787$1124_Y
+  connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5888$1189_Y
+  connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5889$1193_Y
   connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5789$1127_Y
-  connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5790$1131_Y
+  connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5891$1196_Y
+  connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5892$1200_Y
   connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5792$1134_Y
-  connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5793$1138_Y
+  connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5894$1203_Y
+  connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5895$1207_Y
   connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w
-  connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5795$1141_Y
-  connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5796$1145_Y
+  connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5897$1210_Y
+  connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5898$1214_Y
   connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage
   connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24]
   connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16]
@@ -281775,25 +283494,25 @@ module \ls180
   connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8]
   connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0]
   connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we
-  connect \builder_csrbank1_sel $eq$ls180.v:5807$1146_Y
+  connect \builder_csrbank1_sel $eq$ls180.v:5909$1215_Y
   connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_oe1_re $and$ls180.v:5809$1149_Y
-  connect \builder_csrbank1_oe1_we $and$ls180.v:5810$1153_Y
+  connect \builder_csrbank1_oe1_re $and$ls180.v:5911$1218_Y
+  connect \builder_csrbank1_oe1_we $and$ls180.v:5912$1222_Y
   connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_oe0_re $and$ls180.v:5812$1156_Y
-  connect \builder_csrbank1_oe0_we $and$ls180.v:5813$1160_Y
+  connect \builder_csrbank1_oe0_re $and$ls180.v:5914$1225_Y
+  connect \builder_csrbank1_oe0_we $and$ls180.v:5915$1229_Y
   connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_in1_re $and$ls180.v:5815$1163_Y
-  connect \builder_csrbank1_in1_we $and$ls180.v:5816$1167_Y
+  connect \builder_csrbank1_in1_re $and$ls180.v:5917$1232_Y
+  connect \builder_csrbank1_in1_we $and$ls180.v:5918$1236_Y
   connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_in0_re $and$ls180.v:5818$1170_Y
-  connect \builder_csrbank1_in0_we $and$ls180.v:5819$1174_Y
+  connect \builder_csrbank1_in0_re $and$ls180.v:5920$1239_Y
+  connect \builder_csrbank1_in0_we $and$ls180.v:5921$1243_Y
   connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_out1_re $and$ls180.v:5821$1177_Y
-  connect \builder_csrbank1_out1_we $and$ls180.v:5822$1181_Y
+  connect \builder_csrbank1_out1_re $and$ls180.v:5923$1246_Y
+  connect \builder_csrbank1_out1_we $and$ls180.v:5924$1250_Y
   connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w
-  connect \builder_csrbank1_out0_re $and$ls180.v:5824$1184_Y
-  connect \builder_csrbank1_out0_we $and$ls180.v:5825$1188_Y
+  connect \builder_csrbank1_out0_re $and$ls180.v:5926$1253_Y
+  connect \builder_csrbank1_out0_we $and$ls180.v:5927$1257_Y
   connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8]
   connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0]
   connect \builder_csrbank1_in1_w \main_gpio_status [15:8]
@@ -281801,13 +283520,13 @@ module \ls180
   connect \main_gpio_we \builder_csrbank1_in0_we
   connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8]
   connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0]
-  connect \builder_csrbank2_sel $eq$ls180.v:5833$1189_Y
+  connect \builder_csrbank2_sel $eq$ls180.v:5935$1258_Y
   connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0]
-  connect \builder_csrbank2_w0_re $and$ls180.v:5835$1192_Y
-  connect \builder_csrbank2_w0_we $and$ls180.v:5836$1196_Y
+  connect \builder_csrbank2_w0_re $and$ls180.v:5937$1261_Y
+  connect \builder_csrbank2_w0_we $and$ls180.v:5938$1265_Y
   connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0]
-  connect \builder_csrbank2_r_re $and$ls180.v:5838$1199_Y
-  connect \builder_csrbank2_r_we $and$ls180.v:5839$1203_Y
+  connect \builder_csrbank2_r_re $and$ls180.v:5940$1268_Y
+  connect \builder_csrbank2_r_we $and$ls180.v:5941$1272_Y
   connect \main_i2c_scl \main_i2c_storage [0]
   connect \main_i2c_oe \main_i2c_storage [1]
   connect \main_i2c_sda0 \main_i2c_storage [2]
@@ -281815,34 +283534,34 @@ module \ls180
   connect \main_i2c_status \main_i2c_sda1
   connect \builder_csrbank2_r_w \main_i2c_status
   connect \main_i2c_we \builder_csrbank2_r_we
-  connect \builder_csrbank3_sel $eq$ls180.v:5847$1204_Y
+  connect \builder_csrbank3_sel $eq$ls180.v:5949$1273_Y
   connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0]
-  connect \builder_csrbank3_enable0_re $and$ls180.v:5849$1207_Y
-  connect \builder_csrbank3_enable0_we $and$ls180.v:5850$1211_Y
+  connect \builder_csrbank3_enable0_re $and$ls180.v:5951$1276_Y
+  connect \builder_csrbank3_enable0_we $and$ls180.v:5952$1280_Y
   connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_width3_re $and$ls180.v:5852$1214_Y
-  connect \builder_csrbank3_width3_we $and$ls180.v:5853$1218_Y
+  connect \builder_csrbank3_width3_re $and$ls180.v:5954$1283_Y
+  connect \builder_csrbank3_width3_we $and$ls180.v:5955$1287_Y
   connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_width2_re $and$ls180.v:5855$1221_Y
-  connect \builder_csrbank3_width2_we $and$ls180.v:5856$1225_Y
+  connect \builder_csrbank3_width2_re $and$ls180.v:5957$1290_Y
+  connect \builder_csrbank3_width2_we $and$ls180.v:5958$1294_Y
   connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_width1_re $and$ls180.v:5858$1228_Y
-  connect \builder_csrbank3_width1_we $and$ls180.v:5859$1232_Y
+  connect \builder_csrbank3_width1_re $and$ls180.v:5960$1297_Y
+  connect \builder_csrbank3_width1_we $and$ls180.v:5961$1301_Y
   connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_width0_re $and$ls180.v:5861$1235_Y
-  connect \builder_csrbank3_width0_we $and$ls180.v:5862$1239_Y
+  connect \builder_csrbank3_width0_re $and$ls180.v:5963$1304_Y
+  connect \builder_csrbank3_width0_we $and$ls180.v:5964$1308_Y
   connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_period3_re $and$ls180.v:5864$1242_Y
-  connect \builder_csrbank3_period3_we $and$ls180.v:5865$1246_Y
+  connect \builder_csrbank3_period3_re $and$ls180.v:5966$1311_Y
+  connect \builder_csrbank3_period3_we $and$ls180.v:5967$1315_Y
   connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_period2_re $and$ls180.v:5867$1249_Y
-  connect \builder_csrbank3_period2_we $and$ls180.v:5868$1253_Y
+  connect \builder_csrbank3_period2_re $and$ls180.v:5969$1318_Y
+  connect \builder_csrbank3_period2_we $and$ls180.v:5970$1322_Y
   connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_period1_re $and$ls180.v:5870$1256_Y
-  connect \builder_csrbank3_period1_we $and$ls180.v:5871$1260_Y
+  connect \builder_csrbank3_period1_re $and$ls180.v:5972$1325_Y
+  connect \builder_csrbank3_period1_we $and$ls180.v:5973$1329_Y
   connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w
-  connect \builder_csrbank3_period0_re $and$ls180.v:5873$1263_Y
-  connect \builder_csrbank3_period0_we $and$ls180.v:5874$1267_Y
+  connect \builder_csrbank3_period0_re $and$ls180.v:5975$1332_Y
+  connect \builder_csrbank3_period0_we $and$ls180.v:5976$1336_Y
   connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage
   connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24]
   connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16]
@@ -281852,34 +283571,34 @@ module \ls180
   connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16]
   connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8]
   connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0]
-  connect \builder_csrbank4_sel $eq$ls180.v:5884$1268_Y
+  connect \builder_csrbank4_sel $eq$ls180.v:5986$1337_Y
   connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0]
-  connect \builder_csrbank4_enable0_re $and$ls180.v:5886$1271_Y
-  connect \builder_csrbank4_enable0_we $and$ls180.v:5887$1275_Y
+  connect \builder_csrbank4_enable0_re $and$ls180.v:5988$1340_Y
+  connect \builder_csrbank4_enable0_we $and$ls180.v:5989$1344_Y
   connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_width3_re $and$ls180.v:5889$1278_Y
-  connect \builder_csrbank4_width3_we $and$ls180.v:5890$1282_Y
+  connect \builder_csrbank4_width3_re $and$ls180.v:5991$1347_Y
+  connect \builder_csrbank4_width3_we $and$ls180.v:5992$1351_Y
   connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_width2_re $and$ls180.v:5892$1285_Y
-  connect \builder_csrbank4_width2_we $and$ls180.v:5893$1289_Y
+  connect \builder_csrbank4_width2_re $and$ls180.v:5994$1354_Y
+  connect \builder_csrbank4_width2_we $and$ls180.v:5995$1358_Y
   connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_width1_re $and$ls180.v:5895$1292_Y
-  connect \builder_csrbank4_width1_we $and$ls180.v:5896$1296_Y
+  connect \builder_csrbank4_width1_re $and$ls180.v:5997$1361_Y
+  connect \builder_csrbank4_width1_we $and$ls180.v:5998$1365_Y
   connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_width0_re $and$ls180.v:5898$1299_Y
-  connect \builder_csrbank4_width0_we $and$ls180.v:5899$1303_Y
+  connect \builder_csrbank4_width0_re $and$ls180.v:6000$1368_Y
+  connect \builder_csrbank4_width0_we $and$ls180.v:6001$1372_Y
   connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_period3_re $and$ls180.v:5901$1306_Y
-  connect \builder_csrbank4_period3_we $and$ls180.v:5902$1310_Y
+  connect \builder_csrbank4_period3_re $and$ls180.v:6003$1375_Y
+  connect \builder_csrbank4_period3_we $and$ls180.v:6004$1379_Y
   connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_period2_re $and$ls180.v:5904$1313_Y
-  connect \builder_csrbank4_period2_we $and$ls180.v:5905$1317_Y
+  connect \builder_csrbank4_period2_re $and$ls180.v:6006$1382_Y
+  connect \builder_csrbank4_period2_we $and$ls180.v:6007$1386_Y
   connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_period1_re $and$ls180.v:5907$1320_Y
-  connect \builder_csrbank4_period1_we $and$ls180.v:5908$1324_Y
+  connect \builder_csrbank4_period1_re $and$ls180.v:6009$1389_Y
+  connect \builder_csrbank4_period1_we $and$ls180.v:6010$1393_Y
   connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w
-  connect \builder_csrbank4_period0_re $and$ls180.v:5910$1327_Y
-  connect \builder_csrbank4_period0_we $and$ls180.v:5911$1331_Y
+  connect \builder_csrbank4_period0_re $and$ls180.v:6012$1396_Y
+  connect \builder_csrbank4_period0_we $and$ls180.v:6013$1400_Y
   connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage
   connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24]
   connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16]
@@ -281889,52 +283608,52 @@ module \ls180
   connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16]
   connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8]
   connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0]
-  connect \builder_csrbank5_sel $eq$ls180.v:5921$1332_Y
+  connect \builder_csrbank5_sel $eq$ls180.v:6023$1401_Y
   connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base7_re $and$ls180.v:5923$1335_Y
-  connect \builder_csrbank5_dma_base7_we $and$ls180.v:5924$1339_Y
+  connect \builder_csrbank5_dma_base7_re $and$ls180.v:6025$1404_Y
+  connect \builder_csrbank5_dma_base7_we $and$ls180.v:6026$1408_Y
   connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base6_re $and$ls180.v:5926$1342_Y
-  connect \builder_csrbank5_dma_base6_we $and$ls180.v:5927$1346_Y
+  connect \builder_csrbank5_dma_base6_re $and$ls180.v:6028$1411_Y
+  connect \builder_csrbank5_dma_base6_we $and$ls180.v:6029$1415_Y
   connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base5_re $and$ls180.v:5929$1349_Y
-  connect \builder_csrbank5_dma_base5_we $and$ls180.v:5930$1353_Y
+  connect \builder_csrbank5_dma_base5_re $and$ls180.v:6031$1418_Y
+  connect \builder_csrbank5_dma_base5_we $and$ls180.v:6032$1422_Y
   connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base4_re $and$ls180.v:5932$1356_Y
-  connect \builder_csrbank5_dma_base4_we $and$ls180.v:5933$1360_Y
+  connect \builder_csrbank5_dma_base4_re $and$ls180.v:6034$1425_Y
+  connect \builder_csrbank5_dma_base4_we $and$ls180.v:6035$1429_Y
   connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base3_re $and$ls180.v:5935$1363_Y
-  connect \builder_csrbank5_dma_base3_we $and$ls180.v:5936$1367_Y
+  connect \builder_csrbank5_dma_base3_re $and$ls180.v:6037$1432_Y
+  connect \builder_csrbank5_dma_base3_we $and$ls180.v:6038$1436_Y
   connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base2_re $and$ls180.v:5938$1370_Y
-  connect \builder_csrbank5_dma_base2_we $and$ls180.v:5939$1374_Y
+  connect \builder_csrbank5_dma_base2_re $and$ls180.v:6040$1439_Y
+  connect \builder_csrbank5_dma_base2_we $and$ls180.v:6041$1443_Y
   connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base1_re $and$ls180.v:5941$1377_Y
-  connect \builder_csrbank5_dma_base1_we $and$ls180.v:5942$1381_Y
+  connect \builder_csrbank5_dma_base1_re $and$ls180.v:6043$1446_Y
+  connect \builder_csrbank5_dma_base1_we $and$ls180.v:6044$1450_Y
   connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_base0_re $and$ls180.v:5944$1384_Y
-  connect \builder_csrbank5_dma_base0_we $and$ls180.v:5945$1388_Y
+  connect \builder_csrbank5_dma_base0_re $and$ls180.v:6046$1453_Y
+  connect \builder_csrbank5_dma_base0_we $and$ls180.v:6047$1457_Y
   connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_length3_re $and$ls180.v:5947$1391_Y
-  connect \builder_csrbank5_dma_length3_we $and$ls180.v:5948$1395_Y
+  connect \builder_csrbank5_dma_length3_re $and$ls180.v:6049$1460_Y
+  connect \builder_csrbank5_dma_length3_we $and$ls180.v:6050$1464_Y
   connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_length2_re $and$ls180.v:5950$1398_Y
-  connect \builder_csrbank5_dma_length2_we $and$ls180.v:5951$1402_Y
+  connect \builder_csrbank5_dma_length2_re $and$ls180.v:6052$1467_Y
+  connect \builder_csrbank5_dma_length2_we $and$ls180.v:6053$1471_Y
   connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_length1_re $and$ls180.v:5953$1405_Y
-  connect \builder_csrbank5_dma_length1_we $and$ls180.v:5954$1409_Y
+  connect \builder_csrbank5_dma_length1_re $and$ls180.v:6055$1474_Y
+  connect \builder_csrbank5_dma_length1_we $and$ls180.v:6056$1478_Y
   connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w
-  connect \builder_csrbank5_dma_length0_re $and$ls180.v:5956$1412_Y
-  connect \builder_csrbank5_dma_length0_we $and$ls180.v:5957$1416_Y
+  connect \builder_csrbank5_dma_length0_re $and$ls180.v:6058$1481_Y
+  connect \builder_csrbank5_dma_length0_we $and$ls180.v:6059$1485_Y
   connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0]
-  connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5959$1419_Y
-  connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5960$1423_Y
+  connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6061$1488_Y
+  connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6062$1492_Y
   connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0]
-  connect \builder_csrbank5_dma_done_re $and$ls180.v:5962$1426_Y
-  connect \builder_csrbank5_dma_done_we $and$ls180.v:5963$1430_Y
+  connect \builder_csrbank5_dma_done_re $and$ls180.v:6064$1495_Y
+  connect \builder_csrbank5_dma_done_we $and$ls180.v:6065$1499_Y
   connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0]
-  connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5965$1433_Y
-  connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5966$1437_Y
+  connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6067$1502_Y
+  connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6068$1506_Y
   connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56]
   connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48]
   connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40]
@@ -281951,106 +283670,106 @@ module \ls180
   connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status
   connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we
   connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage
-  connect \builder_csrbank6_sel $eq$ls180.v:5983$1438_Y
+  connect \builder_csrbank6_sel $eq$ls180.v:6085$1507_Y
   connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5985$1441_Y
-  connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5986$1445_Y
+  connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6087$1510_Y
+  connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6088$1514_Y
   connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5988$1448_Y
-  connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5989$1452_Y
+  connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6090$1517_Y
+  connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6091$1521_Y
   connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5991$1455_Y
-  connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5992$1459_Y
+  connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6093$1524_Y
+  connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6094$1528_Y
   connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5994$1462_Y
-  connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5995$1466_Y
+  connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6096$1531_Y
+  connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6097$1535_Y
   connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5997$1469_Y
-  connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5998$1473_Y
+  connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6099$1538_Y
+  connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6100$1542_Y
   connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6000$1476_Y
-  connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6001$1480_Y
+  connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6102$1545_Y
+  connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6103$1549_Y
   connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6003$1483_Y
-  connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6004$1487_Y
+  connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6105$1552_Y
+  connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6106$1556_Y
   connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6006$1490_Y
-  connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6007$1494_Y
+  connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6108$1559_Y
+  connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6109$1563_Y
   connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0]
-  connect \main_sdcore_cmd_send_re $and$ls180.v:6009$1497_Y
-  connect \main_sdcore_cmd_send_we $and$ls180.v:6010$1501_Y
+  connect \main_sdcore_cmd_send_re $and$ls180.v:6111$1566_Y
+  connect \main_sdcore_cmd_send_we $and$ls180.v:6112$1570_Y
   connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6012$1504_Y
-  connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6013$1508_Y
+  connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6114$1573_Y
+  connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6115$1577_Y
   connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6015$1511_Y
-  connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6016$1515_Y
+  connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6117$1580_Y
+  connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6118$1584_Y
   connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6018$1518_Y
-  connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6019$1522_Y
+  connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6120$1587_Y
+  connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6121$1591_Y
   connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6021$1525_Y
-  connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6022$1529_Y
+  connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6123$1594_Y
+  connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6124$1598_Y
   connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6024$1532_Y
-  connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6025$1536_Y
+  connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6126$1601_Y
+  connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6127$1605_Y
   connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6027$1539_Y
-  connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6028$1543_Y
+  connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6129$1608_Y
+  connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6130$1612_Y
   connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6030$1546_Y
-  connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6031$1550_Y
+  connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6132$1615_Y
+  connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6133$1619_Y
   connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6033$1553_Y
-  connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6034$1557_Y
+  connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6135$1622_Y
+  connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6136$1626_Y
   connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6036$1560_Y
-  connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6037$1564_Y
+  connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6138$1629_Y
+  connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6139$1633_Y
   connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6039$1567_Y
-  connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6040$1571_Y
+  connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6141$1636_Y
+  connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6142$1640_Y
   connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6042$1574_Y
-  connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6043$1578_Y
+  connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6144$1643_Y
+  connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6145$1647_Y
   connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6045$1581_Y
-  connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6046$1585_Y
+  connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6147$1650_Y
+  connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6148$1654_Y
   connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6048$1588_Y
-  connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6049$1592_Y
+  connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6150$1657_Y
+  connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6151$1661_Y
   connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6051$1595_Y
-  connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6052$1599_Y
+  connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6153$1664_Y
+  connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6154$1668_Y
   connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6054$1602_Y
-  connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6055$1606_Y
+  connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6156$1671_Y
+  connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6157$1675_Y
   connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6057$1609_Y
-  connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6058$1613_Y
+  connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6159$1678_Y
+  connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6160$1682_Y
   connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0]
-  connect \builder_csrbank6_cmd_event_re $and$ls180.v:6060$1616_Y
-  connect \builder_csrbank6_cmd_event_we $and$ls180.v:6061$1620_Y
+  connect \builder_csrbank6_cmd_event_re $and$ls180.v:6162$1685_Y
+  connect \builder_csrbank6_cmd_event_we $and$ls180.v:6163$1689_Y
   connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0]
-  connect \builder_csrbank6_data_event_re $and$ls180.v:6063$1623_Y
-  connect \builder_csrbank6_data_event_we $and$ls180.v:6064$1627_Y
+  connect \builder_csrbank6_data_event_re $and$ls180.v:6165$1692_Y
+  connect \builder_csrbank6_data_event_we $and$ls180.v:6166$1696_Y
   connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0]
-  connect \builder_csrbank6_block_length1_re $and$ls180.v:6066$1630_Y
-  connect \builder_csrbank6_block_length1_we $and$ls180.v:6067$1634_Y
+  connect \builder_csrbank6_block_length1_re $and$ls180.v:6168$1699_Y
+  connect \builder_csrbank6_block_length1_we $and$ls180.v:6169$1703_Y
   connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_block_length0_re $and$ls180.v:6069$1637_Y
-  connect \builder_csrbank6_block_length0_we $and$ls180.v:6070$1641_Y
+  connect \builder_csrbank6_block_length0_re $and$ls180.v:6171$1706_Y
+  connect \builder_csrbank6_block_length0_we $and$ls180.v:6172$1710_Y
   connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_block_count3_re $and$ls180.v:6072$1644_Y
-  connect \builder_csrbank6_block_count3_we $and$ls180.v:6073$1648_Y
+  connect \builder_csrbank6_block_count3_re $and$ls180.v:6174$1713_Y
+  connect \builder_csrbank6_block_count3_we $and$ls180.v:6175$1717_Y
   connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_block_count2_re $and$ls180.v:6075$1651_Y
-  connect \builder_csrbank6_block_count2_we $and$ls180.v:6076$1655_Y
+  connect \builder_csrbank6_block_count2_re $and$ls180.v:6177$1720_Y
+  connect \builder_csrbank6_block_count2_we $and$ls180.v:6178$1724_Y
   connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_block_count1_re $and$ls180.v:6078$1658_Y
-  connect \builder_csrbank6_block_count1_we $and$ls180.v:6079$1662_Y
+  connect \builder_csrbank6_block_count1_re $and$ls180.v:6180$1727_Y
+  connect \builder_csrbank6_block_count1_we $and$ls180.v:6181$1731_Y
   connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w
-  connect \builder_csrbank6_block_count0_re $and$ls180.v:6081$1665_Y
-  connect \builder_csrbank6_block_count0_we $and$ls180.v:6082$1669_Y
+  connect \builder_csrbank6_block_count0_re $and$ls180.v:6183$1734_Y
+  connect \builder_csrbank6_block_count0_we $and$ls180.v:6184$1738_Y
   connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24]
   connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16]
   connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8]
@@ -282086,64 +283805,64 @@ module \ls180
   connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16]
   connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8]
   connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0]
-  connect \builder_csrbank7_sel $eq$ls180.v:6118$1670_Y
+  connect \builder_csrbank7_sel $eq$ls180.v:6220$1739_Y
   connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base7_re $and$ls180.v:6120$1673_Y
-  connect \builder_csrbank7_dma_base7_we $and$ls180.v:6121$1677_Y
+  connect \builder_csrbank7_dma_base7_re $and$ls180.v:6222$1742_Y
+  connect \builder_csrbank7_dma_base7_we $and$ls180.v:6223$1746_Y
   connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base6_re $and$ls180.v:6123$1680_Y
-  connect \builder_csrbank7_dma_base6_we $and$ls180.v:6124$1684_Y
+  connect \builder_csrbank7_dma_base6_re $and$ls180.v:6225$1749_Y
+  connect \builder_csrbank7_dma_base6_we $and$ls180.v:6226$1753_Y
   connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base5_re $and$ls180.v:6126$1687_Y
-  connect \builder_csrbank7_dma_base5_we $and$ls180.v:6127$1691_Y
+  connect \builder_csrbank7_dma_base5_re $and$ls180.v:6228$1756_Y
+  connect \builder_csrbank7_dma_base5_we $and$ls180.v:6229$1760_Y
   connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base4_re $and$ls180.v:6129$1694_Y
-  connect \builder_csrbank7_dma_base4_we $and$ls180.v:6130$1698_Y
+  connect \builder_csrbank7_dma_base4_re $and$ls180.v:6231$1763_Y
+  connect \builder_csrbank7_dma_base4_we $and$ls180.v:6232$1767_Y
   connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base3_re $and$ls180.v:6132$1701_Y
-  connect \builder_csrbank7_dma_base3_we $and$ls180.v:6133$1705_Y
+  connect \builder_csrbank7_dma_base3_re $and$ls180.v:6234$1770_Y
+  connect \builder_csrbank7_dma_base3_we $and$ls180.v:6235$1774_Y
   connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base2_re $and$ls180.v:6135$1708_Y
-  connect \builder_csrbank7_dma_base2_we $and$ls180.v:6136$1712_Y
+  connect \builder_csrbank7_dma_base2_re $and$ls180.v:6237$1777_Y
+  connect \builder_csrbank7_dma_base2_we $and$ls180.v:6238$1781_Y
   connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base1_re $and$ls180.v:6138$1715_Y
-  connect \builder_csrbank7_dma_base1_we $and$ls180.v:6139$1719_Y
+  connect \builder_csrbank7_dma_base1_re $and$ls180.v:6240$1784_Y
+  connect \builder_csrbank7_dma_base1_we $and$ls180.v:6241$1788_Y
   connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_base0_re $and$ls180.v:6141$1722_Y
-  connect \builder_csrbank7_dma_base0_we $and$ls180.v:6142$1726_Y
+  connect \builder_csrbank7_dma_base0_re $and$ls180.v:6243$1791_Y
+  connect \builder_csrbank7_dma_base0_we $and$ls180.v:6244$1795_Y
   connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_length3_re $and$ls180.v:6144$1729_Y
-  connect \builder_csrbank7_dma_length3_we $and$ls180.v:6145$1733_Y
+  connect \builder_csrbank7_dma_length3_re $and$ls180.v:6246$1798_Y
+  connect \builder_csrbank7_dma_length3_we $and$ls180.v:6247$1802_Y
   connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_length2_re $and$ls180.v:6147$1736_Y
-  connect \builder_csrbank7_dma_length2_we $and$ls180.v:6148$1740_Y
+  connect \builder_csrbank7_dma_length2_re $and$ls180.v:6249$1805_Y
+  connect \builder_csrbank7_dma_length2_we $and$ls180.v:6250$1809_Y
   connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_length1_re $and$ls180.v:6150$1743_Y
-  connect \builder_csrbank7_dma_length1_we $and$ls180.v:6151$1747_Y
+  connect \builder_csrbank7_dma_length1_re $and$ls180.v:6252$1812_Y
+  connect \builder_csrbank7_dma_length1_we $and$ls180.v:6253$1816_Y
   connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_length0_re $and$ls180.v:6153$1750_Y
-  connect \builder_csrbank7_dma_length0_we $and$ls180.v:6154$1754_Y
+  connect \builder_csrbank7_dma_length0_re $and$ls180.v:6255$1819_Y
+  connect \builder_csrbank7_dma_length0_we $and$ls180.v:6256$1823_Y
   connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0]
-  connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6156$1757_Y
-  connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6157$1761_Y
+  connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6258$1826_Y
+  connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6259$1830_Y
   connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0]
-  connect \builder_csrbank7_dma_done_re $and$ls180.v:6159$1764_Y
-  connect \builder_csrbank7_dma_done_we $and$ls180.v:6160$1768_Y
+  connect \builder_csrbank7_dma_done_re $and$ls180.v:6261$1833_Y
+  connect \builder_csrbank7_dma_done_we $and$ls180.v:6262$1837_Y
   connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0]
-  connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6162$1771_Y
-  connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6163$1775_Y
+  connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6264$1840_Y
+  connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6265$1844_Y
   connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6165$1778_Y
-  connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6166$1782_Y
+  connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6267$1847_Y
+  connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6268$1851_Y
   connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6168$1785_Y
-  connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6169$1789_Y
+  connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6270$1854_Y
+  connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6271$1858_Y
   connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6171$1792_Y
-  connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6172$1796_Y
+  connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6273$1861_Y
+  connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6274$1865_Y
   connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w
-  connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6174$1799_Y
-  connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6175$1803_Y
+  connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6276$1868_Y
+  connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6277$1872_Y
   connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56]
   connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48]
   connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40]
@@ -282165,54 +283884,54 @@ module \ls180
   connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8]
   connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0]
   connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we
-  connect \builder_csrbank8_sel $eq$ls180.v:6197$1804_Y
+  connect \builder_csrbank8_sel $eq$ls180.v:6299$1873_Y
   connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0]
-  connect \builder_csrbank8_card_detect_re $and$ls180.v:6199$1807_Y
-  connect \builder_csrbank8_card_detect_we $and$ls180.v:6200$1811_Y
+  connect \builder_csrbank8_card_detect_re $and$ls180.v:6301$1876_Y
+  connect \builder_csrbank8_card_detect_we $and$ls180.v:6302$1880_Y
   connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0]
-  connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6202$1814_Y
-  connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6203$1818_Y
+  connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6304$1883_Y
+  connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6305$1887_Y
   connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w
-  connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6205$1821_Y
-  connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6206$1825_Y
+  connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6307$1890_Y
+  connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6308$1894_Y
   connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0]
-  connect \main_sdphy_init_initialize_re $and$ls180.v:6208$1828_Y
-  connect \main_sdphy_init_initialize_we $and$ls180.v:6209$1832_Y
+  connect \main_sdphy_init_initialize_re $and$ls180.v:6310$1897_Y
+  connect \main_sdphy_init_initialize_we $and$ls180.v:6311$1901_Y
   connect \builder_csrbank8_card_detect_w \main_sdphy_status
   connect \main_sdphy_we \builder_csrbank8_card_detect_we
   connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8]
   connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0]
-  connect \builder_csrbank9_sel $eq$ls180.v:6214$1833_Y
+  connect \builder_csrbank9_sel $eq$ls180.v:6316$1902_Y
   connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0]
-  connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6216$1836_Y
-  connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6217$1840_Y
+  connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6318$1905_Y
+  connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6319$1909_Y
   connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0]
-  connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6219$1843_Y
-  connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6220$1847_Y
+  connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6321$1912_Y
+  connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6322$1916_Y
   connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0]
-  connect \main_sdram_command_issue_re $and$ls180.v:6222$1850_Y
-  connect \main_sdram_command_issue_we $and$ls180.v:6223$1854_Y
+  connect \main_sdram_command_issue_re $and$ls180.v:6324$1919_Y
+  connect \main_sdram_command_issue_we $and$ls180.v:6325$1923_Y
   connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0]
-  connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6225$1857_Y
-  connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6226$1861_Y
+  connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6327$1926_Y
+  connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6328$1930_Y
   connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w
-  connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6228$1864_Y
-  connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6229$1868_Y
+  connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6330$1933_Y
+  connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6331$1937_Y
   connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0]
-  connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6231$1871_Y
-  connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6232$1875_Y
+  connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6333$1940_Y
+  connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6334$1944_Y
   connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w
-  connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6234$1878_Y
-  connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6235$1882_Y
+  connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6336$1947_Y
+  connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6337$1951_Y
   connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w
-  connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6237$1885_Y
-  connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6238$1889_Y
+  connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6339$1954_Y
+  connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6340$1958_Y
   connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w
-  connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6240$1892_Y
-  connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6241$1896_Y
+  connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6342$1961_Y
+  connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6343$1965_Y
   connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w
-  connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6243$1899_Y
-  connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6244$1903_Y
+  connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6345$1968_Y
+  connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6346$1972_Y
   connect \main_sdram_sel \main_sdram_storage [0]
   connect \main_sdram_cke \main_sdram_storage [1]
   connect \main_sdram_odt \main_sdram_storage [2]
@@ -282227,28 +283946,28 @@ module \ls180
   connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8]
   connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0]
   connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we
-  connect \builder_csrbank10_sel $eq$ls180.v:6259$1904_Y
+  connect \builder_csrbank10_sel $eq$ls180.v:6361$1973_Y
   connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w
-  connect \builder_csrbank10_control1_re $and$ls180.v:6261$1907_Y
-  connect \builder_csrbank10_control1_we $and$ls180.v:6262$1911_Y
+  connect \builder_csrbank10_control1_re $and$ls180.v:6363$1976_Y
+  connect \builder_csrbank10_control1_we $and$ls180.v:6364$1980_Y
   connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w
-  connect \builder_csrbank10_control0_re $and$ls180.v:6264$1914_Y
-  connect \builder_csrbank10_control0_we $and$ls180.v:6265$1918_Y
+  connect \builder_csrbank10_control0_re $and$ls180.v:6366$1983_Y
+  connect \builder_csrbank10_control0_we $and$ls180.v:6367$1987_Y
   connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0]
-  connect \builder_csrbank10_status_re $and$ls180.v:6267$1921_Y
-  connect \builder_csrbank10_status_we $and$ls180.v:6268$1925_Y
+  connect \builder_csrbank10_status_re $and$ls180.v:6369$1990_Y
+  connect \builder_csrbank10_status_we $and$ls180.v:6370$1994_Y
   connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w
-  connect \builder_csrbank10_mosi0_re $and$ls180.v:6270$1928_Y
-  connect \builder_csrbank10_mosi0_we $and$ls180.v:6271$1932_Y
+  connect \builder_csrbank10_mosi0_re $and$ls180.v:6372$1997_Y
+  connect \builder_csrbank10_mosi0_we $and$ls180.v:6373$2001_Y
   connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w
-  connect \builder_csrbank10_miso_re $and$ls180.v:6273$1935_Y
-  connect \builder_csrbank10_miso_we $and$ls180.v:6274$1939_Y
+  connect \builder_csrbank10_miso_re $and$ls180.v:6375$2004_Y
+  connect \builder_csrbank10_miso_we $and$ls180.v:6376$2008_Y
   connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0]
-  connect \builder_csrbank10_cs0_re $and$ls180.v:6276$1942_Y
-  connect \builder_csrbank10_cs0_we $and$ls180.v:6277$1946_Y
+  connect \builder_csrbank10_cs0_re $and$ls180.v:6378$2011_Y
+  connect \builder_csrbank10_cs0_we $and$ls180.v:6379$2015_Y
   connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0]
-  connect \builder_csrbank10_loopback0_re $and$ls180.v:6279$1949_Y
-  connect \builder_csrbank10_loopback0_we $and$ls180.v:6280$1953_Y
+  connect \builder_csrbank10_loopback0_re $and$ls180.v:6381$2018_Y
+  connect \builder_csrbank10_loopback0_we $and$ls180.v:6382$2022_Y
   connect \main_spimaster10_length \main_spimaster11_storage [15:8]
   connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8]
   connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0]
@@ -282261,34 +283980,34 @@ module \ls180
   connect \main_spimaster20_sel \main_spimaster21_storage
   connect \builder_csrbank10_cs0_w \main_spimaster21_storage
   connect \builder_csrbank10_loopback0_w \main_spimaster23_storage
-  connect \builder_csrbank11_sel $eq$ls180.v:6299$1955_Y
+  connect \builder_csrbank11_sel $eq$ls180.v:6401$2024_Y
   connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_control1_re $and$ls180.v:6301$1958_Y
-  connect \builder_csrbank11_control1_we $and$ls180.v:6302$1962_Y
+  connect \builder_csrbank11_control1_re $and$ls180.v:6403$2027_Y
+  connect \builder_csrbank11_control1_we $and$ls180.v:6404$2031_Y
   connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_control0_re $and$ls180.v:6304$1965_Y
-  connect \builder_csrbank11_control0_we $and$ls180.v:6305$1969_Y
+  connect \builder_csrbank11_control0_re $and$ls180.v:6406$2034_Y
+  connect \builder_csrbank11_control0_we $and$ls180.v:6407$2038_Y
   connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0]
-  connect \builder_csrbank11_status_re $and$ls180.v:6307$1972_Y
-  connect \builder_csrbank11_status_we $and$ls180.v:6308$1976_Y
+  connect \builder_csrbank11_status_re $and$ls180.v:6409$2041_Y
+  connect \builder_csrbank11_status_we $and$ls180.v:6410$2045_Y
   connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_mosi0_re $and$ls180.v:6310$1979_Y
-  connect \builder_csrbank11_mosi0_we $and$ls180.v:6311$1983_Y
+  connect \builder_csrbank11_mosi0_re $and$ls180.v:6412$2048_Y
+  connect \builder_csrbank11_mosi0_we $and$ls180.v:6413$2052_Y
   connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_miso_re $and$ls180.v:6313$1986_Y
-  connect \builder_csrbank11_miso_we $and$ls180.v:6314$1990_Y
+  connect \builder_csrbank11_miso_re $and$ls180.v:6415$2055_Y
+  connect \builder_csrbank11_miso_we $and$ls180.v:6416$2059_Y
   connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0]
-  connect \builder_csrbank11_cs0_re $and$ls180.v:6316$1993_Y
-  connect \builder_csrbank11_cs0_we $and$ls180.v:6317$1997_Y
+  connect \builder_csrbank11_cs0_re $and$ls180.v:6418$2062_Y
+  connect \builder_csrbank11_cs0_we $and$ls180.v:6419$2066_Y
   connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0]
-  connect \builder_csrbank11_loopback0_re $and$ls180.v:6319$2000_Y
-  connect \builder_csrbank11_loopback0_we $and$ls180.v:6320$2004_Y
+  connect \builder_csrbank11_loopback0_re $and$ls180.v:6421$2069_Y
+  connect \builder_csrbank11_loopback0_we $and$ls180.v:6422$2073_Y
   connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6322$2007_Y
-  connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6323$2011_Y
+  connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6424$2076_Y
+  connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6425$2080_Y
   connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w
-  connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6325$2014_Y
-  connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6326$2018_Y
+  connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6427$2083_Y
+  connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6428$2087_Y
   connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8]
   connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8]
   connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0]
@@ -282303,58 +284022,58 @@ module \ls180
   connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage
   connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8]
   connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0]
-  connect \builder_csrbank12_sel $eq$ls180.v:6347$2020_Y
+  connect \builder_csrbank12_sel $eq$ls180.v:6449$2089_Y
   connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_load3_re $and$ls180.v:6349$2023_Y
-  connect \builder_csrbank12_load3_we $and$ls180.v:6350$2027_Y
+  connect \builder_csrbank12_load3_re $and$ls180.v:6451$2092_Y
+  connect \builder_csrbank12_load3_we $and$ls180.v:6452$2096_Y
   connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_load2_re $and$ls180.v:6352$2030_Y
-  connect \builder_csrbank12_load2_we $and$ls180.v:6353$2034_Y
+  connect \builder_csrbank12_load2_re $and$ls180.v:6454$2099_Y
+  connect \builder_csrbank12_load2_we $and$ls180.v:6455$2103_Y
   connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_load1_re $and$ls180.v:6355$2037_Y
-  connect \builder_csrbank12_load1_we $and$ls180.v:6356$2041_Y
+  connect \builder_csrbank12_load1_re $and$ls180.v:6457$2106_Y
+  connect \builder_csrbank12_load1_we $and$ls180.v:6458$2110_Y
   connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_load0_re $and$ls180.v:6358$2044_Y
-  connect \builder_csrbank12_load0_we $and$ls180.v:6359$2048_Y
+  connect \builder_csrbank12_load0_re $and$ls180.v:6460$2113_Y
+  connect \builder_csrbank12_load0_we $and$ls180.v:6461$2117_Y
   connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_reload3_re $and$ls180.v:6361$2051_Y
-  connect \builder_csrbank12_reload3_we $and$ls180.v:6362$2055_Y
+  connect \builder_csrbank12_reload3_re $and$ls180.v:6463$2120_Y
+  connect \builder_csrbank12_reload3_we $and$ls180.v:6464$2124_Y
   connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_reload2_re $and$ls180.v:6364$2058_Y
-  connect \builder_csrbank12_reload2_we $and$ls180.v:6365$2062_Y
+  connect \builder_csrbank12_reload2_re $and$ls180.v:6466$2127_Y
+  connect \builder_csrbank12_reload2_we $and$ls180.v:6467$2131_Y
   connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_reload1_re $and$ls180.v:6367$2065_Y
-  connect \builder_csrbank12_reload1_we $and$ls180.v:6368$2069_Y
+  connect \builder_csrbank12_reload1_re $and$ls180.v:6469$2134_Y
+  connect \builder_csrbank12_reload1_we $and$ls180.v:6470$2138_Y
   connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_reload0_re $and$ls180.v:6370$2072_Y
-  connect \builder_csrbank12_reload0_we $and$ls180.v:6371$2076_Y
+  connect \builder_csrbank12_reload0_re $and$ls180.v:6472$2141_Y
+  connect \builder_csrbank12_reload0_we $and$ls180.v:6473$2145_Y
   connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0]
-  connect \builder_csrbank12_en0_re $and$ls180.v:6373$2079_Y
-  connect \builder_csrbank12_en0_we $and$ls180.v:6374$2083_Y
+  connect \builder_csrbank12_en0_re $and$ls180.v:6475$2148_Y
+  connect \builder_csrbank12_en0_we $and$ls180.v:6476$2152_Y
   connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0]
-  connect \builder_csrbank12_update_value0_re $and$ls180.v:6376$2086_Y
-  connect \builder_csrbank12_update_value0_we $and$ls180.v:6377$2090_Y
+  connect \builder_csrbank12_update_value0_re $and$ls180.v:6478$2155_Y
+  connect \builder_csrbank12_update_value0_we $and$ls180.v:6479$2159_Y
   connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_value3_re $and$ls180.v:6379$2093_Y
-  connect \builder_csrbank12_value3_we $and$ls180.v:6380$2097_Y
+  connect \builder_csrbank12_value3_re $and$ls180.v:6481$2162_Y
+  connect \builder_csrbank12_value3_we $and$ls180.v:6482$2166_Y
   connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_value2_re $and$ls180.v:6382$2100_Y
-  connect \builder_csrbank12_value2_we $and$ls180.v:6383$2104_Y
+  connect \builder_csrbank12_value2_re $and$ls180.v:6484$2169_Y
+  connect \builder_csrbank12_value2_we $and$ls180.v:6485$2173_Y
   connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_value1_re $and$ls180.v:6385$2107_Y
-  connect \builder_csrbank12_value1_we $and$ls180.v:6386$2111_Y
+  connect \builder_csrbank12_value1_re $and$ls180.v:6487$2176_Y
+  connect \builder_csrbank12_value1_we $and$ls180.v:6488$2180_Y
   connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w
-  connect \builder_csrbank12_value0_re $and$ls180.v:6388$2114_Y
-  connect \builder_csrbank12_value0_we $and$ls180.v:6389$2118_Y
+  connect \builder_csrbank12_value0_re $and$ls180.v:6490$2183_Y
+  connect \builder_csrbank12_value0_we $and$ls180.v:6491$2187_Y
   connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0]
-  connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6391$2121_Y
-  connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6392$2125_Y
+  connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6493$2190_Y
+  connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6494$2194_Y
   connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0]
-  connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6394$2128_Y
-  connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6395$2132_Y
+  connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6496$2197_Y
+  connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6497$2201_Y
   connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0]
-  connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6397$2135_Y
-  connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6398$2139_Y
+  connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6499$2204_Y
+  connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6500$2208_Y
   connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24]
   connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16]
   connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8]
@@ -282371,31 +284090,31 @@ module \ls180
   connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0]
   connect \main_libresocsim_value_we \builder_csrbank12_value0_we
   connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage
-  connect \builder_csrbank13_sel $eq$ls180.v:6415$2140_Y
+  connect \builder_csrbank13_sel $eq$ls180.v:6517$2209_Y
   connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w
-  connect \main_uart_rxtx_re $and$ls180.v:6417$2143_Y
-  connect \main_uart_rxtx_we $and$ls180.v:6418$2147_Y
+  connect \main_uart_rxtx_re $and$ls180.v:6519$2212_Y
+  connect \main_uart_rxtx_we $and$ls180.v:6520$2216_Y
   connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0]
-  connect \builder_csrbank13_txfull_re $and$ls180.v:6420$2150_Y
-  connect \builder_csrbank13_txfull_we $and$ls180.v:6421$2154_Y
+  connect \builder_csrbank13_txfull_re $and$ls180.v:6522$2219_Y
+  connect \builder_csrbank13_txfull_we $and$ls180.v:6523$2223_Y
   connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0]
-  connect \builder_csrbank13_rxempty_re $and$ls180.v:6423$2157_Y
-  connect \builder_csrbank13_rxempty_we $and$ls180.v:6424$2161_Y
+  connect \builder_csrbank13_rxempty_re $and$ls180.v:6525$2226_Y
+  connect \builder_csrbank13_rxempty_we $and$ls180.v:6526$2230_Y
   connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0]
-  connect \main_uart_eventmanager_status_re $and$ls180.v:6426$2164_Y
-  connect \main_uart_eventmanager_status_we $and$ls180.v:6427$2168_Y
+  connect \main_uart_eventmanager_status_re $and$ls180.v:6528$2233_Y
+  connect \main_uart_eventmanager_status_we $and$ls180.v:6529$2237_Y
   connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0]
-  connect \main_uart_eventmanager_pending_re $and$ls180.v:6429$2171_Y
-  connect \main_uart_eventmanager_pending_we $and$ls180.v:6430$2175_Y
+  connect \main_uart_eventmanager_pending_re $and$ls180.v:6531$2240_Y
+  connect \main_uart_eventmanager_pending_we $and$ls180.v:6532$2244_Y
   connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0]
-  connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6432$2178_Y
-  connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6433$2182_Y
+  connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6534$2247_Y
+  connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6535$2251_Y
   connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0]
-  connect \builder_csrbank13_txempty_re $and$ls180.v:6435$2185_Y
-  connect \builder_csrbank13_txempty_we $and$ls180.v:6436$2189_Y
+  connect \builder_csrbank13_txempty_re $and$ls180.v:6537$2254_Y
+  connect \builder_csrbank13_txempty_we $and$ls180.v:6538$2258_Y
   connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0]
-  connect \builder_csrbank13_rxfull_re $and$ls180.v:6438$2192_Y
-  connect \builder_csrbank13_rxfull_we $and$ls180.v:6439$2196_Y
+  connect \builder_csrbank13_rxfull_re $and$ls180.v:6540$2261_Y
+  connect \builder_csrbank13_rxfull_we $and$ls180.v:6541$2265_Y
   connect \builder_csrbank13_txfull_w \main_uart_txfull_status
   connect \main_uart_txfull_we \builder_csrbank13_txfull_we
   connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status
@@ -282405,19 +284124,19 @@ module \ls180
   connect \main_uart_txempty_we \builder_csrbank13_txempty_we
   connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status
   connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we
-  connect \builder_csrbank14_sel $eq$ls180.v:6449$2197_Y
+  connect \builder_csrbank14_sel $eq$ls180.v:6551$2266_Y
   connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w
-  connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6451$2200_Y
-  connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6452$2204_Y
+  connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6553$2269_Y
+  connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6554$2273_Y
   connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w
-  connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6454$2207_Y
-  connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6455$2211_Y
+  connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6556$2276_Y
+  connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6557$2280_Y
   connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w
-  connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6457$2214_Y
-  connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6458$2218_Y
+  connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6559$2283_Y
+  connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6560$2287_Y
   connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w
-  connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6460$2221_Y
-  connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6461$2225_Y
+  connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6562$2290_Y
+  connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6563$2294_Y
   connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24]
   connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16]
   connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8]
@@ -282471,7 +284190,7 @@ module \ls180
   connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w
   connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w
   connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w
-  connect \builder_csr_interconnect_dat_r $or$ls180.v:6515$2239_Y
+  connect \builder_csr_interconnect_dat_r $or$ls180.v:6617$2308_Y
   connect \sdrio_clk \sys_clk_1
   connect \sdrio_clk_1 \sys_clk_1
   connect \sdrio_clk_2 \sys_clk_1
@@ -282548,23 +284267,26 @@ module \ls180
   connect \sdrio_clk_66 \sys_clk_1
   connect \sdrio_clk_67 \sys_clk_1
   connect \sdrio_clk_68 \sys_clk_1
-  connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10055$2693_DATA
+  connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10172$2771_DATA
+  connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10192$2785_DATA
+  connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10212$2799_DATA
+  connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10232$2813_DATA
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10073$2700_DATA
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10250$2820_DATA
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10087$2707_DATA
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10264$2827_DATA
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10101$2714_DATA
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10278$2834_DATA
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10115$2721_DATA
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10292$2841_DATA
   connect \main_uart_tx_fifo_wrport_dat_r \memdat_4
   connect \main_uart_tx_fifo_rdport_dat_r \memdat_5
   connect \main_uart_rx_fifo_wrport_dat_r \memdat_6
   connect \main_uart_rx_fifo_rdport_dat_r \memdat_7
   connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8
-  connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10163$2742_DATA
+  connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10340$2862_DATA
   connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
-  connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10177$2749_DATA
+  connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10354$2869_DATA
 end
 attribute \src "libresoc.v:135159.1-135217.10"
 attribute \cells_not_processed 1