create FastTuple2 function

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 6c522e351b7ea2a6f67c5a8c0f6758ce2f77be7a..de2aaf921f8db990f7480317117afec841c2cf5a 100644 (file)
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -52,7 +52,8 @@ package slow_peripherals;
                        method Bit#(1) mtip_int;
                        method Bit#(`DATA) mtime;
                `endif
-               `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
+               `ifdef PLIC method ActionValue#(SlowTuple2#(Bool,Bool)) intrpt_note;
+        `endif
         interface IOCellSide iocell_side; // mandatory interface
         `ifdef PLIC
 {1}
@@ -60,7 +61,7 @@ package slow_peripherals;
        endinterface
        /*================================*/
 
-       function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
+       function SlowTuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
                      fn_address_mapping (Bit#(`ADDR) addr);
         `ifdef CLINT
             if(addr>=`ClintBase && addr<=`ClintEnd)

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 2d0d64a39f3457d0f26d4f9f85f59051d862c12f..2d72e72724748c15a25c24278f0e61aa509d997a 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -39,6 +39,7 @@ package Soc;
     import Connectable::*;
     import Clocks::*;
     /*========================== */
+{10}
     /*=== Project imports === */
     import ConcatReg::*;
     import AXI4_Types::*;
@@ -114,6 +115,39 @@ package Soc;
 {1}
     endinterface
 
+function FastTuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
+                fn_addr_to_slave_num  (Bit#(`PADDR) addr);
+
+    if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
+        return tuple2(True,fromInteger(valueOf(Sdram_slave_num)));
+    else if(addr>=`DebugBase && addr<=`DebugEnd)
+        return tuple2(True,fromInteger(valueOf(Debug_slave_num)));
+    `ifdef SDRAM
+        else if(addr>=`SDRAMCfgBase && addr<=`SDRAMCfgEnd )
+            return tuple2(True,fromInteger(valueOf(Sdram_cfg_slave_num)));
+    `endif
+    `ifdef BOOTROM
+        else if(addr>=`BootRomBase && addr<=`BootRomEnd)
+            return tuple2(True,fromInteger(valueOf(BootRom_slave_num)));
+    `endif
+    `ifdef DMA
+        else if(addr>=`DMABase && addr<=`DMAEnd)
+            return tuple2(True,fromInteger(valueOf(Dma_slave_num)));
+    `endif
+    `ifdef VME
+        else if(addr>=`VMEBase && addr<=`VMEEnd)
+            return tuple2(True,fromInteger(valueOf(VME_slave_num)));
+    `endif
+    `ifdef TCMemory
+        else if(addr>=`TCMBase && addr<=`TCMEnd)
+            return tuple2(True,fromInteger(valueOf(TCM_slave_num)));
+    `endif
+        else 
+{11}
+            return tuple2(False,?);
+endfunction
+
+
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 0e450f457ba562e962bdc88c272245d7eb7867e1..c88080dbb0b6d7e2168875c82d28b9f0df4b88a1 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -486,9 +486,14 @@ class PeripheralInterfaces(object):
                 ret.append(self.data[name].slowifdecl().format(i, name))
         return '\n'.join(list(filter(None, ret)))
 
+    def axi_fastmem_def(self, *args):
+        return self._axi_reg_def(0x50000000, *args)
+
     def axi_reg_def(self, *args):
+        return self._axi_reg_def(0x00011100, *args)
+
+    def _axi_reg_def(self, start, *args):
         ret = []
-        start = 0x00011100  # start of AXI peripherals address
         for (name, count) in self.ifacecount:
             for i in range(count):
                 if self.is_on_fastbus(name, i):

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index fb452b06332c148ad5566d1e3610350e5fcafae8..8d6953829e3f21bef66ca02564106239d1104926 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -137,7 +137,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
     imports = ifaces.slowimport()
     ifdecl = ifaces.fastifdecl()
 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
-    regdef = ifaces.axi_reg_def()
+    regdef = ifaces.axi_fastmem_def()
     slavedecl = ifaces.axi_fastslave_idx()
     mastdecl = ifaces.axi_master_idx()
     fnaddrmap = ifaces.axi_addr_map()
@@ -155,7 +155,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
                                    slavedecl, mastdecl, mkcon,
                                    inst, dma, num_dmachannels,
-                                   pincon,
+                                   pincon, regdef, fnaddrmap,
                                    ))