return false;
uint32_t bin_w, bin_h;
- bin_w = div_align(key->width, nbins_x, screen->gmem_alignw);
- bin_h = div_align(key->height, nbins_y, screen->gmem_alignh);
+ bin_w = div_align(key->width, nbins_x, screen->tile_alignw);
+ bin_h = div_align(key->height, nbins_y, screen->tile_alignh);
gmem->bin_w = bin_w;
gmem->bin_h = bin_h;
/* first, find a bin width that satisfies the maximum width
* restrictions:
*/
- while (div_align(key->width, nbins_x, screen->gmem_alignw) > max_width) {
+ while (div_align(key->width, nbins_x, screen->tile_alignw) > max_width) {
nbins_x++;
}
}
if (screen->gpu_id >= 600) {
- screen->gmem_alignw = 32;
- screen->gmem_alignh = 32;
+ screen->gmem_alignw = 16;
+ screen->gmem_alignh = 4;
+ screen->tile_alignw = 32;
+ screen->tile_alignh = 32;
screen->num_vsc_pipes = 32;
} else if (screen->gpu_id >= 500) {
- screen->gmem_alignw = 64;
- screen->gmem_alignh = 32;
+ screen->gmem_alignw = screen->tile_alignw = 64;
+ screen->gmem_alignh = screen->tile_alignh = 32;
screen->num_vsc_pipes = 16;
} else {
- screen->gmem_alignw = 32;
- screen->gmem_alignh = 32;
+ screen->gmem_alignw = screen->tile_alignw = 32;
+ screen->gmem_alignh = screen->tile_alignh = 32;
screen->num_vsc_pipes = 8;
}
uint32_t max_freq;
uint32_t ram_size;
uint32_t max_rts; /* max # of render targets */
- uint32_t gmem_alignw, gmem_alignh;
+ uint32_t gmem_alignw, gmem_alignh; /* gmem load/store granularity */
+ uint32_t tile_alignw, tile_alignh; /* alignment for tile sizes */
uint32_t num_vsc_pipes;
uint32_t priority_mask;
bool has_timestamp;