move mul data struct to separate module

diff --git a/src/ieee754/fpmul/datastructs.py b/src/ieee754/fpmul/datastructs.py
new file mode 100644 (file)
index 0000000..26914e5
--- /dev/null
+++ b/src/ieee754/fpmul/datastructs.py
@@ -0,0 +1,28 @@
+"""IEEE754 Floating Point Multiplier Pipeline
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+"""
+
+from nmigen import Signal
+
+from ieee754.fpcommon.fpbase import FPNumBaseRecord
+from ieee754.fpcommon.getop import FPPipeContext
+
+
+class FPMulStage0Data:
+
+    def __init__(self, pspec):
+        width = pspec.width
+        self.z = FPNumBaseRecord(width, False)
+        self.out_do_z = Signal(reset_less=True)
+        self.oz = Signal(width, reset_less=True)
+        mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        self.product = Signal(mw, reset_less=True)
+        self.ctx = FPPipeContext(pspec)
+        self.muxid = self.ctx.muxid
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+                self.product.eq(i.product), self.ctx.eq(i.ctx)]
+

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 428c275312bcbaff40e02597e3904295fcdb7031..97821a65a182aa80cc972cf29fd1768c3f51d9a4 100644 (file)
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -4,30 +4,14 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class FPMulStage0Data:
-
-    def __init__(self, pspec):
-        width = pspec.width
-        self.z = FPNumBaseRecord(width, False)
-        self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-        mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
-        self.product = Signal(mw, reset_less=True)
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def eq(self, i):
-        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.product.eq(i.product), self.ctx.eq(i.ctx)]
+from ieee754.fpmul.datastructs import FPMulStage0Data
 
 
 class FPMulStage0Mod(PipeModBase):

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index 67e915172d9427e2135315bf6aed3e8e26cbd1fb..b83432ff3d771da2274a87b6e4f5f803737c7916 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -4,7 +4,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase