add convenience variables in TestMemory

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index d4a13557283e05784b06f16299c0c284bfc6b19d..72a24ab7dca4c949c3ea3db635b77fef7dd2c6f9 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -5,6 +5,8 @@ class TestMemory(Elaboratable):
     def __init__(self, regwid, addrw):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
+        self.depth = depth
+        self.regwid = regwid
         self.mem   = Memory(width=regwid, depth=depth,
                             init=range(0, depth*2, 2))
         self.rdport = self.mem.read_port() # not now transparent=False)