relay hwacha cause/aux to scause/sbadaddr

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index b4d0d78fdb929f5d52f9729a5f10526cc9481d14..83116f22bd28cd42b4e971fecea363c22a3a8e73 100644 (file)
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -596,10 +596,10 @@ vtcode2 ## testnum: \
 handler ## testnum: \
   vxcptkill; \
   li TESTNUM,2; \
-  vxcptcause a0; \
+  csrr a0, scause; \
   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
   bne a0,a1,fail; \
-  vxcptaux a0; \
+  csrr a0, sbadaddr; \
   la a1, illegal ## testnum; \
   lw a2, 0(a1); \
   bne a0, a2, fail; \
@@ -655,10 +655,10 @@ vtcode2 ## testnum: \
 handler ## testnum: \
   vxcptkill; \
   li TESTNUM,2; \
-  vxcptcause a0; \
+  csrr a0, scause; \
   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
   bne a0,a1,fail; \
-  vxcptaux a0; \
+  csrr a0, sbadaddr; \
   la a1,illegal ## testnum; \
   bne a0,a1,fail; \
   vsetcfg 32,0; \

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index a2c982744e16616f8b536d32522d9469133c6b67..03227eb2a166dd9d4b356fb6dbc0db04e25df4c6 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -30,12 +30,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_CFG
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 1
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index db077445aea213a709ac241601696885942e62ae..dc4d3a41a0435439340d5d8af0ebdf14b4befca7 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -29,12 +29,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_CFG
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 0
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index ae46fe0eda7c2e9773b9d3b40e33a6e4b35ae922..b7dfc2819adfbddfe2126c87bd3c282699d9a9b9 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -36,12 +36,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 0xff00002b
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index dd616970adef770f5715bbb2827e49e1e5fd7a2f..e2164137047d0552ea6420f1a44151dd74caa625 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -44,12 +44,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,illegal
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 398396e3be52e41e7df1b606f6f8806aeee905b8..79b21b1d3d9b183c1c2e506645bb839d272b6963 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -40,12 +40,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 1390b54d7074720b3eb0929f4a8d02ddfc8d24d4..9bd3cd8e6711184bcb497dbb294fb060e29be1f3 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -42,12 +42,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_STORE
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4, dest+1
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 4276b6495887161623aa97c023147f7ca81c6597..85882b8b2a34a50ec17eec9ca2a9323b93d97cff 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -41,12 +41,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 2271e8f6c8673415526015ab4a550837b165c56a..35cb828b7182f4e4714a79b5b270d0e89805e7dc 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -44,12 +44,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_STORE
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 25c23c512b49907b377550dacf5540a9397ae7a1..d7c96b3f0c8dc0ffeb248db849a375067eeff35d 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -34,12 +34,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,vtcode1+2
   andi a3, a3, -4 # mask off lower bits so that may
   andi a4, a4, -4 # ignore impl. specific behavior

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index b7b169efa1f19922197580026f8bdbf23f8f9c7f..65c5288a8e7e683f08f60bdb12a1722028e0b09f 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -36,12 +36,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4, privileged_inst
   lw a5, 0(a4)
   bne a3,a5,fail