for simulatio keep the simulated dram in the

same clock domain as the main sim, for now

diff --git a/src/ls2.py b/src/ls2.py
index f564b46aaca6272c4150083701da78a556ed2d9e..926256c5e807db1c4297f53ac96ee1f798097dba 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -190,12 +190,19 @@ class DDR3SoC(SoC, Elaboratable):
                                 geom_settings=ddrmodule.geom_settings,
                                 timing_settings=ddrmodule.timing_settings,
                                 clk_freq=clk_freq)
-            self.dramcore = drs(dramcore)
-            self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+            self._decoder.add(dramcore.bus, addr=dramcore_addr)
 
             # map the DRAM onto Wishbone
-            self.drambone = drs(gramWishbone(self.dramcore))
-            self._decoder.add(self.drambone.bus, addr=ddr_addr)
+            drambone = gramWishbone(dramcore)
+            self._decoder.add(drambone.bus, addr=ddr_addr)
+
+            # for simulation do not use a separate clock domain (yet)
+            if fpga == 'sim':
+                self.dramcore = dramcore
+                self.drambone = drambone
+            else:
+                self.dramcore = drs(dramcore)
+                self.drambone = drs(drambone)
 
         self.memory_map = self._decoder.bus.memory_map