update comments

https://bugs.libre-soc.org/show_bug.cgi?id=686#c51

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 60a8e9df6be79ef2d30eff8625d6fb1103bed2c3..d1d8e20949a4d7d6474348f67b34c2c2c59643bb 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -3,6 +3,7 @@
 related bugs:
 
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
+ * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 """
 from nmigen import Module, Signal, Cat, ClockSignal
 from nmigen.hdl.xfrm import ResetInserter
@@ -310,6 +311,12 @@ class TestRunner(FHDLTestCase):
                 yield
                 yield
 
+                # TODO, here is where the static (expected) results
+                # can be checked: register check (TODO, memory check)
+                # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
+                # yield from check_regs(self, sim, core, test, code,
+                #                       >>>expected_data<<<)
+
                 # get CR
                 cr = yield from get_dmi(dmi, DBGCore.CR)
                 print("after test %s cr value %x" % (test.name, cr))