dcache.py fix formatting

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 3abbac42d0828c32863d14a3317ccd0bccac1891..27b7a045a2c7d81d842658247acadd9b07d44835 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -560,8 +560,10 @@ class Dcache(Elaboratable):
 #      std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
 #     signal tlb_plru_victim : tlb_plru_out_t;
         # TLB PLRU output interface
-        DEF TLBPLRUOut():
-            return Array(Signal(TLB_WAY_BITS) for x in range(TLB_SET_SIZE))
+        def TLBPLRUOut():
+            return Array(
+                Signal(TLB_WAY_BITS) for x in range(TLB_SET_SIZE)
+            )
 
         tlb_plru_victim = TLBPLRUOut()