add rfid and td/tw trap test

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 90df1ac65a3612918811054a597128c7291e1ee5..e6ee584035d77db781e75a4ddd5b119496f573fb 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -582,7 +582,7 @@ class PowerDecode2(Elaboratable):
         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 
-        # TODO, privileged?
+        # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
         with m.If(op.internal_op == InternalOp.OP_TRAP):
             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 3d63754b7253b2c6eaa73959bd85acb9dcf7685c..8c32fc73dd2666c36d52564e2c0321bb2e795169 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -78,8 +78,14 @@ class TrapTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_trap_eq_imm(self):
-        insns = ["twi", "tdi"]
+    def test_1_rfid(self):
+        lst = ["rfid"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 1
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_0_trap_eq_imm(self):
+        insns = ["tw", "td"]
         for i in range(2):
             choice = random.choice(insns)
             lst = [f"{choice} 4, 1, %d" % i] # TO=4: trap equal
@@ -87,6 +93,16 @@ class TrapTestCase(FHDLTestCase):
             initial_regs[1] = 1
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_0_trap_eq(self):
+        insns = ["twi", "tdi"]
+        for i in range(2):
+            choice = insns[i]
+            lst = [f"{choice} 4, 1, 2"] # TO=4: trap equal
+            initial_regs = [0] * 32
+            initial_regs[1] = 1
+            initial_regs[2] = 1
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         pspec = TrapPipeSpec(id_wid=2)
         alu = TrapBasePipe(pspec)