set SRR0 in OP_SC

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index a241a7d48eb24f208d11f3387ba747915737db87..3fdfd81e13965ac13dee797d1bf6c38c83cb9ddf 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -211,6 +211,8 @@ class TrapMainStage(PipeModBase):
                 comb += nia_o.ok.eq(1)
                 comb += srr1_o.data.eq(msr_i)
                 comb += srr1_o.ok.eq(1)
+                comb += srr0_o.data.eq(cia_i+4) # addr to begin from on return
+                comb += srr0_o.ok.eq(1)
 
             # TODO (later)
             #with m.Case(InternalOp.OP_ADDPCIS):