add option to use new mmu_cache_wb ConfigMemoryPortInterface

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 85a14869ba76ebd7b070ed398cf95e459a4ea13c..108c9c77c40cce1fd02d50f1192f0955674e30af 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -135,8 +135,11 @@ class TestRunner(FHDLTestCase):
         pc_i = Signal(32)
         svstate_i = Signal(32)
 
-        pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
-                             imem_ifacetype='test_bare_wb',
+        ldst_ifacetype = 'mmu_cache_wb' if microwatt_mmu else 'test_bare_wb'
+        imem_ifacetype = 'test_bare_wb'
+
+        pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
+                             imem_ifacetype=imem_ifacetype,
                              addr_wid=48,
                              mask_wid=8,
                              imem_reg_wid=64,