add beginnings of TestIssuer class, to issue instructions to simple core

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index aea3ea9960d8e34ff3f52101f6db9c656dde6515..545bd51913bd11fa98792d2fc45ac548f08a7cff 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -29,6 +29,7 @@ from soc.fu.compunits.compunits import AllFunctionUnits
 from soc.regfile.regfiles import RegFiles
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
 from soc.experiment.testmem import TestMemory # test only for instructions
 import operator
@@ -67,7 +68,7 @@ class NonProductionCore(Elaboratable):
         self.regs = RegFiles()
 
         # instruction decoder
-        self.pdecode = pdecode = create_pdecode()
+        pdecode = create_pdecode()
         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
 
         # issue/valid/busy signalling
@@ -312,6 +313,35 @@ class NonProductionCore(Elaboratable):
         return list(self)
 
 
+class TestIssuer(Elaboratable):
+    """TestIssuer - reads instructions from TestMemory and issues them
+
+    efficiency and speed is not the main goal here: functional correctness is.
+    """
+    def __init__(self, addrwid=6, idepth=16):
+        # main instruction core
+        self.core = core = NonProductionCore(addrwid)
+
+        # Test Instruction memory
+        self.imem = TestMemory(32, idepth)
+        self.i_rd = self.imem.read_port()
+        #self.i_wr = self.imem.write_port() errr...
+
+        # instruction go/monitor
+        self.go_insn_i = Signal(reset_less=True)
+        self.pc_o = Signal(64, reset_less=True)
+        self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
+        self.busy_o = core.busy_o
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules.core = core = self.core
+        m.submodules.imem = imem = self.imem
+
+        current_pc = Signal(64, reset_less=True)
+
+
 if __name__ == '__main__':
     dut = NonProductionCore()
     vl = rtlil.convert(dut, ports=dut.ports())

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index c2a0692e4162238790efbd78fd5c31bd43031709..4460a79a7096dd44649c6becc84534461bbde6dc 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -64,7 +64,6 @@ class TestRunner(FHDLTestCase):
         ivalid_i = Signal()
 
         m.submodules.core = core = NonProductionCore()
-        pdecode = core.pdecode
         pdecode2 = core.pdecode2
         l0 = core.l0