def create_test():
x = """\
-def getfn({0}):
- def test({0}):
- args = ({0})
- return test2(*args)
+from myhdl import block
+@block
+def test(testfn, {0}):
+ args = ({0})
+ return testfn(*args)
return test
"""
args = ['clk', 'muxes', 'pins', 'fns']
x = x.format(args)
print x
print repr(x)
- y = {'test2': test2, 'block': block}
+ with open("testmod.py", "w") as f:
+ f.write(x)
+ x = "from testmod import test"
code = compile(x, '<string>', 'exec')
+ y = {}
exec code in y
- x = y["getfn"]
- #print inspect.getsourcelines(proxy)
- #print inspect.getsourcelines(x)
+ x = y["test"]
def fn(*args):
return block(x)
return wrapper
+@block
def test2(clk, muxes, pins, fns):
muxinst = []
fns.append(IO("inout", "fnname%d" % i))
clk = Signal(bool(0))
- mux_inst = Test(clk, muxes, pins, fns)
+ mux_inst = test(test2, clk, muxes, pins, fns)
@instance
def clk_signal():
fns.append(IO("inout", "fnname%d" % i))
clk = Signal(bool(0))
- mux_inst = Test(clk, muxes, pins, fns)
+ mux_inst = test(test2, clk, muxes, pins, fns)
+ mux_inst.convert(hdl="Verilog", initial_values=True)
+ #mux_inst = Test(clk, muxes, pins, fns)
#toVerilog(mux_inst, clk, muxes, pins, fns)
#deco = Deco()
#b = _Block(mux_inst, deco, "test", "test.py", 1, clk, muxes, pins, fns)
tb.config_sim(trace=True)
tb.run_sim(66 * period) # run for 15 clock cycle
-#test = create_test()
+test = create_test()
if __name__ == '__main__':