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add XER bits to register enums
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 8 Oct 2022 10:04:05 +0000 (11:04 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 8 Oct 2022 10:04:05 +0000 (11:04 +0100)
src/openpower/decoder/power_enums.py patch | blob | history

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 081a703c7a43677d3b8432a0c0efccceef845ded..f3da7119cf0453b0b1e1d745ea103e2fb999ba63 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -414,6 +414,13 @@ class RegType(Enum):
     BI = CR_BIT
     BT = CR_BIT
 
+    XER_BIT = 4   # XER bits, includes OV, OV32, SO, CA, CA32
+    OV = XER_BIT
+    OV32 = XER_BIT
+    CA = XER_BIT
+    CA32 = XER_BIT
+    SO = XER_BIT
+
     @classmethod
     def _missing_(cls, value):
         if isinstance(value, SVExtraReg):