reduce power-on-delay bits to 2 for icarus sim ecp5

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 75467423b7960316dbed4e79f6412e7bd6cea1e7..5c975d66c1dacaed906e13e96cb4781ceb64593a 100644 (file)
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -169,8 +169,9 @@ class PLL(Elaboratable):
 
 
 class ECP5CRG(Elaboratable):
-    def __init__(self, sys_clk_freq=100e6):
+    def __init__(self, sys_clk_freq=100e6, pod_bits=25):
         self.sys_clk_freq = sys_clk_freq
+        self.pod_bits = pod_bits
 
     def elaborate(self, platform):
         m = Module()
@@ -207,7 +208,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
 
         # Power-on delay (655us)
-        podcnt = Signal(25, reset=-1)
+        podcnt = Signal(self.pod_bits, reset=-1)
         pod_done = Signal()
         with m.If((podcnt != 0) & pll.locked):
             m.d.rawclk += podcnt.eq(podcnt-1)

diff --git a/src/ls2.py b/src/ls2.py
index 3aa51e48d9d3f017e707303961ec666b7527e9bd..ea500f5274b2afe543be878eef309f09b133be56 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -271,8 +271,11 @@ class DDR3SoC(SoC, Elaboratable):
             firmware = "firmware/main.bin"
 
         # set up clock request generator
+        pod_bits = 25
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
-            self.crg = ECP5CRG(clk_freq)
+            if fpga == ['isim']:
+                pod_bits = 2
+            self.crg = ECP5CRG(clk_freq, pod_bits)
         if fpga in ['arty_a7']:
             self.crg = ArtyA7CRG(clk_freq)