* pipe_context
*/
-void r600_gfx_write_fence(struct r600_common_context *ctx,
+void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
uint64_t va, uint32_t old_value, uint32_t new_value)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
radeon_emit(cs, new_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
+
+ r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
}
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
if (screen->chip_class == CIK)
dwords *= 2;
+ if (!screen->info.has_virtual_memory)
+ dwords += 2;
+
return dwords;
}
struct pipe_resource *resource);
/* r600_common_pipe.c */
-void r600_gfx_write_fence(struct r600_common_context *ctx,
+void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
uint64_t va, uint32_t old_value, uint32_t new_value);
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
void r600_gfx_wait_fence(struct r600_common_context *ctx,
uint64_t va)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
+ uint64_t fence_va = 0;
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0xFFFF);
- va += ctx->max_db * 16 - 8;
- r600_gfx_write_fence(ctx, va, 0, 0x80000000);
+ fence_va = va + ctx->max_db * 16 - 8;
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
radeon_emit(cs, 0);
radeon_emit(cs, 0);
- va += 8;
- r600_gfx_write_fence(ctx, va, 0, 0x80000000);
+ fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
unsigned sample_size = (query->result_size - 8) / 2;
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0xFFFF);
- va += sample_size;
- r600_gfx_write_fence(ctx, va, 0, 0x80000000);
+ fence_va = va + sample_size;
break;
}
default:
}
r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
+
+ if (fence_va)
+ r600_gfx_write_fence(ctx, query->buffer.buf, fence_va, 0, 0x80000000);
}
static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
- r600_gfx_write_fence(ctx, va, 1, 0);
+ r600_gfx_write_fence(ctx, buffer, va, 1, 0);
r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));