add first i-cache fetch (non-virtual), no MMU lookup, copied unit

test from basic one in soc/experiment/icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 470f57180dd3171324d09b9621eee2a65a5f266f..e6f35c5990eb5775db37cf03e957f306c16b64ca 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -324,7 +324,7 @@ class ICache(Elaboratable):
                             granularity=8,
                             features={'stall'},
                             alignment=0,
-                            name="dcache")
+                            name="icache_wb")
 
         self.log_out        = Signal(54)
 

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 28364213c3e835847561fd3aadaaca114f2c6ddf..ab247ef2895bed23e6723300155830ddb2fe102e 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -1,4 +1,5 @@
-from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
+from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal,
+                    Const)
 from nmigen.cli import main
 from nmigen.cli import rtlil
 from nmutil.mask import Mask, masked
@@ -62,6 +63,45 @@ test_dcbz = True
 test_random = True
 
 
+def _test_loadstore1_ifetch(dut, mem):
+    mmu = dut.submodules.mmu
+    pi = dut.submodules.ldst.pi
+    icache = dut.submodules.ldst.icache
+    wbget.stop = False
+
+    print("=== test loadstore instruction ===")
+
+    addr = 0
+
+    i_in = icache.i_in
+    i_out  = icache.i_out
+    m_out = icache.m_in
+
+    yield i_in.priv_mode.eq(1)
+    yield i_in.req.eq(0)
+    yield i_in.nia.eq(0)
+    yield i_in.stop_mark.eq(0)
+    yield m_out.tlbld.eq(0)
+    yield m_out.tlbie.eq(0)
+    yield m_out.addr.eq(0)
+    yield m_out.pte.eq(0)
+    yield
+
+    # miss, stalls for a bit
+    yield i_in.req.eq(1)
+    yield i_in.nia.eq(Const(0x0000000000000004, 64))
+    yield
+    valid = yield i_out.valid
+    while not valid:
+        yield
+        valid = yield i_out.valid
+    yield i_in.req.eq(0)
+
+    print("=== test loadstore instruction ===")
+
+    wbget.stop = True
+
+
 def _test_loadstore1_invalid(dut, mem):
     mmu = dut.submodules.mmu
     pi = dut.submodules.ldst.pi
@@ -204,6 +244,26 @@ def _test_loadstore1(dut, mem):
     wbget.stop = True
 
 
+def test_loadstore1_ifetch():
+
+    m, cmpi = setup_mmu()
+
+    mem = pagetables.test1
+
+    # nmigen Simulation
+    sim = Simulator(m)
+    sim.add_clock(1e-6)
+
+    icache = m.submodules.ldst.icache
+    sim.add_sync_process(wrap(_test_loadstore1_ifetch(m, mem)))
+    # add two wb_get processes onto the *same* memory dictionary.
+    # this shouuuld work.... cross-fingers...
+    sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
+    sim.add_sync_process(wrap(wb_get(icache.bus, mem)))
+    with sim.write_vcd('test_loadstore1_ifetch.vcd'):
+        sim.run()
+
+
 def test_loadstore1():
 
     m, cmpi = setup_mmu()
@@ -237,5 +297,6 @@ def test_loadstore1_invalid():
 
 
 if __name__ == '__main__':
-    test_loadstore1()
-    test_loadstore1_invalid()
+    #test_loadstore1()
+    #test_loadstore1_invalid()
+    test_loadstore1_ifetch()