rename function which needs replacing

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index d93bd594e84f52614c8bd1992d941250fdd3444d..e6c6d3fb4b52c0238de44863d409f57c95357ca0 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -123,7 +123,7 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase):
 stop = False
 
 
-def wb_get(dc):
+def todo_replace_wb_get(dc):
     """simulator process for getting memory load requests
     """
 
@@ -242,7 +242,7 @@ def test_mmu():
     sim.add_clock(1e-6)
 
     sim.add_sync_process(wrap(mmu_sim(dut)))
-    sim.add_sync_process(wrap(wb_get(dcache)))
+    sim.add_sync_process(wrap(todo_replace_wb_get(dcache)))
     with sim.write_vcd('test_mmu_pi.vcd'):
         sim.run()