id_wid (muxid bitwidth) based on num_rows, not the data width

diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py
index 0a40d2b69e19c69b09dc4bf21183e95af10be87d..c00ab6e7e5d06431d70b3854c65fb0d17779d8e8 100644 (file)
--- a/src/ieee754/fclass/pipeline.py
+++ b/src/ieee754/fclass/pipeline.py
@@ -63,11 +63,10 @@ class FPClassMuxInOutBase(ReservationStations):
     def __init__(self, modkls, in_width, out_width,
                        num_rows, op_wid=0, pkls=FPClassBasePipe):
         self.op_wid = op_wid
-        self.id_wid = num_bits(in_width)
-        self.out_id_wid = num_bits(out_width)
+        self.id_wid = num_bits(num_rows)
 
-        self.in_pspec = PipelineSpec(in_width, self.id_wid, self.op_wid)
-        self.out_pspec = PipelineSpec(out_width, self.out_id_wid, op_wid)
+        self.in_pspec = PipelineSpec(in_width, self.id_wid, op_wid)
+        self.out_pspec = PipelineSpec(out_width, self.id_wid, op_wid)
 
         self.alu = pkls(modkls, self.in_pspec, self.out_pspec)
         ReservationStations.__init__(self, num_rows)

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 505bc6e88b1328055735ce8757ca0ec5b569071e..d8f0db06cb6124045b0b070f7f2e7af03b3f15e5 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -97,11 +97,10 @@ class FPCVTMuxInOutBase(ReservationStations):
     def __init__(self, modkls, e_extra, in_width, out_width,
                        num_rows, op_wid=0, pkls=FPCVTBasePipe):
         self.op_wid = op_wid
-        self.id_wid = num_bits(in_width)
-        self.out_id_wid = num_bits(out_width)
+        self.id_wid = num_bits(num_rows)
 
-        self.in_pspec = PipelineSpec(in_width, self.id_wid, self.op_wid)
-        self.out_pspec = PipelineSpec(out_width, self.out_id_wid, op_wid)
+        self.in_pspec = PipelineSpec(in_width, id_wid, self.op_wid)
+        self.out_pspec = PipelineSpec(out_width, id_wid, op_wid)
 
         self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec)
         ReservationStations.__init__(self, num_rows)

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 5d622132d317f55a8beed143209d3b0bea57781f..424d39e74a6e61f01cc7b3f2e1cd657d84e1614e 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -84,7 +84,7 @@ class FPADDMuxInOut(ReservationStations):
     """
 
     def __init__(self, width, num_rows, op_wid=None):
-        self.id_wid = num_bits(width)
+        self.id_wid = num_bits(num_rows)
         self.op_wid = op_wid
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         self.alu = FPADDBasePipe(self.pspec)

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index bcd99e26dddcffbf35aa6cfe75511312149022d8..4330df44525807d38fac114b462a035bd5f6996c 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -156,7 +156,7 @@ class FPDIVMuxInOut(ReservationStations):
     """
 
     def __init__(self, width, num_rows, op_wid=2):
-        self.id_wid = num_bits(width)  # FIXME: shouldn't this be num_rows?
+        self.id_wid = num_bits(num_rows)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         # get the standard mantissa width, store in the pspec
         fmt = FPFormat.standard(width)

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index 589d106663349ffdc39e7fad802f31706eaadb51..adb66a373805456cae458410f87cc57493ecf587 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -81,7 +81,7 @@ class FPMULMuxInOut(ReservationStations):
     """
 
     def __init__(self, width, num_rows, op_wid=0):
-        self.id_wid = num_bits(width)
+        self.id_wid = num_bits(num_rows)
         self.op_wid = op_wid
         self.pspec = PipelineSpec(width, self.id_wid, self.op_wid)
         self.alu = FPMULBasePipe(self.pspec)