orangecrab: set clock frequency, remove ignored iostandard

diff --git a/src/ls2.py b/src/ls2.py
index a9590853bce643a53f9280fa3465dbb534aa79e8..514b724f335048f34aed6ebb2478ac2373a4603c 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -869,6 +869,8 @@ def build_platform(fpga, firmware):
         clk_freq = 50e6
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
+    if fpga == 'orangecrab':
+        clk_freq = 50e6
 
     # merge dram_clk_freq with clk_freq if the same
     if clk_freq == dram_clk_freq:
@@ -885,8 +887,7 @@ def build_platform(fpga, firmware):
     if platform is not None:
         if fpga=="orangecrab":
             # assumes an FT232 USB-UART soldered onto these two pins.
-            orangecrab_uart = UARTResource(0, rx="N17", tx="M18",
-                                attrs=Attrs(IOSTANDARD="LVCMOS33"))
+            orangecrab_uart = UARTResource(0, rx="N17", tx="M18")
             platform.add_resources([orangecrab_uart])
 
         uart_pins = platform.request("uart", 0)