rename truncaddr to splitaddr, return LSBs and MSBs

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 919d39bec7f539bdc99e5cc0bbfce4c9a4f24974..b0c9ca82cbd11e61972f7795502ba456b89b7ee6 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -330,10 +330,10 @@ class L0CacheBuffer(Elaboratable):
     def addrbits(self):
         return log2_int(self.mem.regwid//8)
 
-    def truncaddr(self, addr):
-        """truncates the address to the top bits of the memory granularity
+    def splitaddr(self, addr):
+        """split the address into top and bottom bits of the memory granularity
         """
-        return addr[self.addrbits:]
+        return addr[:self.addrbits], addr[self.addrbits:]
 
     def elaborate(self, platform):
         m = Module()