add Test 24, add built-in process function into FIFOControl

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 98f29d2bfb99675b3a9336b830c2991c2401ade0..62eb7d890a025b20e9b2ed3763dccd6fa9c94d1e 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -1034,25 +1034,42 @@ class FIFOControl(ControlBase):
     def elaborate(self, platform):
         self.m = m = ControlBase._elaborate(self, platform)
 
-        (fwidth, _) = self.p.i_data.shape()
+        (fwidth, _) = self.n.o_data.shape()
         fifo = SyncFIFO(fwidth, self.fdepth)
         m.submodules.fifo = fifo
 
-        # prev: make the FIFO "look" like a PrevControl...
-        fp = PrevControl()
-        fp.i_valid = fifo.we
-        fp._o_ready = fifo.writable
-        fp.i_data = fifo.din
-        m.d.comb += fp._connect_in(self.p, True, fn=flatten)
+        # store result of processing in combinatorial temporary
+        result = self.stage.ospec()
+        m.d.comb += eq(result, self.stage.process(self.p.i_data))
+
+        # connect previous rdy/valid/data - do flatten on i_data
+        # NOTE: cannot do the PrevControl-looking trick because
+        # of need to process the data.  shaaaame....
+        m.d.comb += [fifo.we.eq(self.p.i_valid_test),
+                     self.p.o_ready.eq(fifo.writable),
+                     eq(fifo.din, flatten(result)),
+                   ]
 
         # next: make the FIFO "look" like a NextControl...
         fn = NextControl()
-        fn.o_valid = fifo.readable
-        fn.i_ready = fifo.re
-        fn.o_data = fifo.dout
-        # ... so we can do this!
-        m.d.comb += fn._connect_out(self.n, fn=flatten)
+        fn.o_valid, fn.i_ready, fn.o_data = fifo.readable, fifo.re, fifo.dout
+        m.d.comb += fn._connect_out(self.n, fn=flatten) # ...so we can do this!
 
         # err... that should be all!
         return m
 
+        # XXX
+        # XXX UNUSED CODE!
+        # XXX
+
+        # prev: make the FIFO "look" like a PrevControl...
+        fp = PrevControl()
+        fp.i_valid, fp._o_ready, fp.i_data = fifo.we, fifo.writable, fifo.din
+        m.d.comb += fp._connect_in(self.p, True, fn=flatten)
+
+        # connect next rdy/valid/data - do flatten on o_data
+        m.d.comb += [self.n.o_valid.eq(fifo.readable),
+                     fifo.re.eq(self.n.i_ready_test),
+                     flatten(self.n.o_data).eq(fifo.dout),
+                   ]
+

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index b0e31b27c76709ea4df0b9330ee82e15a9cfea22..0726bd3fdedfbc6d143ce400b79c187bf5a25e1c 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -577,8 +577,8 @@ class TestInputAdd:
 def test8_resultfn(o_data, expected, i, o):
     res = expected.op1 + expected.op2 # these are a TestInputAdd instance
     assert o_data == res, \
-                "%d-%d data %x not match %s\n" \
-                % (i, o, o_data, repr(expected))
+                "%d-%d data %s res %x not match %s\n" \
+                % (i, o, repr(o_data), res, repr(expected))
 
 def data_2op():
         data = []
@@ -865,6 +865,18 @@ class ExampleFIFORecordObjectPipe(ControlBase):
 # Test 24
 ######################################################################
 
+class FIFOTestRecordAddStageControl(FIFOControl):
+
+    def __init__(self):
+        stage = ExampleAddRecordObjectStage()
+        FIFOControl.__init__(self, 2, stage)
+
+
+
+######################################################################
+# Test 25
+######################################################################
+
 def iospecfn24():
     return (Signal(16, name="src1"), Signal(16, name="src2"))
 
@@ -1185,7 +1197,6 @@ if __name__ == '__main__':
     with open("test_addrecord22.il", "w") as f:
         f.write(vl)
 
-
     print ("test 23")
     dut = ExampleFIFORecordObjectPipe()
     data=data_2op()
@@ -1199,6 +1210,19 @@ if __name__ == '__main__':
     with open("test_addrecord23.il", "w") as f:
         f.write(vl)
 
+    print ("test 24")
+    dut = FIFOTestRecordAddStageControl()
+    data=data_2op()
+    test = Test5(dut, test8_resultfn, data=data)
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data.op1, dut.p.i_data.op2] + \
+             [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_addrecord24.il", "w") as f:
+        f.write(vl)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord24.vcd")
+
     print ("test 997")
     dut = ExampleBufPassThruPipe2()
     data = data_chain1()