create actual FPADD Pipeline from stages

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 399e1a0c1340d9ba54661490b73fd7742d6fc3b7..71d2b5dc071479f3f074de29ac1fd8473ffaf043 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -454,7 +454,7 @@ class FPAddSpecialCases(FPState):
             m.next = "denormalise"
 
 
-class FPAddSpecialCasesDeNorm(FPState):
+class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -464,6 +464,7 @@ class FPAddSpecialCasesDeNorm(FPState):
         FPState.__init__(self, "special_cases")
         self.smod = FPAddSpecialCasesMod(width, id_wid)
         self.dmod = FPAddDeNormMod(width, id_wid)
+        UnbufferedPipeline.__init__(self, self)
         self.o = self.ospec()
 
     def ispec(self):
@@ -768,16 +769,18 @@ class FPAddAlignSingle(FPState):
         m.next = "add_0"
 
 
-class FPAddAlignSingleAdd(FPState):
+class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         self.width = width
         self.id_wid = id_wid
+        UnbufferedPipeline.__init__(self, self)
         self.a1o = self.ospec()
 
     def ispec(self):
-        return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
+        return FPSCData(self.width, self.id_wid)
+        #return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 
     def ospec(self):
         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
@@ -1330,12 +1333,13 @@ class FPNorm1Multi(FPState):
             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 
 
-class FPNormToPack(FPState):
+class FPNormToPack(FPState, UnbufferedPipeline):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "normalise_1")
         self.id_wid = id_wid
         self.width = width
+        UnbufferedPipeline.__init__(self, self)
 
     def ispec(self):
         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
@@ -1890,12 +1894,18 @@ class FPADDBasePipe1(UnbufferedPipeline):
 class FPADDBasePipe(ControlBase):
     def __init__(self, width, id_wid):
         ControlBase.__init__(self)
-        self.pipe1 = FPADDBasePipe1(width, id_wid)
-        self._eqs = self.connect([self.pipe1])
+        #self.pipe1 = FPADDBasePipe1(width, id_wid)
+        self.pipe1 = FPAddSpecialCasesDeNorm(width, id_wid)
+        self.pipe2 = FPAddAlignSingleAdd(width, id_wid)
+        self.pipe3 = FPNormToPack(width, id_wid)
+
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.pipe1 = self.pipe1
+        m.submodules.scnorm = self.pipe1
+        m.submodules.addalign = self.pipe2
+        m.submodules.normpack = self.pipe3
         m.d.comb += self._eqs
         return m
 

diff --git a/src/add/test_fpadd_pipe.py b/src/add/test_fpadd_pipe.py
index 577117d38702f0b315d4406895fdc05b363e8a4e..32bf072d09b9517307ede1bdce6eaa2b35aee9b6 100644 (file)
--- a/src/add/test_fpadd_pipe.py
+++ b/src/add/test_fpadd_pipe.py
@@ -1,4 +1,4 @@
-""" key strategic example showing how to do multi-input fan-in into a 
+""" key strategic example showing how to do multi-input fan-in into a
     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,
@@ -13,6 +13,7 @@ from nmigen.cli import verilog, rtlil
 
 from nmigen_add_experiment import (FPADDMuxInOut,)
 
+from sfpy import Float32
 
 class InputTest:
     def __init__(self, dut):
@@ -20,14 +21,16 @@ class InputTest:
         self.di = {}
         self.do = {}
         self.tlen = 4
+        self.width = 32
         for mid in range(dut.num_rows):
             self.di[mid] = {}
             self.do[mid] = []
             for i in range(self.tlen):
-                op1 = randint(0, 255) 
-                op2 = randint(0, 255) 
+                op1 = randint(0, (1<<self.width)-1)
+                op2 = randint(0, (1<<self.width)-1)
+                res = Float32(op1) + Float32(op2)
                 self.di[mid][i] = (op1, op2)
-                self.do[mid].append(op1 + op2)
+                self.do[mid].append(res.bits)
 
     def send(self, mid):
         for i in range(self.tlen):
@@ -43,7 +46,11 @@ class InputTest:
                 yield
                 o_p_ready = yield rs.o_ready
 
-            print ("send", mid, i, op1, op2, op1+op2)
+            fop1 = Float32(op1)
+            fop2 = Float32(op2)
+            res = fop1 + fop2
+            print ("send", mid, i, hex(op1), hex(op2), hex(res.bits),
+                           fop1, fop2, res)
 
             yield rs.i_valid.eq(0)
             # wait random period of time before queueing another value
@@ -83,13 +90,14 @@ class InputTest:
             out_mid = yield n.o_data.mid
             out_z = yield n.o_data.z
 
-            print ("recv", out_mid, out_z)
-
             out_i = 0
 
+            print ("recv", out_mid, hex(out_z), "expected",
+                        hex(self.do[mid][out_i] ))
+
             # see if this output has occurred already, delete it if it has
             assert mid == out_mid, "out_mid %d not correct %d" % (out_mid, mid)
-            assert self.do[mid][out_i] == out_z # pass-through data
+            assert self.do[mid][out_i] == out_z
             del self.do[mid][out_i]
 
             # check if there's any more outputs
@@ -100,7 +108,7 @@ class InputTest:
 
 
 if __name__ == '__main__':
-    dut = FPADDMuxInOut(16, 2, 4)
+    dut = FPADDMuxInOut(32, 2, 4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fpadd_pipe.il", "w") as f:
         f.write(vl)