more verbose debug information tracking down SO/OV/OV32

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 42c56516a88a5234f81d37975aa9b64d2fd4b717..829a304fed0e74fa19b4199dbe3d183efc3a9c57 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -48,6 +48,8 @@ def get_cu_inputs(dec2, sim):
         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
         res['xer_so'] = so
 
+    print ("alu get_cu_inputs", res)
+
     return res
 
 
@@ -103,10 +105,41 @@ class ALUTestCase(FHDLTestCase):
     def __init__(self, name):
         super().__init__(name)
         self.test_name = name
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
+    def test_1_regression(self):
+        lst = [f"extsw 3, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xb6a1fc6c8576af91
+        self.run_tst_program(Program(lst), initial_regs)
+        lst = [f"subf 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x3d7f3f7ca24bac7b
+        initial_regs[2] = 0xf6b2ac5e13ee15c2
+        self.run_tst_program(Program(lst), initial_regs)
+        lst = [f"subf 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x833652d96c7c0058
+        initial_regs[2] = 0x1c27ecff8a086c1a
+        self.run_tst_program(Program(lst), initial_regs)
+        lst = [f"extsb 3, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x7f9497aaff900ea0
+        self.run_tst_program(Program(lst), initial_regs)
+        lst = [f"add. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xc523e996a8ff6215
+        initial_regs[2] = 0xe1e5b9cc9864c4a8
+        self.run_tst_program(Program(lst), initial_regs)
+        lst = [f"add 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x2e08ae202742baf8
+        initial_regs[2] = 0x86c43ece9efe5baa
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_rand(self):
         insns = ["add", "add.", "subf"]
         for i in range(40):
@@ -203,17 +236,22 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
                                 test.mem, test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                index = simulator.pc.CIA.value//4
+                index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]
 
-                    print("0x{:X}".format(ins & 0xffffffff))
+                    print("instruction: 0x{:X}".format(ins & 0xffffffff))
                     print(code)
+                    if 'XER' in sim.spr:
+                        so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+                        ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+                        ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+                        print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
@@ -221,11 +259,11 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
                     fn_unit = yield pdecode2.e.fn_unit
                     self.assertEqual(fn_unit, Function.ALU.value)
-                    yield from set_alu_inputs(alu, pdecode2, simulator)
+                    yield from set_alu_inputs(alu, pdecode2, sim)
                     yield
                     opname = code.split(' ')[0]
-                    yield from simulator.call(opname)
-                    index = simulator.pc.CIA.value//4
+                    yield from sim.call(opname)
+                    index = sim.pc.CIA.value//4
 
                     vld = yield alu.n.valid_o
                     while not vld:
@@ -236,14 +274,14 @@ class TestRunner(FHDLTestCase):
                     out_reg_valid = yield pdecode2.e.write_reg.ok
                     if out_reg_valid:
                         write_reg_idx = yield pdecode2.e.write_reg.data
-                        expected = simulator.gpr(write_reg_idx).value
+                        expected = sim.gpr(write_reg_idx).value
                         print(f"expected {expected:x}, actual: {alu_out:x}")
                         self.assertEqual(expected, alu_out, code)
                     yield from self.check_extra_alu_outputs(alu, pdecode2,
-                                                            simulator, code)
+                                                            sim, code)
 
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+        with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
                             traces=[]):
             sim.run()
 
@@ -284,6 +322,7 @@ class TestRunner(FHDLTestCase):
             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
             real_ov32 = yield alu.n.data_o.xer_ov.data[1] # OV32 bit
             self.assertEqual(expected_ov32, real_ov32, code)
+            print ("after: so/ov/32", real_so, real_ov, real_ov32)
         else:
             # if OE not enabled, XER SO and OV must correspondingly be false
             so_ok = yield alu.n.data_o.xer_so.ok

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index e2f9c47179936c6ba212363822c5927b57f37019..b1e8d288f9e6248d83c88956fff3bb04207c9c44 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -103,13 +103,13 @@ class TestRunner(FHDLTestCase):
                 print ("sprs", test.sprs)
                 if special_sprs['XER'] in test.sprs:
                     xer = test.sprs[special_sprs['XER']]
-                    sobit = 1 if xer[XER_bits['SO']] else 0
+                    sobit = xer[XER_bits['SO']].value
                     yield xregs.regs[xregs.SO].reg.eq(sobit)
-                    cabit = 1 if xer[XER_bits['CA']] else 0
-                    ca32bit = 1 if xer[XER_bits['CA32']] else 0
+                    cabit = xer[XER_bits['CA']].value
+                    ca32bit = xer[XER_bits['CA32']].value
                     yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
-                    ovbit = 1 if xer[XER_bits['OV']] else 0
-                    ov32bit = 1 if xer[XER_bits['OV32']] else 0
+                    ovbit = xer[XER_bits['OV']].value
+                    ov32bit = xer[XER_bits['OV32']].value
                     yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
                 else:
                     yield xregs.regs[xregs.SO].reg.eq(0)
@@ -120,7 +120,7 @@ class TestRunner(FHDLTestCase):
                 while index < len(instructions):
                     ins, code = instructions[index]
 
-                    print("0x{:X}".format(ins & 0xffffffff))
+                    print("instruction: 0x{:X}".format(ins & 0xffffffff))
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
@@ -132,6 +132,16 @@ class TestRunner(FHDLTestCase):
                     #fuval = self.funit.value
                     #self.assertEqual(fn_unit & fuval, fuval)
 
+                    # XER
+                    so = yield xregs.regs[xregs.SO].reg
+                    ov = yield xregs.regs[xregs.OV].reg
+                    ca = yield xregs.regs[xregs.CA].reg
+                    oe = yield pdecode2.e.oe.oe
+                    oe_ok = yield pdecode2.e.oe.oe_ok
+
+                    print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
+                    print ("oe:", oe, oe_ok)
+
                     # set operand and get inputs
                     yield from set_issue(core, pdecode2, sim)
                     yield Settle()
@@ -177,15 +187,17 @@ class TestRunner(FHDLTestCase):
                     ov = yield xregs.regs[xregs.OV].reg
                     ca = yield xregs.regs[xregs.CA].reg
 
-                    e_so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-                    e_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
-                    e_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
-                    e_ca = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-                    e_ca32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+                    print ("sim SO", sim.spr['XER'][XER_bits['SO']])
+                    e_so = sim.spr['XER'][XER_bits['SO']].value
+                    e_ov = sim.spr['XER'][XER_bits['OV']].value
+                    e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
+                    e_ca = sim.spr['XER'][XER_bits['CA']].value
+                    e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 
                     e_ov = e_ov | (e_ov32<<1)
                     e_ca = e_ca | (e_ca32<<1)
 
+                    print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
                     self.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))