add 2nd test matrix

diff --git a/experiments8/test_fu_reg_matrix.il b/experiments8/test_fu_reg_matrix.il
new file mode 100644 (file)
index 0000000..3637944
--- /dev/null
+++ b/experiments8/test_fu_reg_matrix.il
@@ -0,0 +1,4564 @@
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu0.dst1_c"
+module \dst1_c
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 0 \r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 1 \s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 2 \q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 3 \qlq_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 4 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 5 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst0 4'0000
+    assign \q_dst0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst0 4'0000
+    assign \qn_dst0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst0 4'0000
+    assign \qlq_dst0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu0.dst2_c"
+module \dst2_c
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 0 \r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 1 \s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 2 \q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 3 \qlq_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 4 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 5 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst1 4'0000
+    assign \q_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst1 4'0000
+    assign \qn_dst1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst1 4'0000
+    assign \qlq_dst1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu0.src1_c"
+module \src1_c
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 0 \r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 1 \s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 2 \q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 3 \qlq_src0
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 4 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 5 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src0 4'0000
+    assign \q_src0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src0 4'0000
+    assign \qn_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src0 4'0000
+    assign \qlq_src0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu0.src2_c"
+module \src2_c
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 0 \r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 1 \s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 2 \q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 3 \qlq_src1
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 4 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 5 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src1 4'0000
+    assign \q_src1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src1 4'0000
+    assign \qn_src1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src1 4'0000
+    assign \qlq_src1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu0"
+module \dr_fu0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 0 \dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 1 \dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 2 \src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 3 \src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 4 \dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 5 \dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 6 \src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 7 \src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 input 8 \rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 input 9 \wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 10 \dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 11 \dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 12 \src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 13 \src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 input 14 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 input 15 \go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 input 16 \go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 input 17 \go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 output 18 \v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 output 19 \v_wr_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 20 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 21 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst1_c_r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst1_c_s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst1_c_q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst1_c_qlq_dst0
+  cell \dst1_c \dst1_c
+    connect \r_dst0 \dst1_c_r_dst0
+    connect \s_dst0 \dst1_c_s_dst0
+    connect \q_dst0 \dst1_c_q_dst0
+    connect \qlq_dst0 \dst1_c_qlq_dst0
+    connect \rst \rst
+    connect \clk \clk
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst2_c_r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst2_c_s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst2_c_q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst2_c_qlq_dst1
+  cell \dst2_c \dst2_c
+    connect \r_dst1 \dst2_c_r_dst1
+    connect \s_dst1 \dst2_c_s_dst1
+    connect \q_dst1 \dst2_c_q_dst1
+    connect \qlq_dst1 \dst2_c_qlq_dst1
+    connect \rst \rst
+    connect \clk \clk
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src1_c_r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src1_c_s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src1_c_q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src1_c_qlq_src0
+  cell \src1_c \src1_c
+    connect \r_src0 \src1_c_r_src0
+    connect \s_src0 \src1_c_s_src0
+    connect \q_src0 \src1_c_q_src0
+    connect \qlq_src0 \src1_c_qlq_src0
+    connect \rst \rst
+    connect \clk \clk
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src2_c_r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src2_c_s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src2_c_q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src2_c_qlq_src1
+  cell \src2_c \src2_c
+    connect \r_src1 \src2_c_r_src1
+    connect \s_src1 \src2_c_s_src1
+    connect \q_src1 \src2_c_q_src1
+    connect \qlq_src1 \src2_c_qlq_src1
+    connect \rst \rst
+    connect \clk \clk
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $1
+  end
+  process $group_0
+    assign \wdi0 4'0000
+    assign \wdi0 $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $3
+  end
+  process $group_1
+    assign \wdi1 4'0000
+    assign \wdi1 $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $5
+  end
+  process $group_2
+    assign \rdi0 4'0000
+    assign \rdi0 $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $7
+  end
+  process $group_3
+    assign \rdi1 4'0000
+    assign \rdi1 $7
+    sync init
+  end
+  process $group_4
+    assign \src1_c_r_src0 4'1111
+    assign \src1_c_r_src0 \rdi0
+    sync init
+  end
+  process $group_5
+    assign \src2_c_r_src1 4'1111
+    assign \src2_c_r_src1 \rdi1
+    sync init
+  end
+  process $group_6
+    assign \dst1_c_r_dst0 4'1111
+    assign \dst1_c_r_dst0 \wdi0
+    sync init
+  end
+  process $group_7
+    assign \dst2_c_r_dst1 4'1111
+    assign \dst2_c_r_dst1 \wdi1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst1
+    connect \Y $9
+  end
+  process $group_8
+    assign \dst1_c_s_dst0 4'0000
+    assign \dst1_c_s_dst0 $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst2
+    connect \Y $11
+  end
+  process $group_9
+    assign \dst2_c_s_dst1 4'0000
+    assign \dst2_c_s_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src1
+    connect \Y $13
+  end
+  process $group_10
+    assign \src1_c_s_src0 4'0000
+    assign \src1_c_s_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src2
+    connect \Y $15
+  end
+  process $group_11
+    assign \src2_c_s_src1 4'0000
+    assign \src2_c_s_src1 $15
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_q_dst0
+    connect \B \rd_pend_i
+    connect \Y $17
+  end
+  process $group_12
+    assign \dst1_fwd_o 4'0000
+    assign \dst1_fwd_o $17
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_q_dst1
+    connect \B \rd_pend_i
+    connect \Y $19
+  end
+  process $group_13
+    assign \dst2_fwd_o 4'0000
+    assign \dst2_fwd_o $19
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_q_src0
+    connect \B \wr_pend_i
+    connect \Y $21
+  end
+  process $group_14
+    assign \src1_fwd_o 4'0000
+    assign \src1_fwd_o $21
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_q_src1
+    connect \B \wr_pend_i
+    connect \Y $23
+  end
+  process $group_15
+    assign \src2_fwd_o 4'0000
+    assign \src2_fwd_o $23
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \Y $25
+  end
+  process $group_16
+    assign \dst1_rsel_o 4'0000
+    assign \dst1_rsel_o $25
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_qlq_dst1
+    connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \Y $27
+  end
+  process $group_17
+    assign \dst2_rsel_o 4'0000
+    assign \dst2_rsel_o $27
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \Y $29
+  end
+  process $group_18
+    assign \src1_rsel_o 4'0000
+    assign \src1_rsel_o $29
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_qlq_src1
+    connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \Y $31
+  end
+  process $group_19
+    assign \src2_rsel_o 4'0000
+    assign \src2_rsel_o $31
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  wire width 4 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  cell $or $34
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B \src2_c_qlq_src1
+    connect \Y $33
+  end
+  process $group_20
+    assign \v_rd_rsel_o 4'0000
+    assign \v_rd_rsel_o $33
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  wire width 4 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  cell $or $36
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B \dst2_c_qlq_dst1
+    connect \Y $35
+  end
+  process $group_21
+    assign \v_wr_rsel_o 4'0000
+    assign \v_wr_rsel_o $35
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu1.dst1_c"
+module \dst1_c$1
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst0 4'0000
+    assign \q_dst0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst0 4'0000
+    assign \qn_dst0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst0 4'0000
+    assign \qlq_dst0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu1.dst2_c"
+module \dst2_c$2
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst1 4'0000
+    assign \q_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst1 4'0000
+    assign \qn_dst1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst1 4'0000
+    assign \qlq_dst1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu1.src1_c"
+module \src1_c$3
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src0 4'0000
+    assign \q_src0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src0 4'0000
+    assign \qn_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src0 4'0000
+    assign \qlq_src0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu1.src2_c"
+module \src2_c$4
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src1 4'0000
+    assign \q_src1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src1 4'0000
+    assign \qn_src1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src1 4'0000
+    assign \qlq_src1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu1"
+module \dr_fu1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 0 \dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 1 \dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 2 \src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 3 \src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 4 \dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 5 \dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 6 \src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 7 \src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 input 8 \rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 input 9 \wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 10 \dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 11 \dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 12 \src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 13 \src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 input 14 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 input 15 \go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 input 16 \go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 input 17 \go_die_i
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 18 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 19 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 output 20 \v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 output 21 \v_wr_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst1_c_r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst1_c_s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst1_c_q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst1_c_qlq_dst0
+  cell \dst1_c$1 \dst1_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_dst0 \dst1_c_r_dst0
+    connect \s_dst0 \dst1_c_s_dst0
+    connect \q_dst0 \dst1_c_q_dst0
+    connect \qlq_dst0 \dst1_c_qlq_dst0
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst2_c_r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst2_c_s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst2_c_q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst2_c_qlq_dst1
+  cell \dst2_c$2 \dst2_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_dst1 \dst2_c_r_dst1
+    connect \s_dst1 \dst2_c_s_dst1
+    connect \q_dst1 \dst2_c_q_dst1
+    connect \qlq_dst1 \dst2_c_qlq_dst1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src1_c_r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src1_c_s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src1_c_q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src1_c_qlq_src0
+  cell \src1_c$3 \src1_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_src0 \src1_c_r_src0
+    connect \s_src0 \src1_c_s_src0
+    connect \q_src0 \src1_c_q_src0
+    connect \qlq_src0 \src1_c_qlq_src0
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src2_c_r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src2_c_s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src2_c_q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src2_c_qlq_src1
+  cell \src2_c$4 \src2_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_src1 \src2_c_r_src1
+    connect \s_src1 \src2_c_s_src1
+    connect \q_src1 \src2_c_q_src1
+    connect \qlq_src1 \src2_c_qlq_src1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $1
+  end
+  process $group_0
+    assign \wdi0 4'0000
+    assign \wdi0 $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $3
+  end
+  process $group_1
+    assign \wdi1 4'0000
+    assign \wdi1 $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $5
+  end
+  process $group_2
+    assign \rdi0 4'0000
+    assign \rdi0 $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $7
+  end
+  process $group_3
+    assign \rdi1 4'0000
+    assign \rdi1 $7
+    sync init
+  end
+  process $group_4
+    assign \src1_c_r_src0 4'1111
+    assign \src1_c_r_src0 \rdi0
+    sync init
+  end
+  process $group_5
+    assign \src2_c_r_src1 4'1111
+    assign \src2_c_r_src1 \rdi1
+    sync init
+  end
+  process $group_6
+    assign \dst1_c_r_dst0 4'1111
+    assign \dst1_c_r_dst0 \wdi0
+    sync init
+  end
+  process $group_7
+    assign \dst2_c_r_dst1 4'1111
+    assign \dst2_c_r_dst1 \wdi1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst1
+    connect \Y $9
+  end
+  process $group_8
+    assign \dst1_c_s_dst0 4'0000
+    assign \dst1_c_s_dst0 $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst2
+    connect \Y $11
+  end
+  process $group_9
+    assign \dst2_c_s_dst1 4'0000
+    assign \dst2_c_s_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src1
+    connect \Y $13
+  end
+  process $group_10
+    assign \src1_c_s_src0 4'0000
+    assign \src1_c_s_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src2
+    connect \Y $15
+  end
+  process $group_11
+    assign \src2_c_s_src1 4'0000
+    assign \src2_c_s_src1 $15
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_q_dst0
+    connect \B \rd_pend_i
+    connect \Y $17
+  end
+  process $group_12
+    assign \dst1_fwd_o 4'0000
+    assign \dst1_fwd_o $17
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_q_dst1
+    connect \B \rd_pend_i
+    connect \Y $19
+  end
+  process $group_13
+    assign \dst2_fwd_o 4'0000
+    assign \dst2_fwd_o $19
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_q_src0
+    connect \B \wr_pend_i
+    connect \Y $21
+  end
+  process $group_14
+    assign \src1_fwd_o 4'0000
+    assign \src1_fwd_o $21
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_q_src1
+    connect \B \wr_pend_i
+    connect \Y $23
+  end
+  process $group_15
+    assign \src2_fwd_o 4'0000
+    assign \src2_fwd_o $23
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \Y $25
+  end
+  process $group_16
+    assign \dst1_rsel_o 4'0000
+    assign \dst1_rsel_o $25
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_qlq_dst1
+    connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \Y $27
+  end
+  process $group_17
+    assign \dst2_rsel_o 4'0000
+    assign \dst2_rsel_o $27
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \Y $29
+  end
+  process $group_18
+    assign \src1_rsel_o 4'0000
+    assign \src1_rsel_o $29
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_qlq_src1
+    connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \Y $31
+  end
+  process $group_19
+    assign \src2_rsel_o 4'0000
+    assign \src2_rsel_o $31
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  wire width 4 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  cell $or $34
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B \src2_c_qlq_src1
+    connect \Y $33
+  end
+  process $group_20
+    assign \v_rd_rsel_o 4'0000
+    assign \v_rd_rsel_o $33
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  wire width 4 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  cell $or $36
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B \dst2_c_qlq_dst1
+    connect \Y $35
+  end
+  process $group_21
+    assign \v_wr_rsel_o 4'0000
+    assign \v_wr_rsel_o $35
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu2.dst1_c"
+module \dst1_c$5
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst0 4'0000
+    assign \q_dst0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst0 4'0000
+    assign \qn_dst0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst0 4'0000
+    assign \qlq_dst0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu2.dst2_c"
+module \dst2_c$6
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_dst1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_dst1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_dst1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_dst1 4'0000
+    assign \q_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_dst1 4'0000
+    assign \qn_dst1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_dst1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_dst1 4'0000
+    assign \qlq_dst1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu2.src1_c"
+module \src1_c$7
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src0
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src0
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src0
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src0 4'0000
+    assign \q_src0 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src0 4'0000
+    assign \qn_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src0
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src0 4'0000
+    assign \qlq_src0 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu2.src2_c"
+module \src2_c$8
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 input 3 \s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 output 4 \q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 output 5 \qlq_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $not $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $3
+    connect \B \s_src1
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
+    switch \rst
+      case 1'1
+        assign \q_int$next 4'0000
+    end
+    sync init
+      update \q_int 4'0000
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $not $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \r_src1
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+  cell $or $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A $9
+    connect \B \s_src1
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src1 4'0000
+    assign \q_src1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \qn_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src1 4'0000
+    assign \qn_src1 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \q_src1
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src1 4'0000
+    assign \qlq_src1 $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.dr_fu2"
+module \dr_fu2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 0 \dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 output 1 \dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 2 \src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 output 3 \src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 4 \dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 output 5 \dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 6 \src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 output 7 \src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 input 8 \rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 input 9 \wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 10 \dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 input 11 \dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 12 \src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 input 13 \src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 input 14 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 input 15 \go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 input 16 \go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 input 17 \go_die_i
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 18 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 19 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 output 20 \v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 output 21 \v_wr_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst1_c_r_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst1_c_s_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst1_c_q_dst0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst1_c_qlq_dst0
+  cell \dst1_c$5 \dst1_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_dst0 \dst1_c_r_dst0
+    connect \s_dst0 \dst1_c_s_dst0
+    connect \q_dst0 \dst1_c_q_dst0
+    connect \qlq_dst0 \dst1_c_qlq_dst0
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \dst2_c_r_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \dst2_c_s_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \dst2_c_q_dst1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \dst2_c_qlq_dst1
+  cell \dst2_c$6 \dst2_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_dst1 \dst2_c_r_dst1
+    connect \s_dst1 \dst2_c_s_dst1
+    connect \q_dst1 \dst2_c_q_dst1
+    connect \qlq_dst1 \dst2_c_qlq_dst1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src1_c_r_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src1_c_s_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src1_c_q_src0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src1_c_qlq_src0
+  cell \src1_c$7 \src1_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_src0 \src1_c_r_src0
+    connect \s_src0 \src1_c_s_src0
+    connect \q_src0 \src1_c_q_src0
+    connect \qlq_src0 \src1_c_qlq_src0
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src2_c_r_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+  wire width 4 \src2_c_s_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src2_c_q_src1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \src2_c_qlq_src1
+  cell \src2_c$8 \src2_c
+    connect \rst \rst
+    connect \clk \clk
+    connect \r_src1 \src2_c_r_src1
+    connect \s_src1 \src2_c_s_src1
+    connect \q_src1 \src2_c_q_src1
+    connect \qlq_src1 \src2_c_qlq_src1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $1
+  end
+  process $group_0
+    assign \wdi0 4'0000
+    assign \wdi0 $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
+  wire width 4 \wdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
+  cell $or $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $3
+  end
+  process $group_1
+    assign \wdi1 4'0000
+    assign \wdi1 $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $5
+  end
+  process $group_2
+    assign \rdi0 4'0000
+    assign \rdi0 $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
+  wire width 4 \rdi1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
+  cell $or $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \Y $7
+  end
+  process $group_3
+    assign \rdi1 4'0000
+    assign \rdi1 $7
+    sync init
+  end
+  process $group_4
+    assign \src1_c_r_src0 4'1111
+    assign \src1_c_r_src0 \rdi0
+    sync init
+  end
+  process $group_5
+    assign \src2_c_r_src1 4'1111
+    assign \src2_c_r_src1 \rdi1
+    sync init
+  end
+  process $group_6
+    assign \dst1_c_r_dst0 4'1111
+    assign \dst1_c_r_dst0 \wdi0
+    sync init
+  end
+  process $group_7
+    assign \dst2_c_r_dst1 4'1111
+    assign \dst2_c_r_dst1 \wdi1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst1
+    connect \Y $9
+  end
+  process $group_8
+    assign \dst1_c_s_dst0 4'0000
+    assign \dst1_c_s_dst0 $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
+  cell $and $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \dst2
+    connect \Y $11
+  end
+  process $group_9
+    assign \dst2_c_s_dst1 4'0000
+    assign \dst2_c_s_dst1 $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src1
+    connect \Y $13
+  end
+  process $group_10
+    assign \src1_c_s_src0 4'0000
+    assign \src1_c_s_src0 $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
+  cell $and $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A { \issue_i \issue_i \issue_i \issue_i }
+    connect \B \src2
+    connect \Y $15
+  end
+  process $group_11
+    assign \src2_c_s_src1 4'0000
+    assign \src2_c_s_src1 $15
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_q_dst0
+    connect \B \rd_pend_i
+    connect \Y $17
+  end
+  process $group_12
+    assign \dst1_fwd_o 4'0000
+    assign \dst1_fwd_o $17
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  wire width 4 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
+  cell $and $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_q_dst1
+    connect \B \rd_pend_i
+    connect \Y $19
+  end
+  process $group_13
+    assign \dst2_fwd_o 4'0000
+    assign \dst2_fwd_o $19
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_q_src0
+    connect \B \wr_pend_i
+    connect \Y $21
+  end
+  process $group_14
+    assign \src1_fwd_o 4'0000
+    assign \src1_fwd_o $21
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  wire width 4 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
+  cell $and $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_q_src1
+    connect \B \wr_pend_i
+    connect \Y $23
+  end
+  process $group_15
+    assign \src2_fwd_o 4'0000
+    assign \src2_fwd_o $23
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
+    connect \Y $25
+  end
+  process $group_16
+    assign \dst1_rsel_o 4'0000
+    assign \dst1_rsel_o $25
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  wire width 4 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
+  cell $and $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst2_c_qlq_dst1
+    connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
+    connect \Y $27
+  end
+  process $group_17
+    assign \dst2_rsel_o 4'0000
+    assign \dst2_rsel_o $27
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
+    connect \Y $29
+  end
+  process $group_18
+    assign \src1_rsel_o 4'0000
+    assign \src1_rsel_o $29
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  wire width 4 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
+  cell $and $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src2_c_qlq_src1
+    connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
+    connect \Y $31
+  end
+  process $group_19
+    assign \src2_rsel_o 4'0000
+    assign \src2_rsel_o $31
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  wire width 4 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
+  cell $or $34
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \src1_c_qlq_src0
+    connect \B \src2_c_qlq_src1
+    connect \Y $33
+  end
+  process $group_20
+    assign \v_rd_rsel_o 4'0000
+    assign \v_rd_rsel_o $33
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  wire width 4 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
+  cell $or $36
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'100
+    connect \A \dst1_c_qlq_dst0
+    connect \B \dst2_c_qlq_dst1
+    connect \Y $35
+  end
+  process $group_21
+    assign \v_wr_rsel_o 4'0000
+    assign \v_wr_rsel_o $35
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.fu_fu0"
+module \fu_fu0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 output 0 \reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 output 1 \reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 2 \dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 output 3 \reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 4 \dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 5 \sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 output 6 \reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 7 \sfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd1_i
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd2_i
+    connect \Y $3
+  end
+  process $group_0
+    assign \reg_rd_src_pend_o 2'00
+    assign \reg_rd_src_pend_o [0] $1
+    assign \reg_rd_src_pend_o [1] $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_rd_src_pend_o
+    connect \Y $5
+  end
+  process $group_1
+    assign \reg_rd_pend_o 1'0
+    assign \reg_rd_pend_o $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd1_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd2_i
+    connect \Y $9
+  end
+  process $group_2
+    assign \reg_wr_dst_pend_o 2'00
+    assign \reg_wr_dst_pend_o [0] $7
+    assign \reg_wr_dst_pend_o [1] $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  cell $reduce_bool $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_wr_dst_pend_o
+    connect \Y $11
+  end
+  process $group_3
+    assign \reg_wr_pend_o 1'0
+    assign \reg_wr_pend_o $11
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.fu_fu1"
+module \fu_fu1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 output 0 \reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 output 1 \reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 2 \dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 output 3 \reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 4 \dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 5 \sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 output 6 \reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 7 \sfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd1_i
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd2_i
+    connect \Y $3
+  end
+  process $group_0
+    assign \reg_rd_src_pend_o 2'00
+    assign \reg_rd_src_pend_o [0] $1
+    assign \reg_rd_src_pend_o [1] $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_rd_src_pend_o
+    connect \Y $5
+  end
+  process $group_1
+    assign \reg_rd_pend_o 1'0
+    assign \reg_rd_pend_o $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd1_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd2_i
+    connect \Y $9
+  end
+  process $group_2
+    assign \reg_wr_dst_pend_o 2'00
+    assign \reg_wr_dst_pend_o [0] $7
+    assign \reg_wr_dst_pend_o [1] $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  cell $reduce_bool $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_wr_dst_pend_o
+    connect \Y $11
+  end
+  process $group_3
+    assign \reg_wr_pend_o 1'0
+    assign \reg_wr_pend_o $11
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.fu_fu2"
+module \fu_fu2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 output 0 \reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 output 1 \reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 2 \dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 output 3 \reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 input 4 \dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 5 \sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 output 6 \reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 input 7 \sfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd1_i
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \sfwd2_i
+    connect \Y $3
+  end
+  process $group_0
+    assign \reg_rd_src_pend_o 2'00
+    assign \reg_rd_src_pend_o [0] $1
+    assign \reg_rd_src_pend_o [1] $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_rd_src_pend_o
+    connect \Y $5
+  end
+  process $group_1
+    assign \reg_rd_pend_o 1'0
+    assign \reg_rd_pend_o $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd1_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \dfwd2_i
+    connect \Y $9
+  end
+  process $group_2
+    assign \reg_wr_dst_pend_o 2'00
+    assign \reg_wr_dst_pend_o [0] $7
+    assign \reg_wr_dst_pend_o [1] $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
+  cell $reduce_bool $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \reg_wr_dst_pend_o
+    connect \Y $11
+  end
+  process $group_3
+    assign \reg_wr_pend_o 1'0
+    assign \reg_wr_pend_o $11
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.rr_r0"
+module \rr_r0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 0 \dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 1 \dst_rsel_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 output 2 \dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 3 \src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 output 4 \src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 5 \src_rsel_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i$1
+    connect \Y $5
+  end
+  process $group_0
+    assign \dest_rsel_o 2'00
+    assign \dest_rsel_o [0] $3
+    assign \dest_rsel_o [1] $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i$2
+    connect \Y $9
+  end
+  process $group_1
+    assign \src_rsel_o 2'00
+    assign \src_rsel_o [0] $7
+    assign \src_rsel_o [1] $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.rr_r1"
+module \rr_r1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 0 \dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 1 \dst_rsel_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 output 2 \dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 3 \src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 output 4 \src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 5 \src_rsel_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i$1
+    connect \Y $5
+  end
+  process $group_0
+    assign \dest_rsel_o 2'00
+    assign \dest_rsel_o [0] $3
+    assign \dest_rsel_o [1] $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i$2
+    connect \Y $9
+  end
+  process $group_1
+    assign \src_rsel_o 2'00
+    assign \src_rsel_o [0] $7
+    assign \src_rsel_o [1] $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.rr_r2"
+module \rr_r2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 0 \dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 1 \dst_rsel_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 output 2 \dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 3 \src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 output 4 \src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 5 \src_rsel_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i$1
+    connect \Y $5
+  end
+  process $group_0
+    assign \dest_rsel_o 2'00
+    assign \dest_rsel_o [0] $3
+    assign \dest_rsel_o [1] $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i$2
+    connect \Y $9
+  end
+  process $group_1
+    assign \src_rsel_o 2'00
+    assign \src_rsel_o [0] $7
+    assign \src_rsel_o [1] $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.rr_r3"
+module \rr_r3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 0 \dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 input 1 \dst_rsel_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 output 2 \dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 3 \src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 output 4 \src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 input 5 \src_rsel_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \dst_rsel_i$1
+    connect \Y $5
+  end
+  process $group_0
+    assign \dest_rsel_o 2'00
+    assign \dest_rsel_o [0] $3
+    assign \dest_rsel_o [1] $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \src_rsel_i$2
+    connect \Y $9
+  end
+  process $group_1
+    assign \src_rsel_o 2'00
+    assign \src_rsel_o [0] $7
+    assign \src_rsel_o [1] $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.rd_v"
+module \rd_v
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
+  wire width 4 output 0 \g_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 input 1 \v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 input 2 \v_rd_rsel_o$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 input 3 \v_rd_rsel_o$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_rd_rsel_o$2 [0] \v_rd_rsel_o$1 [0] \v_rd_rsel_o [0] }
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_rd_rsel_o$2 [1] \v_rd_rsel_o$1 [1] \v_rd_rsel_o [1] }
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_rd_rsel_o$2 [2] \v_rd_rsel_o$1 [2] \v_rd_rsel_o [2] }
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_rd_rsel_o$2 [3] \v_rd_rsel_o$1 [3] \v_rd_rsel_o [3] }
+    connect \Y $9
+  end
+  process $group_0
+    assign \g_pend_o 4'0000
+    assign \g_pend_o { $9 $7 $5 $3 }
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "top.wr_v"
+module \wr_v
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
+  wire width 4 output 0 \g_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 input 1 \v_wr_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 input 2 \v_wr_rsel_o$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 input 3 \v_wr_rsel_o$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_wr_rsel_o$2 [0] \v_wr_rsel_o$1 [0] \v_wr_rsel_o [0] }
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_wr_rsel_o$2 [1] \v_wr_rsel_o$1 [1] \v_wr_rsel_o [1] }
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_wr_rsel_o$2 [2] \v_wr_rsel_o$1 [2] \v_wr_rsel_o [2] }
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
+  cell $reduce_bool $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A { \v_wr_rsel_o$2 [3] \v_wr_rsel_o$1 [3] \v_wr_rsel_o [3] }
+    connect \Y $9
+  end
+  process $group_0
+    assign \g_pend_o 4'0000
+    assign \g_pend_o { $9 $7 $5 $3 }
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \top 1
+attribute \nmigen.hierarchy "top"
+module \top
+  attribute \src "scoremulti/fu_reg_matrix.py:51"
+  wire width 4 input 0 \dst1
+  attribute \src "scoremulti/fu_reg_matrix.py:51"
+  wire width 4 input 1 \dst2
+  attribute \src "scoremulti/fu_reg_matrix.py:43"
+  wire width 4 input 2 \src1
+  attribute \src "scoremulti/fu_reg_matrix.py:43"
+  wire width 4 input 3 \src2
+  attribute \src "scoremulti/fu_reg_matrix.py:73"
+  wire width 3 input 4 \issue_i
+  attribute \src "scoremulti/fu_reg_matrix.py:53"
+  wire width 3 input 5 \gowr1_i
+  attribute \src "scoremulti/fu_reg_matrix.py:53"
+  wire width 3 input 6 \gowr2_i
+  attribute \src "scoremulti/fu_reg_matrix.py:45"
+  wire width 3 input 7 \gord1_i
+  attribute \src "scoremulti/fu_reg_matrix.py:45"
+  wire width 3 input 8 \gord2_i
+  attribute \src "scoremulti/fu_reg_matrix.py:76"
+  wire width 3 input 9 \go_die_i
+  attribute \src "scoremulti/fu_reg_matrix.py:52"
+  wire width 4 input 10 \dst1_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:52"
+  wire width 4 output 11 \dst2_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:44"
+  wire width 4 output 12 \src1_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:44"
+  wire width 4 output 13 \src2_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:89"
+  wire width 3 output 14 \wr_pend_o
+  attribute \src "scoremulti/fu_reg_matrix.py:90"
+  wire width 3 output 15 \rd_pend_o
+  attribute \src "scoremulti/fu_reg_matrix.py:68"
+  wire width 4 input 16 \wr_pend_i
+  attribute \src "scoremulti/fu_reg_matrix.py:69"
+  wire width 4 input 17 \rd_pend_i
+  attribute \src "scoremulti/fu_reg_matrix.py:70"
+  wire width 4 output 18 \v_wr_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:71"
+  wire width 4 output 19 \v_rd_rsel_o
+  attribute \src "scoremulti/fu_reg_matrix.py:58"
+  wire width 3 output 20 \rd_src1_pend_o
+  attribute \src "scoremulti/fu_reg_matrix.py:58"
+  wire width 3 output 21 \rd_src2_pend_o
+  attribute \src "scoremulti/fu_reg_matrix.py:58"
+  wire width 3 input 22 \rd_src3_pend_o
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 23 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 24 \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu0_dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu0_dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu0_src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu0_src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu0_dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu0_dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu0_src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu0_src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 \dr_fu0_rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 \dr_fu0_wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu0_dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu0_dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu0_src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu0_src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 \dr_fu0_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 \dr_fu0_go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 \dr_fu0_go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 \dr_fu0_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 \dr_fu0_v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 \dr_fu0_v_wr_rsel_o
+  cell \dr_fu0 \dr_fu0
+    connect \dst1_fwd_o \dr_fu0_dst1_fwd_o
+    connect \dst2_fwd_o \dr_fu0_dst2_fwd_o
+    connect \src1_fwd_o \dr_fu0_src1_fwd_o
+    connect \src2_fwd_o \dr_fu0_src2_fwd_o
+    connect \dst1_rsel_o \dr_fu0_dst1_rsel_o
+    connect \dst2_rsel_o \dr_fu0_dst2_rsel_o
+    connect \src1_rsel_o \dr_fu0_src1_rsel_o
+    connect \src2_rsel_o \dr_fu0_src2_rsel_o
+    connect \rd_pend_i \dr_fu0_rd_pend_i
+    connect \wr_pend_i \dr_fu0_wr_pend_i
+    connect \dst1 \dr_fu0_dst1
+    connect \dst2 \dr_fu0_dst2
+    connect \src1 \dr_fu0_src1
+    connect \src2 \dr_fu0_src2
+    connect \issue_i \dr_fu0_issue_i
+    connect \go_rd_i \dr_fu0_go_rd_i
+    connect \go_wr_i \dr_fu0_go_wr_i
+    connect \go_die_i \dr_fu0_go_die_i
+    connect \v_rd_rsel_o \dr_fu0_v_rd_rsel_o
+    connect \v_wr_rsel_o \dr_fu0_v_wr_rsel_o
+    connect \rst \rst
+    connect \clk \clk
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu1_dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu1_dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu1_src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu1_src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu1_dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu1_dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu1_src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu1_src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 \dr_fu1_rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 \dr_fu1_wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu1_dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu1_dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu1_src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu1_src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 \dr_fu1_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 \dr_fu1_go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 \dr_fu1_go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 \dr_fu1_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 \dr_fu1_v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 \dr_fu1_v_wr_rsel_o
+  cell \dr_fu1 \dr_fu1
+    connect \dst1_fwd_o \dr_fu1_dst1_fwd_o
+    connect \dst2_fwd_o \dr_fu1_dst2_fwd_o
+    connect \src1_fwd_o \dr_fu1_src1_fwd_o
+    connect \src2_fwd_o \dr_fu1_src2_fwd_o
+    connect \dst1_rsel_o \dr_fu1_dst1_rsel_o
+    connect \dst2_rsel_o \dr_fu1_dst2_rsel_o
+    connect \src1_rsel_o \dr_fu1_src1_rsel_o
+    connect \src2_rsel_o \dr_fu1_src2_rsel_o
+    connect \rd_pend_i \dr_fu1_rd_pend_i
+    connect \wr_pend_i \dr_fu1_wr_pend_i
+    connect \dst1 \dr_fu1_dst1
+    connect \dst2 \dr_fu1_dst2
+    connect \src1 \dr_fu1_src1
+    connect \src2 \dr_fu1_src2
+    connect \issue_i \dr_fu1_issue_i
+    connect \go_rd_i \dr_fu1_go_rd_i
+    connect \go_wr_i \dr_fu1_go_wr_i
+    connect \go_die_i \dr_fu1_go_die_i
+    connect \rst \rst
+    connect \clk \clk
+    connect \v_rd_rsel_o \dr_fu1_v_rd_rsel_o
+    connect \v_wr_rsel_o \dr_fu1_v_wr_rsel_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu2_dst1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
+  wire width 4 \dr_fu2_dst2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu2_src1_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
+  wire width 4 \dr_fu2_src2_fwd_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu2_dst1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
+  wire width 4 \dr_fu2_dst2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu2_src1_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
+  wire width 4 \dr_fu2_src2_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
+  wire width 4 \dr_fu2_rd_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
+  wire width 4 \dr_fu2_wr_pend_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu2_dst1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
+  wire width 4 \dr_fu2_dst2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu2_src1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
+  wire width 4 \dr_fu2_src2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
+  wire width 1 \dr_fu2_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
+  wire width 2 \dr_fu2_go_rd_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
+  wire width 2 \dr_fu2_go_wr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
+  wire width 1 \dr_fu2_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
+  wire width 4 \dr_fu2_v_rd_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
+  wire width 4 \dr_fu2_v_wr_rsel_o
+  cell \dr_fu2 \dr_fu2
+    connect \dst1_fwd_o \dr_fu2_dst1_fwd_o
+    connect \dst2_fwd_o \dr_fu2_dst2_fwd_o
+    connect \src1_fwd_o \dr_fu2_src1_fwd_o
+    connect \src2_fwd_o \dr_fu2_src2_fwd_o
+    connect \dst1_rsel_o \dr_fu2_dst1_rsel_o
+    connect \dst2_rsel_o \dr_fu2_dst2_rsel_o
+    connect \src1_rsel_o \dr_fu2_src1_rsel_o
+    connect \src2_rsel_o \dr_fu2_src2_rsel_o
+    connect \rd_pend_i \dr_fu2_rd_pend_i
+    connect \wr_pend_i \dr_fu2_wr_pend_i
+    connect \dst1 \dr_fu2_dst1
+    connect \dst2 \dr_fu2_dst2
+    connect \src1 \dr_fu2_src1
+    connect \src2 \dr_fu2_src2
+    connect \issue_i \dr_fu2_issue_i
+    connect \go_rd_i \dr_fu2_go_rd_i
+    connect \go_wr_i \dr_fu2_go_wr_i
+    connect \go_die_i \dr_fu2_go_die_i
+    connect \rst \rst
+    connect \clk \clk
+    connect \v_rd_rsel_o \dr_fu2_v_rd_rsel_o
+    connect \v_wr_rsel_o \dr_fu2_v_wr_rsel_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 \fu_fu0_reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 \fu_fu0_reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu0_dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 \fu_fu0_reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu0_dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu0_sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 \fu_fu0_reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu0_sfwd2_i
+  cell \fu_fu0 \fu_fu0
+    connect \reg_wr_pend_o \fu_fu0_reg_wr_pend_o
+    connect \reg_rd_pend_o \fu_fu0_reg_rd_pend_o
+    connect \dfwd1_i \fu_fu0_dfwd1_i
+    connect \reg_wr_dst_pend_o \fu_fu0_reg_wr_dst_pend_o
+    connect \dfwd2_i \fu_fu0_dfwd2_i
+    connect \sfwd1_i \fu_fu0_sfwd1_i
+    connect \reg_rd_src_pend_o \fu_fu0_reg_rd_src_pend_o
+    connect \sfwd2_i \fu_fu0_sfwd2_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 \fu_fu1_reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 \fu_fu1_reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu1_dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 \fu_fu1_reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu1_dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu1_sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 \fu_fu1_reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu1_sfwd2_i
+  cell \fu_fu1 \fu_fu1
+    connect \reg_wr_pend_o \fu_fu1_reg_wr_pend_o
+    connect \reg_rd_pend_o \fu_fu1_reg_rd_pend_o
+    connect \dfwd1_i \fu_fu1_dfwd1_i
+    connect \reg_wr_dst_pend_o \fu_fu1_reg_wr_dst_pend_o
+    connect \dfwd2_i \fu_fu1_dfwd2_i
+    connect \sfwd1_i \fu_fu1_sfwd1_i
+    connect \reg_rd_src_pend_o \fu_fu1_reg_rd_src_pend_o
+    connect \sfwd2_i \fu_fu1_sfwd2_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
+  wire width 1 \fu_fu2_reg_wr_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
+  wire width 1 \fu_fu2_reg_rd_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu2_dfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
+  wire width 2 \fu_fu2_reg_wr_dst_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
+  wire width 4 \fu_fu2_dfwd2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu2_sfwd1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
+  wire width 2 \fu_fu2_reg_rd_src_pend_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
+  wire width 4 \fu_fu2_sfwd2_i
+  cell \fu_fu2 \fu_fu2
+    connect \reg_wr_pend_o \fu_fu2_reg_wr_pend_o
+    connect \reg_rd_pend_o \fu_fu2_reg_rd_pend_o
+    connect \dfwd1_i \fu_fu2_dfwd1_i
+    connect \reg_wr_dst_pend_o \fu_fu2_reg_wr_dst_pend_o
+    connect \dfwd2_i \fu_fu2_dfwd2_i
+    connect \sfwd1_i \fu_fu2_sfwd1_i
+    connect \reg_rd_src_pend_o \fu_fu2_reg_rd_src_pend_o
+    connect \sfwd2_i \fu_fu2_sfwd2_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r0_dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r0_dst_rsel_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 \rr_r0_dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r0_src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 \rr_r0_src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r0_src_rsel_i$2
+  cell \rr_r0 \rr_r0
+    connect \dst_rsel_i \rr_r0_dst_rsel_i
+    connect \dst_rsel_i$1 \rr_r0_dst_rsel_i$1
+    connect \dest_rsel_o \rr_r0_dest_rsel_o
+    connect \src_rsel_i \rr_r0_src_rsel_i
+    connect \src_rsel_o \rr_r0_src_rsel_o
+    connect \src_rsel_i$2 \rr_r0_src_rsel_i$2
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r1_dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r1_dst_rsel_i$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 \rr_r1_dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r1_src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 \rr_r1_src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r1_src_rsel_i$4
+  cell \rr_r1 \rr_r1
+    connect \dst_rsel_i \rr_r1_dst_rsel_i
+    connect \dst_rsel_i$1 \rr_r1_dst_rsel_i$3
+    connect \dest_rsel_o \rr_r1_dest_rsel_o
+    connect \src_rsel_i \rr_r1_src_rsel_i
+    connect \src_rsel_o \rr_r1_src_rsel_o
+    connect \src_rsel_i$2 \rr_r1_src_rsel_i$4
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r2_dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r2_dst_rsel_i$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 \rr_r2_dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r2_src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 \rr_r2_src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r2_src_rsel_i$6
+  cell \rr_r2 \rr_r2
+    connect \dst_rsel_i \rr_r2_dst_rsel_i
+    connect \dst_rsel_i$1 \rr_r2_dst_rsel_i$5
+    connect \dest_rsel_o \rr_r2_dest_rsel_o
+    connect \src_rsel_i \rr_r2_src_rsel_i
+    connect \src_rsel_o \rr_r2_src_rsel_o
+    connect \src_rsel_i$2 \rr_r2_src_rsel_i$6
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r3_dst_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
+  wire width 3 \rr_r3_dst_rsel_i$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
+  wire width 2 \rr_r3_dest_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r3_src_rsel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
+  wire width 2 \rr_r3_src_rsel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
+  wire width 3 \rr_r3_src_rsel_i$8
+  cell \rr_r3 \rr_r3
+    connect \dst_rsel_i \rr_r3_dst_rsel_i
+    connect \dst_rsel_i$1 \rr_r3_dst_rsel_i$7
+    connect \dest_rsel_o \rr_r3_dest_rsel_o
+    connect \src_rsel_i \rr_r3_src_rsel_i
+    connect \src_rsel_o \rr_r3_src_rsel_o
+    connect \src_rsel_i$2 \rr_r3_src_rsel_i$8
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
+  wire width 4 \rd_v_g_pend_o
+  cell \rd_v \rd_v
+    connect \g_pend_o \rd_v_g_pend_o
+    connect \v_rd_rsel_o \dr_fu0_v_rd_rsel_o
+    connect \v_rd_rsel_o$1 \dr_fu1_v_rd_rsel_o
+    connect \v_rd_rsel_o$2 \dr_fu2_v_rd_rsel_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
+  wire width 4 \wr_v_g_pend_o
+  cell \wr_v \wr_v
+    connect \g_pend_o \wr_v_g_pend_o
+    connect \v_wr_rsel_o \dr_fu0_v_wr_rsel_o
+    connect \v_wr_rsel_o$1 \dr_fu1_v_wr_rsel_o
+    connect \v_wr_rsel_o$2 \dr_fu2_v_wr_rsel_o
+  end
+  process $group_0
+    assign \wr_pend_o 3'000
+    assign \wr_pend_o { \fu_fu2_reg_wr_pend_o \fu_fu1_reg_wr_pend_o \fu_fu0_reg_wr_pend_o }
+    sync init
+  end
+  process $group_1
+    assign \rd_pend_o 3'000
+    assign \rd_pend_o { \fu_fu2_reg_rd_pend_o \fu_fu1_reg_rd_pend_o \fu_fu0_reg_rd_pend_o }
+    sync init
+  end
+  process $group_2
+    assign \fu_fu0_dfwd1_i 4'0000
+    assign \fu_fu0_dfwd1_i { \dr_fu0_dst1_fwd_o [3] \dr_fu0_dst1_fwd_o [2] \dr_fu0_dst1_fwd_o [1] \dr_fu0_dst1_fwd_o [0] }
+    sync init
+  end
+  process $group_3
+    assign \fu_fu1_dfwd1_i 4'0000
+    assign \fu_fu1_dfwd1_i { \dr_fu1_dst1_fwd_o [3] \dr_fu1_dst1_fwd_o [2] \dr_fu1_dst1_fwd_o [1] \dr_fu1_dst1_fwd_o [0] }
+    sync init
+  end
+  process $group_4
+    assign \fu_fu2_dfwd1_i 4'0000
+    assign \fu_fu2_dfwd1_i { \dr_fu2_dst1_fwd_o [3] \dr_fu2_dst1_fwd_o [2] \dr_fu2_dst1_fwd_o [1] \dr_fu2_dst1_fwd_o [0] }
+    sync init
+  end
+  attribute \src "scoremulti/fu_reg_matrix.py:59"
+  wire width 3 \wr_dst1_pend_o
+  process $group_5
+    assign \wr_dst1_pend_o 3'000
+    assign \wr_dst1_pend_o { \fu_fu2_reg_wr_dst_pend_o [0] \fu_fu1_reg_wr_dst_pend_o [0] \fu_fu0_reg_wr_dst_pend_o [0] }
+    sync init
+  end
+  process $group_6
+    assign \fu_fu0_dfwd2_i 4'0000
+    assign \fu_fu0_dfwd2_i { \dr_fu0_dst2_fwd_o [3] \dr_fu0_dst2_fwd_o [2] \dr_fu0_dst2_fwd_o [1] \dr_fu0_dst2_fwd_o [0] }
+    sync init
+  end
+  process $group_7
+    assign \fu_fu1_dfwd2_i 4'0000
+    assign \fu_fu1_dfwd2_i { \dr_fu1_dst2_fwd_o [3] \dr_fu1_dst2_fwd_o [2] \dr_fu1_dst2_fwd_o [1] \dr_fu1_dst2_fwd_o [0] }
+    sync init
+  end
+  process $group_8
+    assign \fu_fu2_dfwd2_i 4'0000
+    assign \fu_fu2_dfwd2_i { \dr_fu2_dst2_fwd_o [3] \dr_fu2_dst2_fwd_o [2] \dr_fu2_dst2_fwd_o [1] \dr_fu2_dst2_fwd_o [0] }
+    sync init
+  end
+  attribute \src "scoremulti/fu_reg_matrix.py:59"
+  wire width 3 \wr_dst2_pend_o
+  process $group_9
+    assign \wr_dst2_pend_o 3'000
+    assign \wr_dst2_pend_o { \fu_fu2_reg_wr_dst_pend_o [1] \fu_fu1_reg_wr_dst_pend_o [1] \fu_fu0_reg_wr_dst_pend_o [1] }
+    sync init
+  end
+  process $group_10
+    assign \fu_fu0_sfwd1_i 4'0000
+    assign \fu_fu0_sfwd1_i { \dr_fu0_src1_fwd_o [3] \dr_fu0_src1_fwd_o [2] \dr_fu0_src1_fwd_o [1] \dr_fu0_src1_fwd_o [0] }
+    sync init
+  end
+  process $group_11
+    assign \fu_fu1_sfwd1_i 4'0000
+    assign \fu_fu1_sfwd1_i { \dr_fu1_src1_fwd_o [3] \dr_fu1_src1_fwd_o [2] \dr_fu1_src1_fwd_o [1] \dr_fu1_src1_fwd_o [0] }
+    sync init
+  end
+  process $group_12
+    assign \fu_fu2_sfwd1_i 4'0000
+    assign \fu_fu2_sfwd1_i { \dr_fu2_src1_fwd_o [3] \dr_fu2_src1_fwd_o [2] \dr_fu2_src1_fwd_o [1] \dr_fu2_src1_fwd_o [0] }
+    sync init
+  end
+  process $group_13
+    assign \rd_src1_pend_o 3'000
+    assign \rd_src1_pend_o { \fu_fu2_reg_rd_src_pend_o [0] \fu_fu1_reg_rd_src_pend_o [0] \fu_fu0_reg_rd_src_pend_o [0] }
+    sync init
+  end
+  process $group_14
+    assign \fu_fu0_sfwd2_i 4'0000
+    assign \fu_fu0_sfwd2_i { \dr_fu0_src2_fwd_o [3] \dr_fu0_src2_fwd_o [2] \dr_fu0_src2_fwd_o [1] \dr_fu0_src2_fwd_o [0] }
+    sync init
+  end
+  process $group_15
+    assign \fu_fu1_sfwd2_i 4'0000
+    assign \fu_fu1_sfwd2_i { \dr_fu1_src2_fwd_o [3] \dr_fu1_src2_fwd_o [2] \dr_fu1_src2_fwd_o [1] \dr_fu1_src2_fwd_o [0] }
+    sync init
+  end
+  process $group_16
+    assign \fu_fu2_sfwd2_i 4'0000
+    assign \fu_fu2_sfwd2_i { \dr_fu2_src2_fwd_o [3] \dr_fu2_src2_fwd_o [2] \dr_fu2_src2_fwd_o [1] \dr_fu2_src2_fwd_o [0] }
+    sync init
+  end
+  process $group_17
+    assign \rd_src2_pend_o 3'000
+    assign \rd_src2_pend_o { \fu_fu2_reg_rd_src_pend_o [1] \fu_fu1_reg_rd_src_pend_o [1] \fu_fu0_reg_rd_src_pend_o [1] }
+    sync init
+  end
+  process $group_18
+    assign \rr_r0_dst_rsel_i 3'000
+    assign \rr_r0_dst_rsel_i { \dr_fu2_dst1_rsel_o [0] \dr_fu1_dst1_rsel_o [0] \dr_fu0_dst1_rsel_o [0] }
+    sync init
+  end
+  process $group_19
+    assign \rr_r1_dst_rsel_i 3'000
+    assign \rr_r1_dst_rsel_i { \dr_fu2_dst1_rsel_o [1] \dr_fu1_dst1_rsel_o [1] \dr_fu0_dst1_rsel_o [1] }
+    sync init
+  end
+  process $group_20
+    assign \rr_r2_dst_rsel_i 3'000
+    assign \rr_r2_dst_rsel_i { \dr_fu2_dst1_rsel_o [2] \dr_fu1_dst1_rsel_o [2] \dr_fu0_dst1_rsel_o [2] }
+    sync init
+  end
+  process $group_21
+    assign \rr_r3_dst_rsel_i 3'000
+    assign \rr_r3_dst_rsel_i { \dr_fu2_dst1_rsel_o [3] \dr_fu1_dst1_rsel_o [3] \dr_fu0_dst1_rsel_o [3] }
+    sync init
+  end
+  process $group_22
+    assign \rr_r0_dst_rsel_i$1 3'000
+    assign \rr_r0_dst_rsel_i$1 { \dr_fu2_dst2_rsel_o [0] \dr_fu1_dst2_rsel_o [0] \dr_fu0_dst2_rsel_o [0] }
+    sync init
+  end
+  process $group_23
+    assign \rr_r1_dst_rsel_i$3 3'000
+    assign \rr_r1_dst_rsel_i$3 { \dr_fu2_dst2_rsel_o [1] \dr_fu1_dst2_rsel_o [1] \dr_fu0_dst2_rsel_o [1] }
+    sync init
+  end
+  process $group_24
+    assign \rr_r2_dst_rsel_i$5 3'000
+    assign \rr_r2_dst_rsel_i$5 { \dr_fu2_dst2_rsel_o [2] \dr_fu1_dst2_rsel_o [2] \dr_fu0_dst2_rsel_o [2] }
+    sync init
+  end
+  process $group_25
+    assign \rr_r3_dst_rsel_i$7 3'000
+    assign \rr_r3_dst_rsel_i$7 { \dr_fu2_dst2_rsel_o [3] \dr_fu1_dst2_rsel_o [3] \dr_fu0_dst2_rsel_o [3] }
+    sync init
+  end
+  process $group_26
+    assign \dst2_rsel_o 4'0000
+    assign \dst2_rsel_o { \rr_r3_dest_rsel_o [1] \rr_r2_dest_rsel_o [1] \rr_r1_dest_rsel_o [1] \rr_r0_dest_rsel_o [1] }
+    sync init
+  end
+  process $group_27
+    assign \rr_r0_src_rsel_i 3'000
+    assign \rr_r0_src_rsel_i { \dr_fu2_src1_rsel_o [0] \dr_fu1_src1_rsel_o [0] \dr_fu0_src1_rsel_o [0] }
+    sync init
+  end
+  process $group_28
+    assign \rr_r1_src_rsel_i 3'000
+    assign \rr_r1_src_rsel_i { \dr_fu2_src1_rsel_o [1] \dr_fu1_src1_rsel_o [1] \dr_fu0_src1_rsel_o [1] }
+    sync init
+  end
+  process $group_29
+    assign \rr_r2_src_rsel_i 3'000
+    assign \rr_r2_src_rsel_i { \dr_fu2_src1_rsel_o [2] \dr_fu1_src1_rsel_o [2] \dr_fu0_src1_rsel_o [2] }
+    sync init
+  end
+  process $group_30
+    assign \rr_r3_src_rsel_i 3'000
+    assign \rr_r3_src_rsel_i { \dr_fu2_src1_rsel_o [3] \dr_fu1_src1_rsel_o [3] \dr_fu0_src1_rsel_o [3] }
+    sync init
+  end
+  process $group_31
+    assign \src1_rsel_o 4'0000
+    assign \src1_rsel_o { \rr_r3_src_rsel_o [0] \rr_r2_src_rsel_o [0] \rr_r1_src_rsel_o [0] \rr_r0_src_rsel_o [0] }
+    sync init
+  end
+  process $group_32
+    assign \rr_r0_src_rsel_i$2 3'000
+    assign \rr_r0_src_rsel_i$2 { \dr_fu2_src2_rsel_o [0] \dr_fu1_src2_rsel_o [0] \dr_fu0_src2_rsel_o [0] }
+    sync init
+  end
+  process $group_33
+    assign \rr_r1_src_rsel_i$4 3'000
+    assign \rr_r1_src_rsel_i$4 { \dr_fu2_src2_rsel_o [1] \dr_fu1_src2_rsel_o [1] \dr_fu0_src2_rsel_o [1] }
+    sync init
+  end
+  process $group_34
+    assign \rr_r2_src_rsel_i$6 3'000
+    assign \rr_r2_src_rsel_i$6 { \dr_fu2_src2_rsel_o [2] \dr_fu1_src2_rsel_o [2] \dr_fu0_src2_rsel_o [2] }
+    sync init
+  end
+  process $group_35
+    assign \rr_r3_src_rsel_i$8 3'000
+    assign \rr_r3_src_rsel_i$8 { \dr_fu2_src2_rsel_o [3] \dr_fu1_src2_rsel_o [3] \dr_fu0_src2_rsel_o [3] }
+    sync init
+  end
+  process $group_36
+    assign \src2_rsel_o 4'0000
+    assign \src2_rsel_o { \rr_r3_src_rsel_o [1] \rr_r2_src_rsel_o [1] \rr_r1_src_rsel_o [1] \rr_r0_src_rsel_o [1] }
+    sync init
+  end
+  process $group_37
+    assign \dr_fu0_rd_pend_i 4'0000
+    assign \dr_fu0_rd_pend_i \rd_pend_i
+    sync init
+  end
+  process $group_38
+    assign \dr_fu0_wr_pend_i 4'0000
+    assign \dr_fu0_wr_pend_i \wr_pend_i
+    sync init
+  end
+  process $group_39
+    assign \dr_fu1_rd_pend_i 4'0000
+    assign \dr_fu1_rd_pend_i \rd_pend_i
+    sync init
+  end
+  process $group_40
+    assign \dr_fu1_wr_pend_i 4'0000
+    assign \dr_fu1_wr_pend_i \wr_pend_i
+    sync init
+  end
+  process $group_41
+    assign \dr_fu2_rd_pend_i 4'0000
+    assign \dr_fu2_rd_pend_i \rd_pend_i
+    sync init
+  end
+  process $group_42
+    assign \dr_fu2_wr_pend_i 4'0000
+    assign \dr_fu2_wr_pend_i \wr_pend_i
+    sync init
+  end
+  process $group_43
+    assign \dr_fu0_dst1 4'0000
+    assign \dr_fu0_dst1 \dst1
+    sync init
+  end
+  process $group_44
+    assign \dr_fu1_dst1 4'0000
+    assign \dr_fu1_dst1 \dst1
+    sync init
+  end
+  process $group_45
+    assign \dr_fu2_dst1 4'0000
+    assign \dr_fu2_dst1 \dst1
+    sync init
+  end
+  process $group_46
+    assign \dr_fu0_dst2 4'0000
+    assign \dr_fu0_dst2 \dst2
+    sync init
+  end
+  process $group_47
+    assign \dr_fu1_dst2 4'0000
+    assign \dr_fu1_dst2 \dst2
+    sync init
+  end
+  process $group_48
+    assign \dr_fu2_dst2 4'0000
+    assign \dr_fu2_dst2 \dst2
+    sync init
+  end
+  process $group_49
+    assign \dr_fu0_src1 4'0000
+    assign \dr_fu0_src1 \src1
+    sync init
+  end
+  process $group_50
+    assign \dr_fu1_src1 4'0000
+    assign \dr_fu1_src1 \src1
+    sync init
+  end
+  process $group_51
+    assign \dr_fu2_src1 4'0000
+    assign \dr_fu2_src1 \src1
+    sync init
+  end
+  process $group_52
+    assign \dr_fu0_src2 4'0000
+    assign \dr_fu0_src2 \src2
+    sync init
+  end
+  process $group_53
+    assign \dr_fu1_src2 4'0000
+    assign \dr_fu1_src2 \src2
+    sync init
+  end
+  process $group_54
+    assign \dr_fu2_src2 4'0000
+    assign \dr_fu2_src2 \src2
+    sync init
+  end
+  process $group_55
+    assign \v_rd_rsel_o 4'0000
+    assign \v_rd_rsel_o \rd_v_g_pend_o
+    sync init
+  end
+  process $group_56
+    assign \v_wr_rsel_o 4'0000
+    assign \v_wr_rsel_o \wr_v_g_pend_o
+    sync init
+  end
+  process $group_57
+    assign \dr_fu0_issue_i 1'0
+    assign \dr_fu1_issue_i 1'0
+    assign \dr_fu2_issue_i 1'0
+    assign { \dr_fu2_issue_i \dr_fu1_issue_i \dr_fu0_issue_i } \issue_i
+    sync init
+  end
+  process $group_60
+    assign \dr_fu0_go_rd_i 2'00
+    assign \dr_fu1_go_rd_i 2'00
+    assign \dr_fu2_go_rd_i 2'00
+    assign { \dr_fu2_go_rd_i [0] \dr_fu1_go_rd_i [0] \dr_fu0_go_rd_i [0] } \gord1_i
+    assign { \dr_fu2_go_rd_i [1] \dr_fu1_go_rd_i [1] \dr_fu0_go_rd_i [1] } \gord2_i
+    sync init
+  end
+  process $group_63
+    assign \dr_fu0_go_wr_i 2'00
+    assign \dr_fu1_go_wr_i 2'00
+    assign \dr_fu2_go_wr_i 2'00
+    assign { \dr_fu2_go_wr_i [0] \dr_fu1_go_wr_i [0] \dr_fu0_go_wr_i [0] } \gowr1_i
+    assign { \dr_fu2_go_wr_i [1] \dr_fu1_go_wr_i [1] \dr_fu0_go_wr_i [1] } \gowr2_i
+    sync init
+  end
+  process $group_66
+    assign \dr_fu0_go_die_i 1'0
+    assign \dr_fu1_go_die_i 1'0
+    assign \dr_fu2_go_die_i 1'0
+    assign { \dr_fu2_go_die_i \dr_fu1_go_die_i \dr_fu0_go_die_i } \go_die_i
+    sync init
+  end
+end