add incoming PortInterface to be connected to LoadStoreCompUnit

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index fc950026d7392c7c28f1f4f637fc783d2d6a2c5a..04160db847280eff1c4d67f1af85f02d0f9db43a 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -11,6 +11,7 @@ from soc.decoder.power_fieldsn import SignalBitRange
 from soc.decoder.power_decoder2 import decode_spr_num
 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
 
+from soc.experiment.pimem import PortInterface
 
 class FSMMMUStage(ControlBase):
     def __init__(self, pspec):
@@ -21,6 +22,9 @@ class FSMMMUStage(ControlBase):
         self.p.data_i = MMUInputData(pspec)
         self.n.data_o = MMUOutputData(pspec)
 
+        # incoming PortInterface
+        self.pi = PortInterface("mmupi")
+
         # this Function Unit is extremely unusual in that it actually stores a
         # "thing" rather than "processes inputs and produces outputs".  hence
         # why it has to be a FSM.  linking up LD/ST however is going to have