add invert/zeroing addu subvl predicate test

diff --git a/isa/rv64ui/sv_addi_predicated_subvl.S b/isa/rv64ui/sv_addi_predicated_subvl.S
index 21be1488e250a78f340308421904776a6723a64a..ea30797a70675e3fabd73ee66b7ee68d470aca58 100644 (file)
--- a/isa/rv64ui/sv_addi_predicated_subvl.S
+++ b/isa/rv64ui/sv_addi_predicated_subvl.S
@@ -43,27 +43,25 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_PREDICATION_TEST( 0x1, 0, 0, 0x41424445, 0 )
         SV_PREDICATION_TEST( 0x2, 0, 0, 0x42434344, 0 )
         SV_PREDICATION_TEST( 0x3, 0, 0, 0x42434445, 0 )
-        SV_PREDICATION_TEST( 0x0, 0, 0, 0x41424344, 0 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 0, 0x41424344, 0 )
 
         # zeroing, no inversion
         SV_PREDICATION_TEST( 0x1, 0, 1, 0x00004445, 0 )
         SV_PREDICATION_TEST( 0x2, 0, 1, 0x42430000, 0 )
         SV_PREDICATION_TEST( 0x3, 0, 1, 0x42434445, 0 )
-        SV_PREDICATION_TEST( 0x0, 0, 1, 0x00000000, 0 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 1, 0x00000000, 0 )
 
-/*
         # no zeroing, inversion
-        SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 ) 
-        SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 ) 
-        SV_PREDICATION_TEST( 0x0, 1, 0, 42, 43 ) 
-        SV_PREDICATION_TEST( 0x3, 1, 0, 41, 42 ) 
+        SV_PREDICATION_TEST( 0x1, 1, 0, 0x42434344, 0 )
+        SV_PREDICATION_TEST( 0x2, 1, 0, 0x41424445, 0 )
+        SV_PREDICATION_TEST( 0x3, 1, 0, 0x41424344, 0 )
+        SV_PREDICATION_TEST( 0x0, 1, 0, 0x42434445, 0 )
 
         # zeroing, inversion
-        SV_PREDICATION_TEST( 0x2, 1, 1, 42, 0 ) 
-        SV_PREDICATION_TEST( 0x1, 1, 1, 0, 43 ) 
-        SV_PREDICATION_TEST( 0x0, 1, 1, 42, 43 ) 
-        SV_PREDICATION_TEST( 0x3, 1, 1, 0, 0 ) 
-*/
+        SV_PREDICATION_TEST( 0x1, 1, 1, 0x42430000, 0 )
+        SV_PREDICATION_TEST( 0x2, 1, 1, 0x00004445, 0 )
+        SV_PREDICATION_TEST( 0x3, 1, 1, 0x00000000, 0 )
+        SV_PREDICATION_TEST( 0x0, 1, 1, 0x42434445, 0 )
 
         RVTEST_PASS           # Signal success.
 fail: