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[libreriscv.git]
/
HDL_workflow
/
2021-05-26
lkcl
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2021-05-26
lkcl
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2021-05-26
lkcl
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2021-05-26
lkcl
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2021-05-26
lkcl
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2021-05-26
lkcl
(no commit message)
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2021-05-24
R Veera Kumar
Add pages for cocotb setup and use.
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2021-05-24
R Veera Kumar
Add pages for Icarus Verilog setup and use.
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2021-05-24
R Veera Kumar
Add pages for GHDL setup and use.
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2021-05-22
lkcl
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2021-05-22
lkcl
(no commit message)
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2021-05-20
R Veera Kumar
Add pages for Verilator setup and use.
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2021-05-09
Luke Kenneth Casso...
include link to tasyagle
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2021-04-12
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:libreriscv
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2021-04-11
Luke Kenneth Casso...
update DCD-FT232 image
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2021-04-11
Luke Kenneth Casso...
restore colours back to originals to minimise changes.
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2021-04-11
Luke Kenneth Casso...
re-add removed images
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2021-04-11
colepoirier@1ec9c8...
(no commit message)
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2021-04-11
Luke Kenneth Casso...
add FT232 photo
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2021-04-11
Luke Kenneth Casso...
add ft232 image
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2021-04-11
colepoirier@1ec9c8...
(no commit message)
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2021-04-11
colepoirier
restore ECP5_FPGA.mdwn, ft232r_jtag_wires.jpg, ulx3s_fp...
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2021-04-11
colepoirier@1ec9c8...
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2021-04-11
colepoirier@1ec9c8...
(no commit message)
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2021-04-10
colepoirier
update rotation of ulx32 jtag wires image
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2021-04-10
colepoirier
update ft232r and ulx3s jtag wire images to reflect...
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2021-04-10
colepoirier@1ec9c8...
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2021-04-10
colepoirier@1ec9c8...
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2021-04-09
colepoirier@1ec9c8...
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2021-04-09
colepoirier@1ec9c8...
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2021-04-09
colepoirier@1ec9c8...
(no commit message)
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2021-04-09
colepoirier
add new ft232 wiring colors images of ulx3s and ft232r...
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2021-04-09
colepoirier@1ec9c8...
(no commit message)
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2021-03-30
lkcl
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2021-03-30
lkcl
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2021-03-30
lkcl
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2021-03-29
lkcl
(no commit message)
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2021-03-29
Luke Kenneth Casso...
update litex page
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2021-03-29
Luke Kenneth Casso...
add litex_ls180.mdwn
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2021-03-29
mePy2
placeholders
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2021-03-29
mePy2
corrections
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2021-03-29
mePy2
(no commit message)
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2021-03-29
mePy2
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2021-03-29
mePy2
(no commit message)
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2021-03-29
mePy2
(no commit message)
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2021-03-28
mePy2
(no commit message)
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2021-03-28
mePy2
correctly formatted the text.
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2021-03-28
mePy2
Populated the page with general git info and commands
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2021-03-28
lkcl
(no commit message)
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2021-03-10
lkcl
(no commit message)
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2021-03-10
lkcl
(no commit message)
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2021-03-10
lkcl
(no commit message)
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2021-03-10
R Veera Kumar
Corrections
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2021-03-10
R Veera Kumar
Corrections
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commitdiff
2021-03-10
R Veera Kumar
Installation instructions for nextpnr with ECP5
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2021-03-09
colepoirier@1ec9c8...
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2021-02-24
colepoirier@1ec9c8...
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2021-02-24
colepoirier@1ec9c8...
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2021-02-15
colepoirier@1ec9c8...
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2021-02-15
colepoirier@1ec9c8...
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2020-11-24
colepoirier@1ec9c8...
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2020-11-24
colepoirier@1ec9c8...
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2020-11-23
lkcl
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2020-11-23
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-22
colepoirier@1ec9c8...
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2020-11-16
colepoirier@1ec9c8...
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2020-11-16
colepoirier@1ec9c8...
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2020-11-16
colepoirier@1ec9c8...
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2020-11-16
colepoirier@1ec9c8...
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2020-11-16
colepoirier@1ec9c8...
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-04
Luke Kenneth Casso...
show tab on imag
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2020-11-04
Luke Kenneth Casso...
update FPGA connector images
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2020-11-04
Luke Kenneth Casso...
change to use 3.3v on VERSA X3
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-04
Cole Poirier
HDL_wokflow update ulx3s jtag jumper wire connection...
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commitdiff
2020-11-04
Cole Poirier
HDL_workflow/ECP5_FPGA provide two images showing diffe...
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-04
Cole Poirier
update photo for stlinkv2 JTAG wires in HDL_Workflow...
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-04
colepoirier@1ec9c8...
(no commit message)
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2020-11-03
Luke Kenneth Casso...
colour-mark X3 VERSA ECP5 JTAG pins
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2020-11-03
Luke Kenneth Casso...
update jtag table, add colour to images
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2020-11-03
Luke Kenneth Casso...
add stlinkv2 photos
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2020-11-03
Luke Kenneth Casso...
add stlinkv2 connector images
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2020-11-03
Luke Kenneth Casso...
swap wires around to match ulx3s
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2020-11-03
Luke Kenneth Casso...
format table
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2020-11-03
Luke Kenneth Casso...
add ECP5 JTAG connections
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2020-11-03
Luke Kenneth Casso...
add image links to ECP5 page
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commitdiff
2020-11-03
Luke Kenneth Casso...
add versa ecp5 x3 photo
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commitdiff
2020-11-03
Luke Kenneth Casso...
add VERSA-ECP5 images, rename FPGA page
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2020-11-01
colepoirier@1ec9c8...
(no commit message)
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2020-11-01
colepoirier@1ec9c8...
(no commit message)
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commitdiff
2020-11-01
Cole Poirier
add images to wiki for ulx3s jtag stlinkv2 wires
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