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add Makefile for verilog compilation
[rv32.git]
/ cpu.py
2018-11-28
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2018-11-28
Luke Kenneth Casso...
handle_trap returns values that get manually transferre...
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2018-11-27
Luke Kenneth Casso...
remove trap_handled, remove w_en
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2018-11-27
Luke Kenneth Casso...
move handle trap out to separate module, bit messy
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2018-11-27
Luke Kenneth Casso...
split out cpu_mip to separate module
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2018-11-27
Luke Kenneth Casso...
split out cpu_mie into separate module
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2018-11-27
Luke Kenneth Casso...
split out MStatus to separate module
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2018-11-27
Luke Kenneth Casso...
split cpu loadstore calc out
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2018-11-26
Luke Kenneth Casso...
move get_fetch_action to separate verilog file
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2018-11-26
Luke Kenneth Casso...
prepare get_fetch_action for move to separate module
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2018-11-26
Luke Kenneth Casso...
whoops missed out branch_taken logic from fetch_action
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2018-11-26
Luke Kenneth Casso...
rename register varnames to regfile
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2018-11-26
Luke Kenneth Casso...
reorganise cpu regfile, to separate module, with 2R1W...
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2018-11-26
Luke Kenneth Casso...
complete csrs
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2018-11-26
Luke Kenneth Casso...
add misa and mstatus csrs
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2018-11-26
Luke Kenneth Casso...
start adding csrs
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2018-11-26
Luke Kenneth Casso...
move stuff to MInfo
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2018-11-26
Luke Kenneth Casso...
split CSR to separate class
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2018-11-26
Luke Kenneth Casso...
add handle_main
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2018-11-26
Luke Kenneth Casso...
add counters (TODO)
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2018-11-26
Luke Kenneth Casso...
add csr_is_valid
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2018-11-26
Luke Kenneth Casso...
start on csr op valid
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2018-11-26
Luke Kenneth Casso...
CSR decoding
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2018-11-26
Luke Kenneth Casso...
add handle_trap
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2018-11-26
Luke Kenneth Casso...
add handle_trap
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2018-11-26
Luke Kenneth Casso...
add handle trap
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2018-11-26
Luke Kenneth Casso...
complete get_fetch_action, move to class Fetch
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2018-11-26
Luke Kenneth Casso...
start converting get_fetch_action
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2018-11-26
Luke Kenneth Casso...
create Fetch class
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2018-11-26
Luke Kenneth Casso...
add get_fetch_action ready for conversion
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2018-11-25
Luke Kenneth Casso...
add mstatus, mip and vendor/arch/mimpl
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2018-11-25
Luke Kenneth Casso...
add MISA and MIE
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2018-11-25
Luke Kenneth Casso...
add more logic and mstatus
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2018-11-25
Luke Kenneth Casso...
calculate lui_auipc
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2018-11-25
Luke Kenneth Casso...
minor reorg, add alu
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2018-11-25
Luke Kenneth Casso...
minor reorg, add alu
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2018-11-25
Luke Kenneth Casso...
convert loaded value
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2018-11-25
Luke Kenneth Casso...
load value
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2018-11-25
Luke Kenneth Casso...
more cpu logic
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2018-11-25
Luke Kenneth Casso...
small cpu reorg
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2018-11-25
Luke Kenneth Casso...
add load/store misaligned
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2018-11-25
Luke Kenneth Casso...
add CPU decoder instance
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2018-11-25
Luke Kenneth Casso...
add cpuFetchStage instance
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2018-11-25
Luke Kenneth Casso...
adding call out to cpu_memory_interface verilog module...
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2018-11-24
Luke Kenneth Casso...
stub cpu.py
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