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Keep the DownloadTest source if the test fails.
[riscv-tests.git]
/
debug
/
targets
/
2017-02-17
Tim Newsome
Add HiFive1 target.
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2016-10-19
Tim Newsome
Merge pull request #34 from richardxia/use-port-randomi...
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2016-10-18
Richard Xia
Pull port number from VCS output and pass to OpenOCD.
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2016-10-03
Tim Newsome
Add test for memory read from invalid address.
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2016-08-12
Tim Newsome
Merge pull request #21 from sifive/add_freedom_sim_targets
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2016-08-11
Megan Wachs
Add FreedomU500 & incorporate feedback
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2016-08-08
Megan Wachs
Add U500 Target
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2016-08-08
Megan Wachs
Added FreedomE300 Simulator target
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2016-07-27
Tim Newsome
Rename m2gl_m2s to freedom-e300. (#19)
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2016-07-27
Tim Newsome
Rename m2gl_m2s to freedom-e300.
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2016-07-20
Andrew Waterman
Merge pull request #17 from timsifive/debug
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2016-07-19
Tim Newsome
I think I've finally got malloc working right.
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2016-07-19
Tim Newsome
Increase TCK speed.
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2016-07-19
Tim Newsome
Bump up speed.
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2016-07-19
Tim Newsome
Update IDCODE.
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2016-07-19
Tim Newsome
Add simple register tests.
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2016-07-19
Tim Newsome
Add block test.
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2016-07-19
Tim Newsome
All tests pass with spike now.
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2016-07-19
Tim Newsome
Made some progress towards working with spike.
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2016-07-19
Tim Newsome
WIP on debug testing.
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