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Update README
[riscv-isa-sim.git]
/
debug_rom
/ debug_rom.h
2017-05-17
Palmer Dabbelt
Merge remote-tracking branch 'origin/priv-1.10'
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2017-05-16
Palmer Dabbelt
Merge remote-tracking branch 'origin/debug-0.13' into...
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2017-04-18
Megan Wachs
debug: Add fence and fence.i to ensure Debug RAM is...
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2017-04-18
Megan Wachs
debug: Use a more practical debug ROM
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2016-09-02
Tim Newsome
Merge branch 'master' into trigger
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2016-09-02
Tim Newsome
Rebuild debug ROM because CSR encoding changed.
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2016-06-23
Andrew Waterman
Parameterize debug ROM contents on XLEN
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2016-06-09
Tim Newsome
Fix 2 bugs in Debug ROM: (#52)
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2016-06-03
Tim Newsome
DCSR cause was moved, bug debug ROM wasn't updated
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2016-06-01
Tim Newsome
Move sethaltnot and cleardebint.
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2016-05-24
Tim Newsome
New encoding.h for new CSR addresses.
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2016-05-24
Tim Newsome
Move cleardebint, per spec.
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2016-05-23
Tim Newsome
Change DCSR bits to match spec.
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2016-05-23
Tim Newsome
Use fence.i in Debug ROM.
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2016-05-23
Tim Newsome
Add dret.
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2016-05-23
Tim Newsome
Implement single memory read access.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode, stay in Debug Mode.
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2016-05-23
Tim Newsome
Have Debug memory kind of working again.
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2016-05-23
Tim Newsome
Fix race using fence.
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2016-05-23
Tim Newsome
processor_t unfriends gdbserver_t.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
Jump to the correct (temporary) Debug RAM address.
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2016-05-23
Tim Newsome
Clean up how Debug ROM is included.
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