git.libre-soc.org Git - riscv-isa-sim.git/history

2018-09-25	Luke Kenneth Casso...	change to instruction template parsing, create one...	blob \| commitdiff \| raw
2018-09-24	Luke Kenneth Casso...	create #defines from identified registers, per opcode	blob \| commitdiff \| raw \| diff to current
2018-09-24	Luke Kenneth Casso...	clarify docstring on id_regs.py	blob \| commitdiff \| raw \| diff to current
2018-09-24	Luke Kenneth Casso...	add function identifying the registers in each emulated...	blob \| commitdiff \| raw \| diff to current
2018-09-24	Luke Kenneth Casso...	identify instructions, plan: extract registers	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike